mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_ARM_STD/TARGET_LPC4330/startup_LPC43xx.S@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/***********************************************************************
<> 144:ef7eb2e8f9f7 2 ; * @brief: LPC18xx/43xx M3/M4 startup code
<> 144:ef7eb2e8f9f7 3 ; *
<> 144:ef7eb2e8f9f7 4 ; * @note
<> 144:ef7eb2e8f9f7 5 ; * Copyright(C) NXP Semiconductors, 2012
<> 144:ef7eb2e8f9f7 6 ; * All rights reserved.
<> 144:ef7eb2e8f9f7 7 ; *
<> 144:ef7eb2e8f9f7 8 ; * @par
<> 144:ef7eb2e8f9f7 9 ; * Software that is described herein is for illustrative purposes only
<> 144:ef7eb2e8f9f7 10 ; * which provides customers with programming information regarding the
<> 144:ef7eb2e8f9f7 11 ; * LPC products. This software is supplied "AS IS" without any warranties of
<> 144:ef7eb2e8f9f7 12 ; * any kind, and NXP Semiconductors and its licensor disclaim any and
<> 144:ef7eb2e8f9f7 13 ; * all warranties, express or implied, including all implied warranties of
<> 144:ef7eb2e8f9f7 14 ; * merchantability, fitness for a particular purpose and non-infringement of
<> 144:ef7eb2e8f9f7 15 ; * intellectual property rights. NXP Semiconductors assumes no responsibility
<> 144:ef7eb2e8f9f7 16 ; * or liability for the use of the software, conveys no license or rights under any
<> 144:ef7eb2e8f9f7 17 ; * patent, copyright, mask work right, or any other intellectual property rights in
<> 144:ef7eb2e8f9f7 18 ; * or to any products. NXP Semiconductors reserves the right to make changes
<> 144:ef7eb2e8f9f7 19 ; * in the software without notification. NXP Semiconductors also makes no
<> 144:ef7eb2e8f9f7 20 ; * representation or warranty that such application will be suitable for the
<> 144:ef7eb2e8f9f7 21 ; * specified use without further testing or modification.
<> 144:ef7eb2e8f9f7 22 ; *
<> 144:ef7eb2e8f9f7 23 ; * @par
<> 144:ef7eb2e8f9f7 24 ; * Permission to use, copy, modify, and distribute this software and its
<> 144:ef7eb2e8f9f7 25 ; * documentation is hereby granted, under NXP Semiconductors' and its
<> 144:ef7eb2e8f9f7 26 ; * licensor's relevant copyrights in the software, without fee, provided that it
<> 144:ef7eb2e8f9f7 27 ; * is used in conjunction with NXP Semiconductors microcontrollers. This
<> 144:ef7eb2e8f9f7 28 ; * copyright, permission, and disclaimer notice must appear in all copies of
<> 144:ef7eb2e8f9f7 29 ; * this code.
<> 144:ef7eb2e8f9f7 30 ; */
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 ; __initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX (IRAM1)
<> 144:ef7eb2e8f9f7 33 __initial_sp EQU 0x10092000 ; Top of first RAM segment for LPC43XX (IRAM2)
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 PRESERVE8
<> 144:ef7eb2e8f9f7 36 THUMB
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 41 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 Sign_Value EQU 0x5A5A5A5A
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 __Vectors DCD __initial_sp ; 0 Top of Stack
<> 144:ef7eb2e8f9f7 46 DCD Reset_Handler ; 1 Reset Handler
<> 144:ef7eb2e8f9f7 47 DCD NMI_Handler ; 2 NMI Handler
<> 144:ef7eb2e8f9f7 48 DCD HardFault_Handler ; 3 Hard Fault Handler
<> 144:ef7eb2e8f9f7 49 DCD MemManage_Handler ; 4 MPU Fault Handler
<> 144:ef7eb2e8f9f7 50 DCD BusFault_Handler ; 5 Bus Fault Handler
<> 144:ef7eb2e8f9f7 51 DCD UsageFault_Handler ; 6 Usage Fault Handler
<> 144:ef7eb2e8f9f7 52 DCD Sign_Value ; 7 Reserved
<> 144:ef7eb2e8f9f7 53 DCD UnHandled_Vector ; 8 Reserved
<> 144:ef7eb2e8f9f7 54 DCD UnHandled_Vector ; 9 Reserved
<> 144:ef7eb2e8f9f7 55 DCD UnHandled_Vector ; 10 Reserved
<> 144:ef7eb2e8f9f7 56 DCD SVC_Handler ; 11 SVCall Handler
<> 144:ef7eb2e8f9f7 57 DCD DebugMon_Handler ; 12 Debug Monitor Handler
<> 144:ef7eb2e8f9f7 58 DCD UnHandled_Vector ; 13 Reserved
<> 144:ef7eb2e8f9f7 59 DCD PendSV_Handler ; 14 PendSV Handler
<> 144:ef7eb2e8f9f7 60 DCD SysTick_Handler ; 15 SysTick Handler
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 ; External Interrupts
<> 144:ef7eb2e8f9f7 63 DCD DAC_IRQHandler ; 16 D/A Converter
<> 144:ef7eb2e8f9f7 64 DCD MX_CORE_IRQHandler ; 17 M0/M4 IRQ handler (LPC43XX ONLY)
<> 144:ef7eb2e8f9f7 65 DCD DMA_IRQHandler ; 18 General Purpose DMA
<> 144:ef7eb2e8f9f7 66 DCD UnHandled_Vector ; 19 Reserved
<> 144:ef7eb2e8f9f7 67 DCD FLASHEEPROM_IRQHandler ; 20 ORed flash bank A, flash bank B, EEPROM interrupts
<> 144:ef7eb2e8f9f7 68 DCD ETH_IRQHandler ; 21 Ethernet
<> 144:ef7eb2e8f9f7 69 DCD SDIO_IRQHandler ; 22 SD/MMC
<> 144:ef7eb2e8f9f7 70 DCD LCD_IRQHandler ; 23 LCD
<> 144:ef7eb2e8f9f7 71 DCD USB0_IRQHandler ; 24 USB0
<> 144:ef7eb2e8f9f7 72 DCD USB1_IRQHandler ; 25 USB1
<> 144:ef7eb2e8f9f7 73 DCD SCT_IRQHandler ; 26 State Configurable Timer
<> 144:ef7eb2e8f9f7 74 DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
<> 144:ef7eb2e8f9f7 75 DCD TIMER0_IRQHandler ; 28 Timer0
<> 144:ef7eb2e8f9f7 76 DCD TIMER1_IRQHandler ; 29 Timer1
<> 144:ef7eb2e8f9f7 77 DCD TIMER2_IRQHandler ; 30 Timer2
<> 144:ef7eb2e8f9f7 78 DCD TIMER3_IRQHandler ; 31 Timer3
<> 144:ef7eb2e8f9f7 79 DCD MCPWM_IRQHandler ; 32 Motor Control PWM
<> 144:ef7eb2e8f9f7 80 DCD ADC0_IRQHandler ; 33 A/D Converter 0
<> 144:ef7eb2e8f9f7 81 DCD I2C0_IRQHandler ; 34 I2C0
<> 144:ef7eb2e8f9f7 82 DCD I2C1_IRQHandler ; 35 I2C1
<> 144:ef7eb2e8f9f7 83 DCD SPI_IRQHandler ; 36 SPI (LPC43XX ONLY)
<> 144:ef7eb2e8f9f7 84 DCD ADC1_IRQHandler ; 37 A/D Converter 1
<> 144:ef7eb2e8f9f7 85 DCD SSP0_IRQHandler ; 38 SSP0
<> 144:ef7eb2e8f9f7 86 DCD SSP1_IRQHandler ; 39 SSP1
<> 144:ef7eb2e8f9f7 87 DCD UART0_IRQHandler ; 40 UART0
<> 144:ef7eb2e8f9f7 88 DCD UART1_IRQHandler ; 41 UART1
<> 144:ef7eb2e8f9f7 89 DCD UART2_IRQHandler ; 42 UART2
<> 144:ef7eb2e8f9f7 90 DCD UART3_IRQHandler ; 43 UART3
<> 144:ef7eb2e8f9f7 91 DCD I2S0_IRQHandler ; 44 I2S0
<> 144:ef7eb2e8f9f7 92 DCD I2S1_IRQHandler ; 45 I2S1
<> 144:ef7eb2e8f9f7 93 DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
<> 144:ef7eb2e8f9f7 94 DCD SGPIO_IRQHandler ; 47 SGPIO (LPC43XX ONLY)
<> 144:ef7eb2e8f9f7 95 DCD GPIO0_IRQHandler ; 48 GPIO0
<> 144:ef7eb2e8f9f7 96 DCD GPIO1_IRQHandler ; 49 GPIO1
<> 144:ef7eb2e8f9f7 97 DCD GPIO2_IRQHandler ; 50 GPIO2
<> 144:ef7eb2e8f9f7 98 DCD GPIO3_IRQHandler ; 51 GPIO3
<> 144:ef7eb2e8f9f7 99 DCD GPIO4_IRQHandler ; 52 GPIO4
<> 144:ef7eb2e8f9f7 100 DCD GPIO5_IRQHandler ; 53 GPIO5
<> 144:ef7eb2e8f9f7 101 DCD GPIO6_IRQHandler ; 54 GPIO6
<> 144:ef7eb2e8f9f7 102 DCD GPIO7_IRQHandler ; 55 GPIO7
<> 144:ef7eb2e8f9f7 103 DCD GINT0_IRQHandler ; 56 GINT0
<> 144:ef7eb2e8f9f7 104 DCD GINT1_IRQHandler ; 57 GINT1
<> 144:ef7eb2e8f9f7 105 DCD EVRT_IRQHandler ; 58 Event Router
<> 144:ef7eb2e8f9f7 106 DCD CAN1_IRQHandler ; 59 C_CAN1
<> 144:ef7eb2e8f9f7 107 DCD UnHandled_Vector ; 60 Reserved
<> 144:ef7eb2e8f9f7 108 DCD VADC_IRQHandler ; 61 VADC
<> 144:ef7eb2e8f9f7 109 DCD ATIMER_IRQHandler ; 62 ATIMER
<> 144:ef7eb2e8f9f7 110 DCD RTC_IRQHandler ; 63 RTC
<> 144:ef7eb2e8f9f7 111 DCD UnHandled_Vector ; 64 Reserved
<> 144:ef7eb2e8f9f7 112 DCD WDT_IRQHandler ; 65 WDT
<> 144:ef7eb2e8f9f7 113 DCD UnHandled_Vector ; 66 M0s
<> 144:ef7eb2e8f9f7 114 DCD CAN0_IRQHandler ; 67 C_CAN0
<> 144:ef7eb2e8f9f7 115 DCD QEI_IRQHandler ; 68 QEI
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 ; IF :LNOT::DEF:NO_CRP
<> 144:ef7eb2e8f9f7 119 ; AREA |.ARM.__at_0x02FC|, CODE, READONLY
<> 144:ef7eb2e8f9f7 120 ;CRP_Key DCD 0xFFFFFFFF
<> 144:ef7eb2e8f9f7 121 ; ENDIF
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 ; Reset Handler
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 129 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 130 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 131 IMPORT __main
<> 144:ef7eb2e8f9f7 132 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 133 BLX R0
<> 144:ef7eb2e8f9f7 134 LDR R0, =__main
<> 144:ef7eb2e8f9f7 135 BX R0
<> 144:ef7eb2e8f9f7 136 ENDP
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 142 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 143 B .
<> 144:ef7eb2e8f9f7 144 ENDP
<> 144:ef7eb2e8f9f7 145 HardFault_Handler\
<> 144:ef7eb2e8f9f7 146 PROC
<> 144:ef7eb2e8f9f7 147 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 148 B .
<> 144:ef7eb2e8f9f7 149 ENDP
<> 144:ef7eb2e8f9f7 150 MemManage_Handler\
<> 144:ef7eb2e8f9f7 151 PROC
<> 144:ef7eb2e8f9f7 152 EXPORT MemManage_Handler [WEAK]
<> 144:ef7eb2e8f9f7 153 B .
<> 144:ef7eb2e8f9f7 154 ENDP
<> 144:ef7eb2e8f9f7 155 BusFault_Handler\
<> 144:ef7eb2e8f9f7 156 PROC
<> 144:ef7eb2e8f9f7 157 EXPORT BusFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 158 B .
<> 144:ef7eb2e8f9f7 159 ENDP
<> 144:ef7eb2e8f9f7 160 UsageFault_Handler\
<> 144:ef7eb2e8f9f7 161 PROC
<> 144:ef7eb2e8f9f7 162 EXPORT UsageFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 163 B .
<> 144:ef7eb2e8f9f7 164 ENDP
<> 144:ef7eb2e8f9f7 165 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 166 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 167 B .
<> 144:ef7eb2e8f9f7 168 ENDP
<> 144:ef7eb2e8f9f7 169 DebugMon_Handler\
<> 144:ef7eb2e8f9f7 170 PROC
<> 144:ef7eb2e8f9f7 171 EXPORT DebugMon_Handler [WEAK]
<> 144:ef7eb2e8f9f7 172 B .
<> 144:ef7eb2e8f9f7 173 ENDP
<> 144:ef7eb2e8f9f7 174 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 175 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 176 B .
<> 144:ef7eb2e8f9f7 177 ENDP
<> 144:ef7eb2e8f9f7 178 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 179 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 180 B .
<> 144:ef7eb2e8f9f7 181 ENDP
<> 144:ef7eb2e8f9f7 182 UnHandled_Vector PROC
<> 144:ef7eb2e8f9f7 183 EXPORT UnHandled_Vector [WEAK]
<> 144:ef7eb2e8f9f7 184 B .
<> 144:ef7eb2e8f9f7 185 ENDP
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 Default_Handler PROC
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 EXPORT DAC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 190 EXPORT MX_CORE_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 191 EXPORT DMA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 192 EXPORT FLASHEEPROM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 193 EXPORT ETH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 194 EXPORT SDIO_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 195 EXPORT LCD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 196 EXPORT USB0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 197 EXPORT USB1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 198 EXPORT SCT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 199 EXPORT RIT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 200 EXPORT TIMER0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 201 EXPORT TIMER1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 202 EXPORT TIMER2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 203 EXPORT TIMER3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 204 EXPORT MCPWM_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 205 EXPORT ADC0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 206 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 207 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 208 EXPORT SPI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 209 EXPORT ADC1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 210 EXPORT SSP0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 211 EXPORT SSP1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 212 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 213 EXPORT UART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 214 EXPORT UART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 215 EXPORT UART3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 216 EXPORT I2S0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 217 EXPORT I2S1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 218 EXPORT SPIFI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 219 EXPORT SGPIO_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 220 EXPORT GPIO0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 221 EXPORT GPIO1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 222 EXPORT GPIO2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 223 EXPORT GPIO3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 224 EXPORT GPIO4_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 225 EXPORT GPIO5_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 226 EXPORT GPIO6_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 227 EXPORT GPIO7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 228 EXPORT GINT0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 229 EXPORT GINT1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 230 EXPORT EVRT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 231 EXPORT CAN1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 232 EXPORT VADC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 233 EXPORT ATIMER_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 234 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 235 EXPORT WDT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 236 EXPORT CAN0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 237 EXPORT QEI_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 DAC_IRQHandler
<> 144:ef7eb2e8f9f7 240 MX_CORE_IRQHandler
<> 144:ef7eb2e8f9f7 241 DMA_IRQHandler
<> 144:ef7eb2e8f9f7 242 FLASHEEPROM_IRQHandler
<> 144:ef7eb2e8f9f7 243 ETH_IRQHandler
<> 144:ef7eb2e8f9f7 244 SDIO_IRQHandler
<> 144:ef7eb2e8f9f7 245 LCD_IRQHandler
<> 144:ef7eb2e8f9f7 246 USB0_IRQHandler
<> 144:ef7eb2e8f9f7 247 USB1_IRQHandler
<> 144:ef7eb2e8f9f7 248 SCT_IRQHandler
<> 144:ef7eb2e8f9f7 249 RIT_IRQHandler
<> 144:ef7eb2e8f9f7 250 TIMER0_IRQHandler
<> 144:ef7eb2e8f9f7 251 TIMER1_IRQHandler
<> 144:ef7eb2e8f9f7 252 TIMER2_IRQHandler
<> 144:ef7eb2e8f9f7 253 TIMER3_IRQHandler
<> 144:ef7eb2e8f9f7 254 MCPWM_IRQHandler
<> 144:ef7eb2e8f9f7 255 ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 256 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 257 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 258 SPI_IRQHandler
<> 144:ef7eb2e8f9f7 259 ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 260 SSP0_IRQHandler
<> 144:ef7eb2e8f9f7 261 SSP1_IRQHandler
<> 144:ef7eb2e8f9f7 262 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 263 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 264 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 265 UART3_IRQHandler
<> 144:ef7eb2e8f9f7 266 I2S0_IRQHandler
<> 144:ef7eb2e8f9f7 267 I2S1_IRQHandler
<> 144:ef7eb2e8f9f7 268 SPIFI_IRQHandler
<> 144:ef7eb2e8f9f7 269 SGPIO_IRQHandler
<> 144:ef7eb2e8f9f7 270 GPIO0_IRQHandler
<> 144:ef7eb2e8f9f7 271 GPIO1_IRQHandler
<> 144:ef7eb2e8f9f7 272 GPIO2_IRQHandler
<> 144:ef7eb2e8f9f7 273 GPIO3_IRQHandler
<> 144:ef7eb2e8f9f7 274 GPIO4_IRQHandler
<> 144:ef7eb2e8f9f7 275 GPIO5_IRQHandler
<> 144:ef7eb2e8f9f7 276 GPIO6_IRQHandler
<> 144:ef7eb2e8f9f7 277 GPIO7_IRQHandler
<> 144:ef7eb2e8f9f7 278 GINT0_IRQHandler
<> 144:ef7eb2e8f9f7 279 GINT1_IRQHandler
<> 144:ef7eb2e8f9f7 280 EVRT_IRQHandler
<> 144:ef7eb2e8f9f7 281 CAN1_IRQHandler
<> 144:ef7eb2e8f9f7 282 VADC_IRQHandler
<> 144:ef7eb2e8f9f7 283 ATIMER_IRQHandler
<> 144:ef7eb2e8f9f7 284 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 285 WDT_IRQHandler
<> 144:ef7eb2e8f9f7 286 CAN0_IRQHandler
<> 144:ef7eb2e8f9f7 287 QEI_IRQHandler
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 B .
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 ENDP
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 ALIGN
<> 144:ef7eb2e8f9f7 294 END