mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/can_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
167:e84263d55307 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "can_api.h"
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 19 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include <math.h>
<> 144:ef7eb2e8f9f7 22 #include <string.h>
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #define CAN_NUM 2
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 /* Acceptance filter mode in AFMR register */
<> 144:ef7eb2e8f9f7 27 #define ACCF_OFF 0x01
<> 144:ef7eb2e8f9f7 28 #define ACCF_BYPASS 0x02
<> 144:ef7eb2e8f9f7 29 #define ACCF_ON 0x00
<> 144:ef7eb2e8f9f7 30 #define ACCF_FULLCAN 0x04
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 /* There are several bit timing calculators on the internet.
<> 144:ef7eb2e8f9f7 33 http://www.port.de/engl/canprod/sv_req_form.html
<> 144:ef7eb2e8f9f7 34 http://www.kvaser.com/can/index.htm
<> 144:ef7eb2e8f9f7 35 */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 static const PinMap PinMap_CAN_RD[] = {
<> 144:ef7eb2e8f9f7 38 {P0_0 , CAN_1, 1},
<> 144:ef7eb2e8f9f7 39 {P0_4 , CAN_2, 2},
<> 144:ef7eb2e8f9f7 40 {P0_21, CAN_1, 4},
<> 144:ef7eb2e8f9f7 41 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 42 };
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 static const PinMap PinMap_CAN_TD[] = {
<> 144:ef7eb2e8f9f7 45 {P0_1 , CAN_1, 1},
<> 144:ef7eb2e8f9f7 46 {P0_5 , CAN_2, 2},
<> 144:ef7eb2e8f9f7 47 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 48 };
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 // Type definition to hold a CAN message
<> 144:ef7eb2e8f9f7 51 struct CANMsg {
<> 144:ef7eb2e8f9f7 52 unsigned int reserved1 : 16;
<> 144:ef7eb2e8f9f7 53 unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
<> 144:ef7eb2e8f9f7 54 unsigned int reserved0 : 10;
<> 144:ef7eb2e8f9f7 55 unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
<> 144:ef7eb2e8f9f7 56 unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
<> 144:ef7eb2e8f9f7 57 unsigned int id; // CAN Message ID (11-bit or 29-bit)
<> 144:ef7eb2e8f9f7 58 unsigned char data[8]; // CAN Message Data Bytes 0-7
<> 144:ef7eb2e8f9f7 59 };
<> 144:ef7eb2e8f9f7 60 typedef struct CANMsg CANMsg;
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 static uint32_t can_irq_ids[CAN_NUM] = {0};
<> 144:ef7eb2e8f9f7 63 static can_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 static uint32_t can_disable(can_t *obj) {
<> 144:ef7eb2e8f9f7 66 uint32_t sm = obj->dev->MOD;
<> 144:ef7eb2e8f9f7 67 obj->dev->MOD |= 1;
<> 144:ef7eb2e8f9f7 68 return sm;
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 static inline void can_enable(can_t *obj) {
<> 144:ef7eb2e8f9f7 72 if (obj->dev->MOD & 1) {
<> 144:ef7eb2e8f9f7 73 obj->dev->MOD &= ~(1);
<> 144:ef7eb2e8f9f7 74 }
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 int can_mode(can_t *obj, CanMode mode)
<> 144:ef7eb2e8f9f7 78 {
<> 144:ef7eb2e8f9f7 79 return 0; // not implemented
<> 144:ef7eb2e8f9f7 80 }
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
<> 144:ef7eb2e8f9f7 83 return 0; // not implemented
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 static inline void can_irq(uint32_t icr, uint32_t index) {
<> 144:ef7eb2e8f9f7 87 uint32_t i;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 for(i = 0; i < 8; i++)
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91 if((can_irq_ids[index] != 0) && (icr & (1 << i)))
<> 144:ef7eb2e8f9f7 92 {
<> 144:ef7eb2e8f9f7 93 switch (i) {
<> 144:ef7eb2e8f9f7 94 case 0: irq_handler(can_irq_ids[index], IRQ_RX); break;
<> 144:ef7eb2e8f9f7 95 case 1: irq_handler(can_irq_ids[index], IRQ_TX); break;
<> 144:ef7eb2e8f9f7 96 case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break;
<> 144:ef7eb2e8f9f7 97 case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break;
<> 144:ef7eb2e8f9f7 98 case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break;
<> 144:ef7eb2e8f9f7 99 case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break;
<> 144:ef7eb2e8f9f7 100 case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break;
<> 144:ef7eb2e8f9f7 101 case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break;
<> 144:ef7eb2e8f9f7 102 case 8: irq_handler(can_irq_ids[index], IRQ_READY); break;
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104 }
<> 144:ef7eb2e8f9f7 105 }
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 // Have to check that the CAN block is active before reading the Interrupt
<> 144:ef7eb2e8f9f7 109 // Control Register, or the mbed hangs
<> 144:ef7eb2e8f9f7 110 void can_irq_n() {
<> 144:ef7eb2e8f9f7 111 uint32_t icr;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 if(LPC_SC->PCONP & (1 << 13)) {
<> 144:ef7eb2e8f9f7 114 icr = LPC_CAN1->ICR & 0x1FF;
<> 144:ef7eb2e8f9f7 115 can_irq(icr, 0);
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 if(LPC_SC->PCONP & (1 << 14)) {
<> 144:ef7eb2e8f9f7 119 icr = LPC_CAN2->ICR & 0x1FF;
<> 144:ef7eb2e8f9f7 120 can_irq(icr, 1);
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 // Register CAN object's irq handler
<> 144:ef7eb2e8f9f7 125 void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 126 irq_handler = handler;
<> 144:ef7eb2e8f9f7 127 can_irq_ids[obj->index] = id;
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 // Unregister CAN object's irq handler
<> 144:ef7eb2e8f9f7 131 void can_irq_free(can_t *obj) {
<> 144:ef7eb2e8f9f7 132 obj->dev->IER &= ~(1);
<> 144:ef7eb2e8f9f7 133 can_irq_ids[obj->index] = 0;
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) {
<> 144:ef7eb2e8f9f7 136 NVIC_DisableIRQ(CAN_IRQn);
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 // Clear or set a irq
<> 144:ef7eb2e8f9f7 141 void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
<> 144:ef7eb2e8f9f7 142 uint32_t ier;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 switch (type) {
<> 144:ef7eb2e8f9f7 145 case IRQ_RX: ier = (1 << 0); break;
<> 144:ef7eb2e8f9f7 146 case IRQ_TX: ier = (1 << 1); break;
<> 144:ef7eb2e8f9f7 147 case IRQ_ERROR: ier = (1 << 2); break;
<> 144:ef7eb2e8f9f7 148 case IRQ_OVERRUN: ier = (1 << 3); break;
<> 144:ef7eb2e8f9f7 149 case IRQ_WAKEUP: ier = (1 << 4); break;
<> 144:ef7eb2e8f9f7 150 case IRQ_PASSIVE: ier = (1 << 5); break;
<> 144:ef7eb2e8f9f7 151 case IRQ_ARB: ier = (1 << 6); break;
<> 144:ef7eb2e8f9f7 152 case IRQ_BUS: ier = (1 << 7); break;
<> 144:ef7eb2e8f9f7 153 case IRQ_READY: ier = (1 << 8); break;
<> 144:ef7eb2e8f9f7 154 default: return;
<> 144:ef7eb2e8f9f7 155 }
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 obj->dev->MOD |= 1;
<> 144:ef7eb2e8f9f7 158 if(enable == 0) {
<> 144:ef7eb2e8f9f7 159 obj->dev->IER &= ~ier;
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161 else {
<> 144:ef7eb2e8f9f7 162 obj->dev->IER |= ier;
<> 144:ef7eb2e8f9f7 163 }
<> 144:ef7eb2e8f9f7 164 obj->dev->MOD &= ~(1);
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 // Enable NVIC if at least 1 interrupt is active
<> 144:ef7eb2e8f9f7 167 if(((LPC_SC->PCONP & (1 << 13)) && LPC_CAN1->IER) || ((LPC_SC->PCONP & (1 << 14)) && LPC_CAN2->IER)) {
<> 144:ef7eb2e8f9f7 168 NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
<> 144:ef7eb2e8f9f7 169 NVIC_EnableIRQ(CAN_IRQn);
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171 else {
<> 144:ef7eb2e8f9f7 172 NVIC_DisableIRQ(CAN_IRQn);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 // This table has the sampling points as close to 75% as possible. The first
<> 144:ef7eb2e8f9f7 177 // value is TSEG1, the second TSEG2.
<> 144:ef7eb2e8f9f7 178 static const int timing_pts[23][2] = {
<> 144:ef7eb2e8f9f7 179 {0x0, 0x0}, // 2, 50%
<> 144:ef7eb2e8f9f7 180 {0x1, 0x0}, // 3, 67%
<> 144:ef7eb2e8f9f7 181 {0x2, 0x0}, // 4, 75%
<> 144:ef7eb2e8f9f7 182 {0x3, 0x0}, // 5, 80%
<> 144:ef7eb2e8f9f7 183 {0x3, 0x1}, // 6, 67%
<> 144:ef7eb2e8f9f7 184 {0x4, 0x1}, // 7, 71%
<> 144:ef7eb2e8f9f7 185 {0x5, 0x1}, // 8, 75%
<> 144:ef7eb2e8f9f7 186 {0x6, 0x1}, // 9, 78%
<> 144:ef7eb2e8f9f7 187 {0x6, 0x2}, // 10, 70%
<> 144:ef7eb2e8f9f7 188 {0x7, 0x2}, // 11, 73%
<> 144:ef7eb2e8f9f7 189 {0x8, 0x2}, // 12, 75%
<> 144:ef7eb2e8f9f7 190 {0x9, 0x2}, // 13, 77%
<> 144:ef7eb2e8f9f7 191 {0x9, 0x3}, // 14, 71%
<> 144:ef7eb2e8f9f7 192 {0xA, 0x3}, // 15, 73%
<> 144:ef7eb2e8f9f7 193 {0xB, 0x3}, // 16, 75%
<> 144:ef7eb2e8f9f7 194 {0xC, 0x3}, // 17, 76%
<> 144:ef7eb2e8f9f7 195 {0xD, 0x3}, // 18, 78%
<> 144:ef7eb2e8f9f7 196 {0xD, 0x4}, // 19, 74%
<> 144:ef7eb2e8f9f7 197 {0xE, 0x4}, // 20, 75%
<> 144:ef7eb2e8f9f7 198 {0xF, 0x4}, // 21, 76%
<> 144:ef7eb2e8f9f7 199 {0xF, 0x5}, // 22, 73%
<> 144:ef7eb2e8f9f7 200 {0xF, 0x6}, // 23, 70%
<> 144:ef7eb2e8f9f7 201 {0xF, 0x7}, // 24, 67%
<> 144:ef7eb2e8f9f7 202 };
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 static unsigned int can_speed(unsigned int pclk, unsigned int cclk, unsigned char psjw) {
<> 144:ef7eb2e8f9f7 205 uint32_t btr;
<> 144:ef7eb2e8f9f7 206 uint16_t brp = 0;
<> 144:ef7eb2e8f9f7 207 uint32_t calcbit;
<> 144:ef7eb2e8f9f7 208 uint32_t bitwidth;
<> 144:ef7eb2e8f9f7 209 int hit = 0;
<> 144:ef7eb2e8f9f7 210 int bits;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 bitwidth = (pclk / cclk);
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 brp = bitwidth / 0x18;
<> 144:ef7eb2e8f9f7 215 while ((!hit) && (brp < bitwidth / 4)) {
<> 144:ef7eb2e8f9f7 216 brp++;
<> 144:ef7eb2e8f9f7 217 for (bits = 22; bits > 0; bits--) {
<> 144:ef7eb2e8f9f7 218 calcbit = (bits + 3) * (brp + 1);
<> 144:ef7eb2e8f9f7 219 if (calcbit == bitwidth) {
<> 144:ef7eb2e8f9f7 220 hit = 1;
<> 144:ef7eb2e8f9f7 221 break;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 }
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 if (hit) {
<> 144:ef7eb2e8f9f7 227 btr = ((timing_pts[bits][1] << 20) & 0x00700000)
<> 144:ef7eb2e8f9f7 228 | ((timing_pts[bits][0] << 16) & 0x000F0000)
<> 144:ef7eb2e8f9f7 229 | ((psjw << 14) & 0x0000C000)
<> 144:ef7eb2e8f9f7 230 | ((brp << 0) & 0x000003FF);
<> 144:ef7eb2e8f9f7 231 } else {
<> 144:ef7eb2e8f9f7 232 btr = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 return btr;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
AnnaBridge 167:e84263d55307 239 void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) {
<> 144:ef7eb2e8f9f7 240 CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
<> 144:ef7eb2e8f9f7 241 CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
<> 144:ef7eb2e8f9f7 242 obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
<> 144:ef7eb2e8f9f7 243 MBED_ASSERT((int)obj->dev != NC);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 switch ((int)obj->dev) {
<> 144:ef7eb2e8f9f7 246 case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
<> 144:ef7eb2e8f9f7 247 case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 pinmap_pinout(rd, PinMap_CAN_RD);
<> 144:ef7eb2e8f9f7 251 pinmap_pinout(td, PinMap_CAN_TD);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 switch ((int)obj->dev) {
<> 144:ef7eb2e8f9f7 254 case CAN_1: obj->index = 0; break;
<> 144:ef7eb2e8f9f7 255 case CAN_2: obj->index = 1; break;
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 can_reset(obj);
<> 144:ef7eb2e8f9f7 259 obj->dev->IER = 0; // Disable Interrupts
AnnaBridge 167:e84263d55307 260 can_frequency(obj, hz);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
AnnaBridge 167:e84263d55307 265 void can_init(can_t *obj, PinName rd, PinName td) {
AnnaBridge 167:e84263d55307 266 can_init_freq(obj, rd, td, 100000);
AnnaBridge 167:e84263d55307 267 }
AnnaBridge 167:e84263d55307 268
<> 144:ef7eb2e8f9f7 269 void can_free(can_t *obj) {
<> 144:ef7eb2e8f9f7 270 switch ((int)obj->dev) {
<> 144:ef7eb2e8f9f7 271 case CAN_1: LPC_SC->PCONP &= ~(1 << 13); break;
<> 144:ef7eb2e8f9f7 272 case CAN_2: LPC_SC->PCONP &= ~(1 << 14); break;
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 int can_frequency(can_t *obj, int f) {
<> 144:ef7eb2e8f9f7 277 int pclk = PeripheralClock;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 int btr = can_speed(pclk, (unsigned int)f, 1);
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 if (btr > 0) {
<> 144:ef7eb2e8f9f7 282 uint32_t modmask = can_disable(obj);
<> 144:ef7eb2e8f9f7 283 obj->dev->BTR = btr;
<> 144:ef7eb2e8f9f7 284 obj->dev->MOD = modmask;
<> 144:ef7eb2e8f9f7 285 return 1;
<> 144:ef7eb2e8f9f7 286 } else {
<> 144:ef7eb2e8f9f7 287 return 0;
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 int can_write(can_t *obj, CAN_Message msg, int cc) {
<> 144:ef7eb2e8f9f7 292 unsigned int CANStatus;
<> 144:ef7eb2e8f9f7 293 CANMsg m;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 can_enable(obj);
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 m.id = msg.id ;
<> 144:ef7eb2e8f9f7 298 m.dlc = msg.len & 0xF;
<> 144:ef7eb2e8f9f7 299 m.rtr = msg.type;
<> 144:ef7eb2e8f9f7 300 m.type = msg.format;
<> 144:ef7eb2e8f9f7 301 memcpy(m.data, msg.data, msg.len);
<> 144:ef7eb2e8f9f7 302 const unsigned int *buf = (const unsigned int *)&m;
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 CANStatus = obj->dev->SR;
<> 144:ef7eb2e8f9f7 305 if (CANStatus & 0x00000004) {
<> 144:ef7eb2e8f9f7 306 obj->dev->TFI1 = buf[0] & 0xC00F0000;
<> 144:ef7eb2e8f9f7 307 obj->dev->TID1 = buf[1];
<> 144:ef7eb2e8f9f7 308 obj->dev->TDA1 = buf[2];
<> 144:ef7eb2e8f9f7 309 obj->dev->TDB1 = buf[3];
<> 144:ef7eb2e8f9f7 310 if(cc) {
<> 144:ef7eb2e8f9f7 311 obj->dev->CMR = 0x30;
<> 144:ef7eb2e8f9f7 312 } else {
<> 144:ef7eb2e8f9f7 313 obj->dev->CMR = 0x21;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 return 1;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 } else if (CANStatus & 0x00000400) {
<> 144:ef7eb2e8f9f7 318 obj->dev->TFI2 = buf[0] & 0xC00F0000;
<> 144:ef7eb2e8f9f7 319 obj->dev->TID2 = buf[1];
<> 144:ef7eb2e8f9f7 320 obj->dev->TDA2 = buf[2];
<> 144:ef7eb2e8f9f7 321 obj->dev->TDB2 = buf[3];
<> 144:ef7eb2e8f9f7 322 if (cc) {
<> 144:ef7eb2e8f9f7 323 obj->dev->CMR = 0x50;
<> 144:ef7eb2e8f9f7 324 } else {
<> 144:ef7eb2e8f9f7 325 obj->dev->CMR = 0x41;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327 return 1;
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 } else if (CANStatus & 0x00040000) {
<> 144:ef7eb2e8f9f7 330 obj->dev->TFI3 = buf[0] & 0xC00F0000;
<> 144:ef7eb2e8f9f7 331 obj->dev->TID3 = buf[1];
<> 144:ef7eb2e8f9f7 332 obj->dev->TDA3 = buf[2];
<> 144:ef7eb2e8f9f7 333 obj->dev->TDB3 = buf[3];
<> 144:ef7eb2e8f9f7 334 if (cc) {
<> 144:ef7eb2e8f9f7 335 obj->dev->CMR = 0x90;
<> 144:ef7eb2e8f9f7 336 } else {
<> 144:ef7eb2e8f9f7 337 obj->dev->CMR = 0x81;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 return 1;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 return 0;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 int can_read(can_t *obj, CAN_Message *msg, int handle) {
<> 144:ef7eb2e8f9f7 346 CANMsg x;
<> 144:ef7eb2e8f9f7 347 unsigned int *i = (unsigned int *)&x;
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 can_enable(obj);
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 if (obj->dev->GSR & 0x1) {
<> 144:ef7eb2e8f9f7 352 *i++ = obj->dev->RFS; // Frame
<> 144:ef7eb2e8f9f7 353 *i++ = obj->dev->RID; // ID
<> 144:ef7eb2e8f9f7 354 *i++ = obj->dev->RDA; // Data A
<> 144:ef7eb2e8f9f7 355 *i++ = obj->dev->RDB; // Data B
<> 144:ef7eb2e8f9f7 356 obj->dev->CMR = 0x04; // release receive buffer
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 msg->id = x.id;
<> 144:ef7eb2e8f9f7 359 msg->len = x.dlc;
<> 144:ef7eb2e8f9f7 360 msg->format = (x.type)? CANExtended : CANStandard;
<> 144:ef7eb2e8f9f7 361 msg->type = (x.rtr)? CANRemote: CANData;
<> 144:ef7eb2e8f9f7 362 memcpy(msg->data,x.data,x.dlc);
<> 144:ef7eb2e8f9f7 363 return 1;
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 return 0;
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 void can_reset(can_t *obj) {
<> 144:ef7eb2e8f9f7 370 can_disable(obj);
<> 144:ef7eb2e8f9f7 371 obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 unsigned char can_rderror(can_t *obj) {
<> 144:ef7eb2e8f9f7 375 return (obj->dev->GSR >> 16) & 0xFF;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 unsigned char can_tderror(can_t *obj) {
<> 144:ef7eb2e8f9f7 379 return (obj->dev->GSR >> 24) & 0xFF;
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 void can_monitor(can_t *obj, int silent) {
<> 144:ef7eb2e8f9f7 383 uint32_t mod_mask = can_disable(obj);
<> 144:ef7eb2e8f9f7 384 if (silent) {
<> 144:ef7eb2e8f9f7 385 obj->dev->MOD |= (1 << 1);
<> 144:ef7eb2e8f9f7 386 } else {
<> 144:ef7eb2e8f9f7 387 obj->dev->MOD &= ~(1 << 1);
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 if (!(mod_mask & 1)) {
<> 144:ef7eb2e8f9f7 390 can_enable(obj);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392 }