mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC176X/serial_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 // math.h required for floating point operations for baud rate calculation
<> 144:ef7eb2e8f9f7 17 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 18 #include <math.h>
<> 144:ef7eb2e8f9f7 19 #include <string.h>
<> 144:ef7eb2e8f9f7 20 #include <stdlib.h>
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 23 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 24 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 25 #include "gpio_api.h"
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 /******************************************************************************
<> 144:ef7eb2e8f9f7 28 * INITIALIZATION
<> 144:ef7eb2e8f9f7 29 ******************************************************************************/
<> 144:ef7eb2e8f9f7 30 #define UART_NUM 4
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 static const PinMap PinMap_UART_TX[] = {
<> 144:ef7eb2e8f9f7 33 {P0_0, UART_3, 2},
<> 144:ef7eb2e8f9f7 34 {P0_2, UART_0, 1},
<> 144:ef7eb2e8f9f7 35 {P0_10, UART_2, 1},
<> 144:ef7eb2e8f9f7 36 {P0_15, UART_1, 1},
<> 144:ef7eb2e8f9f7 37 {P0_25, UART_3, 3},
<> 144:ef7eb2e8f9f7 38 {P2_0 , UART_1, 2},
<> 144:ef7eb2e8f9f7 39 {P2_8 , UART_2, 2},
<> 144:ef7eb2e8f9f7 40 {P4_28, UART_3, 3},
<> 144:ef7eb2e8f9f7 41 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 42 };
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 static const PinMap PinMap_UART_RX[] = {
<> 144:ef7eb2e8f9f7 45 {P0_1 , UART_3, 2},
<> 144:ef7eb2e8f9f7 46 {P0_3 , UART_0, 1},
<> 144:ef7eb2e8f9f7 47 {P0_11, UART_2, 1},
<> 144:ef7eb2e8f9f7 48 {P0_16, UART_1, 1},
<> 144:ef7eb2e8f9f7 49 {P0_26, UART_3, 3},
<> 144:ef7eb2e8f9f7 50 {P2_1 , UART_1, 2},
<> 144:ef7eb2e8f9f7 51 {P2_9 , UART_2, 2},
<> 144:ef7eb2e8f9f7 52 {P4_29, UART_3, 3},
<> 144:ef7eb2e8f9f7 53 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 54 };
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 static const PinMap PinMap_UART_RTS[] = {
<> 144:ef7eb2e8f9f7 57 {P0_22, UART_1, 1},
<> 144:ef7eb2e8f9f7 58 {P2_7, UART_1, 2},
<> 144:ef7eb2e8f9f7 59 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 60 };
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 static const PinMap PinMap_UART_CTS[] = {
<> 144:ef7eb2e8f9f7 63 {P0_17, UART_1, 1},
<> 144:ef7eb2e8f9f7 64 {P2_2, UART_1, 2},
<> 144:ef7eb2e8f9f7 65 {NC, NC, 0}
<> 144:ef7eb2e8f9f7 66 };
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #define UART_MCR_RTSEN_MASK (1 << 6)
<> 144:ef7eb2e8f9f7 69 #define UART_MCR_CTSEN_MASK (1 << 7)
<> 144:ef7eb2e8f9f7 70 #define UART_MCR_FLOWCTRL_MASK (UART_MCR_RTSEN_MASK | UART_MCR_CTSEN_MASK)
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 static uart_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 int stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 75 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 struct serial_global_data_s {
<> 144:ef7eb2e8f9f7 78 uint32_t serial_irq_id;
<> 144:ef7eb2e8f9f7 79 gpio_t sw_rts, sw_cts;
<> 144:ef7eb2e8f9f7 80 uint8_t count, rx_irq_set_flow, rx_irq_set_api;
<> 144:ef7eb2e8f9f7 81 };
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 static struct serial_global_data_s uart_data[UART_NUM];
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 void serial_init(serial_t *obj, PinName tx, PinName rx) {
<> 144:ef7eb2e8f9f7 86 int is_stdio_uart = 0;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 // determine the UART to use
<> 144:ef7eb2e8f9f7 89 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 90 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 91 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
<> 144:ef7eb2e8f9f7 92 MBED_ASSERT((int)uart != NC);
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 obj->uart = (LPC_UART_TypeDef *)uart;
<> 144:ef7eb2e8f9f7 95 // enable power
<> 144:ef7eb2e8f9f7 96 switch (uart) {
<> 144:ef7eb2e8f9f7 97 case UART_0: LPC_SC->PCONP |= 1 << 3; break;
<> 144:ef7eb2e8f9f7 98 case UART_1: LPC_SC->PCONP |= 1 << 4; break;
<> 144:ef7eb2e8f9f7 99 case UART_2: LPC_SC->PCONP |= 1 << 24; break;
<> 144:ef7eb2e8f9f7 100 case UART_3: LPC_SC->PCONP |= 1 << 25; break;
<> 144:ef7eb2e8f9f7 101 }
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // enable fifos and default rx trigger level
<> 144:ef7eb2e8f9f7 104 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
<> 144:ef7eb2e8f9f7 105 | 0 << 1 // Rx Fifo Reset
<> 144:ef7eb2e8f9f7 106 | 0 << 2 // Tx Fifo Reset
<> 144:ef7eb2e8f9f7 107 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // disable irqs
<> 144:ef7eb2e8f9f7 110 obj->uart->IER = 0 << 0 // Rx Data available irq enable
<> 144:ef7eb2e8f9f7 111 | 0 << 1 // Tx Fifo empty irq enable
<> 144:ef7eb2e8f9f7 112 | 0 << 2; // Rx Line Status irq enable
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 // set default baud rate and format
<> 144:ef7eb2e8f9f7 115 serial_baud (obj, 9600);
<> 144:ef7eb2e8f9f7 116 serial_format(obj, 8, ParityNone, 1);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 // pinout the chosen uart
<> 144:ef7eb2e8f9f7 119 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 120 pinmap_pinout(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 // set rx/tx pins in PullUp mode
<> 144:ef7eb2e8f9f7 123 if (tx != NC) {
<> 144:ef7eb2e8f9f7 124 pin_mode(tx, PullUp);
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126 if (rx != NC) {
<> 144:ef7eb2e8f9f7 127 pin_mode(rx, PullUp);
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 switch (uart) {
<> 144:ef7eb2e8f9f7 131 case UART_0: obj->index = 0; break;
<> 144:ef7eb2e8f9f7 132 case UART_1: obj->index = 1; break;
<> 144:ef7eb2e8f9f7 133 case UART_2: obj->index = 2; break;
<> 144:ef7eb2e8f9f7 134 case UART_3: obj->index = 3; break;
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136 uart_data[obj->index].sw_rts.pin = NC;
<> 144:ef7eb2e8f9f7 137 uart_data[obj->index].sw_cts.pin = NC;
<> 144:ef7eb2e8f9f7 138 serial_set_flow_control(obj, FlowControlNone, NC, NC);
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 if (is_stdio_uart) {
<> 144:ef7eb2e8f9f7 143 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 144 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 void serial_free(serial_t *obj) {
<> 144:ef7eb2e8f9f7 149 uart_data[obj->index].serial_irq_id = 0;
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 // serial_baud
<> 144:ef7eb2e8f9f7 153 // set the baud rate, taking in to account the current SystemFrequency
<> 144:ef7eb2e8f9f7 154 void serial_baud(serial_t *obj, int baudrate) {
<> 144:ef7eb2e8f9f7 155 MBED_ASSERT((int)obj->uart <= UART_3);
<> 144:ef7eb2e8f9f7 156 // The LPC2300 and LPC1700 have a divider and a fractional divider to control the
<> 144:ef7eb2e8f9f7 157 // baud rate. The formula is:
<> 144:ef7eb2e8f9f7 158 //
<> 144:ef7eb2e8f9f7 159 // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
<> 144:ef7eb2e8f9f7 160 // where:
<> 144:ef7eb2e8f9f7 161 // 1 < MulVal <= 15
<> 144:ef7eb2e8f9f7 162 // 0 <= DivAddVal < 14
<> 144:ef7eb2e8f9f7 163 // DivAddVal < MulVal
<> 144:ef7eb2e8f9f7 164 //
<> 144:ef7eb2e8f9f7 165 // set pclk to /1
<> 144:ef7eb2e8f9f7 166 switch ((int)obj->uart) {
<> 144:ef7eb2e8f9f7 167 case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 << 6); LPC_SC->PCLKSEL0 |= (0x1 << 6); break;
<> 144:ef7eb2e8f9f7 168 case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 << 8); LPC_SC->PCLKSEL0 |= (0x1 << 8); break;
<> 144:ef7eb2e8f9f7 169 case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break;
<> 144:ef7eb2e8f9f7 170 case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break;
<> 144:ef7eb2e8f9f7 171 default: break;
<> 144:ef7eb2e8f9f7 172 }
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 uint32_t PCLK = SystemCoreClock;
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 // First we check to see if the basic divide with no DivAddVal/MulVal
<> 144:ef7eb2e8f9f7 177 // ratio gives us an integer result. If it does, we set DivAddVal = 0,
<> 144:ef7eb2e8f9f7 178 // MulVal = 1. Otherwise, we search the valid ratio value range to find
<> 144:ef7eb2e8f9f7 179 // the closest match. This could be more elegant, using search methods
<> 144:ef7eb2e8f9f7 180 // and/or lookup tables, but the brute force method is not that much
<> 144:ef7eb2e8f9f7 181 // slower, and is more maintainable.
<> 144:ef7eb2e8f9f7 182 uint16_t DL = PCLK / (16 * baudrate);
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 uint8_t DivAddVal = 0;
<> 144:ef7eb2e8f9f7 185 uint8_t MulVal = 1;
<> 144:ef7eb2e8f9f7 186 int hit = 0;
<> 144:ef7eb2e8f9f7 187 uint16_t dlv;
<> 144:ef7eb2e8f9f7 188 uint8_t mv, dav;
<> 144:ef7eb2e8f9f7 189 if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
<> 144:ef7eb2e8f9f7 190 int err_best = baudrate, b;
<> 144:ef7eb2e8f9f7 191 for (mv = 1; mv < 16 && !hit; mv++)
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 for (dav = 0; dav < mv; dav++)
<> 144:ef7eb2e8f9f7 194 {
<> 144:ef7eb2e8f9f7 195 // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
<> 144:ef7eb2e8f9f7 196 // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
<> 144:ef7eb2e8f9f7 197 // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
<> 144:ef7eb2e8f9f7 198 // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
<> 144:ef7eb2e8f9f7 199 // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
<> 144:ef7eb2e8f9f7 202 dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
<> 144:ef7eb2e8f9f7 203 else // 2 bits headroom, use more precision
<> 144:ef7eb2e8f9f7 204 dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
<> 144:ef7eb2e8f9f7 207 if (dlv == 0)
<> 144:ef7eb2e8f9f7 208 dlv = 1;
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 // datasheet says if dav > 0 then DL must be >= 2
<> 144:ef7eb2e8f9f7 211 if ((dav > 0) && (dlv < 2))
<> 144:ef7eb2e8f9f7 212 dlv = 2;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 // integer rearrangement of the baudrate equation (with rounding)
<> 144:ef7eb2e8f9f7 215 b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 // check to see how we went
<> 144:ef7eb2e8f9f7 218 b = abs(b - baudrate);
<> 144:ef7eb2e8f9f7 219 if (b < err_best)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 err_best = b;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 DL = dlv;
<> 144:ef7eb2e8f9f7 224 MulVal = mv;
<> 144:ef7eb2e8f9f7 225 DivAddVal = dav;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 if (b == baudrate)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 hit = 1;
<> 144:ef7eb2e8f9f7 230 break;
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 // set LCR[DLAB] to enable writing to divider registers
<> 144:ef7eb2e8f9f7 238 obj->uart->LCR |= (1 << 7);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 // set divider values
<> 144:ef7eb2e8f9f7 241 obj->uart->DLM = (DL >> 8) & 0xFF;
<> 144:ef7eb2e8f9f7 242 obj->uart->DLL = (DL >> 0) & 0xFF;
<> 144:ef7eb2e8f9f7 243 obj->uart->FDR = (uint32_t) DivAddVal << 0
<> 144:ef7eb2e8f9f7 244 | (uint32_t) MulVal << 4;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 // clear LCR[DLAB]
<> 144:ef7eb2e8f9f7 247 obj->uart->LCR &= ~(1 << 7);
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
<> 144:ef7eb2e8f9f7 251 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
<> 144:ef7eb2e8f9f7 252 MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
<> 144:ef7eb2e8f9f7 253 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
<> 144:ef7eb2e8f9f7 254 (parity == ParityForced1) || (parity == ParityForced0));
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 stop_bits -= 1;
<> 144:ef7eb2e8f9f7 257 data_bits -= 5;
<> 144:ef7eb2e8f9f7 258
AnnaBridge 188:bcfe06ba3d64 259 int parity_enable = 0, parity_select = 0;
<> 144:ef7eb2e8f9f7 260 switch (parity) {
<> 144:ef7eb2e8f9f7 261 case ParityNone: parity_enable = 0; parity_select = 0; break;
<> 144:ef7eb2e8f9f7 262 case ParityOdd : parity_enable = 1; parity_select = 0; break;
<> 144:ef7eb2e8f9f7 263 case ParityEven: parity_enable = 1; parity_select = 1; break;
<> 144:ef7eb2e8f9f7 264 case ParityForced1: parity_enable = 1; parity_select = 2; break;
<> 144:ef7eb2e8f9f7 265 case ParityForced0: parity_enable = 1; parity_select = 3; break;
<> 144:ef7eb2e8f9f7 266 default:
<> 144:ef7eb2e8f9f7 267 break;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 obj->uart->LCR = data_bits << 0
<> 144:ef7eb2e8f9f7 271 | stop_bits << 2
<> 144:ef7eb2e8f9f7 272 | parity_enable << 3
<> 144:ef7eb2e8f9f7 273 | parity_select << 4;
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /******************************************************************************
<> 144:ef7eb2e8f9f7 277 * INTERRUPTS HANDLING
<> 144:ef7eb2e8f9f7 278 ******************************************************************************/
<> 144:ef7eb2e8f9f7 279 static inline void uart_irq(uint32_t iir, uint32_t index, LPC_UART_TypeDef *puart) {
<> 144:ef7eb2e8f9f7 280 // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
<> 144:ef7eb2e8f9f7 281 SerialIrq irq_type;
<> 144:ef7eb2e8f9f7 282 switch (iir) {
<> 144:ef7eb2e8f9f7 283 case 1: irq_type = TxIrq; break;
<> 144:ef7eb2e8f9f7 284 case 2: irq_type = RxIrq; break;
<> 144:ef7eb2e8f9f7 285 default: return;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
<> 144:ef7eb2e8f9f7 288 gpio_write(&uart_data[index].sw_rts, 1);
<> 144:ef7eb2e8f9f7 289 // Disable interrupt if it wasn't enabled by other part of the application
<> 144:ef7eb2e8f9f7 290 if (!uart_data[index].rx_irq_set_api)
<> 144:ef7eb2e8f9f7 291 puart->IER &= ~(1 << RxIrq);
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293 if (uart_data[index].serial_irq_id != 0)
<> 144:ef7eb2e8f9f7 294 if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
<> 144:ef7eb2e8f9f7 295 irq_handler(uart_data[index].serial_irq_id, irq_type);
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0, (LPC_UART_TypeDef*)LPC_UART0);}
<> 144:ef7eb2e8f9f7 299 void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);}
<> 144:ef7eb2e8f9f7 300 void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);}
<> 144:ef7eb2e8f9f7 301 void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);}
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 304 irq_handler = handler;
<> 144:ef7eb2e8f9f7 305 uart_data[obj->index].serial_irq_id = id;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
<> 144:ef7eb2e8f9f7 309 IRQn_Type irq_n = (IRQn_Type)0;
<> 144:ef7eb2e8f9f7 310 uint32_t vector = 0;
<> 144:ef7eb2e8f9f7 311 switch ((int)obj->uart) {
<> 144:ef7eb2e8f9f7 312 case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
<> 144:ef7eb2e8f9f7 313 case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
<> 144:ef7eb2e8f9f7 314 case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
<> 144:ef7eb2e8f9f7 315 case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 if (enable) {
<> 144:ef7eb2e8f9f7 319 obj->uart->IER |= 1 << irq;
<> 144:ef7eb2e8f9f7 320 NVIC_SetVector(irq_n, vector);
<> 144:ef7eb2e8f9f7 321 NVIC_EnableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 322 } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
<> 144:ef7eb2e8f9f7 323 int all_disabled = 0;
<> 144:ef7eb2e8f9f7 324 SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
<> 144:ef7eb2e8f9f7 325 obj->uart->IER &= ~(1 << irq);
<> 144:ef7eb2e8f9f7 326 all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
<> 144:ef7eb2e8f9f7 327 if (all_disabled)
<> 144:ef7eb2e8f9f7 328 NVIC_DisableIRQ(irq_n);
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
<> 144:ef7eb2e8f9f7 333 if (RxIrq == irq)
<> 144:ef7eb2e8f9f7 334 uart_data[obj->index].rx_irq_set_api = enable;
<> 144:ef7eb2e8f9f7 335 serial_irq_set_internal(obj, irq, enable);
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
<> 144:ef7eb2e8f9f7 339 uart_data[obj->index].rx_irq_set_flow = enable;
<> 144:ef7eb2e8f9f7 340 serial_irq_set_internal(obj, RxIrq, enable);
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /******************************************************************************
<> 144:ef7eb2e8f9f7 344 * READ/WRITE
<> 144:ef7eb2e8f9f7 345 ******************************************************************************/
<> 144:ef7eb2e8f9f7 346 int serial_getc(serial_t *obj) {
<> 144:ef7eb2e8f9f7 347 while (!serial_readable(obj));
<> 144:ef7eb2e8f9f7 348 int data = obj->uart->RBR;
<> 144:ef7eb2e8f9f7 349 if (NC != uart_data[obj->index].sw_rts.pin) {
<> 144:ef7eb2e8f9f7 350 gpio_write(&uart_data[obj->index].sw_rts, 0);
<> 144:ef7eb2e8f9f7 351 obj->uart->IER |= 1 << RxIrq;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 return data;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 void serial_putc(serial_t *obj, int c) {
<> 144:ef7eb2e8f9f7 357 while (!serial_writable(obj));
<> 144:ef7eb2e8f9f7 358 obj->uart->THR = c;
<> 144:ef7eb2e8f9f7 359 uart_data[obj->index].count++;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 int serial_readable(serial_t *obj) {
<> 144:ef7eb2e8f9f7 363 return obj->uart->LSR & 0x01;
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 int serial_writable(serial_t *obj) {
<> 144:ef7eb2e8f9f7 367 int isWritable = 1;
<> 144:ef7eb2e8f9f7 368 if (NC != uart_data[obj->index].sw_cts.pin)
<> 144:ef7eb2e8f9f7 369 isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done
<> 144:ef7eb2e8f9f7 370 else {
<> 144:ef7eb2e8f9f7 371 if (obj->uart->LSR & 0x20)
<> 144:ef7eb2e8f9f7 372 uart_data[obj->index].count = 0;
<> 144:ef7eb2e8f9f7 373 else if (uart_data[obj->index].count >= 16)
<> 144:ef7eb2e8f9f7 374 isWritable = 0;
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376 return isWritable;
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 void serial_clear(serial_t *obj) {
<> 144:ef7eb2e8f9f7 380 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
<> 144:ef7eb2e8f9f7 381 | 1 << 1 // rx FIFO reset
<> 144:ef7eb2e8f9f7 382 | 1 << 2 // tx FIFO reset
<> 144:ef7eb2e8f9f7 383 | 0 << 6; // interrupt depth
<> 144:ef7eb2e8f9f7 384 }
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 void serial_pinout_tx(PinName tx) {
<> 144:ef7eb2e8f9f7 387 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 void serial_break_set(serial_t *obj) {
<> 144:ef7eb2e8f9f7 391 obj->uart->LCR |= (1 << 6);
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 void serial_break_clear(serial_t *obj) {
<> 144:ef7eb2e8f9f7 395 obj->uart->LCR &= ~(1 << 6);
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
<> 144:ef7eb2e8f9f7 399 // Only UART1 has hardware flow control on LPC176x
<> 144:ef7eb2e8f9f7 400 LPC_UART1_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)LPC_UART1 ? LPC_UART1 : NULL;
<> 144:ef7eb2e8f9f7 401 int index = obj->index;
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 // First, disable flow control completely
<> 144:ef7eb2e8f9f7 404 if (uart1)
<> 144:ef7eb2e8f9f7 405 uart1->MCR = uart1->MCR & ~UART_MCR_FLOWCTRL_MASK;
<> 144:ef7eb2e8f9f7 406 uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
<> 144:ef7eb2e8f9f7 407 serial_flow_irq_set(obj, 0);
<> 144:ef7eb2e8f9f7 408 if (FlowControlNone == type)
<> 144:ef7eb2e8f9f7 409 return;
<> 144:ef7eb2e8f9f7 410 // Check type(s) of flow control to use
<> 144:ef7eb2e8f9f7 411 UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 412 UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 413 if (((FlowControlCTS == type) || (FlowControlRTSCTS == type)) && (NC != txflow)) {
<> 144:ef7eb2e8f9f7 414 // Can this be enabled in hardware?
<> 144:ef7eb2e8f9f7 415 if ((UART_1 == uart_cts) && (NULL != uart1)) {
<> 144:ef7eb2e8f9f7 416 // Enable auto-CTS mode
<> 144:ef7eb2e8f9f7 417 uart1->MCR |= UART_MCR_CTSEN_MASK;
<> 144:ef7eb2e8f9f7 418 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 419 } else {
<> 144:ef7eb2e8f9f7 420 // Can't enable in hardware, use software emulation
<> 144:ef7eb2e8f9f7 421 gpio_init_in(&uart_data[index].sw_cts, txflow);
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 if (((FlowControlRTS == type) || (FlowControlRTSCTS == type)) && (NC != rxflow)) {
<> 144:ef7eb2e8f9f7 425 // Enable FIFOs, trigger level of 1 char on RX FIFO
<> 144:ef7eb2e8f9f7 426 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
<> 144:ef7eb2e8f9f7 427 | 1 << 1 // Rx Fifo Reset
<> 144:ef7eb2e8f9f7 428 | 1 << 2 // Tx Fifo Reset
<> 144:ef7eb2e8f9f7 429 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
<> 144:ef7eb2e8f9f7 430 // Can this be enabled in hardware?
<> 144:ef7eb2e8f9f7 431 if ((UART_1 == uart_rts) && (NULL != uart1)) {
<> 144:ef7eb2e8f9f7 432 // Enable auto-RTS mode
<> 144:ef7eb2e8f9f7 433 uart1->MCR |= UART_MCR_RTSEN_MASK;
<> 144:ef7eb2e8f9f7 434 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 435 } else { // can't enable in hardware, use software emulation
<> 144:ef7eb2e8f9f7 436 gpio_init_out_ex(&uart_data[index].sw_rts, rxflow, 0);
<> 144:ef7eb2e8f9f7 437 // Enable RX interrupt
<> 144:ef7eb2e8f9f7 438 serial_flow_irq_set(obj, 1);
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442