mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include <stddef.h>
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 19 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 #define CHANNEL_NUM 48
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 static uint32_t channel_ids[CHANNEL_NUM] = {0};
<> 144:ef7eb2e8f9f7 25 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 static void handle_interrupt_in(void) {
<> 144:ef7eb2e8f9f7 28 // Read in all current interrupt registers. We do this once as the
<> 144:ef7eb2e8f9f7 29 // GPIO interrupt registers are on the APB bus, and this is slow.
<> 144:ef7eb2e8f9f7 30 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
<> 144:ef7eb2e8f9f7 31 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
<> 144:ef7eb2e8f9f7 32 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
<> 144:ef7eb2e8f9f7 33 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
<> 144:ef7eb2e8f9f7 34 uint8_t bitloc;
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 while(rise0 > 0) { //Continue as long as there are interrupts pending
<> 144:ef7eb2e8f9f7 37 bitloc = 31 - __CLZ(rise0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
<> 144:ef7eb2e8f9f7 38 if (channel_ids[bitloc] != 0)
<> 144:ef7eb2e8f9f7 39 irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
<> 144:ef7eb2e8f9f7 42 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
<> 144:ef7eb2e8f9f7 43 rise0 -= 1<<bitloc;
<> 144:ef7eb2e8f9f7 44 }
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 while(fall0 > 0) { //Continue as long as there are interrupts pending
<> 144:ef7eb2e8f9f7 47 bitloc = 31 - __CLZ(fall0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
<> 144:ef7eb2e8f9f7 48 if (channel_ids[bitloc] != 0)
<> 144:ef7eb2e8f9f7 49 irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
<> 144:ef7eb2e8f9f7 52 LPC_GPIOINT->IO0IntClr = 1 << bitloc;
<> 144:ef7eb2e8f9f7 53 fall0 -= 1<<bitloc;
<> 144:ef7eb2e8f9f7 54 }
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 //Same for port 2, only we need to watch the channel_index
<> 144:ef7eb2e8f9f7 57 while(rise2 > 0) { //Continue as long as there are interrupts pending
<> 144:ef7eb2e8f9f7 58 bitloc = 31 - __CLZ(rise2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 if (bitloc < 16) //Not sure if this is actually needed
<> 144:ef7eb2e8f9f7 61 if (channel_ids[bitloc+32] != 0)
<> 144:ef7eb2e8f9f7 62 irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
<> 144:ef7eb2e8f9f7 65 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
<> 144:ef7eb2e8f9f7 66 rise2 -= 1<<bitloc;
<> 144:ef7eb2e8f9f7 67 }
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 while(fall2 > 0) { //Continue as long as there are interrupts pending
<> 144:ef7eb2e8f9f7 70 bitloc = 31 - __CLZ(fall2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 if (bitloc < 16) //Not sure if this is actually needed
<> 144:ef7eb2e8f9f7 73 if (channel_ids[bitloc+32] != 0)
<> 144:ef7eb2e8f9f7 74 irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register
<> 144:ef7eb2e8f9f7 77 LPC_GPIOINT->IO2IntClr = 1 << bitloc;
<> 144:ef7eb2e8f9f7 78 fall2 -= 1<<bitloc;
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80 }
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
<> 144:ef7eb2e8f9f7 83 if (pin == NC) return -1;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 irq_handler = handler;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 obj->port = (int)pin & ~0x1F;
<> 144:ef7eb2e8f9f7 88 obj->pin = (int)pin & 0x1F;
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 // Interrupts available only on GPIO0 and GPIO2
<> 144:ef7eb2e8f9f7 91 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
<> 144:ef7eb2e8f9f7 92 error("pins on this port cannot generate interrupts");
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 // put us in the interrupt table
<> 144:ef7eb2e8f9f7 96 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
<> 144:ef7eb2e8f9f7 97 channel_ids[index] = id;
<> 144:ef7eb2e8f9f7 98 obj->ch = index;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
<> 144:ef7eb2e8f9f7 101 NVIC_EnableIRQ(EINT3_IRQn);
<> 144:ef7eb2e8f9f7 102 return 0;
<> 144:ef7eb2e8f9f7 103 }
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 void gpio_irq_free(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 106 channel_ids[obj->ch] = 0;
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
<> 144:ef7eb2e8f9f7 110 // ensure nothing is pending
<> 144:ef7eb2e8f9f7 111 switch (obj->port) {
<> 144:ef7eb2e8f9f7 112 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
<> 144:ef7eb2e8f9f7 113 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // enable the pin interrupt
<> 144:ef7eb2e8f9f7 117 if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 118 switch (obj->port) {
<> 144:ef7eb2e8f9f7 119 case LPC_GPIO0_BASE:
<> 144:ef7eb2e8f9f7 120 if (enable) {
<> 144:ef7eb2e8f9f7 121 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 122 } else {
<> 144:ef7eb2e8f9f7 123 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125 break;
<> 144:ef7eb2e8f9f7 126 case LPC_GPIO2_BASE:
<> 144:ef7eb2e8f9f7 127 if (enable) {
<> 144:ef7eb2e8f9f7 128 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 129 } else {
<> 144:ef7eb2e8f9f7 130 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132 break;
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134 } else {
<> 144:ef7eb2e8f9f7 135 switch (obj->port) {
<> 144:ef7eb2e8f9f7 136 case LPC_GPIO0_BASE:
<> 144:ef7eb2e8f9f7 137 if (enable) {
<> 144:ef7eb2e8f9f7 138 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 139 } else {
<> 144:ef7eb2e8f9f7 140 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142 break;
<> 144:ef7eb2e8f9f7 143 case LPC_GPIO2_BASE:
<> 144:ef7eb2e8f9f7 144 if (enable) {
<> 144:ef7eb2e8f9f7 145 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
<> 144:ef7eb2e8f9f7 146 } else {
<> 144:ef7eb2e8f9f7 147 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149 break;
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 void gpio_irq_enable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 155 NVIC_EnableIRQ(EINT3_IRQn);
<> 144:ef7eb2e8f9f7 156 }
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 void gpio_irq_disable(gpio_irq_t *obj) {
<> 144:ef7eb2e8f9f7 159 NVIC_DisableIRQ(EINT3_IRQn);
<> 144:ef7eb2e8f9f7 160 }
<> 144:ef7eb2e8f9f7 161