mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NXP/TARGET_LPC15XX/analogin_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 17 #include "analogin_api.h"
<> 144:ef7eb2e8f9f7 18 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 19 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #define ANALOGIN_MEDIAN_FILTER 1
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 #define ADC_10BIT_RANGE 0x3FF
<> 144:ef7eb2e8f9f7 24 #define ADC_12BIT_RANGE 0xFFF
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #define ADC_RANGE ADC_12BIT_RANGE
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 static const PinMap PinMap_ADC[] = {
<> 144:ef7eb2e8f9f7 29 {P0_8 , ADC0_0, 0},
<> 144:ef7eb2e8f9f7 30 {P0_7 , ADC0_1, 0},
<> 144:ef7eb2e8f9f7 31 {P0_6 , ADC0_2, 0},
<> 144:ef7eb2e8f9f7 32 {P0_5 , ADC0_3, 0},
<> 144:ef7eb2e8f9f7 33 {P0_4 , ADC0_4, 0},
<> 144:ef7eb2e8f9f7 34 {P0_3 , ADC0_5, 0},
<> 144:ef7eb2e8f9f7 35 {P0_2 , ADC0_6, 0},
<> 144:ef7eb2e8f9f7 36 {P0_1 , ADC0_7, 0},
<> 144:ef7eb2e8f9f7 37 {P1_0 , ADC0_8, 0},
<> 144:ef7eb2e8f9f7 38 {P0_31, ADC0_9, 0},
<> 144:ef7eb2e8f9f7 39 {P0_0 , ADC0_10,0},
<> 144:ef7eb2e8f9f7 40 {P0_30, ADC0_11,0},
<> 144:ef7eb2e8f9f7 41 {P1_1 , ADC1_0, 0},
<> 144:ef7eb2e8f9f7 42 {P0_9 , ADC1_1, 0},
<> 144:ef7eb2e8f9f7 43 {P0_10, ADC1_2, 0},
<> 144:ef7eb2e8f9f7 44 {P0_11, ADC1_3, 0},
<> 144:ef7eb2e8f9f7 45 {P1_2 , ADC1_4, 0},
<> 144:ef7eb2e8f9f7 46 {P1_3 , ADC1_5, 0},
<> 144:ef7eb2e8f9f7 47 {P0_13, ADC1_6, 0},
<> 144:ef7eb2e8f9f7 48 {P0_14, ADC1_7, 0},
<> 144:ef7eb2e8f9f7 49 {P0_15, ADC1_8, 0},
<> 144:ef7eb2e8f9f7 50 {P0_16, ADC1_9, 0},
<> 144:ef7eb2e8f9f7 51 {P1_4 , ADC1_10,0},
<> 144:ef7eb2e8f9f7 52 {P1_5 , ADC1_11,0},
<> 144:ef7eb2e8f9f7 53 };
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 void analogin_init(analogin_t *obj, PinName pin) {
<> 144:ef7eb2e8f9f7 56 obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
<> 144:ef7eb2e8f9f7 57 MBED_ASSERT(obj->adc != (ADCName)NC);
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 uint32_t port = (pin >> 5);
<> 144:ef7eb2e8f9f7 60 // enable clock for GPIOx
<> 144:ef7eb2e8f9f7 61 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1UL << (14 + port));
<> 144:ef7eb2e8f9f7 62 // pin enable
<> 144:ef7eb2e8f9f7 63 LPC_SWM->PINENABLE0 &= ~(1UL << obj->adc);
<> 144:ef7eb2e8f9f7 64 // configure GPIO as input
<> 144:ef7eb2e8f9f7 65 LPC_GPIO_PORT->DIR[port] &= ~(1UL << (pin & 0x1F));
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 // power up ADC
<> 144:ef7eb2e8f9f7 68 if (obj->adc < ADC1_0)
<> 144:ef7eb2e8f9f7 69 {
<> 144:ef7eb2e8f9f7 70 // ADC0
<> 144:ef7eb2e8f9f7 71 LPC_SYSCON->PDRUNCFG &= ~(1 << 10);
<> 144:ef7eb2e8f9f7 72 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 27);
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74 else {
<> 144:ef7eb2e8f9f7 75 // ADC1
<> 144:ef7eb2e8f9f7 76 LPC_SYSCON->PDRUNCFG &= ~(1 << 11);
<> 144:ef7eb2e8f9f7 77 LPC_SYSCON->SYSAHBCLKCTRL0 |= (1 << 28);
<> 144:ef7eb2e8f9f7 78 }
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 // determine the system clock divider for a 500kHz ADC clock during calibration
<> 144:ef7eb2e8f9f7 83 uint32_t clkdiv = (SystemCoreClock / 500000) - 1;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 // perform a self-calibration
<> 144:ef7eb2e8f9f7 86 adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF);
<> 144:ef7eb2e8f9f7 87 while ((adc_reg->CTRL & (1UL << 30)) != 0);
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // Sampling clock: SystemClock divided by 1
<> 144:ef7eb2e8f9f7 90 adc_reg->CTRL = 0;
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 static inline uint32_t adc_read(analogin_t *obj) {
<> 144:ef7eb2e8f9f7 94 uint32_t channels;
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 __IO LPC_ADC0_Type *adc_reg = (obj->adc < ADC1_0) ? (__IO LPC_ADC0_Type*)(LPC_ADC0) : (__IO LPC_ADC0_Type*)(LPC_ADC1);
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 if (obj->adc >= ADC1_0)
<> 144:ef7eb2e8f9f7 99 channels = ((obj->adc - ADC1_0) & 0x1F);
<> 144:ef7eb2e8f9f7 100 else
<> 144:ef7eb2e8f9f7 101 channels = (obj->adc & 0x1F);
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // select channel
<> 144:ef7eb2e8f9f7 104 adc_reg->SEQA_CTRL &= ~(0xFFF);
<> 144:ef7eb2e8f9f7 105 adc_reg->SEQA_CTRL |= (1UL << channels);
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 // start conversion and sequence enable
<> 144:ef7eb2e8f9f7 108 adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31));
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 // Repeatedly get the sample data until DONE bit
<> 144:ef7eb2e8f9f7 111 volatile uint32_t data;
<> 144:ef7eb2e8f9f7 112 do {
<> 144:ef7eb2e8f9f7 113 data = adc_reg->SEQA_GDAT;
<> 144:ef7eb2e8f9f7 114 } while ((data & (1UL << 31)) == 0);
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // Stop conversion
<> 144:ef7eb2e8f9f7 117 adc_reg->SEQA_CTRL &= ~(1UL << 31);
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 return ((data >> 4) & ADC_RANGE);
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 static inline void order(uint32_t *a, uint32_t *b) {
<> 144:ef7eb2e8f9f7 123 if (*a > *b) {
<> 144:ef7eb2e8f9f7 124 uint32_t t = *a;
<> 144:ef7eb2e8f9f7 125 *a = *b;
<> 144:ef7eb2e8f9f7 126 *b = t;
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 static inline uint32_t adc_read_u32(analogin_t *obj) {
<> 144:ef7eb2e8f9f7 131 uint32_t value;
<> 144:ef7eb2e8f9f7 132 #if ANALOGIN_MEDIAN_FILTER
<> 144:ef7eb2e8f9f7 133 uint32_t v1 = adc_read(obj);
<> 144:ef7eb2e8f9f7 134 uint32_t v2 = adc_read(obj);
<> 144:ef7eb2e8f9f7 135 uint32_t v3 = adc_read(obj);
<> 144:ef7eb2e8f9f7 136 order(&v1, &v2);
<> 144:ef7eb2e8f9f7 137 order(&v2, &v3);
<> 144:ef7eb2e8f9f7 138 order(&v1, &v2);
<> 144:ef7eb2e8f9f7 139 value = v2;
<> 144:ef7eb2e8f9f7 140 #else
<> 144:ef7eb2e8f9f7 141 value = adc_read(obj);
<> 144:ef7eb2e8f9f7 142 #endif
<> 144:ef7eb2e8f9f7 143 return value;
<> 144:ef7eb2e8f9f7 144 }
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 uint16_t analogin_read_u16(analogin_t *obj) {
<> 144:ef7eb2e8f9f7 147 uint32_t value = adc_read_u32(obj);
<> 144:ef7eb2e8f9f7 148 return (value << 4) | ((value >> 8) & 0x000F); // 12 bit
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 float analogin_read(analogin_t *obj) {
<> 144:ef7eb2e8f9f7 152 uint32_t value = adc_read_u32(obj);
<> 144:ef7eb2e8f9f7 153 return (float)value * (1.0f / (float)ADC_RANGE);
<> 144:ef7eb2e8f9f7 154 }