mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_clk.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**************************************************************************//**
<> 149:156823d33999 2 * @file clk.c
<> 149:156823d33999 3 * @version V3.00
<> 149:156823d33999 4 * $Revision: 35 $
<> 149:156823d33999 5 * $Date: 15/08/11 10:26a $
<> 149:156823d33999 6 * @brief M451 series CLK driver source file
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2014~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 *****************************************************************************/
<> 149:156823d33999 11
<> 149:156823d33999 12 #include "M451Series.h"
<> 149:156823d33999 13
<> 149:156823d33999 14 /** @addtogroup Standard_Driver Standard Driver
<> 149:156823d33999 15 @{
<> 149:156823d33999 16 */
<> 149:156823d33999 17
<> 149:156823d33999 18 /** @addtogroup CLK_Driver CLK Driver
<> 149:156823d33999 19 @{
<> 149:156823d33999 20 */
<> 149:156823d33999 21
<> 149:156823d33999 22 /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
<> 149:156823d33999 23 @{
<> 149:156823d33999 24 */
<> 149:156823d33999 25
<> 149:156823d33999 26 /**
<> 149:156823d33999 27 * @brief Disable clock divider output function
<> 149:156823d33999 28 * @param None
<> 149:156823d33999 29 * @return None
<> 149:156823d33999 30 * @details This function disable clock divider output function.
<> 149:156823d33999 31 */
<> 149:156823d33999 32 void CLK_DisableCKO(void)
<> 149:156823d33999 33 {
<> 149:156823d33999 34 /* Disable CKO clock source */
<> 149:156823d33999 35 CLK_DisableModuleClock(CLKO_MODULE);
<> 149:156823d33999 36 }
<> 149:156823d33999 37
<> 149:156823d33999 38 /**
<> 149:156823d33999 39 * @brief This function enable clock divider output module clock,
<> 149:156823d33999 40 * enable clock divider output function and set frequency selection.
<> 149:156823d33999 41 * @param[in] u32ClkSrc is frequency divider function clock source. Including :
<> 149:156823d33999 42 * - \ref CLK_CLKSEL1_CLKOSEL_HXT
<> 149:156823d33999 43 * - \ref CLK_CLKSEL1_CLKOSEL_LXT
<> 149:156823d33999 44 * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
<> 149:156823d33999 45 * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
<> 149:156823d33999 46 * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15.
<> 149:156823d33999 47 * @param[in] u32ClkDivBy1En is clock divided by one enabled.
<> 149:156823d33999 48 * @return None
<> 149:156823d33999 49 * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
<> 149:156823d33999 50 * The formula is: \n
<> 149:156823d33999 51 * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
<> 149:156823d33999 52 * This function is just used to set CKO clock.
<> 149:156823d33999 53 * User must enable I/O for CKO clock output pin by themselves. \n
<> 149:156823d33999 54 */
<> 149:156823d33999 55 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
<> 149:156823d33999 56 {
<> 149:156823d33999 57 /* CKO = clock source / 2^(u32ClkDiv + 1) */
<> 149:156823d33999 58 CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
<> 149:156823d33999 59
<> 149:156823d33999 60 /* Enable CKO clock source */
<> 149:156823d33999 61 CLK_EnableModuleClock(CLKO_MODULE);
<> 149:156823d33999 62
<> 149:156823d33999 63 /* Select CKO clock source */
<> 149:156823d33999 64 CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0);
<> 149:156823d33999 65 }
<> 149:156823d33999 66
<> 149:156823d33999 67 /**
<> 149:156823d33999 68 * @brief Enter to Power-down mode
<> 149:156823d33999 69 * @param None
<> 149:156823d33999 70 * @return None
<> 149:156823d33999 71 * @details This function is used to let system enter to Power-down mode. \n
<> 149:156823d33999 72 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 73 */
<> 149:156823d33999 74 void CLK_PowerDown(void)
<> 149:156823d33999 75 {
<> 149:156823d33999 76 /* Set the processor uses deep sleep as its low power mode */
<> 149:156823d33999 77 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 149:156823d33999 78
<> 149:156823d33999 79 /* Set system Power-down enabled and Power-down entry condition */
<> 149:156823d33999 80 CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWTCPU_Msk);
<> 149:156823d33999 81
<> 149:156823d33999 82 /* Chip enter Power-down mode after CPU run WFI instruction */
<> 149:156823d33999 83 __WFI();
<> 149:156823d33999 84 }
<> 149:156823d33999 85
<> 149:156823d33999 86 /**
<> 149:156823d33999 87 * @brief Enter to Idle mode
<> 149:156823d33999 88 * @param None
<> 149:156823d33999 89 * @return None
<> 149:156823d33999 90 * @details This function let system enter to Idle mode. \n
<> 149:156823d33999 91 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 92 */
<> 149:156823d33999 93 void CLK_Idle(void)
<> 149:156823d33999 94 {
<> 149:156823d33999 95 /* Set the processor uses sleep as its low power mode */
<> 149:156823d33999 96 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
<> 149:156823d33999 97
<> 149:156823d33999 98 /* Set chip in idle mode because of WFI command */
<> 149:156823d33999 99 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
<> 149:156823d33999 100
<> 149:156823d33999 101 /* Chip enter idle mode after CPU run WFI instruction */
<> 149:156823d33999 102 __WFI();
<> 149:156823d33999 103 }
<> 149:156823d33999 104
<> 149:156823d33999 105 /**
<> 149:156823d33999 106 * @brief Get external high speed crystal clock frequency
<> 149:156823d33999 107 * @param None
<> 149:156823d33999 108 * @return External high frequency crystal frequency
<> 149:156823d33999 109 * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
<> 149:156823d33999 110 */
<> 149:156823d33999 111 uint32_t CLK_GetHXTFreq(void)
<> 149:156823d33999 112 {
<> 149:156823d33999 113 if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
<> 149:156823d33999 114 return __HXT;
<> 149:156823d33999 115 else
<> 149:156823d33999 116 return 0;
<> 149:156823d33999 117 }
<> 149:156823d33999 118
<> 149:156823d33999 119
<> 149:156823d33999 120 /**
<> 149:156823d33999 121 * @brief Get external low speed crystal clock frequency
<> 149:156823d33999 122 * @param None
<> 149:156823d33999 123 * @return External low speed crystal clock frequency
<> 149:156823d33999 124 * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
<> 149:156823d33999 125 */
<> 149:156823d33999 126 uint32_t CLK_GetLXTFreq(void)
<> 149:156823d33999 127 {
<> 149:156823d33999 128 if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
<> 149:156823d33999 129 return __LXT;
<> 149:156823d33999 130 else
<> 149:156823d33999 131 return 0;
<> 149:156823d33999 132 }
<> 149:156823d33999 133
<> 149:156823d33999 134 /**
<> 149:156823d33999 135 * @brief Get PCLK0 frequency
<> 149:156823d33999 136 * @param None
<> 149:156823d33999 137 * @return PCLK0 frequency
<> 149:156823d33999 138 * @details This function get PCLK0 frequency. The frequency unit is Hz.
<> 149:156823d33999 139 */
<> 149:156823d33999 140 uint32_t CLK_GetPCLK0Freq(void)
<> 149:156823d33999 141 {
<> 149:156823d33999 142 SystemCoreClockUpdate();
<> 149:156823d33999 143 if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk)
<> 149:156823d33999 144 return SystemCoreClock / 2;
<> 149:156823d33999 145 else
<> 149:156823d33999 146 return SystemCoreClock;
<> 149:156823d33999 147 }
<> 149:156823d33999 148
<> 149:156823d33999 149
<> 149:156823d33999 150 /**
<> 149:156823d33999 151 * @brief Get PCLK1 frequency
<> 149:156823d33999 152 * @param None
<> 149:156823d33999 153 * @return PCLK1 frequency
<> 149:156823d33999 154 * @details This function get PCLK1 frequency. The frequency unit is Hz.
<> 149:156823d33999 155 */
<> 149:156823d33999 156 uint32_t CLK_GetPCLK1Freq(void)
<> 149:156823d33999 157 {
<> 149:156823d33999 158 SystemCoreClockUpdate();
<> 149:156823d33999 159 if(CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk)
<> 149:156823d33999 160 return SystemCoreClock / 2;
<> 149:156823d33999 161 else
<> 149:156823d33999 162 return SystemCoreClock;
<> 149:156823d33999 163 }
<> 149:156823d33999 164
<> 149:156823d33999 165
<> 149:156823d33999 166 /**
<> 149:156823d33999 167 * @brief Get HCLK frequency
<> 149:156823d33999 168 * @param None
<> 149:156823d33999 169 * @return HCLK frequency
<> 149:156823d33999 170 * @details This function get HCLK frequency. The frequency unit is Hz.
<> 149:156823d33999 171 */
<> 149:156823d33999 172 uint32_t CLK_GetHCLKFreq(void)
<> 149:156823d33999 173 {
<> 149:156823d33999 174 SystemCoreClockUpdate();
<> 149:156823d33999 175 return SystemCoreClock;
<> 149:156823d33999 176 }
<> 149:156823d33999 177
<> 149:156823d33999 178
<> 149:156823d33999 179 /**
<> 149:156823d33999 180 * @brief Get CPU frequency
<> 149:156823d33999 181 * @param None
<> 149:156823d33999 182 * @return CPU frequency
<> 149:156823d33999 183 * @details This function get CPU frequency. The frequency unit is Hz.
<> 149:156823d33999 184 */
<> 149:156823d33999 185 uint32_t CLK_GetCPUFreq(void)
<> 149:156823d33999 186 {
<> 149:156823d33999 187 SystemCoreClockUpdate();
<> 149:156823d33999 188 return SystemCoreClock;
<> 149:156823d33999 189 }
<> 149:156823d33999 190
<> 149:156823d33999 191
<> 149:156823d33999 192 /**
<> 149:156823d33999 193 * @brief Set HCLK frequency
<> 149:156823d33999 194 * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 72 MHz.
<> 149:156823d33999 195 * @return HCLK frequency
<> 149:156823d33999 196 * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n
<> 149:156823d33999 197 * It would configure PLL frequency to 50MHz ~ 144MHz,
<> 149:156823d33999 198 * set HCLK clock divider as 2 and switch HCLK clock source to PLL. \n
<> 149:156823d33999 199 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 200 */
<> 149:156823d33999 201 uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
<> 149:156823d33999 202 {
<> 149:156823d33999 203 uint32_t u32HIRCSTB;
<> 149:156823d33999 204
<> 149:156823d33999 205 /* Read HIRC clock source stable flag */
<> 149:156823d33999 206 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
<> 149:156823d33999 207
<> 149:156823d33999 208 /* The range of u32Hclk is 25 MHz ~ 72 MHz */
<> 149:156823d33999 209 if(u32Hclk > FREQ_72MHZ)
<> 149:156823d33999 210 u32Hclk = FREQ_72MHZ;
<> 149:156823d33999 211 if(u32Hclk < FREQ_25MHZ)
<> 149:156823d33999 212 u32Hclk = FREQ_25MHZ;
<> 149:156823d33999 213
<> 149:156823d33999 214 /* Switch HCLK clock source to HIRC clock for safe */
<> 149:156823d33999 215 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
<> 149:156823d33999 216 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
<> 149:156823d33999 217 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
<> 149:156823d33999 218 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
<> 149:156823d33999 219
<> 149:156823d33999 220 /* Configure PLL setting if HXT clock is enabled */
<> 149:156823d33999 221 if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
<> 149:156823d33999 222 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, (u32Hclk << 1));
<> 149:156823d33999 223
<> 149:156823d33999 224 /* Configure PLL setting if HXT clock is not enabled */
<> 149:156823d33999 225 else
<> 149:156823d33999 226 {
<> 149:156823d33999 227 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, (u32Hclk << 1));
<> 149:156823d33999 228
<> 149:156823d33999 229 /* Read HIRC clock source stable flag */
<> 149:156823d33999 230 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
<> 149:156823d33999 231 }
<> 149:156823d33999 232
<> 149:156823d33999 233 /* Select HCLK clock source to PLL,
<> 149:156823d33999 234 Select HCLK clock source divider as 2
<> 149:156823d33999 235 and update system core clock
<> 149:156823d33999 236 */
<> 149:156823d33999 237 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2));
<> 149:156823d33999 238
<> 149:156823d33999 239 /* Disable HIRC if HIRC is disabled before setting core clock */
<> 149:156823d33999 240 if(u32HIRCSTB == 0)
<> 149:156823d33999 241 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
<> 149:156823d33999 242
<> 149:156823d33999 243 /* Return actually HCLK frequency is PLL frequency divide 2 */
<> 149:156823d33999 244 return u32Hclk >> 1;
<> 149:156823d33999 245 }
<> 149:156823d33999 246
<> 149:156823d33999 247 /**
<> 149:156823d33999 248 * @brief This function set HCLK clock source and HCLK clock divider
<> 149:156823d33999 249 * @param[in] u32ClkSrc is HCLK clock source. Including :
<> 149:156823d33999 250 * - \ref CLK_CLKSEL0_HCLKSEL_HXT
<> 149:156823d33999 251 * - \ref CLK_CLKSEL0_HCLKSEL_LXT
<> 149:156823d33999 252 * - \ref CLK_CLKSEL0_HCLKSEL_PLL
<> 149:156823d33999 253 * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
<> 149:156823d33999 254 * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
<> 149:156823d33999 255 * @param[in] u32ClkDiv is HCLK clock divider. Including :
<> 149:156823d33999 256 * - \ref CLK_CLKDIV0_HCLK(x)
<> 149:156823d33999 257 * @return None
<> 149:156823d33999 258 * @details This function set HCLK clock source and HCLK clock divider. \n
<> 149:156823d33999 259 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 260 */
<> 149:156823d33999 261 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
<> 149:156823d33999 262 {
<> 149:156823d33999 263 uint32_t u32HIRCSTB;
<> 149:156823d33999 264
<> 149:156823d33999 265 /* Read HIRC clock source stable flag */
<> 149:156823d33999 266 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
<> 149:156823d33999 267
<> 149:156823d33999 268 /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
<> 149:156823d33999 269 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
<> 149:156823d33999 270 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
<> 149:156823d33999 271 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
<> 149:156823d33999 272
<> 149:156823d33999 273 /* Apply new Divider */
<> 149:156823d33999 274 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
<> 149:156823d33999 275
<> 149:156823d33999 276 /* Switch HCLK to new HCLK source */
<> 149:156823d33999 277 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
<> 149:156823d33999 278
<> 149:156823d33999 279 /* Update System Core Clock */
<> 149:156823d33999 280 SystemCoreClockUpdate();
<> 149:156823d33999 281
<> 149:156823d33999 282 /* Disable HIRC if HIRC is disabled before switching HCLK source */
<> 149:156823d33999 283 if(u32HIRCSTB == 0)
<> 149:156823d33999 284 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
<> 149:156823d33999 285 }
<> 149:156823d33999 286
<> 149:156823d33999 287 /**
<> 149:156823d33999 288 * @brief This function set selected module clock source and module clock divider
<> 149:156823d33999 289 * @param[in] u32ModuleIdx is module index.
<> 149:156823d33999 290 * @param[in] u32ClkSrc is module clock source.
<> 149:156823d33999 291 * @param[in] u32ClkDiv is module clock divider.
<> 149:156823d33999 292 * @return None
<> 149:156823d33999 293 * @details Valid parameter combinations listed in following table:
<> 149:156823d33999 294 *
<> 149:156823d33999 295 * |Module index |Clock source |Divider |
<> 149:156823d33999 296 * | :---------------- | :----------------------------------- | :---------------------- |
<> 149:156823d33999 297 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
<> 149:156823d33999 298 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_PCLK0_DIV2048 | x |
<> 149:156823d33999 299 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
<> 149:156823d33999 300 * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x |
<> 149:156823d33999 301 * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x |
<> 149:156823d33999 302 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
<> 149:156823d33999 303 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
<> 149:156823d33999 304 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
<> 149:156823d33999 305 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x |
<> 149:156823d33999 306 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
<> 149:156823d33999 307 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
<> 149:156823d33999 308 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
<> 149:156823d33999 309 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
<> 149:156823d33999 310 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
<> 149:156823d33999 311 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x |
<> 149:156823d33999 312 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
<> 149:156823d33999 313 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
<> 149:156823d33999 314 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
<> 149:156823d33999 315 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
<> 149:156823d33999 316 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
<> 149:156823d33999 317 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x |
<> 149:156823d33999 318 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
<> 149:156823d33999 319 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
<> 149:156823d33999 320 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
<> 149:156823d33999 321 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
<> 149:156823d33999 322 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
<> 149:156823d33999 323 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x |
<> 149:156823d33999 324 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
<> 149:156823d33999 325 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
<> 149:156823d33999 326 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
<> 149:156823d33999 327 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
<> 149:156823d33999 328 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
<> 149:156823d33999 329 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
<> 149:156823d33999 330 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
<> 149:156823d33999 331 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
<> 149:156823d33999 332 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK0 | x |
<> 149:156823d33999 333 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
<> 149:156823d33999 334 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
<> 149:156823d33999 335 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |
<> 149:156823d33999 336 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK1 | x |
<> 149:156823d33999 337 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
<> 149:156823d33999 338 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |
<> 149:156823d33999 339 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |
<> 149:156823d33999 340 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK0 | x |
<> 149:156823d33999 341 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |
<> 149:156823d33999 342 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 343 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 344 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 345 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 346 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 347 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 348 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 349 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 350 * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 351 * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 352 * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 353 * |\ref UART2_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 354 * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 355 * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_LXT |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 356 * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 357 * |\ref UART3_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV0_UART(x) |
<> 149:156823d33999 358 * |\ref USBH_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
<> 149:156823d33999 359 * |\ref USBD_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
<> 149:156823d33999 360 * |\ref OTG_MODULE | x |\ref CLK_CLKDIV0_USB(x) |
<> 149:156823d33999 361 * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |
<> 149:156823d33999 362 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
<> 149:156823d33999 363 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
<> 149:156823d33999 364 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
<> 149:156823d33999 365 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
<> 149:156823d33999 366 * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PLL | x |
<> 149:156823d33999 367 * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PCLK0 | x |
<> 149:156823d33999 368 * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PLL | x |
<> 149:156823d33999 369 * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PCLK1 | x |
<> 149:156823d33999 370 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_PCLK0_DIV2048 | x |
<> 149:156823d33999 371 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
<> 149:156823d33999 372 */
<> 149:156823d33999 373 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
<> 149:156823d33999 374 {
<> 149:156823d33999 375 uint32_t u32sel = 0, u32div = 0;
<> 149:156823d33999 376
<> 149:156823d33999 377 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
<> 149:156823d33999 378 {
<> 149:156823d33999 379 /* Get clock divider control register address */
<> 149:156823d33999 380 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4);
<> 149:156823d33999 381 /* Apply new divider */
<> 149:156823d33999 382 M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
<> 149:156823d33999 383 }
<> 149:156823d33999 384
<> 149:156823d33999 385 if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
<> 149:156823d33999 386 {
<> 149:156823d33999 387 /* Get clock select control register address */
<> 149:156823d33999 388 u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4);
<> 149:156823d33999 389 /* Set new clock selection setting */
<> 149:156823d33999 390 M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
<> 149:156823d33999 391 }
<> 149:156823d33999 392 }
<> 149:156823d33999 393
<> 149:156823d33999 394
<> 149:156823d33999 395 /**
<> 149:156823d33999 396 * @brief Set SysTick clock source
<> 149:156823d33999 397 * @param[in] u32ClkSrc is module clock source. Including:
<> 149:156823d33999 398 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
<> 149:156823d33999 399 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
<> 149:156823d33999 400 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
<> 149:156823d33999 401 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
<> 149:156823d33999 402 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
<> 149:156823d33999 403 * @return None
<> 149:156823d33999 404 * @details This function set SysTick clock source. \n
<> 149:156823d33999 405 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 406 */
<> 149:156823d33999 407 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
<> 149:156823d33999 408 {
<> 149:156823d33999 409 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
<> 149:156823d33999 410
<> 149:156823d33999 411 }
<> 149:156823d33999 412
<> 149:156823d33999 413 /**
<> 149:156823d33999 414 * @brief Enable clock source
<> 149:156823d33999 415 * @param[in] u32ClkMask is clock source mask. Including :
<> 149:156823d33999 416 * - \ref CLK_PWRCTL_HXTEN_Msk
<> 149:156823d33999 417 * - \ref CLK_PWRCTL_LXTEN_Msk
<> 149:156823d33999 418 * - \ref CLK_PWRCTL_HIRCEN_Msk
<> 149:156823d33999 419 * - \ref CLK_PWRCTL_LIRCEN_Msk
<> 149:156823d33999 420 * @return None
<> 149:156823d33999 421 * @details This function enable clock source. \n
<> 149:156823d33999 422 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 423 */
<> 149:156823d33999 424 void CLK_EnableXtalRC(uint32_t u32ClkMask)
<> 149:156823d33999 425 {
<> 149:156823d33999 426 CLK->PWRCTL |= u32ClkMask;
<> 149:156823d33999 427 }
<> 149:156823d33999 428
<> 149:156823d33999 429 /**
<> 149:156823d33999 430 * @brief Disable clock source
<> 149:156823d33999 431 * @param[in] u32ClkMask is clock source mask. Including :
<> 149:156823d33999 432 * - \ref CLK_PWRCTL_HXTEN_Msk
<> 149:156823d33999 433 * - \ref CLK_PWRCTL_LXTEN_Msk
<> 149:156823d33999 434 * - \ref CLK_PWRCTL_HIRCEN_Msk
<> 149:156823d33999 435 * - \ref CLK_PWRCTL_LIRCEN_Msk
<> 149:156823d33999 436 * @return None
<> 149:156823d33999 437 * @details This function disable clock source. \n
<> 149:156823d33999 438 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 439 */
<> 149:156823d33999 440 void CLK_DisableXtalRC(uint32_t u32ClkMask)
<> 149:156823d33999 441 {
<> 149:156823d33999 442 CLK->PWRCTL &= ~u32ClkMask;
<> 149:156823d33999 443 }
<> 149:156823d33999 444
<> 149:156823d33999 445 /**
<> 149:156823d33999 446 * @brief Enable module clock
<> 149:156823d33999 447 * @param[in] u32ModuleIdx is module index. Including :
<> 149:156823d33999 448 * - \ref PDMA_MODULE
<> 149:156823d33999 449 * - \ref ISP_MODULE
<> 149:156823d33999 450 * - \ref EBI_MODULE
<> 149:156823d33999 451 * - \ref USBH_MODULE
<> 149:156823d33999 452 * - \ref CRC_MODULE
<> 149:156823d33999 453 * - \ref WDT_MODULE
<> 149:156823d33999 454 * - \ref WWDT_MODULE
<> 149:156823d33999 455 * - \ref RTC_MODULE
<> 149:156823d33999 456 * - \ref TMR0_MODULE
<> 149:156823d33999 457 * - \ref TMR1_MODULE
<> 149:156823d33999 458 * - \ref TMR2_MODULE
<> 149:156823d33999 459 * - \ref TMR3_MODULE
<> 149:156823d33999 460 * - \ref CLKO_MODULE
<> 149:156823d33999 461 * - \ref ACMP01_MODULE
<> 149:156823d33999 462 * - \ref I2C0_MODULE
<> 149:156823d33999 463 * - \ref I2C1_MODULE
<> 149:156823d33999 464 * - \ref SPI0_MODULE
<> 149:156823d33999 465 * - \ref SPI1_MODULE
<> 149:156823d33999 466 * - \ref SPI2_MODULE
<> 149:156823d33999 467 * - \ref UART0_MODULE
<> 149:156823d33999 468 * - \ref UART1_MODULE
<> 149:156823d33999 469 * - \ref UART2_MODULE
<> 149:156823d33999 470 * - \ref UART3_MODULE
<> 149:156823d33999 471 * - \ref CAN0_MODULE
<> 149:156823d33999 472 * - \ref OTG_MODULE
<> 149:156823d33999 473 * - \ref USBD_MODULE
<> 149:156823d33999 474 * - \ref EADC_MODULE
<> 149:156823d33999 475 * - \ref SC0_MODULE
<> 149:156823d33999 476 * - \ref DAC_MODULE
<> 149:156823d33999 477 * - \ref PWM0_MODULE
<> 149:156823d33999 478 * - \ref PWM1_MODULE
<> 149:156823d33999 479 * - \ref TK_MODULE
<> 149:156823d33999 480 * @return None
<> 149:156823d33999 481 * @details This function is used to enable module clock.
<> 149:156823d33999 482 */
<> 149:156823d33999 483 void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
<> 149:156823d33999 484 {
<> 149:156823d33999 485 *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
<> 149:156823d33999 486 }
<> 149:156823d33999 487
<> 149:156823d33999 488 /**
<> 149:156823d33999 489 * @brief Disable module clock
<> 149:156823d33999 490 * @param[in] u32ModuleIdx is module index. Including :
<> 149:156823d33999 491 * - \ref PDMA_MODULE
<> 149:156823d33999 492 * - \ref ISP_MODULE
<> 149:156823d33999 493 * - \ref EBI_MODULE
<> 149:156823d33999 494 * - \ref USBH_MODULE
<> 149:156823d33999 495 * - \ref CRC_MODULE
<> 149:156823d33999 496 * - \ref WDT_MODULE
<> 149:156823d33999 497 * - \ref WWDT_MODULE
<> 149:156823d33999 498 * - \ref RTC_MODULE
<> 149:156823d33999 499 * - \ref TMR0_MODULE
<> 149:156823d33999 500 * - \ref TMR1_MODULE
<> 149:156823d33999 501 * - \ref TMR2_MODULE
<> 149:156823d33999 502 * - \ref TMR3_MODULE
<> 149:156823d33999 503 * - \ref CLKO_MODULE
<> 149:156823d33999 504 * - \ref ACMP01_MODULE
<> 149:156823d33999 505 * - \ref I2C0_MODULE
<> 149:156823d33999 506 * - \ref I2C1_MODULE
<> 149:156823d33999 507 * - \ref SPI0_MODULE
<> 149:156823d33999 508 * - \ref SPI1_MODULE
<> 149:156823d33999 509 * - \ref SPI2_MODULE
<> 149:156823d33999 510 * - \ref UART0_MODULE
<> 149:156823d33999 511 * - \ref UART1_MODULE
<> 149:156823d33999 512 * - \ref UART2_MODULE
<> 149:156823d33999 513 * - \ref UART3_MODULE
<> 149:156823d33999 514 * - \ref CAN0_MODULE
<> 149:156823d33999 515 * - \ref OTG_MODULE
<> 149:156823d33999 516 * - \ref USBD_MODULE
<> 149:156823d33999 517 * - \ref EADC_MODULE
<> 149:156823d33999 518 * - \ref SC0_MODULE
<> 149:156823d33999 519 * - \ref DAC_MODULE
<> 149:156823d33999 520 * - \ref PWM0_MODULE
<> 149:156823d33999 521 * - \ref PWM1_MODULE
<> 149:156823d33999 522 * - \ref TK_MODULE
<> 149:156823d33999 523 * @return None
<> 149:156823d33999 524 * @details This function is used to disable module clock.
<> 149:156823d33999 525 */
<> 149:156823d33999 526 void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
<> 149:156823d33999 527 {
<> 149:156823d33999 528 *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (MODULE_APBCLK(u32ModuleIdx) * 4)) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
<> 149:156823d33999 529 }
<> 149:156823d33999 530
<> 149:156823d33999 531
<> 149:156823d33999 532 /**
<> 149:156823d33999 533 * @brief Set PLL frequency
<> 149:156823d33999 534 * @param[in] u32PllClkSrc is PLL clock source. Including :
<> 149:156823d33999 535 * - \ref CLK_PLLCTL_PLLSRC_HXT
<> 149:156823d33999 536 * - \ref CLK_PLLCTL_PLLSRC_HIRC
<> 149:156823d33999 537 * @param[in] u32PllFreq is PLL frequency.
<> 149:156823d33999 538 * @return PLL frequency
<> 149:156823d33999 539 * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
<> 149:156823d33999 540 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 541 */
<> 149:156823d33999 542 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
<> 149:156823d33999 543 {
<> 149:156823d33999 544 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
<> 149:156823d33999 545 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
<> 149:156823d33999 546
<> 149:156823d33999 547 /* Disable PLL first to avoid unstable when setting PLL */
<> 149:156823d33999 548 CLK_DisablePLL();
<> 149:156823d33999 549
<> 149:156823d33999 550 /* PLL source clock is from HXT */
<> 149:156823d33999 551 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
<> 149:156823d33999 552 {
<> 149:156823d33999 553 /* Enable HXT clock */
<> 149:156823d33999 554 CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
<> 149:156823d33999 555
<> 149:156823d33999 556 /* Wait for HXT clock ready */
<> 149:156823d33999 557 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
<> 149:156823d33999 558
<> 149:156823d33999 559 /* Select PLL source clock from HXT */
<> 149:156823d33999 560 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
<> 149:156823d33999 561 u32PllSrcClk = __HXT;
<> 149:156823d33999 562
<> 149:156823d33999 563 /* u32NR start from 2 */
<> 149:156823d33999 564 u32NR = 2;
<> 149:156823d33999 565 }
<> 149:156823d33999 566
<> 149:156823d33999 567 /* PLL source clock is from HIRC */
<> 149:156823d33999 568 else
<> 149:156823d33999 569 {
<> 149:156823d33999 570 /* Enable HIRC clock */
<> 149:156823d33999 571 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
<> 149:156823d33999 572
<> 149:156823d33999 573 /* Wait for HIRC clock ready */
<> 149:156823d33999 574 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
<> 149:156823d33999 575
<> 149:156823d33999 576 /* Select PLL source clock from HIRC */
<> 149:156823d33999 577 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
<> 149:156823d33999 578 u32PllSrcClk = __HIRC;
<> 149:156823d33999 579
<> 149:156823d33999 580 /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
<> 149:156823d33999 581 u32NR = 4;
<> 149:156823d33999 582 }
<> 149:156823d33999 583
<> 149:156823d33999 584 /* Select "NO" according to request frequency */
<> 149:156823d33999 585 if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq > FREQ_250MHZ))
<> 149:156823d33999 586 {
<> 149:156823d33999 587 u32NO = 0;
<> 149:156823d33999 588 }
<> 149:156823d33999 589 else if((u32PllFreq <= FREQ_250MHZ) && (u32PllFreq > FREQ_125MHZ))
<> 149:156823d33999 590 {
<> 149:156823d33999 591 u32NO = 1;
<> 149:156823d33999 592 u32PllFreq = u32PllFreq << 1;
<> 149:156823d33999 593 }
<> 149:156823d33999 594 else if((u32PllFreq <= FREQ_125MHZ) && (u32PllFreq >= FREQ_50MHZ))
<> 149:156823d33999 595 {
<> 149:156823d33999 596 u32NO = 3;
<> 149:156823d33999 597 u32PllFreq = u32PllFreq << 2;
<> 149:156823d33999 598 }
<> 149:156823d33999 599 else
<> 149:156823d33999 600 {
<> 149:156823d33999 601 /* Wrong frequency request. Just return default setting. */
<> 149:156823d33999 602 goto lexit;
<> 149:156823d33999 603 }
<> 149:156823d33999 604
<> 149:156823d33999 605 /* Find best solution */
<> 149:156823d33999 606 u32Min = (uint32_t) - 1;
<> 149:156823d33999 607 u32MinNR = 0;
<> 149:156823d33999 608 u32MinNF = 0;
<> 149:156823d33999 609 for(; u32NR <= 33; u32NR++)
<> 149:156823d33999 610 {
<> 149:156823d33999 611 u32Tmp = u32PllSrcClk / u32NR;
<> 149:156823d33999 612 if((u32Tmp > 1600000) && (u32Tmp < 16000000))
<> 149:156823d33999 613 {
<> 149:156823d33999 614 for(u32NF = 2; u32NF <= 513; u32NF++)
<> 149:156823d33999 615 {
<> 149:156823d33999 616 u32Tmp2 = u32Tmp * u32NF;
<> 149:156823d33999 617 if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000))
<> 149:156823d33999 618 {
<> 149:156823d33999 619 u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
<> 149:156823d33999 620 if(u32Tmp3 < u32Min)
<> 149:156823d33999 621 {
<> 149:156823d33999 622 u32Min = u32Tmp3;
<> 149:156823d33999 623 u32MinNR = u32NR;
<> 149:156823d33999 624 u32MinNF = u32NF;
<> 149:156823d33999 625
<> 149:156823d33999 626 /* Break when get good results */
<> 149:156823d33999 627 if(u32Min == 0)
<> 149:156823d33999 628 break;
<> 149:156823d33999 629 }
<> 149:156823d33999 630 }
<> 149:156823d33999 631 }
<> 149:156823d33999 632 }
<> 149:156823d33999 633 }
<> 149:156823d33999 634
<> 149:156823d33999 635 /* Enable and apply new PLL setting. */
<> 149:156823d33999 636 CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
<> 149:156823d33999 637
<> 149:156823d33999 638 /* Wait for PLL clock stable */
<> 149:156823d33999 639 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
<> 149:156823d33999 640
<> 149:156823d33999 641 /* Return actual PLL output clock frequency */
<> 149:156823d33999 642 return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
<> 149:156823d33999 643
<> 149:156823d33999 644 lexit:
<> 149:156823d33999 645
<> 149:156823d33999 646 /* Apply default PLL setting and return */
<> 149:156823d33999 647 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
<> 149:156823d33999 648 CLK->PLLCTL = CLK_PLLCTL_72MHz_HXT; /* 72MHz */
<> 149:156823d33999 649 else
<> 149:156823d33999 650 CLK->PLLCTL = CLK_PLLCTL_72MHz_HIRC; /* 71.8848MHz */
<> 149:156823d33999 651
<> 149:156823d33999 652 /* Wait for PLL clock stable */
<> 149:156823d33999 653 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
<> 149:156823d33999 654
<> 149:156823d33999 655 return CLK_GetPLLClockFreq();
<> 149:156823d33999 656
<> 149:156823d33999 657 }
<> 149:156823d33999 658
<> 149:156823d33999 659 /**
<> 149:156823d33999 660 * @brief Disable PLL
<> 149:156823d33999 661 * @param None
<> 149:156823d33999 662 * @return None
<> 149:156823d33999 663 * @details This function set PLL in Power-down mode. \n
<> 149:156823d33999 664 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 665 */
<> 149:156823d33999 666 void CLK_DisablePLL(void)
<> 149:156823d33999 667 {
<> 149:156823d33999 668 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
<> 149:156823d33999 669 }
<> 149:156823d33999 670
<> 149:156823d33999 671
<> 149:156823d33999 672 /**
<> 149:156823d33999 673 * @brief This function check selected clock source status
<> 149:156823d33999 674 * @param[in] u32ClkMask is selected clock source. Including :
<> 149:156823d33999 675 * - \ref CLK_STATUS_HXTSTB_Msk
<> 149:156823d33999 676 * - \ref CLK_STATUS_LXTSTB_Msk
<> 149:156823d33999 677 * - \ref CLK_STATUS_HIRCSTB_Msk
<> 149:156823d33999 678 * - \ref CLK_STATUS_LIRCSTB_Msk
<> 149:156823d33999 679 * - \ref CLK_STATUS_PLLSTB_Msk
<> 149:156823d33999 680 * @retval 0 clock is not stable
<> 149:156823d33999 681 * @retval 1 clock is stable
<> 149:156823d33999 682 * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)
<> 149:156823d33999 683 */
<> 149:156823d33999 684 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
<> 149:156823d33999 685 {
<> 149:156823d33999 686 int32_t i32TimeOutCnt = 2160000;
<> 149:156823d33999 687
<> 149:156823d33999 688 while((CLK->STATUS & u32ClkMask) != u32ClkMask)
<> 149:156823d33999 689 {
<> 149:156823d33999 690 if(i32TimeOutCnt-- <= 0)
<> 149:156823d33999 691 return 0;
<> 149:156823d33999 692 }
<> 149:156823d33999 693
<> 149:156823d33999 694 return 1;
<> 149:156823d33999 695 }
<> 149:156823d33999 696
<> 149:156823d33999 697 /**
<> 149:156823d33999 698 * @brief Enable System Tick counter
<> 149:156823d33999 699 * @param[in] u32ClkSrc is System Tick clock source. Including:
<> 149:156823d33999 700 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
<> 149:156823d33999 701 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
<> 149:156823d33999 702 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
<> 149:156823d33999 703 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
<> 149:156823d33999 704 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
<> 149:156823d33999 705 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
<> 149:156823d33999 706 * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
<> 149:156823d33999 707 * @return None
<> 149:156823d33999 708 * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
<> 149:156823d33999 709 * The register write-protection function should be disabled before using this function.
<> 149:156823d33999 710 */
<> 149:156823d33999 711 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
<> 149:156823d33999 712 {
<> 149:156823d33999 713 /* Set System Tick counter disabled */
<> 149:156823d33999 714 SysTick->CTRL = 0;
<> 149:156823d33999 715
<> 149:156823d33999 716 /* Set System Tick clock source */
<> 149:156823d33999 717 if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK )
<> 149:156823d33999 718 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
<> 149:156823d33999 719 else
<> 149:156823d33999 720 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
<> 149:156823d33999 721
<> 149:156823d33999 722 /* Set System Tick reload value */
<> 149:156823d33999 723 SysTick->LOAD = u32Count;
<> 149:156823d33999 724
<> 149:156823d33999 725 /* Clear System Tick current value and counter flag */
<> 149:156823d33999 726 SysTick->VAL = 0;
<> 149:156823d33999 727
<> 149:156823d33999 728 /* Set System Tick interrupt enabled and counter enabled */
<> 149:156823d33999 729 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
<> 149:156823d33999 730 }
<> 149:156823d33999 731
<> 149:156823d33999 732 /**
<> 149:156823d33999 733 * @brief Disable System Tick counter
<> 149:156823d33999 734 * @param None
<> 149:156823d33999 735 * @return None
<> 149:156823d33999 736 * @details This function disable System Tick counter.
<> 149:156823d33999 737 */
<> 149:156823d33999 738 void CLK_DisableSysTick(void)
<> 149:156823d33999 739 {
<> 149:156823d33999 740 /* Set System Tick counter disabled */
<> 149:156823d33999 741 SysTick->CTRL = 0;
<> 149:156823d33999 742 }
<> 149:156823d33999 743
<> 149:156823d33999 744
<> 149:156823d33999 745 /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
<> 149:156823d33999 746
<> 149:156823d33999 747 /*@}*/ /* end of group CLK_Driver */
<> 149:156823d33999 748
<> 149:156823d33999 749 /*@}*/ /* end of group Standard_Driver */
<> 149:156823d33999 750
<> 149:156823d33999 751 /*** (C) COPYRIGHT 2014~2015 Nuvoton Technology Corp. ***/