mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_M2351/mbed_overrides.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 187:0387e8f68319 1 /* mbed Microcontroller Library
AnnaBridge 187:0387e8f68319 2 * Copyright (c) 2015-2016 Nuvoton
AnnaBridge 187:0387e8f68319 3 *
AnnaBridge 187:0387e8f68319 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 187:0387e8f68319 5 * you may not use this file except in compliance with the License.
AnnaBridge 187:0387e8f68319 6 * You may obtain a copy of the License at
AnnaBridge 187:0387e8f68319 7 *
AnnaBridge 187:0387e8f68319 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 187:0387e8f68319 9 *
AnnaBridge 187:0387e8f68319 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 187:0387e8f68319 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 187:0387e8f68319 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 187:0387e8f68319 13 * See the License for the specific language governing permissions and
AnnaBridge 187:0387e8f68319 14 * limitations under the License.
AnnaBridge 187:0387e8f68319 15 */
AnnaBridge 187:0387e8f68319 16
AnnaBridge 187:0387e8f68319 17 #include "cmsis.h"
AnnaBridge 187:0387e8f68319 18 #include "mbed_error.h"
AnnaBridge 187:0387e8f68319 19
AnnaBridge 187:0387e8f68319 20 void mbed_sdk_init(void)
AnnaBridge 187:0387e8f68319 21 {
AnnaBridge 187:0387e8f68319 22 // NOTE: Support singleton semantics to be called from other init functions
AnnaBridge 187:0387e8f68319 23 static int inited = 0;
AnnaBridge 187:0387e8f68319 24 if (inited) {
AnnaBridge 187:0387e8f68319 25 return;
AnnaBridge 187:0387e8f68319 26 }
AnnaBridge 187:0387e8f68319 27 inited = 1;
AnnaBridge 187:0387e8f68319 28
AnnaBridge 187:0387e8f68319 29 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 187:0387e8f68319 30 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 187:0387e8f68319 31 /* Init System Clock */
AnnaBridge 187:0387e8f68319 32 /*---------------------------------------------------------------------------------------------------------*/
AnnaBridge 187:0387e8f68319 33 /* Unlock protected registers */
AnnaBridge 187:0387e8f68319 34 SYS_UnlockReg();
AnnaBridge 187:0387e8f68319 35
AnnaBridge 187:0387e8f68319 36 /* Enable HIRC clock (Internal RC 12MHz) */
AnnaBridge 187:0387e8f68319 37 CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
AnnaBridge 187:0387e8f68319 38 /* Enable HXT clock (external XTAL 12MHz) */
AnnaBridge 187:0387e8f68319 39 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
AnnaBridge 187:0387e8f68319 40 /* Enable LIRC for lp_ticker */
AnnaBridge 187:0387e8f68319 41 CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
AnnaBridge 187:0387e8f68319 42 /* Enable LXT for RTC */
AnnaBridge 187:0387e8f68319 43 CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
AnnaBridge 187:0387e8f68319 44 /* Enable HIRC48 clock (Internal RC 48MHz) */
AnnaBridge 187:0387e8f68319 45 CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
AnnaBridge 187:0387e8f68319 46
AnnaBridge 187:0387e8f68319 47 /* Wait for HIRC clock ready */
AnnaBridge 187:0387e8f68319 48 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
AnnaBridge 187:0387e8f68319 49 /* Wait for HXT clock ready */
AnnaBridge 187:0387e8f68319 50 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
AnnaBridge 187:0387e8f68319 51 /* Wait for LIRC clock ready */
AnnaBridge 187:0387e8f68319 52 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
AnnaBridge 187:0387e8f68319 53 /* Wait for LXT clock ready */
AnnaBridge 187:0387e8f68319 54 CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
AnnaBridge 187:0387e8f68319 55 /* Wait for HIRC48 clock ready */
AnnaBridge 187:0387e8f68319 56 CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
AnnaBridge 187:0387e8f68319 57
AnnaBridge 187:0387e8f68319 58
AnnaBridge 187:0387e8f68319 59 #if defined(NU_CHIP_MAJOR) && (NU_CHIP_MAJOR == 1UL)
AnnaBridge 187:0387e8f68319 60 /* NOTE: There is a reset halt issue with PLL in A version. Work around it
AnnaBridge 187:0387e8f68319 61 * by using HIRC48 instead of PLL as HCLK clock source. */
AnnaBridge 187:0387e8f68319 62
AnnaBridge 187:0387e8f68319 63 /* Trim HIRC48 to 48M against LXT */
AnnaBridge 187:0387e8f68319 64
AnnaBridge 187:0387e8f68319 65 /* Reset TISTS48M status flags */
AnnaBridge 187:0387e8f68319 66 SYS->TISTS48M |= (SYS_TISTS48M_FREQLOCK_Msk | SYS_TISTS48M_TFAILIF_Msk | SYS_TISTS48M_CLKERRIF_Msk);
AnnaBridge 187:0387e8f68319 67
AnnaBridge 187:0387e8f68319 68 /* With reference clock from LXT, start trimming HIRC48 to 48M */
AnnaBridge 187:0387e8f68319 69 SYS->TCTL48M = (SYS->TCTL48M & ~(SYS_TCTL48M_FREQSEL_Msk | SYS_TCTL48M_REFCKSEL_Msk)) | (0x01 << SYS_TCTL48M_FREQSEL_Pos) | (0x00 << SYS_TCTL48M_REFCKSEL_Pos);
AnnaBridge 187:0387e8f68319 70
AnnaBridge 187:0387e8f68319 71 /* Wait for HIRC48 clock locked */
AnnaBridge 187:0387e8f68319 72 while (1)
AnnaBridge 187:0387e8f68319 73 {
AnnaBridge 187:0387e8f68319 74 if (SYS->TISTS48M & SYS_TISTS48M_FREQLOCK_Msk)
AnnaBridge 187:0387e8f68319 75 {
AnnaBridge 187:0387e8f68319 76 break;
AnnaBridge 187:0387e8f68319 77 }
AnnaBridge 187:0387e8f68319 78 else if (SYS->TISTS48M & SYS_TISTS48M_TFAILIF_Msk)
AnnaBridge 187:0387e8f68319 79 {
AnnaBridge 187:0387e8f68319 80 error("HIRC48 auto-trim error: SYS_TISTS48M_TFAILIF_Msk");
AnnaBridge 187:0387e8f68319 81 }
AnnaBridge 187:0387e8f68319 82 else if (SYS->TISTS48M & SYS_TISTS48M_CLKERRIF_Msk)
AnnaBridge 187:0387e8f68319 83 {
AnnaBridge 187:0387e8f68319 84 error("HIRC48 auto-trim error: SYS_TISTS48M_CLKERRIF_Msk");
AnnaBridge 187:0387e8f68319 85 }
AnnaBridge 187:0387e8f68319 86 }
AnnaBridge 187:0387e8f68319 87
AnnaBridge 187:0387e8f68319 88 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC48, CLK_CLKDIV0_HCLK(1UL));
AnnaBridge 187:0387e8f68319 89 #else
AnnaBridge 187:0387e8f68319 90 /* Set core clock as 64M from PLL */
AnnaBridge 187:0387e8f68319 91 CLK_SetCoreClock(FREQ_64MHZ);
AnnaBridge 187:0387e8f68319 92 #endif
AnnaBridge 187:0387e8f68319 93
AnnaBridge 187:0387e8f68319 94 /* Update System Core Clock */
AnnaBridge 187:0387e8f68319 95 /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
AnnaBridge 187:0387e8f68319 96 SystemCoreClockUpdate();
AnnaBridge 187:0387e8f68319 97
AnnaBridge 187:0387e8f68319 98 /* Lock protected registers */
AnnaBridge 187:0387e8f68319 99 SYS_LockReg();
AnnaBridge 187:0387e8f68319 100 #else
AnnaBridge 187:0387e8f68319 101 SystemCoreClockUpdate();
AnnaBridge 187:0387e8f68319 102 #endif
AnnaBridge 187:0387e8f68319 103 }