mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_deprecated.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) Nordic Semiconductor ASA
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * 1. Redistributions of source code must retain the above copyright notice, this
<> 144:ef7eb2e8f9f7 9 * list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
<> 144:ef7eb2e8f9f7 16 * contributors to this software may be used to endorse or promote products
<> 144:ef7eb2e8f9f7 17 * derived from this software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 */
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #ifndef NRF51_DEPRECATED_H
<> 144:ef7eb2e8f9f7 34 #define NRF51_DEPRECATED_H
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*lint ++flb "Enter library region */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and
<> 144:ef7eb2e8f9f7 39 * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
<> 144:ef7eb2e8f9f7 40 * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* NVMC */
<> 144:ef7eb2e8f9f7 44 /* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
<> 144:ef7eb2e8f9f7 45 #define ERASEPROTECTEDPAGE ERASEPCR0
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* LPCOMP */
<> 144:ef7eb2e8f9f7 49 /* The interrupt ISR was renamed. Adding old name to the macros. */
<> 144:ef7eb2e8f9f7 50 #define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler
<> 144:ef7eb2e8f9f7 51 #define LPCOMP_COMP_IRQn LPCOMP_IRQn
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /* MPU */
<> 144:ef7eb2e8f9f7 55 /* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
<> 144:ef7eb2e8f9f7 56 #define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos
<> 144:ef7eb2e8f9f7 57 #define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk
<> 144:ef7eb2e8f9f7 58 #define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1
<> 144:ef7eb2e8f9f7 59 #define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* POWER */
<> 144:ef7eb2e8f9f7 63 /* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
<> 144:ef7eb2e8f9f7 64 #define POWER_RAMON_OFFRAM3_Pos (19UL)
<> 144:ef7eb2e8f9f7 65 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos)
<> 144:ef7eb2e8f9f7 66 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL)
<> 144:ef7eb2e8f9f7 67 #define POWER_RAMON_OFFRAM3_RAM3On (1UL)
<> 144:ef7eb2e8f9f7 68 /* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
<> 144:ef7eb2e8f9f7 69 #define POWER_RAMON_OFFRAM2_Pos (18UL)
<> 144:ef7eb2e8f9f7 70 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos)
<> 144:ef7eb2e8f9f7 71 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL)
<> 144:ef7eb2e8f9f7 72 #define POWER_RAMON_OFFRAM2_RAM2On (1UL)
<> 144:ef7eb2e8f9f7 73 /* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
<> 144:ef7eb2e8f9f7 74 #define POWER_RAMON_ONRAM3_Pos (3UL)
<> 144:ef7eb2e8f9f7 75 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos)
<> 144:ef7eb2e8f9f7 76 #define POWER_RAMON_ONRAM3_RAM3Off (0UL)
<> 144:ef7eb2e8f9f7 77 #define POWER_RAMON_ONRAM3_RAM3On (1UL)
<> 144:ef7eb2e8f9f7 78 /* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
<> 144:ef7eb2e8f9f7 79 #define POWER_RAMON_ONRAM2_Pos (2UL)
<> 144:ef7eb2e8f9f7 80 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos)
<> 144:ef7eb2e8f9f7 81 #define POWER_RAMON_ONRAM2_RAM2Off (0UL)
<> 144:ef7eb2e8f9f7 82 #define POWER_RAMON_ONRAM2_RAM2On (1UL)
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /* RADIO */
<> 144:ef7eb2e8f9f7 86 /* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
<> 144:ef7eb2e8f9f7 87 #define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm
<> 144:ef7eb2e8f9f7 88 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
<> 144:ef7eb2e8f9f7 89 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
<> 144:ef7eb2e8f9f7 90 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
<> 144:ef7eb2e8f9f7 91 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
<> 144:ef7eb2e8f9f7 92 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
<> 144:ef7eb2e8f9f7 93 /* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
<> 144:ef7eb2e8f9f7 94 #define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos
<> 144:ef7eb2e8f9f7 95 #define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk
<> 144:ef7eb2e8f9f7 96 #define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled
<> 144:ef7eb2e8f9f7 97 #define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled
<> 144:ef7eb2e8f9f7 98 /* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
<> 144:ef7eb2e8f9f7 99 #define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos
<> 144:ef7eb2e8f9f7 100 #define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk
<> 144:ef7eb2e8f9f7 101 #define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled
<> 144:ef7eb2e8f9f7 102 #define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* FICR */
<> 144:ef7eb2e8f9f7 106 /* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
<> 144:ef7eb2e8f9f7 107 #define SIZERAMBLOCK0 SIZERAMBLOCKS
<> 144:ef7eb2e8f9f7 108 #define SIZERAMBLOCK1 SIZERAMBLOCKS
<> 144:ef7eb2e8f9f7 109 #define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
<> 144:ef7eb2e8f9f7 110 #define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
<> 144:ef7eb2e8f9f7 111 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
<> 144:ef7eb2e8f9f7 112 #define DEVICEID0 DEVICEID[0]
<> 144:ef7eb2e8f9f7 113 #define DEVICEID1 DEVICEID[1]
<> 144:ef7eb2e8f9f7 114 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
<> 144:ef7eb2e8f9f7 115 #define ER0 ER[0]
<> 144:ef7eb2e8f9f7 116 #define ER1 ER[1]
<> 144:ef7eb2e8f9f7 117 #define ER2 ER[2]
<> 144:ef7eb2e8f9f7 118 #define ER3 ER[3]
<> 144:ef7eb2e8f9f7 119 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
<> 144:ef7eb2e8f9f7 120 #define IR0 IR[0]
<> 144:ef7eb2e8f9f7 121 #define IR1 IR[1]
<> 144:ef7eb2e8f9f7 122 #define IR2 IR[2]
<> 144:ef7eb2e8f9f7 123 #define IR3 IR[3]
<> 144:ef7eb2e8f9f7 124 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
<> 144:ef7eb2e8f9f7 125 #define DEVICEADDR0 DEVICEADDR[0]
<> 144:ef7eb2e8f9f7 126 #define DEVICEADDR1 DEVICEADDR[1]
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* PPI */
<> 144:ef7eb2e8f9f7 130 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
<> 144:ef7eb2e8f9f7 131 #define TASKS_CHG0EN TASKS_CHG[0].EN
<> 144:ef7eb2e8f9f7 132 #define TASKS_CHG0DIS TASKS_CHG[0].DIS
<> 144:ef7eb2e8f9f7 133 #define TASKS_CHG1EN TASKS_CHG[1].EN
<> 144:ef7eb2e8f9f7 134 #define TASKS_CHG1DIS TASKS_CHG[1].DIS
<> 144:ef7eb2e8f9f7 135 #define TASKS_CHG2EN TASKS_CHG[2].EN
<> 144:ef7eb2e8f9f7 136 #define TASKS_CHG2DIS TASKS_CHG[2].DIS
<> 144:ef7eb2e8f9f7 137 #define TASKS_CHG3EN TASKS_CHG[3].EN
<> 144:ef7eb2e8f9f7 138 #define TASKS_CHG3DIS TASKS_CHG[3].DIS
<> 144:ef7eb2e8f9f7 139 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
<> 144:ef7eb2e8f9f7 140 #define CH0_EEP CH[0].EEP
<> 144:ef7eb2e8f9f7 141 #define CH0_TEP CH[0].TEP
<> 144:ef7eb2e8f9f7 142 #define CH1_EEP CH[1].EEP
<> 144:ef7eb2e8f9f7 143 #define CH1_TEP CH[1].TEP
<> 144:ef7eb2e8f9f7 144 #define CH2_EEP CH[2].EEP
<> 144:ef7eb2e8f9f7 145 #define CH2_TEP CH[2].TEP
<> 144:ef7eb2e8f9f7 146 #define CH3_EEP CH[3].EEP
<> 144:ef7eb2e8f9f7 147 #define CH3_TEP CH[3].TEP
<> 144:ef7eb2e8f9f7 148 #define CH4_EEP CH[4].EEP
<> 144:ef7eb2e8f9f7 149 #define CH4_TEP CH[4].TEP
<> 144:ef7eb2e8f9f7 150 #define CH5_EEP CH[5].EEP
<> 144:ef7eb2e8f9f7 151 #define CH5_TEP CH[5].TEP
<> 144:ef7eb2e8f9f7 152 #define CH6_EEP CH[6].EEP
<> 144:ef7eb2e8f9f7 153 #define CH6_TEP CH[6].TEP
<> 144:ef7eb2e8f9f7 154 #define CH7_EEP CH[7].EEP
<> 144:ef7eb2e8f9f7 155 #define CH7_TEP CH[7].TEP
<> 144:ef7eb2e8f9f7 156 #define CH8_EEP CH[8].EEP
<> 144:ef7eb2e8f9f7 157 #define CH8_TEP CH[8].TEP
<> 144:ef7eb2e8f9f7 158 #define CH9_EEP CH[9].EEP
<> 144:ef7eb2e8f9f7 159 #define CH9_TEP CH[9].TEP
<> 144:ef7eb2e8f9f7 160 #define CH10_EEP CH[10].EEP
<> 144:ef7eb2e8f9f7 161 #define CH10_TEP CH[10].TEP
<> 144:ef7eb2e8f9f7 162 #define CH11_EEP CH[11].EEP
<> 144:ef7eb2e8f9f7 163 #define CH11_TEP CH[11].TEP
<> 144:ef7eb2e8f9f7 164 #define CH12_EEP CH[12].EEP
<> 144:ef7eb2e8f9f7 165 #define CH12_TEP CH[12].TEP
<> 144:ef7eb2e8f9f7 166 #define CH13_EEP CH[13].EEP
<> 144:ef7eb2e8f9f7 167 #define CH13_TEP CH[13].TEP
<> 144:ef7eb2e8f9f7 168 #define CH14_EEP CH[14].EEP
<> 144:ef7eb2e8f9f7 169 #define CH14_TEP CH[14].TEP
<> 144:ef7eb2e8f9f7 170 #define CH15_EEP CH[15].EEP
<> 144:ef7eb2e8f9f7 171 #define CH15_TEP CH[15].TEP
<> 144:ef7eb2e8f9f7 172 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
<> 144:ef7eb2e8f9f7 173 #define CHG0 CHG[0]
<> 144:ef7eb2e8f9f7 174 #define CHG1 CHG[1]
<> 144:ef7eb2e8f9f7 175 #define CHG2 CHG[2]
<> 144:ef7eb2e8f9f7 176 #define CHG3 CHG[3]
<> 144:ef7eb2e8f9f7 177 /* All bitfield macros for the CHGx registers therefore changed name. */
<> 144:ef7eb2e8f9f7 178 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
<> 144:ef7eb2e8f9f7 179 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
<> 144:ef7eb2e8f9f7 180 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
<> 144:ef7eb2e8f9f7 181 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
<> 144:ef7eb2e8f9f7 182 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
<> 144:ef7eb2e8f9f7 183 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
<> 144:ef7eb2e8f9f7 184 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
<> 144:ef7eb2e8f9f7 185 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
<> 144:ef7eb2e8f9f7 186 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
<> 144:ef7eb2e8f9f7 187 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
<> 144:ef7eb2e8f9f7 188 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
<> 144:ef7eb2e8f9f7 189 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
<> 144:ef7eb2e8f9f7 190 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
<> 144:ef7eb2e8f9f7 191 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
<> 144:ef7eb2e8f9f7 192 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
<> 144:ef7eb2e8f9f7 193 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
<> 144:ef7eb2e8f9f7 194 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
<> 144:ef7eb2e8f9f7 195 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
<> 144:ef7eb2e8f9f7 196 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
<> 144:ef7eb2e8f9f7 197 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
<> 144:ef7eb2e8f9f7 198 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
<> 144:ef7eb2e8f9f7 199 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
<> 144:ef7eb2e8f9f7 200 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
<> 144:ef7eb2e8f9f7 201 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
<> 144:ef7eb2e8f9f7 202 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
<> 144:ef7eb2e8f9f7 203 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
<> 144:ef7eb2e8f9f7 204 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
<> 144:ef7eb2e8f9f7 205 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
<> 144:ef7eb2e8f9f7 206 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
<> 144:ef7eb2e8f9f7 207 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
<> 144:ef7eb2e8f9f7 208 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
<> 144:ef7eb2e8f9f7 209 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
<> 144:ef7eb2e8f9f7 210 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
<> 144:ef7eb2e8f9f7 211 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
<> 144:ef7eb2e8f9f7 212 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
<> 144:ef7eb2e8f9f7 213 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
<> 144:ef7eb2e8f9f7 214 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
<> 144:ef7eb2e8f9f7 215 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
<> 144:ef7eb2e8f9f7 216 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
<> 144:ef7eb2e8f9f7 217 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
<> 144:ef7eb2e8f9f7 218 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
<> 144:ef7eb2e8f9f7 219 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
<> 144:ef7eb2e8f9f7 220 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
<> 144:ef7eb2e8f9f7 221 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
<> 144:ef7eb2e8f9f7 222 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
<> 144:ef7eb2e8f9f7 223 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
<> 144:ef7eb2e8f9f7 224 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
<> 144:ef7eb2e8f9f7 225 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
<> 144:ef7eb2e8f9f7 226 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
<> 144:ef7eb2e8f9f7 227 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
<> 144:ef7eb2e8f9f7 228 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
<> 144:ef7eb2e8f9f7 229 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
<> 144:ef7eb2e8f9f7 230 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
<> 144:ef7eb2e8f9f7 231 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
<> 144:ef7eb2e8f9f7 232 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
<> 144:ef7eb2e8f9f7 233 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
<> 144:ef7eb2e8f9f7 234 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
<> 144:ef7eb2e8f9f7 235 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
<> 144:ef7eb2e8f9f7 236 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
<> 144:ef7eb2e8f9f7 237 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
<> 144:ef7eb2e8f9f7 238 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
<> 144:ef7eb2e8f9f7 239 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
<> 144:ef7eb2e8f9f7 240 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
<> 144:ef7eb2e8f9f7 241 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
<> 144:ef7eb2e8f9f7 242 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
<> 144:ef7eb2e8f9f7 243 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
<> 144:ef7eb2e8f9f7 244 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
<> 144:ef7eb2e8f9f7 245 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
<> 144:ef7eb2e8f9f7 246 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
<> 144:ef7eb2e8f9f7 247 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
<> 144:ef7eb2e8f9f7 248 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
<> 144:ef7eb2e8f9f7 249 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
<> 144:ef7eb2e8f9f7 250 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
<> 144:ef7eb2e8f9f7 251 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
<> 144:ef7eb2e8f9f7 252 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
<> 144:ef7eb2e8f9f7 253 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
<> 144:ef7eb2e8f9f7 254 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
<> 144:ef7eb2e8f9f7 255 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
<> 144:ef7eb2e8f9f7 256 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
<> 144:ef7eb2e8f9f7 257 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
<> 144:ef7eb2e8f9f7 258 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
<> 144:ef7eb2e8f9f7 259 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
<> 144:ef7eb2e8f9f7 260 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
<> 144:ef7eb2e8f9f7 261 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
<> 144:ef7eb2e8f9f7 262 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
<> 144:ef7eb2e8f9f7 263 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
<> 144:ef7eb2e8f9f7 264 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
<> 144:ef7eb2e8f9f7 265 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
<> 144:ef7eb2e8f9f7 266 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
<> 144:ef7eb2e8f9f7 267 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
<> 144:ef7eb2e8f9f7 268 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
<> 144:ef7eb2e8f9f7 269 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
<> 144:ef7eb2e8f9f7 270 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
<> 144:ef7eb2e8f9f7 271 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
<> 144:ef7eb2e8f9f7 272 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
<> 144:ef7eb2e8f9f7 273 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
<> 144:ef7eb2e8f9f7 274 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
<> 144:ef7eb2e8f9f7 275 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
<> 144:ef7eb2e8f9f7 276 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
<> 144:ef7eb2e8f9f7 277 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
<> 144:ef7eb2e8f9f7 278 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
<> 144:ef7eb2e8f9f7 279 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
<> 144:ef7eb2e8f9f7 280 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
<> 144:ef7eb2e8f9f7 281 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
<> 144:ef7eb2e8f9f7 282 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
<> 144:ef7eb2e8f9f7 283 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
<> 144:ef7eb2e8f9f7 284 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
<> 144:ef7eb2e8f9f7 285 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
<> 144:ef7eb2e8f9f7 286 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
<> 144:ef7eb2e8f9f7 287 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
<> 144:ef7eb2e8f9f7 288 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
<> 144:ef7eb2e8f9f7 289 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
<> 144:ef7eb2e8f9f7 290 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
<> 144:ef7eb2e8f9f7 291 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
<> 144:ef7eb2e8f9f7 292 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
<> 144:ef7eb2e8f9f7 293 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
<> 144:ef7eb2e8f9f7 294 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
<> 144:ef7eb2e8f9f7 295 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
<> 144:ef7eb2e8f9f7 296 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
<> 144:ef7eb2e8f9f7 297 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
<> 144:ef7eb2e8f9f7 298 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
<> 144:ef7eb2e8f9f7 299 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
<> 144:ef7eb2e8f9f7 300 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
<> 144:ef7eb2e8f9f7 301 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
<> 144:ef7eb2e8f9f7 302 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
<> 144:ef7eb2e8f9f7 303 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
<> 144:ef7eb2e8f9f7 304 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
<> 144:ef7eb2e8f9f7 305 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
<> 144:ef7eb2e8f9f7 306 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
<> 144:ef7eb2e8f9f7 307 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
<> 144:ef7eb2e8f9f7 308 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
<> 144:ef7eb2e8f9f7 309 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
<> 144:ef7eb2e8f9f7 310 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
<> 144:ef7eb2e8f9f7 311 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
<> 144:ef7eb2e8f9f7 312 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
<> 144:ef7eb2e8f9f7 313 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
<> 144:ef7eb2e8f9f7 314 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
<> 144:ef7eb2e8f9f7 315 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
<> 144:ef7eb2e8f9f7 316 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
<> 144:ef7eb2e8f9f7 317 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
<> 144:ef7eb2e8f9f7 318 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
<> 144:ef7eb2e8f9f7 319 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
<> 144:ef7eb2e8f9f7 320 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
<> 144:ef7eb2e8f9f7 321 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
<> 144:ef7eb2e8f9f7 322 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
<> 144:ef7eb2e8f9f7 323 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
<> 144:ef7eb2e8f9f7 324 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
<> 144:ef7eb2e8f9f7 325 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
<> 144:ef7eb2e8f9f7 326 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
<> 144:ef7eb2e8f9f7 327 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
<> 144:ef7eb2e8f9f7 328 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
<> 144:ef7eb2e8f9f7 329 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
<> 144:ef7eb2e8f9f7 330 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
<> 144:ef7eb2e8f9f7 331 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
<> 144:ef7eb2e8f9f7 332 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
<> 144:ef7eb2e8f9f7 333 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
<> 144:ef7eb2e8f9f7 334 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
<> 144:ef7eb2e8f9f7 335 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
<> 144:ef7eb2e8f9f7 336 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
<> 144:ef7eb2e8f9f7 337 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
<> 144:ef7eb2e8f9f7 338 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
<> 144:ef7eb2e8f9f7 339 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
<> 144:ef7eb2e8f9f7 340 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
<> 144:ef7eb2e8f9f7 341 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
<> 144:ef7eb2e8f9f7 342 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
<> 144:ef7eb2e8f9f7 343 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
<> 144:ef7eb2e8f9f7 344 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
<> 144:ef7eb2e8f9f7 345 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
<> 144:ef7eb2e8f9f7 346 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
<> 144:ef7eb2e8f9f7 347 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
<> 144:ef7eb2e8f9f7 348 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
<> 144:ef7eb2e8f9f7 349 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
<> 144:ef7eb2e8f9f7 350 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
<> 144:ef7eb2e8f9f7 351 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
<> 144:ef7eb2e8f9f7 352 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
<> 144:ef7eb2e8f9f7 353 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
<> 144:ef7eb2e8f9f7 354 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
<> 144:ef7eb2e8f9f7 355 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
<> 144:ef7eb2e8f9f7 356 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
<> 144:ef7eb2e8f9f7 357 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
<> 144:ef7eb2e8f9f7 358 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
<> 144:ef7eb2e8f9f7 359 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
<> 144:ef7eb2e8f9f7 360 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
<> 144:ef7eb2e8f9f7 361 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
<> 144:ef7eb2e8f9f7 362 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
<> 144:ef7eb2e8f9f7 363 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
<> 144:ef7eb2e8f9f7 364 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
<> 144:ef7eb2e8f9f7 365 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
<> 144:ef7eb2e8f9f7 366 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
<> 144:ef7eb2e8f9f7 367 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
<> 144:ef7eb2e8f9f7 368 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
<> 144:ef7eb2e8f9f7 369 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
<> 144:ef7eb2e8f9f7 370 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
<> 144:ef7eb2e8f9f7 371 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
<> 144:ef7eb2e8f9f7 372 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
<> 144:ef7eb2e8f9f7 373 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
<> 144:ef7eb2e8f9f7 374 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
<> 144:ef7eb2e8f9f7 375 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
<> 144:ef7eb2e8f9f7 376 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
<> 144:ef7eb2e8f9f7 377 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
<> 144:ef7eb2e8f9f7 378 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
<> 144:ef7eb2e8f9f7 379 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
<> 144:ef7eb2e8f9f7 380 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
<> 144:ef7eb2e8f9f7 381 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
<> 144:ef7eb2e8f9f7 382 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
<> 144:ef7eb2e8f9f7 383 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
<> 144:ef7eb2e8f9f7 384 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
<> 144:ef7eb2e8f9f7 385 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
<> 144:ef7eb2e8f9f7 386 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
<> 144:ef7eb2e8f9f7 387 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
<> 144:ef7eb2e8f9f7 388 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
<> 144:ef7eb2e8f9f7 389 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
<> 144:ef7eb2e8f9f7 390 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
<> 144:ef7eb2e8f9f7 391 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
<> 144:ef7eb2e8f9f7 392 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
<> 144:ef7eb2e8f9f7 393 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
<> 144:ef7eb2e8f9f7 394 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
<> 144:ef7eb2e8f9f7 395 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
<> 144:ef7eb2e8f9f7 396 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
<> 144:ef7eb2e8f9f7 397 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
<> 144:ef7eb2e8f9f7 398 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
<> 144:ef7eb2e8f9f7 399 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
<> 144:ef7eb2e8f9f7 400 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
<> 144:ef7eb2e8f9f7 401 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
<> 144:ef7eb2e8f9f7 402 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
<> 144:ef7eb2e8f9f7 403 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
<> 144:ef7eb2e8f9f7 404 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
<> 144:ef7eb2e8f9f7 405 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
<> 144:ef7eb2e8f9f7 406 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
<> 144:ef7eb2e8f9f7 407 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
<> 144:ef7eb2e8f9f7 408 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
<> 144:ef7eb2e8f9f7 409 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
<> 144:ef7eb2e8f9f7 410 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
<> 144:ef7eb2e8f9f7 411 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
<> 144:ef7eb2e8f9f7 412 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
<> 144:ef7eb2e8f9f7 413 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
<> 144:ef7eb2e8f9f7 414 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
<> 144:ef7eb2e8f9f7 415 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
<> 144:ef7eb2e8f9f7 416 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
<> 144:ef7eb2e8f9f7 417 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
<> 144:ef7eb2e8f9f7 418 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
<> 144:ef7eb2e8f9f7 419 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
<> 144:ef7eb2e8f9f7 420 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
<> 144:ef7eb2e8f9f7 421 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
<> 144:ef7eb2e8f9f7 422 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
<> 144:ef7eb2e8f9f7 423 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
<> 144:ef7eb2e8f9f7 424 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
<> 144:ef7eb2e8f9f7 425 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
<> 144:ef7eb2e8f9f7 426 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
<> 144:ef7eb2e8f9f7 427 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
<> 144:ef7eb2e8f9f7 428 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
<> 144:ef7eb2e8f9f7 429 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
<> 144:ef7eb2e8f9f7 430 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
<> 144:ef7eb2e8f9f7 431 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
<> 144:ef7eb2e8f9f7 432 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
<> 144:ef7eb2e8f9f7 433 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /*lint --flb "Leave library region" */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 #endif /* NRF51_DEPRECATED_H */
<> 144:ef7eb2e8f9f7 440