mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) Nordic Semiconductor ASA
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * 1. Redistributions of source code must retain the above copyright notice, this
<> 144:ef7eb2e8f9f7 9 * list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
<> 144:ef7eb2e8f9f7 12 * list of conditions and the following disclaimer in the documentation and/or
<> 144:ef7eb2e8f9f7 13 * other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
<> 144:ef7eb2e8f9f7 16 * contributors to this software may be used to endorse or promote products
<> 144:ef7eb2e8f9f7 17 * derived from this software without specific prior written permission.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 */
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #ifndef NRF51_H
<> 144:ef7eb2e8f9f7 34 #define NRF51_H
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 37 extern "C" {
<> 144:ef7eb2e8f9f7 38 #endif
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /* ------------------------- Interrupt Number Definition ------------------------ */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 typedef enum {
<> 144:ef7eb2e8f9f7 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
<> 144:ef7eb2e8f9f7 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
<> 144:ef7eb2e8f9f7 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
<> 144:ef7eb2e8f9f7 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
<> 144:ef7eb2e8f9f7 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
<> 144:ef7eb2e8f9f7 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
<> 144:ef7eb2e8f9f7 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
<> 144:ef7eb2e8f9f7 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
<> 144:ef7eb2e8f9f7 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
<> 144:ef7eb2e8f9f7 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
<> 144:ef7eb2e8f9f7 54 RADIO_IRQn = 1, /*!< 1 RADIO */
<> 144:ef7eb2e8f9f7 55 UART0_IRQn = 2, /*!< 2 UART0 */
<> 144:ef7eb2e8f9f7 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
<> 144:ef7eb2e8f9f7 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
<> 144:ef7eb2e8f9f7 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
<> 144:ef7eb2e8f9f7 59 ADC_IRQn = 7, /*!< 7 ADC */
<> 144:ef7eb2e8f9f7 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
<> 144:ef7eb2e8f9f7 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
<> 144:ef7eb2e8f9f7 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
<> 144:ef7eb2e8f9f7 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
<> 144:ef7eb2e8f9f7 64 TEMP_IRQn = 12, /*!< 12 TEMP */
<> 144:ef7eb2e8f9f7 65 RNG_IRQn = 13, /*!< 13 RNG */
<> 144:ef7eb2e8f9f7 66 ECB_IRQn = 14, /*!< 14 ECB */
<> 144:ef7eb2e8f9f7 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
<> 144:ef7eb2e8f9f7 68 WDT_IRQn = 16, /*!< 16 WDT */
<> 144:ef7eb2e8f9f7 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
<> 144:ef7eb2e8f9f7 70 QDEC_IRQn = 18, /*!< 18 QDEC */
<> 144:ef7eb2e8f9f7 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
<> 144:ef7eb2e8f9f7 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
<> 144:ef7eb2e8f9f7 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
<> 144:ef7eb2e8f9f7 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
<> 144:ef7eb2e8f9f7 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
<> 144:ef7eb2e8f9f7 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
<> 144:ef7eb2e8f9f7 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
<> 144:ef7eb2e8f9f7 78 } IRQn_Type;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @addtogroup Configuration_of_CMSIS
<> 144:ef7eb2e8f9f7 82 * @{
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 87 /* ================ Processor and Core Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 88 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
<> 144:ef7eb2e8f9f7 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
<> 144:ef7eb2e8f9f7 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 95 /** @} */ /* End of group Configuration_of_CMSIS */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
<> 144:ef7eb2e8f9f7 98 #include "system_nrf51.h" /*!< nrf51 System */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 102 /* ================ Device Specific Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 103 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup Device_Peripheral_Registers
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* ------------------- Start of section using anonymous unions ------------------ */
<> 144:ef7eb2e8f9f7 112 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 113 #pragma push
<> 144:ef7eb2e8f9f7 114 #pragma anon_unions
<> 144:ef7eb2e8f9f7 115 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 116 #pragma language=extended
<> 144:ef7eb2e8f9f7 117 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 118 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 119 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 120 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 121 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 122 #pragma warning 586
<> 144:ef7eb2e8f9f7 123 #else
<> 144:ef7eb2e8f9f7 124 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 125 #endif
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 typedef struct {
<> 144:ef7eb2e8f9f7 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
<> 144:ef7eb2e8f9f7 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
<> 144:ef7eb2e8f9f7 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
<> 144:ef7eb2e8f9f7 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
<> 144:ef7eb2e8f9f7 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
<> 144:ef7eb2e8f9f7 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
<> 144:ef7eb2e8f9f7 135 } AMLI_RAMPRI_Type;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 typedef struct {
<> 144:ef7eb2e8f9f7 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
<> 144:ef7eb2e8f9f7 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
<> 144:ef7eb2e8f9f7 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
<> 144:ef7eb2e8f9f7 141 } SPIM_PSEL_Type;
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 typedef struct {
<> 144:ef7eb2e8f9f7 144 __IO uint32_t PTR; /*!< Data pointer. */
<> 144:ef7eb2e8f9f7 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
<> 144:ef7eb2e8f9f7 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
<> 144:ef7eb2e8f9f7 147 } SPIM_RXD_Type;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 typedef struct {
<> 144:ef7eb2e8f9f7 150 __IO uint32_t PTR; /*!< Data pointer. */
<> 144:ef7eb2e8f9f7 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
<> 144:ef7eb2e8f9f7 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
<> 144:ef7eb2e8f9f7 153 } SPIM_TXD_Type;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 typedef struct {
<> 144:ef7eb2e8f9f7 156 __O uint32_t EN; /*!< Enable channel group. */
<> 144:ef7eb2e8f9f7 157 __O uint32_t DIS; /*!< Disable channel group. */
<> 144:ef7eb2e8f9f7 158 } PPI_TASKS_CHG_Type;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 typedef struct {
<> 144:ef7eb2e8f9f7 161 __IO uint32_t EEP; /*!< Channel event end-point. */
<> 144:ef7eb2e8f9f7 162 __IO uint32_t TEP; /*!< Channel task end-point. */
<> 144:ef7eb2e8f9f7 163 } PPI_CH_Type;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 167 /* ================ POWER ================ */
<> 144:ef7eb2e8f9f7 168 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /**
<> 144:ef7eb2e8f9f7 172 * @brief Power Control. (POWER)
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 typedef struct { /*!< POWER Structure */
<> 144:ef7eb2e8f9f7 176 __I uint32_t RESERVED0[30];
<> 144:ef7eb2e8f9f7 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
<> 144:ef7eb2e8f9f7 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
<> 144:ef7eb2e8f9f7 179 __I uint32_t RESERVED1[34];
<> 144:ef7eb2e8f9f7 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
<> 144:ef7eb2e8f9f7 181 __I uint32_t RESERVED2[126];
<> 144:ef7eb2e8f9f7 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 184 __I uint32_t RESERVED3[61];
<> 144:ef7eb2e8f9f7 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
<> 144:ef7eb2e8f9f7 186 __I uint32_t RESERVED4[9];
<> 144:ef7eb2e8f9f7 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
<> 144:ef7eb2e8f9f7 188 __I uint32_t RESERVED5[53];
<> 144:ef7eb2e8f9f7 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
<> 144:ef7eb2e8f9f7 190 __I uint32_t RESERVED6[3];
<> 144:ef7eb2e8f9f7 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
<> 144:ef7eb2e8f9f7 192 __I uint32_t RESERVED7[2];
<> 144:ef7eb2e8f9f7 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
<> 144:ef7eb2e8f9f7 194 register. */
<> 144:ef7eb2e8f9f7 195 __I uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 196 __IO uint32_t RAMON; /*!< Ram on/off. */
<> 144:ef7eb2e8f9f7 197 __I uint32_t RESERVED9[7];
<> 144:ef7eb2e8f9f7 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
<> 144:ef7eb2e8f9f7 199 is a retained register. */
<> 144:ef7eb2e8f9f7 200 __I uint32_t RESERVED10[3];
<> 144:ef7eb2e8f9f7 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
<> 144:ef7eb2e8f9f7 202 __I uint32_t RESERVED11[8];
<> 144:ef7eb2e8f9f7 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
<> 144:ef7eb2e8f9f7 204 __I uint32_t RESERVED12[291];
<> 144:ef7eb2e8f9f7 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
<> 144:ef7eb2e8f9f7 206 } NRF_POWER_Type;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 210 /* ================ CLOCK ================ */
<> 144:ef7eb2e8f9f7 211 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @brief Clock control. (CLOCK)
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 typedef struct { /*!< CLOCK Structure */
<> 144:ef7eb2e8f9f7 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
<> 144:ef7eb2e8f9f7 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
<> 144:ef7eb2e8f9f7 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
<> 144:ef7eb2e8f9f7 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
<> 144:ef7eb2e8f9f7 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
<> 144:ef7eb2e8f9f7 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
<> 144:ef7eb2e8f9f7 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
<> 144:ef7eb2e8f9f7 226 __I uint32_t RESERVED0[57];
<> 144:ef7eb2e8f9f7 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
<> 144:ef7eb2e8f9f7 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
<> 144:ef7eb2e8f9f7 229 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
<> 144:ef7eb2e8f9f7 232 __I uint32_t RESERVED2[124];
<> 144:ef7eb2e8f9f7 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 235 __I uint32_t RESERVED3[63];
<> 144:ef7eb2e8f9f7 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
<> 144:ef7eb2e8f9f7 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
<> 144:ef7eb2e8f9f7 238 __I uint32_t RESERVED4;
<> 144:ef7eb2e8f9f7 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
<> 144:ef7eb2e8f9f7 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
<> 144:ef7eb2e8f9f7 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
<> 144:ef7eb2e8f9f7 242 triggered. */
<> 144:ef7eb2e8f9f7 243 __I uint32_t RESERVED5[62];
<> 144:ef7eb2e8f9f7 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
<> 144:ef7eb2e8f9f7 245 __I uint32_t RESERVED6[7];
<> 144:ef7eb2e8f9f7 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
<> 144:ef7eb2e8f9f7 247 __I uint32_t RESERVED7[5];
<> 144:ef7eb2e8f9f7 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
<> 144:ef7eb2e8f9f7 249 } NRF_CLOCK_Type;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 253 /* ================ MPU ================ */
<> 144:ef7eb2e8f9f7 254 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Memory Protection Unit. (MPU)
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 typedef struct { /*!< MPU Structure */
<> 144:ef7eb2e8f9f7 262 __I uint32_t RESERVED0[330];
<> 144:ef7eb2e8f9f7 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
<> 144:ef7eb2e8f9f7 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
<> 144:ef7eb2e8f9f7 265 __I uint32_t RESERVED1[52];
<> 144:ef7eb2e8f9f7 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
<> 144:ef7eb2e8f9f7 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
<> 144:ef7eb2e8f9f7 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
<> 144:ef7eb2e8f9f7 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
<> 144:ef7eb2e8f9f7 270 } NRF_MPU_Type;
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 274 /* ================ AMLI ================ */
<> 144:ef7eb2e8f9f7 275 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief AHB Multi-Layer Interface. (AMLI)
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 typedef struct { /*!< AMLI Structure */
<> 144:ef7eb2e8f9f7 283 __I uint32_t RESERVED0[896];
<> 144:ef7eb2e8f9f7 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
<> 144:ef7eb2e8f9f7 285 } NRF_AMLI_Type;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 289 /* ================ RADIO ================ */
<> 144:ef7eb2e8f9f7 290 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief The radio. (RADIO)
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 typedef struct { /*!< RADIO Structure */
<> 144:ef7eb2e8f9f7 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
<> 144:ef7eb2e8f9f7 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
<> 144:ef7eb2e8f9f7 300 __O uint32_t TASKS_START; /*!< Start radio. */
<> 144:ef7eb2e8f9f7 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
<> 144:ef7eb2e8f9f7 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
<> 144:ef7eb2e8f9f7 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
<> 144:ef7eb2e8f9f7 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
<> 144:ef7eb2e8f9f7 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
<> 144:ef7eb2e8f9f7 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
<> 144:ef7eb2e8f9f7 307 __I uint32_t RESERVED0[55];
<> 144:ef7eb2e8f9f7 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
<> 144:ef7eb2e8f9f7 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
<> 144:ef7eb2e8f9f7 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
<> 144:ef7eb2e8f9f7 311 __IO uint32_t EVENTS_END; /*!< End event. */
<> 144:ef7eb2e8f9f7 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
<> 144:ef7eb2e8f9f7 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
<> 144:ef7eb2e8f9f7 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
<> 144:ef7eb2e8f9f7 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
<> 144:ef7eb2e8f9f7 316 sample is ready for readout at the RSSISAMPLE register. */
<> 144:ef7eb2e8f9f7 317 __I uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
<> 144:ef7eb2e8f9f7 319 __I uint32_t RESERVED2[53];
<> 144:ef7eb2e8f9f7 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
<> 144:ef7eb2e8f9f7 321 __I uint32_t RESERVED3[64];
<> 144:ef7eb2e8f9f7 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 324 __I uint32_t RESERVED4[61];
<> 144:ef7eb2e8f9f7 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
<> 144:ef7eb2e8f9f7 326 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 327 __I uint32_t RXMATCH; /*!< Received address. */
<> 144:ef7eb2e8f9f7 328 __I uint32_t RXCRC; /*!< Received CRC. */
<> 144:ef7eb2e8f9f7 329 __I uint32_t DAI; /*!< Device address match index. */
<> 144:ef7eb2e8f9f7 330 __I uint32_t RESERVED6[60];
<> 144:ef7eb2e8f9f7 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
<> 144:ef7eb2e8f9f7 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
<> 144:ef7eb2e8f9f7 333 __IO uint32_t TXPOWER; /*!< Output power. */
<> 144:ef7eb2e8f9f7 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
<> 144:ef7eb2e8f9f7 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
<> 144:ef7eb2e8f9f7 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
<> 144:ef7eb2e8f9f7 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
<> 144:ef7eb2e8f9f7 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
<> 144:ef7eb2e8f9f7 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
<> 144:ef7eb2e8f9f7 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
<> 144:ef7eb2e8f9f7 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
<> 144:ef7eb2e8f9f7 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
<> 144:ef7eb2e8f9f7 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
<> 144:ef7eb2e8f9f7 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
<> 144:ef7eb2e8f9f7 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
<> 144:ef7eb2e8f9f7 346 __IO uint32_t TEST; /*!< Test features enable register. */
<> 144:ef7eb2e8f9f7 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
<> 144:ef7eb2e8f9f7 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
<> 144:ef7eb2e8f9f7 349 __I uint32_t RESERVED7;
<> 144:ef7eb2e8f9f7 350 __I uint32_t STATE; /*!< Current radio state. */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
<> 144:ef7eb2e8f9f7 352 __I uint32_t RESERVED8[2];
<> 144:ef7eb2e8f9f7 353 __IO uint32_t BCC; /*!< Bit counter compare. */
<> 144:ef7eb2e8f9f7 354 __I uint32_t RESERVED9[39];
<> 144:ef7eb2e8f9f7 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
<> 144:ef7eb2e8f9f7 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
<> 144:ef7eb2e8f9f7 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
<> 144:ef7eb2e8f9f7 358 __I uint32_t RESERVED10[56];
<> 144:ef7eb2e8f9f7 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
<> 144:ef7eb2e8f9f7 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
<> 144:ef7eb2e8f9f7 364 __I uint32_t RESERVED11[561];
<> 144:ef7eb2e8f9f7 365 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 366 } NRF_RADIO_Type;
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 370 /* ================ UART ================ */
<> 144:ef7eb2e8f9f7 371 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 typedef struct { /*!< UART Structure */
<> 144:ef7eb2e8f9f7 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
<> 144:ef7eb2e8f9f7 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
<> 144:ef7eb2e8f9f7 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
<> 144:ef7eb2e8f9f7 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
<> 144:ef7eb2e8f9f7 383 __I uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
<> 144:ef7eb2e8f9f7 385 __I uint32_t RESERVED1[56];
<> 144:ef7eb2e8f9f7 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
<> 144:ef7eb2e8f9f7 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
<> 144:ef7eb2e8f9f7 389 __I uint32_t RESERVED2[4];
<> 144:ef7eb2e8f9f7 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
<> 144:ef7eb2e8f9f7 391 __I uint32_t RESERVED3;
<> 144:ef7eb2e8f9f7 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
<> 144:ef7eb2e8f9f7 393 __I uint32_t RESERVED4[7];
<> 144:ef7eb2e8f9f7 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
<> 144:ef7eb2e8f9f7 395 __I uint32_t RESERVED5[46];
<> 144:ef7eb2e8f9f7 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
<> 144:ef7eb2e8f9f7 397 __I uint32_t RESERVED6[64];
<> 144:ef7eb2e8f9f7 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 400 __I uint32_t RESERVED7[93];
<> 144:ef7eb2e8f9f7 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
<> 144:ef7eb2e8f9f7 402 __I uint32_t RESERVED8[31];
<> 144:ef7eb2e8f9f7 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
<> 144:ef7eb2e8f9f7 404 __I uint32_t RESERVED9;
<> 144:ef7eb2e8f9f7 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
<> 144:ef7eb2e8f9f7 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
<> 144:ef7eb2e8f9f7 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
<> 144:ef7eb2e8f9f7 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
<> 144:ef7eb2e8f9f7 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
<> 144:ef7eb2e8f9f7 410 Once read the character is consumed. If read when no character
<> 144:ef7eb2e8f9f7 411 available, the UART will stop working. */
<> 144:ef7eb2e8f9f7 412 __O uint32_t TXD; /*!< TXD register. */
<> 144:ef7eb2e8f9f7 413 __I uint32_t RESERVED10;
<> 144:ef7eb2e8f9f7 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
<> 144:ef7eb2e8f9f7 415 __I uint32_t RESERVED11[17];
<> 144:ef7eb2e8f9f7 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
<> 144:ef7eb2e8f9f7 417 __I uint32_t RESERVED12[675];
<> 144:ef7eb2e8f9f7 418 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 419 } NRF_UART_Type;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 423 /* ================ SPI ================ */
<> 144:ef7eb2e8f9f7 424 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /**
<> 144:ef7eb2e8f9f7 428 * @brief SPI master 0. (SPI)
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 typedef struct { /*!< SPI Structure */
<> 144:ef7eb2e8f9f7 432 __I uint32_t RESERVED0[66];
<> 144:ef7eb2e8f9f7 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
<> 144:ef7eb2e8f9f7 434 __I uint32_t RESERVED1[126];
<> 144:ef7eb2e8f9f7 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 437 __I uint32_t RESERVED2[125];
<> 144:ef7eb2e8f9f7 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
<> 144:ef7eb2e8f9f7 439 __I uint32_t RESERVED3;
<> 144:ef7eb2e8f9f7 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
<> 144:ef7eb2e8f9f7 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
<> 144:ef7eb2e8f9f7 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
<> 144:ef7eb2e8f9f7 443 __I uint32_t RESERVED4;
<> 144:ef7eb2e8f9f7 444 __I uint32_t RXD; /*!< RX data. */
<> 144:ef7eb2e8f9f7 445 __IO uint32_t TXD; /*!< TX data. */
<> 144:ef7eb2e8f9f7 446 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
<> 144:ef7eb2e8f9f7 448 __I uint32_t RESERVED6[11];
<> 144:ef7eb2e8f9f7 449 __IO uint32_t CONFIG; /*!< Configuration register. */
<> 144:ef7eb2e8f9f7 450 __I uint32_t RESERVED7[681];
<> 144:ef7eb2e8f9f7 451 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 452 } NRF_SPI_Type;
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 456 /* ================ TWI ================ */
<> 144:ef7eb2e8f9f7 457 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @brief Two-wire interface master 0. (TWI)
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 typedef struct { /*!< TWI Structure */
<> 144:ef7eb2e8f9f7 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
<> 144:ef7eb2e8f9f7 466 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
<> 144:ef7eb2e8f9f7 468 __I uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
<> 144:ef7eb2e8f9f7 470 __I uint32_t RESERVED2;
<> 144:ef7eb2e8f9f7 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
<> 144:ef7eb2e8f9f7 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
<> 144:ef7eb2e8f9f7 473 __I uint32_t RESERVED3[56];
<> 144:ef7eb2e8f9f7 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
<> 144:ef7eb2e8f9f7 476 __I uint32_t RESERVED4[4];
<> 144:ef7eb2e8f9f7 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
<> 144:ef7eb2e8f9f7 478 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
<> 144:ef7eb2e8f9f7 480 __I uint32_t RESERVED6[4];
<> 144:ef7eb2e8f9f7 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
<> 144:ef7eb2e8f9f7 482 __I uint32_t RESERVED7[3];
<> 144:ef7eb2e8f9f7 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
<> 144:ef7eb2e8f9f7 484 __I uint32_t RESERVED8[45];
<> 144:ef7eb2e8f9f7 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
<> 144:ef7eb2e8f9f7 486 __I uint32_t RESERVED9[64];
<> 144:ef7eb2e8f9f7 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 489 __I uint32_t RESERVED10[110];
<> 144:ef7eb2e8f9f7 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
<> 144:ef7eb2e8f9f7 491 __I uint32_t RESERVED11[14];
<> 144:ef7eb2e8f9f7 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
<> 144:ef7eb2e8f9f7 493 __I uint32_t RESERVED12;
<> 144:ef7eb2e8f9f7 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
<> 144:ef7eb2e8f9f7 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
<> 144:ef7eb2e8f9f7 496 __I uint32_t RESERVED13[2];
<> 144:ef7eb2e8f9f7 497 __I uint32_t RXD; /*!< RX data register. */
<> 144:ef7eb2e8f9f7 498 __IO uint32_t TXD; /*!< TX data register. */
<> 144:ef7eb2e8f9f7 499 __I uint32_t RESERVED14;
<> 144:ef7eb2e8f9f7 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
<> 144:ef7eb2e8f9f7 501 __I uint32_t RESERVED15[24];
<> 144:ef7eb2e8f9f7 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
<> 144:ef7eb2e8f9f7 503 __I uint32_t RESERVED16[668];
<> 144:ef7eb2e8f9f7 504 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 505 } NRF_TWI_Type;
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 509 /* ================ SPIS ================ */
<> 144:ef7eb2e8f9f7 510 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @brief SPI slave 1. (SPIS)
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 typedef struct { /*!< SPIS Structure */
<> 144:ef7eb2e8f9f7 518 __I uint32_t RESERVED0[9];
<> 144:ef7eb2e8f9f7 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
<> 144:ef7eb2e8f9f7 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
<> 144:ef7eb2e8f9f7 521 __I uint32_t RESERVED1[54];
<> 144:ef7eb2e8f9f7 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
<> 144:ef7eb2e8f9f7 523 __I uint32_t RESERVED2[2];
<> 144:ef7eb2e8f9f7 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
<> 144:ef7eb2e8f9f7 525 __I uint32_t RESERVED3[5];
<> 144:ef7eb2e8f9f7 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
<> 144:ef7eb2e8f9f7 527 __I uint32_t RESERVED4[53];
<> 144:ef7eb2e8f9f7 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
<> 144:ef7eb2e8f9f7 529 __I uint32_t RESERVED5[64];
<> 144:ef7eb2e8f9f7 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 532 __I uint32_t RESERVED6[61];
<> 144:ef7eb2e8f9f7 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
<> 144:ef7eb2e8f9f7 534 __I uint32_t RESERVED7[15];
<> 144:ef7eb2e8f9f7 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
<> 144:ef7eb2e8f9f7 536 __I uint32_t RESERVED8[47];
<> 144:ef7eb2e8f9f7 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
<> 144:ef7eb2e8f9f7 538 __I uint32_t RESERVED9;
<> 144:ef7eb2e8f9f7 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
<> 144:ef7eb2e8f9f7 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
<> 144:ef7eb2e8f9f7 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
<> 144:ef7eb2e8f9f7 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
<> 144:ef7eb2e8f9f7 543 __I uint32_t RESERVED10[7];
<> 144:ef7eb2e8f9f7 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
<> 144:ef7eb2e8f9f7 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
<> 144:ef7eb2e8f9f7 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
<> 144:ef7eb2e8f9f7 547 __I uint32_t RESERVED11;
<> 144:ef7eb2e8f9f7 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
<> 144:ef7eb2e8f9f7 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
<> 144:ef7eb2e8f9f7 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
<> 144:ef7eb2e8f9f7 551 __I uint32_t RESERVED12;
<> 144:ef7eb2e8f9f7 552 __IO uint32_t CONFIG; /*!< Configuration register. */
<> 144:ef7eb2e8f9f7 553 __I uint32_t RESERVED13;
<> 144:ef7eb2e8f9f7 554 __IO uint32_t DEF; /*!< Default character. */
<> 144:ef7eb2e8f9f7 555 __I uint32_t RESERVED14[24];
<> 144:ef7eb2e8f9f7 556 __IO uint32_t ORC; /*!< Over-read character. */
<> 144:ef7eb2e8f9f7 557 __I uint32_t RESERVED15[654];
<> 144:ef7eb2e8f9f7 558 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 559 } NRF_SPIS_Type;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 563 /* ================ SPIM ================ */
<> 144:ef7eb2e8f9f7 564 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @brief SPI master with easyDMA 1. (SPIM)
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 typedef struct { /*!< SPIM Structure */
<> 144:ef7eb2e8f9f7 572 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
<> 144:ef7eb2e8f9f7 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
<> 144:ef7eb2e8f9f7 575 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
<> 144:ef7eb2e8f9f7 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
<> 144:ef7eb2e8f9f7 578 __I uint32_t RESERVED2[56];
<> 144:ef7eb2e8f9f7 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
<> 144:ef7eb2e8f9f7 580 __I uint32_t RESERVED3[2];
<> 144:ef7eb2e8f9f7 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
<> 144:ef7eb2e8f9f7 582 __I uint32_t RESERVED4[3];
<> 144:ef7eb2e8f9f7 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
<> 144:ef7eb2e8f9f7 584 __I uint32_t RESERVED5[10];
<> 144:ef7eb2e8f9f7 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
<> 144:ef7eb2e8f9f7 586 __I uint32_t RESERVED6[109];
<> 144:ef7eb2e8f9f7 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 589 __I uint32_t RESERVED7[125];
<> 144:ef7eb2e8f9f7 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
<> 144:ef7eb2e8f9f7 591 __I uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
<> 144:ef7eb2e8f9f7 593 __I uint32_t RESERVED9[4];
<> 144:ef7eb2e8f9f7 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
<> 144:ef7eb2e8f9f7 595 __I uint32_t RESERVED10[3];
<> 144:ef7eb2e8f9f7 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
<> 144:ef7eb2e8f9f7 597 __I uint32_t RESERVED11;
<> 144:ef7eb2e8f9f7 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
<> 144:ef7eb2e8f9f7 599 __I uint32_t RESERVED12;
<> 144:ef7eb2e8f9f7 600 __IO uint32_t CONFIG; /*!< Configuration register. */
<> 144:ef7eb2e8f9f7 601 __I uint32_t RESERVED13[26];
<> 144:ef7eb2e8f9f7 602 __IO uint32_t ORC; /*!< Over-read character. */
<> 144:ef7eb2e8f9f7 603 __I uint32_t RESERVED14[654];
<> 144:ef7eb2e8f9f7 604 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 605 } NRF_SPIM_Type;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 609 /* ================ GPIOTE ================ */
<> 144:ef7eb2e8f9f7 610 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /**
<> 144:ef7eb2e8f9f7 614 * @brief GPIO tasks and events. (GPIOTE)
<> 144:ef7eb2e8f9f7 615 */
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 typedef struct { /*!< GPIOTE Structure */
<> 144:ef7eb2e8f9f7 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
<> 144:ef7eb2e8f9f7 619 __I uint32_t RESERVED0[60];
<> 144:ef7eb2e8f9f7 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
<> 144:ef7eb2e8f9f7 621 __I uint32_t RESERVED1[27];
<> 144:ef7eb2e8f9f7 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
<> 144:ef7eb2e8f9f7 623 __I uint32_t RESERVED2[97];
<> 144:ef7eb2e8f9f7 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 626 __I uint32_t RESERVED3[129];
<> 144:ef7eb2e8f9f7 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
<> 144:ef7eb2e8f9f7 628 __I uint32_t RESERVED4[695];
<> 144:ef7eb2e8f9f7 629 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 630 } NRF_GPIOTE_Type;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 634 /* ================ ADC ================ */
<> 144:ef7eb2e8f9f7 635 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @brief Analog to digital converter. (ADC)
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 typedef struct { /*!< ADC Structure */
<> 144:ef7eb2e8f9f7 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
<> 144:ef7eb2e8f9f7 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
<> 144:ef7eb2e8f9f7 645 __I uint32_t RESERVED0[62];
<> 144:ef7eb2e8f9f7 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
<> 144:ef7eb2e8f9f7 647 __I uint32_t RESERVED1[128];
<> 144:ef7eb2e8f9f7 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 650 __I uint32_t RESERVED2[61];
<> 144:ef7eb2e8f9f7 651 __I uint32_t BUSY; /*!< ADC busy register. */
<> 144:ef7eb2e8f9f7 652 __I uint32_t RESERVED3[63];
<> 144:ef7eb2e8f9f7 653 __IO uint32_t ENABLE; /*!< ADC enable. */
<> 144:ef7eb2e8f9f7 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
<> 144:ef7eb2e8f9f7 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
<> 144:ef7eb2e8f9f7 656 __I uint32_t RESERVED4[700];
<> 144:ef7eb2e8f9f7 657 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 658 } NRF_ADC_Type;
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 662 /* ================ TIMER ================ */
<> 144:ef7eb2e8f9f7 663 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @brief Timer 0. (TIMER)
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 typedef struct { /*!< TIMER Structure */
<> 144:ef7eb2e8f9f7 671 __O uint32_t TASKS_START; /*!< Start Timer. */
<> 144:ef7eb2e8f9f7 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
<> 144:ef7eb2e8f9f7 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
<> 144:ef7eb2e8f9f7 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
<> 144:ef7eb2e8f9f7 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
<> 144:ef7eb2e8f9f7 676 __I uint32_t RESERVED0[11];
<> 144:ef7eb2e8f9f7 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
<> 144:ef7eb2e8f9f7 678 __I uint32_t RESERVED1[60];
<> 144:ef7eb2e8f9f7 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
<> 144:ef7eb2e8f9f7 680 __I uint32_t RESERVED2[44];
<> 144:ef7eb2e8f9f7 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
<> 144:ef7eb2e8f9f7 682 __I uint32_t RESERVED3[64];
<> 144:ef7eb2e8f9f7 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 685 __I uint32_t RESERVED4[126];
<> 144:ef7eb2e8f9f7 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
<> 144:ef7eb2e8f9f7 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
<> 144:ef7eb2e8f9f7 688 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
<> 144:ef7eb2e8f9f7 690 clock frequency is divided by 2^SCALE. */
<> 144:ef7eb2e8f9f7 691 __I uint32_t RESERVED6[11];
<> 144:ef7eb2e8f9f7 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
<> 144:ef7eb2e8f9f7 693 __I uint32_t RESERVED7[683];
<> 144:ef7eb2e8f9f7 694 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 695 } NRF_TIMER_Type;
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 699 /* ================ RTC ================ */
<> 144:ef7eb2e8f9f7 700 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /**
<> 144:ef7eb2e8f9f7 704 * @brief Real time counter 0. (RTC)
<> 144:ef7eb2e8f9f7 705 */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 typedef struct { /*!< RTC Structure */
<> 144:ef7eb2e8f9f7 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
<> 144:ef7eb2e8f9f7 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
<> 144:ef7eb2e8f9f7 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
<> 144:ef7eb2e8f9f7 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
<> 144:ef7eb2e8f9f7 712 __I uint32_t RESERVED0[60];
<> 144:ef7eb2e8f9f7 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
<> 144:ef7eb2e8f9f7 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
<> 144:ef7eb2e8f9f7 715 __I uint32_t RESERVED1[14];
<> 144:ef7eb2e8f9f7 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
<> 144:ef7eb2e8f9f7 717 __I uint32_t RESERVED2[109];
<> 144:ef7eb2e8f9f7 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 720 __I uint32_t RESERVED3[13];
<> 144:ef7eb2e8f9f7 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
<> 144:ef7eb2e8f9f7 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
<> 144:ef7eb2e8f9f7 723 the value of EVTEN. */
<> 144:ef7eb2e8f9f7 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
<> 144:ef7eb2e8f9f7 725 gives the value of EVTEN. */
<> 144:ef7eb2e8f9f7 726 __I uint32_t RESERVED4[110];
<> 144:ef7eb2e8f9f7 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
<> 144:ef7eb2e8f9f7 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
<> 144:ef7eb2e8f9f7 729 Must be written when RTC is STOPed. */
<> 144:ef7eb2e8f9f7 730 __I uint32_t RESERVED5[13];
<> 144:ef7eb2e8f9f7 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
<> 144:ef7eb2e8f9f7 732 __I uint32_t RESERVED6[683];
<> 144:ef7eb2e8f9f7 733 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 734 } NRF_RTC_Type;
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 738 /* ================ TEMP ================ */
<> 144:ef7eb2e8f9f7 739 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /**
<> 144:ef7eb2e8f9f7 743 * @brief Temperature Sensor. (TEMP)
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 typedef struct { /*!< TEMP Structure */
<> 144:ef7eb2e8f9f7 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
<> 144:ef7eb2e8f9f7 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
<> 144:ef7eb2e8f9f7 749 __I uint32_t RESERVED0[62];
<> 144:ef7eb2e8f9f7 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
<> 144:ef7eb2e8f9f7 751 __I uint32_t RESERVED1[128];
<> 144:ef7eb2e8f9f7 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 754 __I uint32_t RESERVED2[127];
<> 144:ef7eb2e8f9f7 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
<> 144:ef7eb2e8f9f7 756 __I uint32_t RESERVED3[700];
<> 144:ef7eb2e8f9f7 757 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 758 } NRF_TEMP_Type;
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 762 /* ================ RNG ================ */
<> 144:ef7eb2e8f9f7 763 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /**
<> 144:ef7eb2e8f9f7 767 * @brief Random Number Generator. (RNG)
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 typedef struct { /*!< RNG Structure */
<> 144:ef7eb2e8f9f7 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
<> 144:ef7eb2e8f9f7 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
<> 144:ef7eb2e8f9f7 773 __I uint32_t RESERVED0[62];
<> 144:ef7eb2e8f9f7 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
<> 144:ef7eb2e8f9f7 775 __I uint32_t RESERVED1[63];
<> 144:ef7eb2e8f9f7 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
<> 144:ef7eb2e8f9f7 777 __I uint32_t RESERVED2[64];
<> 144:ef7eb2e8f9f7 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
<> 144:ef7eb2e8f9f7 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
<> 144:ef7eb2e8f9f7 780 __I uint32_t RESERVED3[126];
<> 144:ef7eb2e8f9f7 781 __IO uint32_t CONFIG; /*!< Configuration register. */
<> 144:ef7eb2e8f9f7 782 __I uint32_t VALUE; /*!< RNG random number. */
<> 144:ef7eb2e8f9f7 783 __I uint32_t RESERVED4[700];
<> 144:ef7eb2e8f9f7 784 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 785 } NRF_RNG_Type;
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 789 /* ================ ECB ================ */
<> 144:ef7eb2e8f9f7 790 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 /**
<> 144:ef7eb2e8f9f7 794 * @brief AES ECB Mode Encryption. (ECB)
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 typedef struct { /*!< ECB Structure */
<> 144:ef7eb2e8f9f7 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
<> 144:ef7eb2e8f9f7 799 will not initiate a new encryption and the ERRORECB event will
<> 144:ef7eb2e8f9f7 800 be triggered. */
<> 144:ef7eb2e8f9f7 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
<> 144:ef7eb2e8f9f7 802 this will will trigger the ERRORECB event. */
<> 144:ef7eb2e8f9f7 803 __I uint32_t RESERVED0[62];
<> 144:ef7eb2e8f9f7 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
<> 144:ef7eb2e8f9f7 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
<> 144:ef7eb2e8f9f7 806 error. */
<> 144:ef7eb2e8f9f7 807 __I uint32_t RESERVED1[127];
<> 144:ef7eb2e8f9f7 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 810 __I uint32_t RESERVED2[126];
<> 144:ef7eb2e8f9f7 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
<> 144:ef7eb2e8f9f7 812 __I uint32_t RESERVED3[701];
<> 144:ef7eb2e8f9f7 813 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 814 } NRF_ECB_Type;
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 818 /* ================ AAR ================ */
<> 144:ef7eb2e8f9f7 819 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /**
<> 144:ef7eb2e8f9f7 823 * @brief Accelerated Address Resolver. (AAR)
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 typedef struct { /*!< AAR Structure */
<> 144:ef7eb2e8f9f7 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
<> 144:ef7eb2e8f9f7 828 data structure. */
<> 144:ef7eb2e8f9f7 829 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
<> 144:ef7eb2e8f9f7 831 __I uint32_t RESERVED1[61];
<> 144:ef7eb2e8f9f7 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
<> 144:ef7eb2e8f9f7 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
<> 144:ef7eb2e8f9f7 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
<> 144:ef7eb2e8f9f7 835 __I uint32_t RESERVED2[126];
<> 144:ef7eb2e8f9f7 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 838 __I uint32_t RESERVED3[61];
<> 144:ef7eb2e8f9f7 839 __I uint32_t STATUS; /*!< Resolution status. */
<> 144:ef7eb2e8f9f7 840 __I uint32_t RESERVED4[63];
<> 144:ef7eb2e8f9f7 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
<> 144:ef7eb2e8f9f7 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
<> 144:ef7eb2e8f9f7 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
<> 144:ef7eb2e8f9f7 844 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
<> 144:ef7eb2e8f9f7 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
<> 144:ef7eb2e8f9f7 847 during resolution. A minimum of 3 bytes must be reserved. */
<> 144:ef7eb2e8f9f7 848 __I uint32_t RESERVED6[697];
<> 144:ef7eb2e8f9f7 849 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 850 } NRF_AAR_Type;
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 854 /* ================ CCM ================ */
<> 144:ef7eb2e8f9f7 855 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /**
<> 144:ef7eb2e8f9f7 859 * @brief AES CCM Mode Encryption. (CCM)
<> 144:ef7eb2e8f9f7 860 */
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 typedef struct { /*!< CCM Structure */
<> 144:ef7eb2e8f9f7 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
<> 144:ef7eb2e8f9f7 864 itself when completed. */
<> 144:ef7eb2e8f9f7 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
<> 144:ef7eb2e8f9f7 866 completed. */
<> 144:ef7eb2e8f9f7 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
<> 144:ef7eb2e8f9f7 868 __I uint32_t RESERVED0[61];
<> 144:ef7eb2e8f9f7 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
<> 144:ef7eb2e8f9f7 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
<> 144:ef7eb2e8f9f7 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
<> 144:ef7eb2e8f9f7 872 __I uint32_t RESERVED1[61];
<> 144:ef7eb2e8f9f7 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
<> 144:ef7eb2e8f9f7 874 __I uint32_t RESERVED2[64];
<> 144:ef7eb2e8f9f7 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 877 __I uint32_t RESERVED3[61];
<> 144:ef7eb2e8f9f7 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
<> 144:ef7eb2e8f9f7 879 __I uint32_t RESERVED4[63];
<> 144:ef7eb2e8f9f7 880 __IO uint32_t ENABLE; /*!< CCM enable. */
<> 144:ef7eb2e8f9f7 881 __IO uint32_t MODE; /*!< Operation mode. */
<> 144:ef7eb2e8f9f7 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
<> 144:ef7eb2e8f9f7 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
<> 144:ef7eb2e8f9f7 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
<> 144:ef7eb2e8f9f7 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
<> 144:ef7eb2e8f9f7 886 during resolution. A minimum of 43 bytes must be reserved. */
<> 144:ef7eb2e8f9f7 887 __I uint32_t RESERVED5[697];
<> 144:ef7eb2e8f9f7 888 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 889 } NRF_CCM_Type;
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 893 /* ================ WDT ================ */
<> 144:ef7eb2e8f9f7 894 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief Watchdog Timer. (WDT)
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 typedef struct { /*!< WDT Structure */
<> 144:ef7eb2e8f9f7 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
<> 144:ef7eb2e8f9f7 903 __I uint32_t RESERVED0[63];
<> 144:ef7eb2e8f9f7 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
<> 144:ef7eb2e8f9f7 905 __I uint32_t RESERVED1[128];
<> 144:ef7eb2e8f9f7 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 908 __I uint32_t RESERVED2[61];
<> 144:ef7eb2e8f9f7 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
<> 144:ef7eb2e8f9f7 910 __I uint32_t REQSTATUS; /*!< Request status. */
<> 144:ef7eb2e8f9f7 911 __I uint32_t RESERVED3[63];
<> 144:ef7eb2e8f9f7 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
<> 144:ef7eb2e8f9f7 913 __IO uint32_t RREN; /*!< Reload request enable. */
<> 144:ef7eb2e8f9f7 914 __IO uint32_t CONFIG; /*!< Configuration register. */
<> 144:ef7eb2e8f9f7 915 __I uint32_t RESERVED4[60];
<> 144:ef7eb2e8f9f7 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
<> 144:ef7eb2e8f9f7 917 __I uint32_t RESERVED5[631];
<> 144:ef7eb2e8f9f7 918 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 919 } NRF_WDT_Type;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 923 /* ================ QDEC ================ */
<> 144:ef7eb2e8f9f7 924 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @brief Rotary decoder. (QDEC)
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 typedef struct { /*!< QDEC Structure */
<> 144:ef7eb2e8f9f7 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
<> 144:ef7eb2e8f9f7 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
<> 144:ef7eb2e8f9f7 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
<> 144:ef7eb2e8f9f7 935 and clears the ACC registers. */
<> 144:ef7eb2e8f9f7 936 __I uint32_t RESERVED0[61];
<> 144:ef7eb2e8f9f7 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
<> 144:ef7eb2e8f9f7 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
<> 144:ef7eb2e8f9f7 939 ACC register different than zero. */
<> 144:ef7eb2e8f9f7 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
<> 144:ef7eb2e8f9f7 941 __I uint32_t RESERVED1[61];
<> 144:ef7eb2e8f9f7 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
<> 144:ef7eb2e8f9f7 943 __I uint32_t RESERVED2[64];
<> 144:ef7eb2e8f9f7 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 946 __I uint32_t RESERVED3[125];
<> 144:ef7eb2e8f9f7 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
<> 144:ef7eb2e8f9f7 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
<> 144:ef7eb2e8f9f7 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
<> 144:ef7eb2e8f9f7 950 __I int32_t SAMPLE; /*!< Motion sample value. */
<> 144:ef7eb2e8f9f7 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
<> 144:ef7eb2e8f9f7 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
<> 144:ef7eb2e8f9f7 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
<> 144:ef7eb2e8f9f7 954 task. */
<> 144:ef7eb2e8f9f7 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
<> 144:ef7eb2e8f9f7 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
<> 144:ef7eb2e8f9f7 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
<> 144:ef7eb2e8f9f7 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
<> 144:ef7eb2e8f9f7 959 __I uint32_t RESERVED4[5];
<> 144:ef7eb2e8f9f7 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
<> 144:ef7eb2e8f9f7 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
<> 144:ef7eb2e8f9f7 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
<> 144:ef7eb2e8f9f7 963 task. */
<> 144:ef7eb2e8f9f7 964 __I uint32_t RESERVED5[684];
<> 144:ef7eb2e8f9f7 965 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 966 } NRF_QDEC_Type;
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 970 /* ================ LPCOMP ================ */
<> 144:ef7eb2e8f9f7 971 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /**
<> 144:ef7eb2e8f9f7 975 * @brief Low power comparator. (LPCOMP)
<> 144:ef7eb2e8f9f7 976 */
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 typedef struct { /*!< LPCOMP Structure */
<> 144:ef7eb2e8f9f7 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
<> 144:ef7eb2e8f9f7 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
<> 144:ef7eb2e8f9f7 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
<> 144:ef7eb2e8f9f7 982 __I uint32_t RESERVED0[61];
<> 144:ef7eb2e8f9f7 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
<> 144:ef7eb2e8f9f7 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
<> 144:ef7eb2e8f9f7 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
<> 144:ef7eb2e8f9f7 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
<> 144:ef7eb2e8f9f7 987 __I uint32_t RESERVED1[60];
<> 144:ef7eb2e8f9f7 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
<> 144:ef7eb2e8f9f7 989 __I uint32_t RESERVED2[64];
<> 144:ef7eb2e8f9f7 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
<> 144:ef7eb2e8f9f7 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
<> 144:ef7eb2e8f9f7 992 __I uint32_t RESERVED3[61];
<> 144:ef7eb2e8f9f7 993 __I uint32_t RESULT; /*!< Result of last compare. */
<> 144:ef7eb2e8f9f7 994 __I uint32_t RESERVED4[63];
<> 144:ef7eb2e8f9f7 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
<> 144:ef7eb2e8f9f7 996 __IO uint32_t PSEL; /*!< Input pin select. */
<> 144:ef7eb2e8f9f7 997 __IO uint32_t REFSEL; /*!< Reference select. */
<> 144:ef7eb2e8f9f7 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
<> 144:ef7eb2e8f9f7 999 __I uint32_t RESERVED5[4];
<> 144:ef7eb2e8f9f7 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
<> 144:ef7eb2e8f9f7 1001 __I uint32_t RESERVED6[694];
<> 144:ef7eb2e8f9f7 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
<> 144:ef7eb2e8f9f7 1003 } NRF_LPCOMP_Type;
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1007 /* ================ SWI ================ */
<> 144:ef7eb2e8f9f7 1008 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /**
<> 144:ef7eb2e8f9f7 1012 * @brief SW Interrupts. (SWI)
<> 144:ef7eb2e8f9f7 1013 */
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 typedef struct { /*!< SWI Structure */
<> 144:ef7eb2e8f9f7 1016 __I uint32_t UNUSED; /*!< Unused. */
<> 144:ef7eb2e8f9f7 1017 } NRF_SWI_Type;
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1021 /* ================ NVMC ================ */
<> 144:ef7eb2e8f9f7 1022 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /**
<> 144:ef7eb2e8f9f7 1026 * @brief Non Volatile Memory Controller. (NVMC)
<> 144:ef7eb2e8f9f7 1027 */
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 typedef struct { /*!< NVMC Structure */
<> 144:ef7eb2e8f9f7 1030 __I uint32_t RESERVED0[256];
<> 144:ef7eb2e8f9f7 1031 __I uint32_t READY; /*!< Ready flag. */
<> 144:ef7eb2e8f9f7 1032 __I uint32_t RESERVED1[64];
<> 144:ef7eb2e8f9f7 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 union {
<> 144:ef7eb2e8f9f7 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
<> 144:ef7eb2e8f9f7 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
<> 144:ef7eb2e8f9f7 1038 };
<> 144:ef7eb2e8f9f7 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
<> 144:ef7eb2e8f9f7 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
<> 144:ef7eb2e8f9f7 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
<> 144:ef7eb2e8f9f7 1042 } NRF_NVMC_Type;
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1046 /* ================ PPI ================ */
<> 144:ef7eb2e8f9f7 1047 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /**
<> 144:ef7eb2e8f9f7 1051 * @brief PPI controller. (PPI)
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 typedef struct { /*!< PPI Structure */
<> 144:ef7eb2e8f9f7 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
<> 144:ef7eb2e8f9f7 1056 __I uint32_t RESERVED0[312];
<> 144:ef7eb2e8f9f7 1057 __IO uint32_t CHEN; /*!< Channel enable. */
<> 144:ef7eb2e8f9f7 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
<> 144:ef7eb2e8f9f7 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
<> 144:ef7eb2e8f9f7 1060 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
<> 144:ef7eb2e8f9f7 1062 __I uint32_t RESERVED2[156];
<> 144:ef7eb2e8f9f7 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
<> 144:ef7eb2e8f9f7 1064 } NRF_PPI_Type;
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1068 /* ================ FICR ================ */
<> 144:ef7eb2e8f9f7 1069 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071
<> 144:ef7eb2e8f9f7 1072 /**
<> 144:ef7eb2e8f9f7 1073 * @brief Factory Information Configuration. (FICR)
<> 144:ef7eb2e8f9f7 1074 */
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 typedef struct { /*!< FICR Structure */
<> 144:ef7eb2e8f9f7 1077 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
<> 144:ef7eb2e8f9f7 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
<> 144:ef7eb2e8f9f7 1080 __I uint32_t RESERVED1[4];
<> 144:ef7eb2e8f9f7 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
<> 144:ef7eb2e8f9f7 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
<> 144:ef7eb2e8f9f7 1083 __I uint32_t RESERVED2;
<> 144:ef7eb2e8f9f7 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 union {
<> 144:ef7eb2e8f9f7 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
<> 144:ef7eb2e8f9f7 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
<> 144:ef7eb2e8f9f7 1089 instead. */
<> 144:ef7eb2e8f9f7 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
<> 144:ef7eb2e8f9f7 1091 };
<> 144:ef7eb2e8f9f7 1092 __I uint32_t RESERVED3[5];
<> 144:ef7eb2e8f9f7 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
<> 144:ef7eb2e8f9f7 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
<> 144:ef7eb2e8f9f7 1095 __I uint32_t RESERVED4[6];
<> 144:ef7eb2e8f9f7 1096 __I uint32_t ER[4]; /*!< Encryption root. */
<> 144:ef7eb2e8f9f7 1097 __I uint32_t IR[4]; /*!< Identity root. */
<> 144:ef7eb2e8f9f7 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
<> 144:ef7eb2e8f9f7 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
<> 144:ef7eb2e8f9f7 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
<> 144:ef7eb2e8f9f7 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
<> 144:ef7eb2e8f9f7 1102 mode. */
<> 144:ef7eb2e8f9f7 1103 __I uint32_t RESERVED5[10];
<> 144:ef7eb2e8f9f7 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
<> 144:ef7eb2e8f9f7 1105 mode. */
<> 144:ef7eb2e8f9f7 1106 } NRF_FICR_Type;
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1110 /* ================ UICR ================ */
<> 144:ef7eb2e8f9f7 1111 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 /**
<> 144:ef7eb2e8f9f7 1115 * @brief User Information Configuration. (UICR)
<> 144:ef7eb2e8f9f7 1116 */
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 typedef struct { /*!< UICR Structure */
<> 144:ef7eb2e8f9f7 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
<> 144:ef7eb2e8f9f7 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
<> 144:ef7eb2e8f9f7 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
<> 144:ef7eb2e8f9f7 1122 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 1123 __I uint32_t FWID; /*!< Firmware ID. */
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 union {
<> 144:ef7eb2e8f9f7 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
<> 144:ef7eb2e8f9f7 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
<> 144:ef7eb2e8f9f7 1128 };
<> 144:ef7eb2e8f9f7 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
<> 144:ef7eb2e8f9f7 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
<> 144:ef7eb2e8f9f7 1131 } NRF_UICR_Type;
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1135 /* ================ GPIO ================ */
<> 144:ef7eb2e8f9f7 1136 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /**
<> 144:ef7eb2e8f9f7 1140 * @brief General purpose input and output. (GPIO)
<> 144:ef7eb2e8f9f7 1141 */
<> 144:ef7eb2e8f9f7 1142
<> 144:ef7eb2e8f9f7 1143 typedef struct { /*!< GPIO Structure */
<> 144:ef7eb2e8f9f7 1144 __I uint32_t RESERVED0[321];
<> 144:ef7eb2e8f9f7 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
<> 144:ef7eb2e8f9f7 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
<> 144:ef7eb2e8f9f7 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
<> 144:ef7eb2e8f9f7 1148 __I uint32_t IN; /*!< Read GPIO port. */
<> 144:ef7eb2e8f9f7 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
<> 144:ef7eb2e8f9f7 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
<> 144:ef7eb2e8f9f7 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
<> 144:ef7eb2e8f9f7 1152 __I uint32_t RESERVED1[120];
<> 144:ef7eb2e8f9f7 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
<> 144:ef7eb2e8f9f7 1154 } NRF_GPIO_Type;
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* -------------------- End of section using anonymous unions ------------------- */
<> 144:ef7eb2e8f9f7 1158 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 1159 #pragma pop
<> 144:ef7eb2e8f9f7 1160 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 1161 /* leave anonymous unions enabled */
<> 144:ef7eb2e8f9f7 1162 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 1163 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 1164 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 1165 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 1166 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 1167 #pragma warning restore
<> 144:ef7eb2e8f9f7 1168 #else
<> 144:ef7eb2e8f9f7 1169 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 1170 #endif
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1176 /* ================ Peripheral memory map ================ */
<> 144:ef7eb2e8f9f7 1177 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 #define NRF_POWER_BASE 0x40000000UL
<> 144:ef7eb2e8f9f7 1180 #define NRF_CLOCK_BASE 0x40000000UL
<> 144:ef7eb2e8f9f7 1181 #define NRF_MPU_BASE 0x40000000UL
<> 144:ef7eb2e8f9f7 1182 #define NRF_AMLI_BASE 0x40000000UL
<> 144:ef7eb2e8f9f7 1183 #define NRF_RADIO_BASE 0x40001000UL
<> 144:ef7eb2e8f9f7 1184 #define NRF_UART0_BASE 0x40002000UL
<> 144:ef7eb2e8f9f7 1185 #define NRF_SPI0_BASE 0x40003000UL
<> 144:ef7eb2e8f9f7 1186 #define NRF_TWI0_BASE 0x40003000UL
<> 144:ef7eb2e8f9f7 1187 #define NRF_SPI1_BASE 0x40004000UL
<> 144:ef7eb2e8f9f7 1188 #define NRF_TWI1_BASE 0x40004000UL
<> 144:ef7eb2e8f9f7 1189 #define NRF_SPIS1_BASE 0x40004000UL
<> 144:ef7eb2e8f9f7 1190 #define NRF_SPIM1_BASE 0x40004000UL
<> 144:ef7eb2e8f9f7 1191 #define NRF_GPIOTE_BASE 0x40006000UL
<> 144:ef7eb2e8f9f7 1192 #define NRF_ADC_BASE 0x40007000UL
<> 144:ef7eb2e8f9f7 1193 #define NRF_TIMER0_BASE 0x40008000UL
<> 144:ef7eb2e8f9f7 1194 #define NRF_TIMER1_BASE 0x40009000UL
<> 144:ef7eb2e8f9f7 1195 #define NRF_TIMER2_BASE 0x4000A000UL
<> 144:ef7eb2e8f9f7 1196 #define NRF_RTC0_BASE 0x4000B000UL
<> 144:ef7eb2e8f9f7 1197 #define NRF_TEMP_BASE 0x4000C000UL
<> 144:ef7eb2e8f9f7 1198 #define NRF_RNG_BASE 0x4000D000UL
<> 144:ef7eb2e8f9f7 1199 #define NRF_ECB_BASE 0x4000E000UL
<> 144:ef7eb2e8f9f7 1200 #define NRF_AAR_BASE 0x4000F000UL
<> 144:ef7eb2e8f9f7 1201 #define NRF_CCM_BASE 0x4000F000UL
<> 144:ef7eb2e8f9f7 1202 #define NRF_WDT_BASE 0x40010000UL
<> 144:ef7eb2e8f9f7 1203 #define NRF_RTC1_BASE 0x40011000UL
<> 144:ef7eb2e8f9f7 1204 #define NRF_QDEC_BASE 0x40012000UL
<> 144:ef7eb2e8f9f7 1205 #define NRF_LPCOMP_BASE 0x40013000UL
<> 144:ef7eb2e8f9f7 1206 #define NRF_SWI_BASE 0x40014000UL
<> 144:ef7eb2e8f9f7 1207 #define NRF_NVMC_BASE 0x4001E000UL
<> 144:ef7eb2e8f9f7 1208 #define NRF_PPI_BASE 0x4001F000UL
<> 144:ef7eb2e8f9f7 1209 #define NRF_FICR_BASE 0x10000000UL
<> 144:ef7eb2e8f9f7 1210 #define NRF_UICR_BASE 0x10001000UL
<> 144:ef7eb2e8f9f7 1211 #define NRF_GPIO_BASE 0x50000000UL
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1215 /* ================ Peripheral declaration ================ */
<> 144:ef7eb2e8f9f7 1216 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
<> 144:ef7eb2e8f9f7 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
<> 144:ef7eb2e8f9f7 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
<> 144:ef7eb2e8f9f7 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
<> 144:ef7eb2e8f9f7 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
<> 144:ef7eb2e8f9f7 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
<> 144:ef7eb2e8f9f7 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
<> 144:ef7eb2e8f9f7 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
<> 144:ef7eb2e8f9f7 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
<> 144:ef7eb2e8f9f7 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
<> 144:ef7eb2e8f9f7 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
<> 144:ef7eb2e8f9f7 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
<> 144:ef7eb2e8f9f7 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
<> 144:ef7eb2e8f9f7 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
<> 144:ef7eb2e8f9f7 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
<> 144:ef7eb2e8f9f7 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
<> 144:ef7eb2e8f9f7 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
<> 144:ef7eb2e8f9f7 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
<> 144:ef7eb2e8f9f7 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
<> 144:ef7eb2e8f9f7 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
<> 144:ef7eb2e8f9f7 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
<> 144:ef7eb2e8f9f7 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
<> 144:ef7eb2e8f9f7 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
<> 144:ef7eb2e8f9f7 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
<> 144:ef7eb2e8f9f7 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
<> 144:ef7eb2e8f9f7 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
<> 144:ef7eb2e8f9f7 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
<> 144:ef7eb2e8f9f7 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
<> 144:ef7eb2e8f9f7 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
<> 144:ef7eb2e8f9f7 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
<> 144:ef7eb2e8f9f7 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
<> 144:ef7eb2e8f9f7 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
<> 144:ef7eb2e8f9f7 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /** @} */ /* End of group Device_Peripheral_Registers */
<> 144:ef7eb2e8f9f7 1254 /** @} */ /* End of group nrf51 */
<> 144:ef7eb2e8f9f7 1255 /** @} */ /* End of group Nordic Semiconductor */
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1258 }
<> 144:ef7eb2e8f9f7 1259 #endif
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 #endif /* nrf51_H */