mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_DELTA_DFCM_NNN40/mbed_overrides.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 /* No init flash in this version, 2015/10/27 */
<> 144:ef7eb2e8f9f7 20 #if 0
<> 144:ef7eb2e8f9f7 21 #define SPIM1_SCK_PIN 11u /**< SPI clock GPIO pin number. */
<> 144:ef7eb2e8f9f7 22 #define SPIM1_MOSI_PIN 15u /**< SPI Master Out Slave In GPIO pin number. */
<> 144:ef7eb2e8f9f7 23 #define SPIM1_MISO_PIN 9u /**< SPI Master In Slave Out GPIO pin number. */
<> 144:ef7eb2e8f9f7 24 #define SPIM1_SS_PIN 28u /**< SPI Slave Select GPIO pin number. */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #define CMD_POWER_UP (0xAB)
<> 144:ef7eb2e8f9f7 27 #define CMD_POWER_DOWN (0xB9)
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 void flash_init(void)
<> 144:ef7eb2e8f9f7 30 {
<> 144:ef7eb2e8f9f7 31 NRF_GPIO->PIN_CNF[SPIM1_MOSI_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
<> 144:ef7eb2e8f9f7 32 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
<> 144:ef7eb2e8f9f7 33 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
<> 144:ef7eb2e8f9f7 34 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
<> 144:ef7eb2e8f9f7 35 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
<> 144:ef7eb2e8f9f7 36 NRF_GPIO->PIN_CNF[SPIM1_MISO_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
<> 144:ef7eb2e8f9f7 37 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
<> 144:ef7eb2e8f9f7 38 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
<> 144:ef7eb2e8f9f7 39 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
<> 144:ef7eb2e8f9f7 40 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
<> 144:ef7eb2e8f9f7 41 NRF_GPIO->PIN_CNF[SPIM1_SCK_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
<> 144:ef7eb2e8f9f7 42 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
<> 144:ef7eb2e8f9f7 43 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
<> 144:ef7eb2e8f9f7 44 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
<> 144:ef7eb2e8f9f7 45 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 NRF_GPIO->PIN_CNF[SPIM1_SS_PIN] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
<> 144:ef7eb2e8f9f7 48 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
<> 144:ef7eb2e8f9f7 49 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
<> 144:ef7eb2e8f9f7 50 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
<> 144:ef7eb2e8f9f7 51 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
<> 144:ef7eb2e8f9f7 52 //cs = 1;
<> 144:ef7eb2e8f9f7 53 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 NRF_SPI1->ENABLE = 1;
<> 144:ef7eb2e8f9f7 56 NRF_SPI1->PSELSCK = SPIM1_SCK_PIN;
<> 144:ef7eb2e8f9f7 57 NRF_SPI1->PSELMOSI = SPIM1_MISO_PIN;
<> 144:ef7eb2e8f9f7 58 NRF_SPI1->PSELMISO = SPIM1_MOSI_PIN;
<> 144:ef7eb2e8f9f7 59 //spi.frequency(1000000);
<> 144:ef7eb2e8f9f7 60 NRF_SPI1->FREQUENCY = 0x10000000; //1MHz
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 //spi.format(8,0);
<> 144:ef7eb2e8f9f7 63 uint32_t config_mode = 0;
<> 144:ef7eb2e8f9f7 64 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); //mode 0
<> 144:ef7eb2e8f9f7 65 NRF_SPI1->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
<> 144:ef7eb2e8f9f7 66 //cs = 0;
<> 144:ef7eb2e8f9f7 67 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
<> 144:ef7eb2e8f9f7 68 //spi.write(CMD_POWER_UP);
<> 144:ef7eb2e8f9f7 69 while (!NRF_SPI1->EVENTS_READY == 0) {
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71 NRF_SPI1->TXD = (uint32_t)CMD_POWER_UP;
<> 144:ef7eb2e8f9f7 72 while (!NRF_SPI1->EVENTS_READY == 1) {
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74 NRF_SPI1->EVENTS_READY = 0;
<> 144:ef7eb2e8f9f7 75 NRF_SPI1->RXD;
<> 144:ef7eb2e8f9f7 76 //wait_ms(30);
<> 144:ef7eb2e8f9f7 77 // Deselect the device
<> 144:ef7eb2e8f9f7 78 //cs = 1;
<> 144:ef7eb2e8f9f7 79 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 }
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 void flash_powerDown(void)
<> 144:ef7eb2e8f9f7 84 {
<> 144:ef7eb2e8f9f7 85 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN28_Clear << GPIO_OUTCLR_PIN28_Pos);
<> 144:ef7eb2e8f9f7 86 //spi.write(CMD_POWER_DOWN);
<> 144:ef7eb2e8f9f7 87 while (!NRF_SPI1->EVENTS_READY == 0) {
<> 144:ef7eb2e8f9f7 88 }
<> 144:ef7eb2e8f9f7 89 NRF_SPI1->TXD = (uint32_t)CMD_POWER_DOWN;
<> 144:ef7eb2e8f9f7 90 while (!NRF_SPI1->EVENTS_READY == 1) {
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92 NRF_SPI1->EVENTS_READY = 0;
<> 144:ef7eb2e8f9f7 93 NRF_SPI1->RXD;
<> 144:ef7eb2e8f9f7 94 NRF_GPIO->OUTSET = (GPIO_OUTSET_PIN28_High << GPIO_OUTSET_PIN28_Pos);
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 //wait for sleep
<> 144:ef7eb2e8f9f7 97 //wait_us(3);
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99 /* No init flash in this version, 2015/10/27 */
<> 144:ef7eb2e8f9f7 100 #endif
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 void mbed_sdk_init()
<> 144:ef7eb2e8f9f7 103 {
<> 144:ef7eb2e8f9f7 104 // Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
<> 144:ef7eb2e8f9f7 105 NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
<> 144:ef7eb2e8f9f7 106 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
<> 144:ef7eb2e8f9f7 107 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
<> 144:ef7eb2e8f9f7 108 | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
<> 144:ef7eb2e8f9f7 109 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 // Config External Crystal to 32MHz
<> 144:ef7eb2e8f9f7 114 NRF_CLOCK->XTALFREQ = 0x00;
<> 144:ef7eb2e8f9f7 115 NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
<> 144:ef7eb2e8f9f7 116 NRF_CLOCK->TASKS_HFCLKSTART = 1;
<> 144:ef7eb2e8f9f7 117 while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
<> 144:ef7eb2e8f9f7 118 {// Do nothing.
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /* No init flash in this version, 2015/10/27 */
<> 144:ef7eb2e8f9f7 122 // flash_init();
<> 144:ef7eb2e8f9f7 123 //
<> 144:ef7eb2e8f9f7 124 // //nrf_delay_ms(10);
<> 144:ef7eb2e8f9f7 125 // flash_powerDown();
<> 144:ef7eb2e8f9f7 126 /* No init flash in this version, 2015/10/27 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 }