mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Maxim/TARGET_MAX32625/device/wdt2_regs.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
150:02e0a0aed4ec 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_WDT2_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_WDT2_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t ctrl; /* 0x0000 Watchdog Timer 2 Control Register */
<> 150:02e0a0aed4ec 66 __IO uint32_t clear; /* 0x0004 Watchdog Timer 2 Clear Register (Feed Dog) */
<> 150:02e0a0aed4ec 67 __IO uint32_t flags; /* 0x0008 Watchdog Timer 2 Interrupt and Reset Flags */
<> 150:02e0a0aed4ec 68 __IO uint32_t enable; /* 0x000C Watchdog Timer 2 Interrupt/Reset Enable/Disable Controls */
<> 150:02e0a0aed4ec 69 __I uint32_t rsv010; /* 0x0010 */
<> 150:02e0a0aed4ec 70 __IO uint32_t lock_ctrl; /* 0x0014 Watchdog Timer 2 Register Setting Lock for Control Register */
<> 150:02e0a0aed4ec 71 } mxc_wdt2_regs_t;
<> 150:02e0a0aed4ec 72
<> 150:02e0a0aed4ec 73
<> 150:02e0a0aed4ec 74 /*
<> 150:02e0a0aed4ec 75 Register offsets for module WDT2.
<> 150:02e0a0aed4ec 76 */
<> 150:02e0a0aed4ec 77
<> 150:02e0a0aed4ec 78 #define MXC_R_WDT2_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 79 #define MXC_R_WDT2_OFFS_CLEAR ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 80 #define MXC_R_WDT2_OFFS_FLAGS ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 81 #define MXC_R_WDT2_OFFS_ENABLE ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 82 #define MXC_R_WDT2_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 83
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85 /*
<> 150:02e0a0aed4ec 86 Field positions and masks for module WDT2.
<> 150:02e0a0aed4ec 87 */
<> 150:02e0a0aed4ec 88
<> 150:02e0a0aed4ec 89 #define MXC_F_WDT2_CTRL_INT_PERIOD_POS 0
<> 150:02e0a0aed4ec 90 #define MXC_F_WDT2_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 91 #define MXC_F_WDT2_CTRL_RST_PERIOD_POS 4
<> 150:02e0a0aed4ec 92 #define MXC_F_WDT2_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 93 #define MXC_F_WDT2_CTRL_EN_TIMER_POS 8
<> 150:02e0a0aed4ec 94 #define MXC_F_WDT2_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_POS))
<> 150:02e0a0aed4ec 95 #define MXC_F_WDT2_CTRL_EN_CLOCK_POS 9
<> 150:02e0a0aed4ec 96 #define MXC_F_WDT2_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_CLOCK_POS))
<> 150:02e0a0aed4ec 97 #define MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS 10
<> 150:02e0a0aed4ec 98 #define MXC_F_WDT2_CTRL_EN_TIMER_SLP ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS))
<> 150:02e0a0aed4ec 99
<> 150:02e0a0aed4ec 100 #define MXC_F_WDT2_FLAGS_TIMEOUT_POS 0
<> 150:02e0a0aed4ec 101 #define MXC_F_WDT2_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_TIMEOUT_POS))
<> 150:02e0a0aed4ec 102 #define MXC_F_WDT2_FLAGS_RESET_OUT_POS 2
<> 150:02e0a0aed4ec 103 #define MXC_F_WDT2_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_RESET_OUT_POS))
<> 150:02e0a0aed4ec 104
<> 150:02e0a0aed4ec 105 #define MXC_F_WDT2_ENABLE_TIMEOUT_POS 0
<> 150:02e0a0aed4ec 106 #define MXC_F_WDT2_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_TIMEOUT_POS))
<> 150:02e0a0aed4ec 107 #define MXC_F_WDT2_ENABLE_RESET_OUT_POS 2
<> 150:02e0a0aed4ec 108 #define MXC_F_WDT2_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_RESET_OUT_POS))
<> 150:02e0a0aed4ec 109
<> 150:02e0a0aed4ec 110 #define MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS 0
<> 150:02e0a0aed4ec 111 #define MXC_F_WDT2_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS))
<> 150:02e0a0aed4ec 112
<> 150:02e0a0aed4ec 113
<> 150:02e0a0aed4ec 114
<> 150:02e0a0aed4ec 115 /*
<> 150:02e0a0aed4ec 116 Field values and shifted values for module WDT2.
<> 150:02e0a0aed4ec 117 */
<> 150:02e0a0aed4ec 118
<> 150:02e0a0aed4ec 119 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 120 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 121 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 122 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 123 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL))
<> 150:02e0a0aed4ec 124 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL))
<> 150:02e0a0aed4ec 125 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL))
<> 150:02e0a0aed4ec 126 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL))
<> 150:02e0a0aed4ec 127 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL))
<> 150:02e0a0aed4ec 128 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL))
<> 150:02e0a0aed4ec 129 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL))
<> 150:02e0a0aed4ec 130 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL))
<> 150:02e0a0aed4ec 131 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL))
<> 150:02e0a0aed4ec 132 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL))
<> 150:02e0a0aed4ec 133 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL))
<> 150:02e0a0aed4ec 134 #define MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL))
<> 150:02e0a0aed4ec 135
<> 150:02e0a0aed4ec 136 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 137 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 138 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 139 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 140 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 141 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 142 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 143 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 144 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 145 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 146 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 147 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 148 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 149 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 150 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 151 #define MXC_S_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS))
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 154 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 155 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 156 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 157 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL))
<> 150:02e0a0aed4ec 158 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL))
<> 150:02e0a0aed4ec 159 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL))
<> 150:02e0a0aed4ec 160 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL))
<> 150:02e0a0aed4ec 161 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL))
<> 150:02e0a0aed4ec 162 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL))
<> 150:02e0a0aed4ec 163 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL))
<> 150:02e0a0aed4ec 164 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL))
<> 150:02e0a0aed4ec 165 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL))
<> 150:02e0a0aed4ec 166 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL))
<> 150:02e0a0aed4ec 167 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL))
<> 150:02e0a0aed4ec 168 #define MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL))
<> 150:02e0a0aed4ec 169
<> 150:02e0a0aed4ec 170 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 171 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 172 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 173 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 174 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 175 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 176 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 177 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 178 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 179 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 180 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 181 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 182 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 183 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 184 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 185 #define MXC_S_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS))
<> 150:02e0a0aed4ec 186
<> 150:02e0a0aed4ec 187
<> 150:02e0a0aed4ec 188 #define MXC_V_WDT2_LOCK_KEY 0x24
<> 150:02e0a0aed4ec 189 #define MXC_V_WDT2_UNLOCK_KEY 0x42
<> 150:02e0a0aed4ec 190
<> 150:02e0a0aed4ec 191 #define MXC_V_WDT2_RESET_KEY_0 0xA5
<> 150:02e0a0aed4ec 192 #define MXC_V_WDT2_RESET_KEY_1 0x5A
<> 150:02e0a0aed4ec 193
<> 150:02e0a0aed4ec 194
<> 150:02e0a0aed4ec 195 #ifdef __cplusplus
<> 150:02e0a0aed4ec 196 }
<> 150:02e0a0aed4ec 197 #endif
<> 150:02e0a0aed4ec 198
<> 150:02e0a0aed4ec 199 #endif /* _MXC_WDT2_REGS_H_ */
<> 150:02e0a0aed4ec 200