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mbed library sources. Supersedes mbed-src.

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targets/TARGET_Maxim/TARGET_MAX32625/device/adc_regs.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
150:02e0a0aed4ec 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_ADC_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_ADC_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t ctrl; /* 0x0000 ADC Control */
<> 150:02e0a0aed4ec 66 __IO uint32_t status; /* 0x0004 ADC Status */
<> 150:02e0a0aed4ec 67 __IO uint32_t data; /* 0x0008 ADC Output Data */
<> 150:02e0a0aed4ec 68 __IO uint32_t intr; /* 0x000C ADC Interrupt Control Register */
<> 150:02e0a0aed4ec 69 __IO uint32_t limit[4]; /* 0x0010-0x001C ADC Limit 0..3 */
<> 150:02e0a0aed4ec 70 __IO uint32_t afe_ctrl; /* 0x0020 AFE Control Register */
<> 150:02e0a0aed4ec 71 __IO uint32_t ro_cal0; /* 0x0024 RO Trim Calibration Register 0 */
<> 150:02e0a0aed4ec 72 __IO uint32_t ro_cal1; /* 0x0028 RO Trim Calibration Register 1 */
<> 150:02e0a0aed4ec 73 __IO uint32_t ro_cal2; /* 0x002C RO Trim Calibration Register 2 */
<> 150:02e0a0aed4ec 74 } mxc_adc_regs_t;
<> 150:02e0a0aed4ec 75
<> 150:02e0a0aed4ec 76
<> 150:02e0a0aed4ec 77 /*
<> 150:02e0a0aed4ec 78 Register offsets for module ADC.
<> 150:02e0a0aed4ec 79 */
<> 150:02e0a0aed4ec 80
<> 150:02e0a0aed4ec 81 #define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 82 #define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 83 #define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 84 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 85 #define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 86 #define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 87 #define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL)
<> 150:02e0a0aed4ec 88 #define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL)
<> 150:02e0a0aed4ec 89 #define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL)
<> 150:02e0a0aed4ec 90 #define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL)
<> 150:02e0a0aed4ec 91 #define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL)
<> 150:02e0a0aed4ec 92 #define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL)
<> 150:02e0a0aed4ec 93
<> 150:02e0a0aed4ec 94
<> 150:02e0a0aed4ec 95 /*
<> 150:02e0a0aed4ec 96 Field positions and masks for module ADC.
<> 150:02e0a0aed4ec 97 */
<> 150:02e0a0aed4ec 98
<> 150:02e0a0aed4ec 99 #define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0
<> 150:02e0a0aed4ec 100 #define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS))
<> 150:02e0a0aed4ec 101 #define MXC_F_ADC_CTRL_ADC_PU_POS 1
<> 150:02e0a0aed4ec 102 #define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS))
<> 150:02e0a0aed4ec 103 #define MXC_F_ADC_CTRL_BUF_PU_POS 2
<> 150:02e0a0aed4ec 104 #define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS))
<> 150:02e0a0aed4ec 105 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3
<> 150:02e0a0aed4ec 106 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS))
<> 150:02e0a0aed4ec 107 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4
<> 150:02e0a0aed4ec 108 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS))
<> 150:02e0a0aed4ec 109 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5
<> 150:02e0a0aed4ec 110 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS))
<> 150:02e0a0aed4ec 111 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6
<> 150:02e0a0aed4ec 112 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS))
<> 150:02e0a0aed4ec 113 #define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7
<> 150:02e0a0aed4ec 114 #define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS))
<> 150:02e0a0aed4ec 115 #define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8
<> 150:02e0a0aed4ec 116 #define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS))
<> 150:02e0a0aed4ec 117 #define MXC_F_ADC_CTRL_ADC_SCALE_POS 9
<> 150:02e0a0aed4ec 118 #define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS))
<> 150:02e0a0aed4ec 119 #define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10
<> 150:02e0a0aed4ec 120 #define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS))
<> 150:02e0a0aed4ec 121 #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11
<> 150:02e0a0aed4ec 122 #define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS))
<> 150:02e0a0aed4ec 123 #define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12
<> 150:02e0a0aed4ec 124 #define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS))
<> 150:02e0a0aed4ec 125
<> 150:02e0a0aed4ec 126 #if (MXC_ADC_REV == 0)
<> 150:02e0a0aed4ec 127 #define MXC_F_ADC_CTRL_ADC_XREF_POS 16
<> 150:02e0a0aed4ec 128 #define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS))
<> 150:02e0a0aed4ec 129 #endif
<> 150:02e0a0aed4ec 130
<> 150:02e0a0aed4ec 131 #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17
<> 150:02e0a0aed4ec 132 #define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS))
<> 150:02e0a0aed4ec 133 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24
<> 150:02e0a0aed4ec 134 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS))
<> 150:02e0a0aed4ec 135
<> 150:02e0a0aed4ec 136 #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0
<> 150:02e0a0aed4ec 137 #define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS))
<> 150:02e0a0aed4ec 138 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1
<> 150:02e0a0aed4ec 139 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS))
<> 150:02e0a0aed4ec 140 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2
<> 150:02e0a0aed4ec 141 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS))
<> 150:02e0a0aed4ec 142 #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3
<> 150:02e0a0aed4ec 143 #define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS))
<> 150:02e0a0aed4ec 144
<> 150:02e0a0aed4ec 145 #define MXC_F_ADC_DATA_ADC_DATA_POS 0
<> 150:02e0a0aed4ec 146 #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS))
<> 150:02e0a0aed4ec 147
<> 150:02e0a0aed4ec 148 #define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0
<> 150:02e0a0aed4ec 149 #define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS))
<> 150:02e0a0aed4ec 150 #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1
<> 150:02e0a0aed4ec 151 #define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS))
<> 150:02e0a0aed4ec 152 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2
<> 150:02e0a0aed4ec 153 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS))
<> 150:02e0a0aed4ec 154 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3
<> 150:02e0a0aed4ec 155 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS))
<> 150:02e0a0aed4ec 156 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4
<> 150:02e0a0aed4ec 157 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS))
<> 150:02e0a0aed4ec 158 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5
<> 150:02e0a0aed4ec 159 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS))
<> 150:02e0a0aed4ec 160 #define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16
<> 150:02e0a0aed4ec 161 #define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS))
<> 150:02e0a0aed4ec 162 #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17
<> 150:02e0a0aed4ec 163 #define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS))
<> 150:02e0a0aed4ec 164 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18
<> 150:02e0a0aed4ec 165 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS))
<> 150:02e0a0aed4ec 166 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19
<> 150:02e0a0aed4ec 167 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS))
<> 150:02e0a0aed4ec 168 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20
<> 150:02e0a0aed4ec 169 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS))
<> 150:02e0a0aed4ec 170 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21
<> 150:02e0a0aed4ec 171 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS))
<> 150:02e0a0aed4ec 172 #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22
<> 150:02e0a0aed4ec 173 #define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS))
<> 150:02e0a0aed4ec 174
<> 150:02e0a0aed4ec 175 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0
<> 150:02e0a0aed4ec 176 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS))
<> 150:02e0a0aed4ec 177 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12
<> 150:02e0a0aed4ec 178 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS))
<> 150:02e0a0aed4ec 179 #define MXC_F_ADC_LIMIT0_CH_SEL_POS 24
<> 150:02e0a0aed4ec 180 #define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS))
<> 150:02e0a0aed4ec 181 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28
<> 150:02e0a0aed4ec 182 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 183 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29
<> 150:02e0a0aed4ec 184 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 185
<> 150:02e0a0aed4ec 186 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0
<> 150:02e0a0aed4ec 187 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS))
<> 150:02e0a0aed4ec 188 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12
<> 150:02e0a0aed4ec 189 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS))
<> 150:02e0a0aed4ec 190 #define MXC_F_ADC_LIMIT1_CH_SEL_POS 24
<> 150:02e0a0aed4ec 191 #define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS))
<> 150:02e0a0aed4ec 192 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28
<> 150:02e0a0aed4ec 193 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 194 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29
<> 150:02e0a0aed4ec 195 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 196
<> 150:02e0a0aed4ec 197 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0
<> 150:02e0a0aed4ec 198 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS))
<> 150:02e0a0aed4ec 199 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12
<> 150:02e0a0aed4ec 200 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS))
<> 150:02e0a0aed4ec 201 #define MXC_F_ADC_LIMIT2_CH_SEL_POS 24
<> 150:02e0a0aed4ec 202 #define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS))
<> 150:02e0a0aed4ec 203 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28
<> 150:02e0a0aed4ec 204 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 205 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29
<> 150:02e0a0aed4ec 206 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0
<> 150:02e0a0aed4ec 209 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS))
<> 150:02e0a0aed4ec 210 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12
<> 150:02e0a0aed4ec 211 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS))
<> 150:02e0a0aed4ec 212 #define MXC_F_ADC_LIMIT3_CH_SEL_POS 24
<> 150:02e0a0aed4ec 213 #define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS))
<> 150:02e0a0aed4ec 214 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28
<> 150:02e0a0aed4ec 215 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 216 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29
<> 150:02e0a0aed4ec 217 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS))
<> 150:02e0a0aed4ec 218
<> 150:02e0a0aed4ec 219 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8
<> 150:02e0a0aed4ec 220 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS))
<> 150:02e0a0aed4ec 221 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9
<> 150:02e0a0aed4ec 222 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS))
<> 150:02e0a0aed4ec 223
<> 150:02e0a0aed4ec 224 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
<> 150:02e0a0aed4ec 225 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
<> 150:02e0a0aed4ec 226 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
<> 150:02e0a0aed4ec 227 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
<> 150:02e0a0aed4ec 228 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
<> 150:02e0a0aed4ec 229 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
<> 150:02e0a0aed4ec 230 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4
<> 150:02e0a0aed4ec 231 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS))
<> 150:02e0a0aed4ec 232 #define MXC_F_ADC_RO_CAL0_DUMMY_POS 5
<> 150:02e0a0aed4ec 233 #define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS))
<> 150:02e0a0aed4ec 234 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
<> 150:02e0a0aed4ec 235 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
<> 150:02e0a0aed4ec 236 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
<> 150:02e0a0aed4ec 237 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
<> 150:02e0a0aed4ec 238
<> 150:02e0a0aed4ec 239 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
<> 150:02e0a0aed4ec 240 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
<> 150:02e0a0aed4ec 241 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
<> 150:02e0a0aed4ec 242 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
<> 150:02e0a0aed4ec 243 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
<> 150:02e0a0aed4ec 244 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
<> 150:02e0a0aed4ec 245
<> 150:02e0a0aed4ec 246 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0
<> 150:02e0a0aed4ec 247 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS))
<> 150:02e0a0aed4ec 248
<> 150:02e0a0aed4ec 249 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 250 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 251 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 252 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 253 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL))
<> 150:02e0a0aed4ec 254 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL))
<> 150:02e0a0aed4ec 255 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL))
<> 150:02e0a0aed4ec 256 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL))
<> 150:02e0a0aed4ec 257 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL))
<> 150:02e0a0aed4ec 258 #define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL))
<> 150:02e0a0aed4ec 259 #define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL))
<> 150:02e0a0aed4ec 260
<> 150:02e0a0aed4ec 261 #if(MXC_ADC_REV > 0)
<> 150:02e0a0aed4ec 262 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL))
<> 150:02e0a0aed4ec 263 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL))
<> 150:02e0a0aed4ec 264 #endif
<> 150:02e0a0aed4ec 265
<> 150:02e0a0aed4ec 266 #ifdef __cplusplus
<> 150:02e0a0aed4ec 267 }
<> 150:02e0a0aed4ec 268 #endif
<> 150:02e0a0aed4ec 269
<> 150:02e0a0aed4ec 270 #endif /* _MXC_ADC_REGS_H_ */
<> 150:02e0a0aed4ec 271