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targets/TARGET_Maxim/TARGET_MAX32620C/device/wdt_regs.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 186:707f6e361f3e 1 /*******************************************************************************
Anna Bridge 186:707f6e361f3e 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Anna Bridge 186:707f6e361f3e 3 *
Anna Bridge 186:707f6e361f3e 4 * Permission is hereby granted, free of charge, to any person obtaining a
Anna Bridge 186:707f6e361f3e 5 * copy of this software and associated documentation files (the "Software"),
Anna Bridge 186:707f6e361f3e 6 * to deal in the Software without restriction, including without limitation
Anna Bridge 186:707f6e361f3e 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Anna Bridge 186:707f6e361f3e 8 * and/or sell copies of the Software, and to permit persons to whom the
Anna Bridge 186:707f6e361f3e 9 * Software is furnished to do so, subject to the following conditions:
Anna Bridge 186:707f6e361f3e 10 *
Anna Bridge 186:707f6e361f3e 11 * The above copyright notice and this permission notice shall be included
Anna Bridge 186:707f6e361f3e 12 * in all copies or substantial portions of the Software.
Anna Bridge 186:707f6e361f3e 13 *
Anna Bridge 186:707f6e361f3e 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Anna Bridge 186:707f6e361f3e 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Anna Bridge 186:707f6e361f3e 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Anna Bridge 186:707f6e361f3e 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Anna Bridge 186:707f6e361f3e 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Anna Bridge 186:707f6e361f3e 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Anna Bridge 186:707f6e361f3e 20 * OTHER DEALINGS IN THE SOFTWARE.
Anna Bridge 186:707f6e361f3e 21 *
Anna Bridge 186:707f6e361f3e 22 * Except as contained in this notice, the name of Maxim Integrated
Anna Bridge 186:707f6e361f3e 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Anna Bridge 186:707f6e361f3e 24 * Products, Inc. Branding Policy.
Anna Bridge 186:707f6e361f3e 25 *
Anna Bridge 186:707f6e361f3e 26 * The mere transfer of this software does not imply any licenses
Anna Bridge 186:707f6e361f3e 27 * of trade secrets, proprietary technology, copyrights, patents,
Anna Bridge 186:707f6e361f3e 28 * trademarks, maskwork rights, or any other form of intellectual
Anna Bridge 186:707f6e361f3e 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Anna Bridge 186:707f6e361f3e 30 * ownership rights.
Anna Bridge 186:707f6e361f3e 31 *
Anna Bridge 186:707f6e361f3e 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
Anna Bridge 186:707f6e361f3e 33 * $Revision: 21839 $
Anna Bridge 186:707f6e361f3e 34 *
Anna Bridge 186:707f6e361f3e 35 ******************************************************************************/
Anna Bridge 186:707f6e361f3e 36
Anna Bridge 186:707f6e361f3e 37 #ifndef _MXC_WDT_REGS_H_
Anna Bridge 186:707f6e361f3e 38 #define _MXC_WDT_REGS_H_
Anna Bridge 186:707f6e361f3e 39
Anna Bridge 186:707f6e361f3e 40 #ifdef __cplusplus
Anna Bridge 186:707f6e361f3e 41 extern "C" {
Anna Bridge 186:707f6e361f3e 42 #endif
Anna Bridge 186:707f6e361f3e 43
Anna Bridge 186:707f6e361f3e 44 #include <stdint.h>
Anna Bridge 186:707f6e361f3e 45
Anna Bridge 186:707f6e361f3e 46 /*
Anna Bridge 186:707f6e361f3e 47 If types are not defined elsewhere (CMSIS) define them here
Anna Bridge 186:707f6e361f3e 48 */
Anna Bridge 186:707f6e361f3e 49 #ifndef __IO
Anna Bridge 186:707f6e361f3e 50 #define __IO volatile
Anna Bridge 186:707f6e361f3e 51 #endif
Anna Bridge 186:707f6e361f3e 52 #ifndef __I
Anna Bridge 186:707f6e361f3e 53 #define __I volatile const
Anna Bridge 186:707f6e361f3e 54 #endif
Anna Bridge 186:707f6e361f3e 55 #ifndef __O
Anna Bridge 186:707f6e361f3e 56 #define __O volatile
Anna Bridge 186:707f6e361f3e 57 #endif
Anna Bridge 186:707f6e361f3e 58 #ifndef __RO
Anna Bridge 186:707f6e361f3e 59 #define __RO volatile const
Anna Bridge 186:707f6e361f3e 60 #endif
Anna Bridge 186:707f6e361f3e 61
Anna Bridge 186:707f6e361f3e 62
Anna Bridge 186:707f6e361f3e 63 /*
Anna Bridge 186:707f6e361f3e 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
Anna Bridge 186:707f6e361f3e 65 access to each register in module.
Anna Bridge 186:707f6e361f3e 66 */
Anna Bridge 186:707f6e361f3e 67
Anna Bridge 186:707f6e361f3e 68 /* Offset Register Description
Anna Bridge 186:707f6e361f3e 69 ============= ============================================================================ */
Anna Bridge 186:707f6e361f3e 70 typedef struct {
Anna Bridge 186:707f6e361f3e 71 __IO uint32_t ctrl; /* 0x0000 Watchdog Timer Control Register */
Anna Bridge 186:707f6e361f3e 72 __IO uint32_t clear; /* 0x0004 Watchdog Timer Clear Register (Feed Dog) */
Anna Bridge 186:707f6e361f3e 73 __IO uint32_t flags; /* 0x0008 Watchdog Timer Interrupt and Reset Flags */
Anna Bridge 186:707f6e361f3e 74 __IO uint32_t enable; /* 0x000C Watchdog Timer Interrupt/Reset Enable/Disable Controls */
Anna Bridge 186:707f6e361f3e 75 __RO uint32_t rsv010; /* 0x0010 */
Anna Bridge 186:707f6e361f3e 76 __IO uint32_t lock_ctrl; /* 0x0014 Watchdog Timer Register Setting Lock for Control Register */
Anna Bridge 186:707f6e361f3e 77 } mxc_wdt_regs_t;
Anna Bridge 186:707f6e361f3e 78
Anna Bridge 186:707f6e361f3e 79
Anna Bridge 186:707f6e361f3e 80 /*
Anna Bridge 186:707f6e361f3e 81 Register offsets for module WDT.
Anna Bridge 186:707f6e361f3e 82 */
Anna Bridge 186:707f6e361f3e 83
Anna Bridge 186:707f6e361f3e 84 #define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL)
Anna Bridge 186:707f6e361f3e 85 #define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL)
Anna Bridge 186:707f6e361f3e 86 #define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL)
Anna Bridge 186:707f6e361f3e 87 #define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL)
Anna Bridge 186:707f6e361f3e 88 #define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL)
Anna Bridge 186:707f6e361f3e 89
Anna Bridge 186:707f6e361f3e 90
Anna Bridge 186:707f6e361f3e 91 /*
Anna Bridge 186:707f6e361f3e 92 Field positions and masks for module WDT.
Anna Bridge 186:707f6e361f3e 93 */
Anna Bridge 186:707f6e361f3e 94
Anna Bridge 186:707f6e361f3e 95 #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0
Anna Bridge 186:707f6e361f3e 96 #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 97 #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4
Anna Bridge 186:707f6e361f3e 98 #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 99 #define MXC_F_WDT_CTRL_EN_TIMER_POS 8
Anna Bridge 186:707f6e361f3e 100 #define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
Anna Bridge 186:707f6e361f3e 101 #define MXC_F_WDT_CTRL_EN_CLOCK_POS 9
Anna Bridge 186:707f6e361f3e 102 #define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
Anna Bridge 186:707f6e361f3e 103 #define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12
Anna Bridge 186:707f6e361f3e 104 #define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 105
Anna Bridge 186:707f6e361f3e 106 #define MXC_F_WDT_FLAGS_TIMEOUT_POS 0
Anna Bridge 186:707f6e361f3e 107 #define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
Anna Bridge 186:707f6e361f3e 108 #define MXC_F_WDT_FLAGS_PRE_WIN_POS 1
Anna Bridge 186:707f6e361f3e 109 #define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
Anna Bridge 186:707f6e361f3e 110 #define MXC_F_WDT_FLAGS_RESET_OUT_POS 2
Anna Bridge 186:707f6e361f3e 111 #define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
Anna Bridge 186:707f6e361f3e 112
Anna Bridge 186:707f6e361f3e 113 #define MXC_F_WDT_ENABLE_TIMEOUT_POS 0
Anna Bridge 186:707f6e361f3e 114 #define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
Anna Bridge 186:707f6e361f3e 115 #define MXC_F_WDT_ENABLE_PRE_WIN_POS 1
Anna Bridge 186:707f6e361f3e 116 #define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
Anna Bridge 186:707f6e361f3e 117 #define MXC_F_WDT_ENABLE_RESET_OUT_POS 2
Anna Bridge 186:707f6e361f3e 118 #define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
Anna Bridge 186:707f6e361f3e 119
Anna Bridge 186:707f6e361f3e 120 #define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0
Anna Bridge 186:707f6e361f3e 121 #define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
Anna Bridge 186:707f6e361f3e 122
Anna Bridge 186:707f6e361f3e 123
Anna Bridge 186:707f6e361f3e 124
Anna Bridge 186:707f6e361f3e 125 /*
Anna Bridge 186:707f6e361f3e 126 Field values and shifted values for module WDT.
Anna Bridge 186:707f6e361f3e 127 */
Anna Bridge 186:707f6e361f3e 128
Anna Bridge 186:707f6e361f3e 129 #define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL))
Anna Bridge 186:707f6e361f3e 130 #define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL))
Anna Bridge 186:707f6e361f3e 131 #define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL))
Anna Bridge 186:707f6e361f3e 132 #define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL))
Anna Bridge 186:707f6e361f3e 133 #define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL))
Anna Bridge 186:707f6e361f3e 134 #define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL))
Anna Bridge 186:707f6e361f3e 135 #define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL))
Anna Bridge 186:707f6e361f3e 136 #define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL))
Anna Bridge 186:707f6e361f3e 137 #define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL))
Anna Bridge 186:707f6e361f3e 138 #define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL))
Anna Bridge 186:707f6e361f3e 139 #define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL))
Anna Bridge 186:707f6e361f3e 140 #define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL))
Anna Bridge 186:707f6e361f3e 141 #define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL))
Anna Bridge 186:707f6e361f3e 142 #define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL))
Anna Bridge 186:707f6e361f3e 143 #define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL))
Anna Bridge 186:707f6e361f3e 144 #define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL))
Anna Bridge 186:707f6e361f3e 145
Anna Bridge 186:707f6e361f3e 146 #define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 147 #define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 148 #define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 149 #define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 150 #define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 151 #define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 152 #define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 153 #define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 154 #define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 155 #define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 156 #define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 157 #define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 158 #define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 159 #define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 160 #define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 161 #define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 162
Anna Bridge 186:707f6e361f3e 163 #define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL))
Anna Bridge 186:707f6e361f3e 164 #define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL))
Anna Bridge 186:707f6e361f3e 165 #define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL))
Anna Bridge 186:707f6e361f3e 166 #define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL))
Anna Bridge 186:707f6e361f3e 167 #define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL))
Anna Bridge 186:707f6e361f3e 168 #define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL))
Anna Bridge 186:707f6e361f3e 169 #define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL))
Anna Bridge 186:707f6e361f3e 170 #define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL))
Anna Bridge 186:707f6e361f3e 171 #define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL))
Anna Bridge 186:707f6e361f3e 172 #define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL))
Anna Bridge 186:707f6e361f3e 173 #define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL))
Anna Bridge 186:707f6e361f3e 174 #define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL))
Anna Bridge 186:707f6e361f3e 175 #define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL))
Anna Bridge 186:707f6e361f3e 176 #define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL))
Anna Bridge 186:707f6e361f3e 177 #define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL))
Anna Bridge 186:707f6e361f3e 178 #define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL))
Anna Bridge 186:707f6e361f3e 179
Anna Bridge 186:707f6e361f3e 180 #define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 181 #define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 182 #define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 183 #define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 184 #define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 185 #define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 186 #define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 187 #define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 188 #define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 189 #define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 190 #define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 191 #define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 192 #define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 193 #define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 194 #define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 195 #define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 196
Anna Bridge 186:707f6e361f3e 197 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL))
Anna Bridge 186:707f6e361f3e 198 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL))
Anna Bridge 186:707f6e361f3e 199 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL))
Anna Bridge 186:707f6e361f3e 200 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL))
Anna Bridge 186:707f6e361f3e 201 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL))
Anna Bridge 186:707f6e361f3e 202 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL))
Anna Bridge 186:707f6e361f3e 203 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL))
Anna Bridge 186:707f6e361f3e 204 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL))
Anna Bridge 186:707f6e361f3e 205 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL))
Anna Bridge 186:707f6e361f3e 206 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL))
Anna Bridge 186:707f6e361f3e 207 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL))
Anna Bridge 186:707f6e361f3e 208 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL))
Anna Bridge 186:707f6e361f3e 209 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL))
Anna Bridge 186:707f6e361f3e 210 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL))
Anna Bridge 186:707f6e361f3e 211 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL))
Anna Bridge 186:707f6e361f3e 212 #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL))
Anna Bridge 186:707f6e361f3e 213
Anna Bridge 186:707f6e361f3e 214 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 215 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 216 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 217 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 218 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 219 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 220 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 221 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 222 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 223 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 224 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 225 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 226 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 227 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 228 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 229 #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
Anna Bridge 186:707f6e361f3e 230
Anna Bridge 186:707f6e361f3e 231
Anna Bridge 186:707f6e361f3e 232 #define MXC_V_WDT_LOCK_KEY 0x24
Anna Bridge 186:707f6e361f3e 233 #define MXC_V_WDT_UNLOCK_KEY 0x42
Anna Bridge 186:707f6e361f3e 234
Anna Bridge 186:707f6e361f3e 235 #define MXC_V_WDT_RESET_KEY_0 0xA5
Anna Bridge 186:707f6e361f3e 236 #define MXC_V_WDT_RESET_KEY_1 0x5A
Anna Bridge 186:707f6e361f3e 237
Anna Bridge 186:707f6e361f3e 238
Anna Bridge 186:707f6e361f3e 239 #ifdef __cplusplus
Anna Bridge 186:707f6e361f3e 240 }
Anna Bridge 186:707f6e361f3e 241 #endif
Anna Bridge 186:707f6e361f3e 242
Anna Bridge 186:707f6e361f3e 243 #endif /* _MXC_WDT_REGS_H_ */
Anna Bridge 186:707f6e361f3e 244