mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Maxim/TARGET_MAX32620C/device/system_max32620.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 186:707f6e361f3e 1 /*******************************************************************************
Anna Bridge 186:707f6e361f3e 2 * Copyright (C) 2018 Maxim Integrated Products, Inc., All Rights Reserved.
Anna Bridge 186:707f6e361f3e 3 *
Anna Bridge 186:707f6e361f3e 4 * Permission is hereby granted, free of charge, to any person obtaining a
Anna Bridge 186:707f6e361f3e 5 * copy of this software and associated documentation files (the "Software"),
Anna Bridge 186:707f6e361f3e 6 * to deal in the Software without restriction, including without limitation
Anna Bridge 186:707f6e361f3e 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Anna Bridge 186:707f6e361f3e 8 * and/or sell copies of the Software, and to permit persons to whom the
Anna Bridge 186:707f6e361f3e 9 * Software is furnished to do so, subject to the following conditions:
Anna Bridge 186:707f6e361f3e 10 *
Anna Bridge 186:707f6e361f3e 11 * The above copyright notice and this permission notice shall be included
Anna Bridge 186:707f6e361f3e 12 * in all copies or substantial portions of the Software.
Anna Bridge 186:707f6e361f3e 13 *
Anna Bridge 186:707f6e361f3e 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Anna Bridge 186:707f6e361f3e 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Anna Bridge 186:707f6e361f3e 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Anna Bridge 186:707f6e361f3e 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Anna Bridge 186:707f6e361f3e 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Anna Bridge 186:707f6e361f3e 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Anna Bridge 186:707f6e361f3e 20 * OTHER DEALINGS IN THE SOFTWARE.
Anna Bridge 186:707f6e361f3e 21 *
Anna Bridge 186:707f6e361f3e 22 * Except as contained in this notice, the name of Maxim Integrated
Anna Bridge 186:707f6e361f3e 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Anna Bridge 186:707f6e361f3e 24 * Products, Inc. Branding Policy.
Anna Bridge 186:707f6e361f3e 25 *
Anna Bridge 186:707f6e361f3e 26 * The mere transfer of this software does not imply any licenses
Anna Bridge 186:707f6e361f3e 27 * of trade secrets, proprietary technology, copyrights, patents,
Anna Bridge 186:707f6e361f3e 28 * trademarks, maskwork rights, or any other form of intellectual
Anna Bridge 186:707f6e361f3e 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Anna Bridge 186:707f6e361f3e 30 * ownership rights.
Anna Bridge 186:707f6e361f3e 31 *
Anna Bridge 186:707f6e361f3e 32 ******************************************************************************/
Anna Bridge 186:707f6e361f3e 33
Anna Bridge 186:707f6e361f3e 34 #include <string.h>
Anna Bridge 186:707f6e361f3e 35 #include <stdio.h>
Anna Bridge 186:707f6e361f3e 36 #include <stdlib.h>
Anna Bridge 186:707f6e361f3e 37 #include "max32620.h"
Anna Bridge 186:707f6e361f3e 38 #include "clkman_regs.h"
Anna Bridge 186:707f6e361f3e 39 #include "adc_regs.h"
Anna Bridge 186:707f6e361f3e 40 #include "pwrseq_regs.h"
Anna Bridge 186:707f6e361f3e 41 #include "pwrman_regs.h"
Anna Bridge 186:707f6e361f3e 42 #include "icc_regs.h"
Anna Bridge 186:707f6e361f3e 43 #include "flc_regs.h"
Anna Bridge 186:707f6e361f3e 44 #include "rtc_regs.h"
Anna Bridge 186:707f6e361f3e 45 #include "trim_regs.h"
Anna Bridge 186:707f6e361f3e 46
Anna Bridge 186:707f6e361f3e 47 #ifndef RO_FREQ
Anna Bridge 186:707f6e361f3e 48 #define RO_FREQ 96000000
Anna Bridge 186:707f6e361f3e 49 #endif
Anna Bridge 186:707f6e361f3e 50
Anna Bridge 186:707f6e361f3e 51 #ifndef LP0_POST_HOOK
Anna Bridge 186:707f6e361f3e 52 #define LP0_POST_HOOK
Anna Bridge 186:707f6e361f3e 53 #endif
Anna Bridge 186:707f6e361f3e 54
Anna Bridge 186:707f6e361f3e 55 // NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will
Anna Bridge 186:707f6e361f3e 56 // be AFTER SystemInit() runs. This is required so the hal drivers will have
Anna Bridge 186:707f6e361f3e 57 // the correct value when the DATA sections are initialized.
Anna Bridge 186:707f6e361f3e 58 uint32_t SystemCoreClock = RO_FREQ;
Anna Bridge 186:707f6e361f3e 59
Anna Bridge 186:707f6e361f3e 60 void SystemCoreClockUpdate(void)
Anna Bridge 186:707f6e361f3e 61 {
Anna Bridge 186:707f6e361f3e 62 if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) {
Anna Bridge 186:707f6e361f3e 63 /* 4 MHz source */
Anna Bridge 186:707f6e361f3e 64 if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) {
Anna Bridge 186:707f6e361f3e 65 SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >>
Anna Bridge 186:707f6e361f3e 66 MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)));
Anna Bridge 186:707f6e361f3e 67 } else {
Anna Bridge 186:707f6e361f3e 68 SystemCoreClock = 4000000;
Anna Bridge 186:707f6e361f3e 69 }
Anna Bridge 186:707f6e361f3e 70 } else {
Anna Bridge 186:707f6e361f3e 71 /* 96 MHz source */
Anna Bridge 186:707f6e361f3e 72 if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) {
Anna Bridge 186:707f6e361f3e 73 SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >>
Anna Bridge 186:707f6e361f3e 74 MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)));
Anna Bridge 186:707f6e361f3e 75 } else {
Anna Bridge 186:707f6e361f3e 76 SystemCoreClock = RO_FREQ;
Anna Bridge 186:707f6e361f3e 77 }
Anna Bridge 186:707f6e361f3e 78 }
Anna Bridge 186:707f6e361f3e 79 }
Anna Bridge 186:707f6e361f3e 80
Anna Bridge 186:707f6e361f3e 81 void CLKMAN_TrimRO(void)
Anna Bridge 186:707f6e361f3e 82 {
Anna Bridge 186:707f6e361f3e 83 uint32_t running;
Anna Bridge 186:707f6e361f3e 84 uint32_t trim;
Anna Bridge 186:707f6e361f3e 85
Anna Bridge 186:707f6e361f3e 86 /* Step 1: enable 32KHz RTC */
Anna Bridge 186:707f6e361f3e 87 running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
Anna Bridge 186:707f6e361f3e 88 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
Anna Bridge 186:707f6e361f3e 89
Anna Bridge 186:707f6e361f3e 90 /* Wait for RTC warm-up */
Anna Bridge 186:707f6e361f3e 91 while(MXC_RTCCFG->osc_ctrl & MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE) {}
Anna Bridge 186:707f6e361f3e 92
Anna Bridge 186:707f6e361f3e 93 /* Step 2: enable RO calibration complete interrupt */
Anna Bridge 186:707f6e361f3e 94 MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IE;
Anna Bridge 186:707f6e361f3e 95
Anna Bridge 186:707f6e361f3e 96 /* Step 3: clear RO calibration complete interrupt */
Anna Bridge 186:707f6e361f3e 97 MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IF;
Anna Bridge 186:707f6e361f3e 98
Anna Bridge 186:707f6e361f3e 99 /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
Anna Bridge 186:707f6e361f3e 100
Anna Bridge 186:707f6e361f3e 101 /* Step 5: write initial trim to frequency calibration initial condition register */
Anna Bridge 186:707f6e361f3e 102 trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
Anna Bridge 186:707f6e361f3e 103 MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
Anna Bridge 186:707f6e361f3e 104 ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
Anna Bridge 186:707f6e361f3e 105
Anna Bridge 186:707f6e361f3e 106 /* Step 6: load initial trim to active frequency trim register */
Anna Bridge 186:707f6e361f3e 107 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
Anna Bridge 186:707f6e361f3e 108
Anna Bridge 186:707f6e361f3e 109 /* Step 7: enable frequency loop to control RO trim */
Anna Bridge 186:707f6e361f3e 110 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
Anna Bridge 186:707f6e361f3e 111
Anna Bridge 186:707f6e361f3e 112 /* Step 8: run frequency calibration in atomic mode */
Anna Bridge 186:707f6e361f3e 113 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
Anna Bridge 186:707f6e361f3e 114
Anna Bridge 186:707f6e361f3e 115 /* Step 9: waiting for ro_cal_done flag */
Anna Bridge 186:707f6e361f3e 116 while(!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
Anna Bridge 186:707f6e361f3e 117
Anna Bridge 186:707f6e361f3e 118 /* Step 10: stop frequency calibration */
Anna Bridge 186:707f6e361f3e 119 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
Anna Bridge 186:707f6e361f3e 120
Anna Bridge 186:707f6e361f3e 121 /* Step 11: disable RO calibration complete interrupt */
Anna Bridge 186:707f6e361f3e 122 MXC_ADC->intr &= ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
Anna Bridge 186:707f6e361f3e 123
Anna Bridge 186:707f6e361f3e 124 /* Step 12: read final frequency trim value */
Anna Bridge 186:707f6e361f3e 125 trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
Anna Bridge 186:707f6e361f3e 126
Anna Bridge 186:707f6e361f3e 127 /* Step 13: write final trim to RO flash trim shadow register */
Anna Bridge 186:707f6e361f3e 128 MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
Anna Bridge 186:707f6e361f3e 129 ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
Anna Bridge 186:707f6e361f3e 130
Anna Bridge 186:707f6e361f3e 131 /* Step 14: restore RTC status */
Anna Bridge 186:707f6e361f3e 132 if (!running) {
Anna Bridge 186:707f6e361f3e 133 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
Anna Bridge 186:707f6e361f3e 134 }
Anna Bridge 186:707f6e361f3e 135
Anna Bridge 186:707f6e361f3e 136 /* Step 15: disable frequency loop to control RO trim */
Anna Bridge 186:707f6e361f3e 137 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
Anna Bridge 186:707f6e361f3e 138 }
Anna Bridge 186:707f6e361f3e 139
Anna Bridge 186:707f6e361f3e 140 static void ICC_Enable(void)
Anna Bridge 186:707f6e361f3e 141 {
Anna Bridge 186:707f6e361f3e 142 /* Invalidate cache and wait until ready */
Anna Bridge 186:707f6e361f3e 143 MXC_ICC->invdt_all = 1;
Anna Bridge 186:707f6e361f3e 144 while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
Anna Bridge 186:707f6e361f3e 145
Anna Bridge 186:707f6e361f3e 146 /* Enable cache */
Anna Bridge 186:707f6e361f3e 147 MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
Anna Bridge 186:707f6e361f3e 148
Anna Bridge 186:707f6e361f3e 149 /* Must invalidate a second time for proper use */
Anna Bridge 186:707f6e361f3e 150 MXC_ICC->invdt_all = 1;
Anna Bridge 186:707f6e361f3e 151 }
Anna Bridge 186:707f6e361f3e 152
Anna Bridge 186:707f6e361f3e 153 /* This function is called before C runtime initialization and can be
Anna Bridge 186:707f6e361f3e 154 * implemented by the application for early initializations. If a value other
Anna Bridge 186:707f6e361f3e 155 * than '0' is returned, the C runtime initialization will be skipped.
Anna Bridge 186:707f6e361f3e 156 *
Anna Bridge 186:707f6e361f3e 157 * You may over-ride this function in your program by defining a custom
Anna Bridge 186:707f6e361f3e 158 * PreInit(), but care should be taken to reproduce the initilization steps
Anna Bridge 186:707f6e361f3e 159 * or a non-functional system may result.
Anna Bridge 186:707f6e361f3e 160 */
Anna Bridge 186:707f6e361f3e 161 __weak int PreInit(void)
Anna Bridge 186:707f6e361f3e 162 {
Anna Bridge 186:707f6e361f3e 163 /* Increase system clock to 96 MHz */
Anna Bridge 186:707f6e361f3e 164 MXC_CLKMAN->clk_ctrl |= MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO;
Anna Bridge 186:707f6e361f3e 165
Anna Bridge 186:707f6e361f3e 166 /* Performance-measurement hook, may be defined as nothing */
Anna Bridge 186:707f6e361f3e 167 LP0_POST_HOOK;
Anna Bridge 186:707f6e361f3e 168
Anna Bridge 186:707f6e361f3e 169 /* Enable cache here to reduce boot time */
Anna Bridge 186:707f6e361f3e 170 ICC_Enable();
Anna Bridge 186:707f6e361f3e 171
Anna Bridge 186:707f6e361f3e 172 return 0;
Anna Bridge 186:707f6e361f3e 173 }
Anna Bridge 186:707f6e361f3e 174
Anna Bridge 186:707f6e361f3e 175 /* Override this function for early platform initialization
Anna Bridge 186:707f6e361f3e 176 */
Anna Bridge 186:707f6e361f3e 177 __weak void low_level_init(void) {}
Anna Bridge 186:707f6e361f3e 178
Anna Bridge 186:707f6e361f3e 179 /* This function is called just before control is transferred to main().
Anna Bridge 186:707f6e361f3e 180 */
Anna Bridge 186:707f6e361f3e 181 void SystemInit(void)
Anna Bridge 186:707f6e361f3e 182 {
Anna Bridge 186:707f6e361f3e 183 /* Copy trim information from shadow registers into power manager registers */
Anna Bridge 186:707f6e361f3e 184 /* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */
Anna Bridge 186:707f6e361f3e 185 if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
Anna Bridge 186:707f6e361f3e 186 (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
Anna Bridge 186:707f6e361f3e 187 (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
Anna Bridge 186:707f6e361f3e 188 MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
Anna Bridge 186:707f6e361f3e 189 MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
Anna Bridge 186:707f6e361f3e 190 } else {
Anna Bridge 186:707f6e361f3e 191 /* No valid info block, use some reasonable defaults */
Anna Bridge 186:707f6e361f3e 192 MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
Anna Bridge 186:707f6e361f3e 193 MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
Anna Bridge 186:707f6e361f3e 194 }
Anna Bridge 186:707f6e361f3e 195
Anna Bridge 186:707f6e361f3e 196 /* Improve flash access timing */
Anna Bridge 186:707f6e361f3e 197 MXC_FLC->perform |= (MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS |
Anna Bridge 186:707f6e361f3e 198 MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT |
Anna Bridge 186:707f6e361f3e 199 MXC_F_FLC_PERFORM_AUTO_TACC |
Anna Bridge 186:707f6e361f3e 200 MXC_F_FLC_PERFORM_AUTO_CLKDIV);
Anna Bridge 186:707f6e361f3e 201
Anna Bridge 186:707f6e361f3e 202 /* First, eliminate the unnecessary RTC handshake between clock domains. Must be set as a pair. */
Anna Bridge 186:707f6e361f3e 203 MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS |
Anna Bridge 186:707f6e361f3e 204 MXC_F_RTC_CTRL_AGGRESSIVE_RST);
Anna Bridge 186:707f6e361f3e 205 /* Enable fast read of the RTC timer value, and fast write of all other RTC registers */
Anna Bridge 186:707f6e361f3e 206 MXC_PWRSEQ->rtc_ctrl2 |= (MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE |
Anna Bridge 186:707f6e361f3e 207 MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR);
Anna Bridge 186:707f6e361f3e 208 MXC_PWRSEQ->rtc_ctrl2 &= ~(MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD);
Anna Bridge 186:707f6e361f3e 209
Anna Bridge 186:707f6e361f3e 210 /* Clear the GPIO WUD event if not waking up from LP0 */
Anna Bridge 186:707f6e361f3e 211 /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
Anna Bridge 186:707f6e361f3e 212 if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ||
Anna Bridge 186:707f6e361f3e 213 !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
Anna Bridge 186:707f6e361f3e 214 /* Clear GPIO WUD event and configuration registers, globally */
Anna Bridge 186:707f6e361f3e 215 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
Anna Bridge 186:707f6e361f3e 216 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
Anna Bridge 186:707f6e361f3e 217 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
Anna Bridge 186:707f6e361f3e 218 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
Anna Bridge 186:707f6e361f3e 219 } else {
Anna Bridge 186:707f6e361f3e 220 /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
Anna Bridge 186:707f6e361f3e 221 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
Anna Bridge 186:707f6e361f3e 222 /* LP0 wake-up: Turn off special switch to eliminate ~50nA of leakage on VDD12 */
Anna Bridge 186:707f6e361f3e 223 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
Anna Bridge 186:707f6e361f3e 224 }
Anna Bridge 186:707f6e361f3e 225
Anna Bridge 186:707f6e361f3e 226 /* Turn on retention regulator */
Anna Bridge 186:707f6e361f3e 227 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN |
Anna Bridge 186:707f6e361f3e 228 MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
Anna Bridge 186:707f6e361f3e 229
Anna Bridge 186:707f6e361f3e 230 /* Turn on Auto GPIO Freeze/UnFreeze in sleep modes */
Anna Bridge 186:707f6e361f3e 231 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE;
Anna Bridge 186:707f6e361f3e 232
Anna Bridge 186:707f6e361f3e 233 /* Adjust settings in the retention controller for fastest wake-up time */
Anna Bridge 186:707f6e361f3e 234 MXC_PWRSEQ->retn_ctrl0 |= (MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY |
Anna Bridge 186:707f6e361f3e 235 MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH);
Anna Bridge 186:707f6e361f3e 236 MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK);
Anna Bridge 186:707f6e361f3e 237
Anna Bridge 186:707f6e361f3e 238
Anna Bridge 186:707f6e361f3e 239 /* Set retention controller TWake cycle count to 1us to minimize the wake-up time */
Anna Bridge 186:707f6e361f3e 240 /* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */
Anna Bridge 186:707f6e361f3e 241 MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) |
Anna Bridge 186:707f6e361f3e 242 (1 << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS);
Anna Bridge 186:707f6e361f3e 243
Anna Bridge 186:707f6e361f3e 244 /* Improve wake-up time by changing ROSEL to 140ns */
Anna Bridge 186:707f6e361f3e 245 MXC_PWRSEQ->reg3 = (1 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS) |
Anna Bridge 186:707f6e361f3e 246 (1 << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS) |
Anna Bridge 186:707f6e361f3e 247 (MXC_PWRSEQ->reg3 & ~(MXC_F_PWRSEQ_REG3_PWR_ROSEL |
Anna Bridge 186:707f6e361f3e 248 MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL));
Anna Bridge 186:707f6e361f3e 249
Anna Bridge 186:707f6e361f3e 250 /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
Anna Bridge 186:707f6e361f3e 251 MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
Anna Bridge 186:707f6e361f3e 252
Anna Bridge 186:707f6e361f3e 253 /* Set this so all bits of PWR_MSK_FLAGS are active low to mask the corresponding flags */
Anna Bridge 186:707f6e361f3e 254 MXC_PWRSEQ->pwr_misc |= MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS;
Anna Bridge 186:707f6e361f3e 255
Anna Bridge 186:707f6e361f3e 256 /* Clear this bit to get the latest PT */
Anna Bridge 186:707f6e361f3e 257 MXC_PWRMAN->pt_regmap_ctrl &= ~MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE;
Anna Bridge 186:707f6e361f3e 258
Anna Bridge 186:707f6e361f3e 259 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
Anna Bridge 186:707f6e361f3e 260 /* Grant full access, per "Table B3-24 CPACR bit assignments". */
Anna Bridge 186:707f6e361f3e 261 /* DDI0403D "ARMv7-M Architecture Reference Manual" */
Anna Bridge 186:707f6e361f3e 262 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
Anna Bridge 186:707f6e361f3e 263 __DSB();
Anna Bridge 186:707f6e361f3e 264 __ISB();
Anna Bridge 186:707f6e361f3e 265
Anna Bridge 186:707f6e361f3e 266 /* Early platform initialization */
Anna Bridge 186:707f6e361f3e 267 low_level_init();
Anna Bridge 186:707f6e361f3e 268
Anna Bridge 186:707f6e361f3e 269 /* Perform an initial trim of the internal ring oscillator */
Anna Bridge 186:707f6e361f3e 270 CLKMAN_TrimRO();
Anna Bridge 186:707f6e361f3e 271 }