mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_Maxim/TARGET_MAX32620C/device/spis_regs.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 186:707f6e361f3e
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Anna Bridge |
186:707f6e361f3e | 1 | /******************************************************************************* |
Anna Bridge |
186:707f6e361f3e | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
Anna Bridge |
186:707f6e361f3e | 3 | * |
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186:707f6e361f3e | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
Anna Bridge |
186:707f6e361f3e | 5 | * copy of this software and associated documentation files (the "Software"), |
Anna Bridge |
186:707f6e361f3e | 6 | * to deal in the Software without restriction, including without limitation |
Anna Bridge |
186:707f6e361f3e | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
Anna Bridge |
186:707f6e361f3e | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Anna Bridge |
186:707f6e361f3e | 9 | * Software is furnished to do so, subject to the following conditions: |
Anna Bridge |
186:707f6e361f3e | 10 | * |
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186:707f6e361f3e | 11 | * The above copyright notice and this permission notice shall be included |
Anna Bridge |
186:707f6e361f3e | 12 | * in all copies or substantial portions of the Software. |
Anna Bridge |
186:707f6e361f3e | 13 | * |
Anna Bridge |
186:707f6e361f3e | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Anna Bridge |
186:707f6e361f3e | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Anna Bridge |
186:707f6e361f3e | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Anna Bridge |
186:707f6e361f3e | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
Anna Bridge |
186:707f6e361f3e | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Anna Bridge |
186:707f6e361f3e | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Anna Bridge |
186:707f6e361f3e | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Anna Bridge |
186:707f6e361f3e | 21 | * |
Anna Bridge |
186:707f6e361f3e | 22 | * Except as contained in this notice, the name of Maxim Integrated |
Anna Bridge |
186:707f6e361f3e | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
Anna Bridge |
186:707f6e361f3e | 24 | * Products, Inc. Branding Policy. |
Anna Bridge |
186:707f6e361f3e | 25 | * |
Anna Bridge |
186:707f6e361f3e | 26 | * The mere transfer of this software does not imply any licenses |
Anna Bridge |
186:707f6e361f3e | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Anna Bridge |
186:707f6e361f3e | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Anna Bridge |
186:707f6e361f3e | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
Anna Bridge |
186:707f6e361f3e | 30 | * ownership rights. |
Anna Bridge |
186:707f6e361f3e | 31 | * |
Anna Bridge |
186:707f6e361f3e | 32 | * $Date: 2016-06-03 14:21:38 -0500 (Fri, 03 Jun 2016) $ |
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186:707f6e361f3e | 33 | * $Revision: 23194 $ |
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186:707f6e361f3e | 34 | * |
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186:707f6e361f3e | 35 | ******************************************************************************/ |
Anna Bridge |
186:707f6e361f3e | 36 | |
Anna Bridge |
186:707f6e361f3e | 37 | #ifndef _MXC_SPIS_REGS_H_ |
Anna Bridge |
186:707f6e361f3e | 38 | #define _MXC_SPIS_REGS_H_ |
Anna Bridge |
186:707f6e361f3e | 39 | |
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186:707f6e361f3e | 40 | #ifdef __cplusplus |
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186:707f6e361f3e | 41 | extern "C" { |
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186:707f6e361f3e | 42 | #endif |
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186:707f6e361f3e | 43 | |
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186:707f6e361f3e | 44 | #include <stdint.h> |
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186:707f6e361f3e | 45 | |
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186:707f6e361f3e | 46 | /* |
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186:707f6e361f3e | 47 | If types are not defined elsewhere (CMSIS) define them here |
Anna Bridge |
186:707f6e361f3e | 48 | */ |
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186:707f6e361f3e | 49 | #ifndef __IO |
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186:707f6e361f3e | 50 | #define __IO volatile |
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186:707f6e361f3e | 51 | #endif |
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186:707f6e361f3e | 52 | #ifndef __I |
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186:707f6e361f3e | 53 | #define __I volatile const |
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186:707f6e361f3e | 54 | #endif |
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186:707f6e361f3e | 55 | #ifndef __O |
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186:707f6e361f3e | 56 | #define __O volatile |
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186:707f6e361f3e | 57 | #endif |
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186:707f6e361f3e | 58 | #ifndef __RO |
Anna Bridge |
186:707f6e361f3e | 59 | #define __RO volatile const |
Anna Bridge |
186:707f6e361f3e | 60 | #endif |
Anna Bridge |
186:707f6e361f3e | 61 | |
Anna Bridge |
186:707f6e361f3e | 62 | |
Anna Bridge |
186:707f6e361f3e | 63 | /* |
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186:707f6e361f3e | 64 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
Anna Bridge |
186:707f6e361f3e | 65 | access to each register in module. |
Anna Bridge |
186:707f6e361f3e | 66 | */ |
Anna Bridge |
186:707f6e361f3e | 67 | |
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186:707f6e361f3e | 68 | /* Offset Register Description |
Anna Bridge |
186:707f6e361f3e | 69 | ============= ============================================================================ */ |
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186:707f6e361f3e | 70 | typedef struct { |
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186:707f6e361f3e | 71 | __IO uint32_t gen_ctrl; /* 0x0000 SPI Slave General Control Register */ |
Anna Bridge |
186:707f6e361f3e | 72 | __IO uint32_t fifo_ctrl; /* 0x0004 SPI Slave FIFO Control Register */ |
Anna Bridge |
186:707f6e361f3e | 73 | __IO uint32_t fifo_stat; /* 0x0008 SPI Slave FIFO Status Register */ |
Anna Bridge |
186:707f6e361f3e | 74 | __IO uint32_t intfl; /* 0x000C SPI Slave Interrupt Flags */ |
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186:707f6e361f3e | 75 | __IO uint32_t inten; /* 0x0010 SPI Slave Interrupt Enable/Disable Settings */ |
Anna Bridge |
186:707f6e361f3e | 76 | } mxc_spis_regs_t; |
Anna Bridge |
186:707f6e361f3e | 77 | |
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186:707f6e361f3e | 78 | |
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186:707f6e361f3e | 79 | /* Offset Register Description |
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186:707f6e361f3e | 80 | ============= ============================================================================ */ |
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186:707f6e361f3e | 81 | typedef struct { |
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186:707f6e361f3e | 82 | union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */ |
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186:707f6e361f3e | 83 | __IO uint8_t tx_8[2048]; |
Anna Bridge |
186:707f6e361f3e | 84 | __IO uint16_t tx_16[1024]; |
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186:707f6e361f3e | 85 | __IO uint32_t tx_32[512]; |
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186:707f6e361f3e | 86 | }; |
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186:707f6e361f3e | 87 | union { /* 0x0800-0x0FFC SPI Slave FIFO RX Read Space */ |
Anna Bridge |
186:707f6e361f3e | 88 | __IO uint8_t rx_8[2048]; |
Anna Bridge |
186:707f6e361f3e | 89 | __IO uint16_t rx_16[1024]; |
Anna Bridge |
186:707f6e361f3e | 90 | __IO uint32_t rx_32[512]; |
Anna Bridge |
186:707f6e361f3e | 91 | }; |
Anna Bridge |
186:707f6e361f3e | 92 | } mxc_spis_fifo_regs_t; |
Anna Bridge |
186:707f6e361f3e | 93 | |
Anna Bridge |
186:707f6e361f3e | 94 | |
Anna Bridge |
186:707f6e361f3e | 95 | /* |
Anna Bridge |
186:707f6e361f3e | 96 | Register offsets for module SPIS. |
Anna Bridge |
186:707f6e361f3e | 97 | */ |
Anna Bridge |
186:707f6e361f3e | 98 | |
Anna Bridge |
186:707f6e361f3e | 99 | #define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL) |
Anna Bridge |
186:707f6e361f3e | 100 | #define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL) |
Anna Bridge |
186:707f6e361f3e | 101 | #define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL) |
Anna Bridge |
186:707f6e361f3e | 102 | #define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL) |
Anna Bridge |
186:707f6e361f3e | 103 | #define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL) |
Anna Bridge |
186:707f6e361f3e | 104 | #define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL) |
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186:707f6e361f3e | 105 | #define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL) |
Anna Bridge |
186:707f6e361f3e | 106 | |
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186:707f6e361f3e | 107 | |
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186:707f6e361f3e | 108 | /* |
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186:707f6e361f3e | 109 | Field positions and masks for module SPIS. |
Anna Bridge |
186:707f6e361f3e | 110 | */ |
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186:707f6e361f3e | 111 | |
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186:707f6e361f3e | 112 | #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0 |
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186:707f6e361f3e | 113 | #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS)) |
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186:707f6e361f3e | 114 | #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1 |
Anna Bridge |
186:707f6e361f3e | 115 | #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS)) |
Anna Bridge |
186:707f6e361f3e | 116 | #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2 |
Anna Bridge |
186:707f6e361f3e | 117 | #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS)) |
Anna Bridge |
186:707f6e361f3e | 118 | #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4 |
Anna Bridge |
186:707f6e361f3e | 119 | #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS)) |
Anna Bridge |
186:707f6e361f3e | 120 | #define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16 |
Anna Bridge |
186:707f6e361f3e | 121 | #define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS)) |
Anna Bridge |
186:707f6e361f3e | 122 | #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20 |
Anna Bridge |
186:707f6e361f3e | 123 | #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS)) |
Anna Bridge |
186:707f6e361f3e | 124 | |
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186:707f6e361f3e | 125 | #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 |
Anna Bridge |
186:707f6e361f3e | 126 | #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) |
Anna Bridge |
186:707f6e361f3e | 127 | #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8 |
Anna Bridge |
186:707f6e361f3e | 128 | #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) |
Anna Bridge |
186:707f6e361f3e | 129 | |
Anna Bridge |
186:707f6e361f3e | 130 | #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0 |
Anna Bridge |
186:707f6e361f3e | 131 | #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS)) |
Anna Bridge |
186:707f6e361f3e | 132 | #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8 |
Anna Bridge |
186:707f6e361f3e | 133 | #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS)) |
Anna Bridge |
186:707f6e361f3e | 134 | |
Anna Bridge |
186:707f6e361f3e | 135 | #define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0 |
Anna Bridge |
186:707f6e361f3e | 136 | #define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS)) |
Anna Bridge |
186:707f6e361f3e | 137 | #define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1 |
Anna Bridge |
186:707f6e361f3e | 138 | #define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS)) |
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186:707f6e361f3e | 139 | #define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2 |
Anna Bridge |
186:707f6e361f3e | 140 | #define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS)) |
Anna Bridge |
186:707f6e361f3e | 141 | #define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3 |
Anna Bridge |
186:707f6e361f3e | 142 | #define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS)) |
Anna Bridge |
186:707f6e361f3e | 143 | #define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4 |
Anna Bridge |
186:707f6e361f3e | 144 | #define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS)) |
Anna Bridge |
186:707f6e361f3e | 145 | #define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5 |
Anna Bridge |
186:707f6e361f3e | 146 | #define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS)) |
Anna Bridge |
186:707f6e361f3e | 147 | #define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6 |
Anna Bridge |
186:707f6e361f3e | 148 | #define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS)) |
Anna Bridge |
186:707f6e361f3e | 149 | |
Anna Bridge |
186:707f6e361f3e | 150 | #define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0 |
Anna Bridge |
186:707f6e361f3e | 151 | #define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS)) |
Anna Bridge |
186:707f6e361f3e | 152 | #define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1 |
Anna Bridge |
186:707f6e361f3e | 153 | #define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS)) |
Anna Bridge |
186:707f6e361f3e | 154 | #define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2 |
Anna Bridge |
186:707f6e361f3e | 155 | #define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS)) |
Anna Bridge |
186:707f6e361f3e | 156 | #define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3 |
Anna Bridge |
186:707f6e361f3e | 157 | #define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS)) |
Anna Bridge |
186:707f6e361f3e | 158 | #define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4 |
Anna Bridge |
186:707f6e361f3e | 159 | #define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS)) |
Anna Bridge |
186:707f6e361f3e | 160 | #define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5 |
Anna Bridge |
186:707f6e361f3e | 161 | #define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS)) |
Anna Bridge |
186:707f6e361f3e | 162 | #define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6 |
Anna Bridge |
186:707f6e361f3e | 163 | #define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS)) |
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186:707f6e361f3e | 164 | |
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186:707f6e361f3e | 165 | #ifdef __cplusplus |
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186:707f6e361f3e | 166 | } |
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186:707f6e361f3e | 167 | #endif |
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186:707f6e361f3e | 168 | |
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186:707f6e361f3e | 169 | #endif /* _MXC_SPIS_REGS_H_ */ |
Anna Bridge |
186:707f6e361f3e | 170 |