mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_Maxim/TARGET_MAX32620C/device/spib_regs.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 186:707f6e361f3e
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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186:707f6e361f3e | 1 | /******************************************************************************* |
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186:707f6e361f3e | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
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186:707f6e361f3e | 3 | * |
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186:707f6e361f3e | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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186:707f6e361f3e | 5 | * copy of this software and associated documentation files (the "Software"), |
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186:707f6e361f3e | 6 | * to deal in the Software without restriction, including without limitation |
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186:707f6e361f3e | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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186:707f6e361f3e | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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186:707f6e361f3e | 9 | * Software is furnished to do so, subject to the following conditions: |
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186:707f6e361f3e | 10 | * |
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186:707f6e361f3e | 11 | * The above copyright notice and this permission notice shall be included |
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186:707f6e361f3e | 12 | * in all copies or substantial portions of the Software. |
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186:707f6e361f3e | 13 | * |
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186:707f6e361f3e | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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186:707f6e361f3e | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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186:707f6e361f3e | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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186:707f6e361f3e | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
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186:707f6e361f3e | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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186:707f6e361f3e | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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186:707f6e361f3e | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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186:707f6e361f3e | 21 | * |
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186:707f6e361f3e | 22 | * Except as contained in this notice, the name of Maxim Integrated |
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186:707f6e361f3e | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
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186:707f6e361f3e | 24 | * Products, Inc. Branding Policy. |
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186:707f6e361f3e | 25 | * |
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186:707f6e361f3e | 26 | * The mere transfer of this software does not imply any licenses |
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186:707f6e361f3e | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Anna Bridge |
186:707f6e361f3e | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Anna Bridge |
186:707f6e361f3e | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
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186:707f6e361f3e | 30 | * ownership rights. |
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186:707f6e361f3e | 31 | * |
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186:707f6e361f3e | 32 | * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $ |
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186:707f6e361f3e | 33 | * $Revision: 21838 $ |
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186:707f6e361f3e | 34 | * |
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186:707f6e361f3e | 35 | ******************************************************************************/ |
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186:707f6e361f3e | 36 | |
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186:707f6e361f3e | 37 | #ifndef _MXC_SPIB_REGS_H_ |
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186:707f6e361f3e | 38 | #define _MXC_SPIB_REGS_H_ |
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186:707f6e361f3e | 39 | |
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186:707f6e361f3e | 40 | #ifdef __cplusplus |
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186:707f6e361f3e | 41 | extern "C" { |
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186:707f6e361f3e | 42 | #endif |
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186:707f6e361f3e | 43 | |
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186:707f6e361f3e | 44 | #include <stdint.h> |
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186:707f6e361f3e | 45 | |
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186:707f6e361f3e | 46 | /* |
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186:707f6e361f3e | 47 | If types are not defined elsewhere (CMSIS) define them here |
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186:707f6e361f3e | 48 | */ |
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186:707f6e361f3e | 49 | #ifndef __IO |
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186:707f6e361f3e | 50 | #define __IO volatile |
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186:707f6e361f3e | 51 | #endif |
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186:707f6e361f3e | 52 | #ifndef __I |
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186:707f6e361f3e | 53 | #define __I volatile const |
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186:707f6e361f3e | 54 | #endif |
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186:707f6e361f3e | 55 | #ifndef __O |
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186:707f6e361f3e | 56 | #define __O volatile |
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186:707f6e361f3e | 57 | #endif |
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186:707f6e361f3e | 58 | #ifndef __RO |
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186:707f6e361f3e | 59 | #define __RO volatile const |
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186:707f6e361f3e | 60 | #endif |
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186:707f6e361f3e | 61 | |
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186:707f6e361f3e | 62 | |
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186:707f6e361f3e | 63 | /* |
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186:707f6e361f3e | 64 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
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186:707f6e361f3e | 65 | access to each register in module. |
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186:707f6e361f3e | 66 | */ |
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186:707f6e361f3e | 67 | |
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186:707f6e361f3e | 68 | /* Offset Register Description |
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186:707f6e361f3e | 69 | ============= ============================================================================ */ |
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186:707f6e361f3e | 70 | typedef struct { |
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186:707f6e361f3e | 71 | __IO uint32_t master_cfg; /* 0x0000 SPIB Master Configuration */ |
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186:707f6e361f3e | 72 | __IO uint32_t oob_ctrl; /* 0x0004 SPIB OOB Control */ |
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186:707f6e361f3e | 73 | __IO uint32_t intfl; /* 0x0008 SPIB Interrupt Flags */ |
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186:707f6e361f3e | 74 | __IO uint32_t inten; /* 0x000C SPIB Interrupt Enables */ |
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186:707f6e361f3e | 75 | __IO uint32_t slave_reg; /* 0x0010 SPIB Slave Register Access */ |
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186:707f6e361f3e | 76 | } mxc_spib_regs_t; |
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186:707f6e361f3e | 77 | |
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186:707f6e361f3e | 78 | |
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186:707f6e361f3e | 79 | /* |
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186:707f6e361f3e | 80 | Register offsets for module SPIB. |
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186:707f6e361f3e | 81 | */ |
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186:707f6e361f3e | 82 | |
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186:707f6e361f3e | 83 | #define MXC_R_SPIB_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) |
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186:707f6e361f3e | 84 | #define MXC_R_SPIB_OFFS_OOB_CTRL ((uint32_t)0x00000004UL) |
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186:707f6e361f3e | 85 | #define MXC_R_SPIB_OFFS_INTFL ((uint32_t)0x00000008UL) |
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186:707f6e361f3e | 86 | #define MXC_R_SPIB_OFFS_INTEN ((uint32_t)0x0000000CUL) |
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186:707f6e361f3e | 87 | #define MXC_R_SPIB_OFFS_SLAVE_REG ((uint32_t)0x00000010UL) |
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186:707f6e361f3e | 88 | |
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186:707f6e361f3e | 89 | |
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186:707f6e361f3e | 90 | /* |
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186:707f6e361f3e | 91 | Field positions and masks for module SPIB. |
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186:707f6e361f3e | 92 | */ |
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186:707f6e361f3e | 93 | |
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186:707f6e361f3e | 94 | #define MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS 0 |
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186:707f6e361f3e | 95 | #define MXC_F_SPIB_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) |
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186:707f6e361f3e | 96 | #define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS 2 |
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186:707f6e361f3e | 97 | #define MXC_F_SPIB_MASTER_CFG_SPI_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) |
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186:707f6e361f3e | 98 | #define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS 8 |
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186:707f6e361f3e | 99 | #define MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_HI_CLK_POS)) |
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186:707f6e361f3e | 100 | #define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS 12 |
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186:707f6e361f3e | 101 | #define MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIB_MASTER_CFG_SCK_LO_CLK_POS)) |
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186:707f6e361f3e | 102 | #define MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS 16 |
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186:707f6e361f3e | 103 | #define MXC_F_SPIB_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) |
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186:707f6e361f3e | 104 | #define MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS 18 |
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186:707f6e361f3e | 105 | #define MXC_F_SPIB_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) |
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186:707f6e361f3e | 106 | |
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186:707f6e361f3e | 107 | #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS 0 |
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186:707f6e361f3e | 108 | #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) |
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186:707f6e361f3e | 109 | #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS 1 |
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186:707f6e361f3e | 110 | #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) |
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186:707f6e361f3e | 111 | #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS 2 |
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186:707f6e361f3e | 112 | #define MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2 ((uint32_t)(0x00000001UL << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) |
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186:707f6e361f3e | 113 | |
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186:707f6e361f3e | 114 | #define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS 0 |
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186:707f6e361f3e | 115 | #define MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) |
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186:707f6e361f3e | 116 | #define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS 1 |
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186:707f6e361f3e | 117 | #define MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) |
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186:707f6e361f3e | 118 | #define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS 2 |
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186:707f6e361f3e | 119 | #define MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) |
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186:707f6e361f3e | 120 | |
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186:707f6e361f3e | 121 | #define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS 0 |
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186:707f6e361f3e | 122 | #define MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) |
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186:707f6e361f3e | 123 | #define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS 1 |
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186:707f6e361f3e | 124 | #define MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) |
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186:707f6e361f3e | 125 | #define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS 2 |
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186:707f6e361f3e | 126 | #define MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP ((uint32_t)(0x00000001UL << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) |
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186:707f6e361f3e | 127 | |
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186:707f6e361f3e | 128 | #define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS 0 |
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186:707f6e361f3e | 129 | #define MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ENABLE_SLAVE_REG_ACCESS_POS)) |
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186:707f6e361f3e | 130 | #define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS 1 |
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186:707f6e361f3e | 131 | #define MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_START_ACCESS_CYCLE_POS)) |
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186:707f6e361f3e | 132 | #define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS 2 |
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186:707f6e361f3e | 133 | #define MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE ((uint32_t)(0x00000001UL << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) |
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186:707f6e361f3e | 134 | #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS 8 |
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186:707f6e361f3e | 135 | #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_WRITE_DATA_POS)) |
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186:707f6e361f3e | 136 | #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS 16 |
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186:707f6e361f3e | 137 | #define MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA ((uint32_t)(0x000000FFUL << MXC_F_SPIB_SLAVE_REG_SLAVE_REG_READ_DATA_POS)) |
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186:707f6e361f3e | 138 | |
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186:707f6e361f3e | 139 | |
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186:707f6e361f3e | 140 | |
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186:707f6e361f3e | 141 | /* |
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186:707f6e361f3e | 142 | Field values and shifted values for module SPIB. |
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186:707f6e361f3e | 143 | */ |
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186:707f6e361f3e | 144 | |
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186:707f6e361f3e | 145 | #define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 146 | #define MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) |
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186:707f6e361f3e | 147 | |
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186:707f6e361f3e | 148 | #define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) |
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186:707f6e361f3e | 149 | #define MXC_S_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIB_MASTER_CFG_SPI_MODE_POS)) |
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186:707f6e361f3e | 150 | |
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186:707f6e361f3e | 151 | #define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 152 | #define MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 153 | |
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186:707f6e361f3e | 154 | #define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_HIGH << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) |
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186:707f6e361f3e | 155 | #define MXC_S_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW ((uint32_t)(MXC_V_SPIB_MASTER_CFG_SPI_WIDTH_ACTIVE_LOW << MXC_F_SPIB_MASTER_CFG_SPI_WIDTH_POS)) |
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186:707f6e361f3e | 156 | |
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186:707f6e361f3e | 157 | #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 158 | #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 159 | #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) |
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186:707f6e361f3e | 160 | #define MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) |
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186:707f6e361f3e | 161 | |
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186:707f6e361f3e | 162 | #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) |
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186:707f6e361f3e | 163 | #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) |
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186:707f6e361f3e | 164 | #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) |
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186:707f6e361f3e | 165 | #define MXC_S_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_ACT_DELAY_POS)) |
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186:707f6e361f3e | 166 | |
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186:707f6e361f3e | 167 | #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 168 | #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 169 | #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) |
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186:707f6e361f3e | 170 | #define MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) |
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186:707f6e361f3e | 171 | |
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186:707f6e361f3e | 172 | #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) |
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186:707f6e361f3e | 173 | #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) |
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186:707f6e361f3e | 174 | #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) |
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186:707f6e361f3e | 175 | #define MXC_S_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIB_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIB_MASTER_CFG_INACT_DELAY_POS)) |
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186:707f6e361f3e | 176 | |
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186:707f6e361f3e | 177 | #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 178 | #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 179 | |
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186:707f6e361f3e | 180 | #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) |
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186:707f6e361f3e | 181 | #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT0_POS)) |
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186:707f6e361f3e | 182 | |
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186:707f6e361f3e | 183 | #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 184 | #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 185 | |
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186:707f6e361f3e | 186 | #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) |
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186:707f6e361f3e | 187 | #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT1_POS)) |
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186:707f6e361f3e | 188 | |
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186:707f6e361f3e | 189 | #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 190 | #define MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 191 | |
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186:707f6e361f3e | 192 | #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_DISABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) |
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186:707f6e361f3e | 193 | #define MXC_S_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED ((uint32_t)(MXC_V_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_ENABLED << MXC_F_SPIB_OOB_CTRL_MONITOR_SLAVE_INT2_POS)) |
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186:707f6e361f3e | 194 | |
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186:707f6e361f3e | 195 | #define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 196 | #define MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 197 | |
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186:707f6e361f3e | 198 | #define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_NONE << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) |
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186:707f6e361f3e | 199 | #define MXC_S_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT0_SYS_INT_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT0_SYS_INT_POS)) |
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186:707f6e361f3e | 200 | |
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186:707f6e361f3e | 201 | #define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 202 | #define MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 203 | |
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186:707f6e361f3e | 204 | #define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_NONE << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) |
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186:707f6e361f3e | 205 | #define MXC_S_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT1_SYS_RST_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT1_SYS_RST_POS)) |
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186:707f6e361f3e | 206 | |
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186:707f6e361f3e | 207 | #define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 208 | #define MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 209 | |
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186:707f6e361f3e | 210 | #define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_NONE << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) |
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186:707f6e361f3e | 211 | #define MXC_S_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED ((uint32_t)(MXC_V_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_DETECTED << MXC_F_SPIB_INTFL_SLAVE_INT2_BAD_AHB_RESP_POS)) |
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186:707f6e361f3e | 212 | |
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186:707f6e361f3e | 213 | #define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 214 | #define MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 215 | |
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186:707f6e361f3e | 216 | #define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) |
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186:707f6e361f3e | 217 | #define MXC_S_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT0_SYS_INT_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT0_SYS_INT_POS)) |
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186:707f6e361f3e | 218 | |
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186:707f6e361f3e | 219 | #define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 220 | #define MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 221 | |
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186:707f6e361f3e | 222 | #define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) |
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186:707f6e361f3e | 223 | #define MXC_S_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT1_SYS_RST_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT1_SYS_RST_POS)) |
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186:707f6e361f3e | 224 | |
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186:707f6e361f3e | 225 | #define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 226 | #define MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 227 | |
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186:707f6e361f3e | 228 | #define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_DISABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) |
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186:707f6e361f3e | 229 | #define MXC_S_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED ((uint32_t)(MXC_V_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_ENABLED << MXC_F_SPIB_INTEN_SLAVE_INT2_BAD_AHB_RESP_POS)) |
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186:707f6e361f3e | 230 | |
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186:707f6e361f3e | 231 | #define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 232 | #define MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 233 | |
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186:707f6e361f3e | 234 | #define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_READ ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_READ << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) |
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186:707f6e361f3e | 235 | #define MXC_S_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE ((uint32_t)(MXC_V_SPIB_SLAVE_REG_ACCESS_TYPE_WRITE << MXC_F_SPIB_SLAVE_REG_ACCESS_TYPE_POS)) |
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186:707f6e361f3e | 236 | |
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186:707f6e361f3e | 237 | |
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186:707f6e361f3e | 238 | |
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186:707f6e361f3e | 239 | #ifdef __cplusplus |
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186:707f6e361f3e | 240 | } |
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186:707f6e361f3e | 241 | #endif |
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186:707f6e361f3e | 242 | |
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186:707f6e361f3e | 243 | #endif /* _MXC_SPIB_REGS_H_ */ |
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186:707f6e361f3e | 244 |