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mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_Maxim/TARGET_MAX32620C/device/pt_regs.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 186:707f6e361f3e
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
186:707f6e361f3e | 1 | /******************************************************************************* |
| Anna Bridge |
186:707f6e361f3e | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Anna Bridge |
186:707f6e361f3e | 3 | * |
| Anna Bridge |
186:707f6e361f3e | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Anna Bridge |
186:707f6e361f3e | 5 | * copy of this software and associated documentation files (the "Software"), |
| Anna Bridge |
186:707f6e361f3e | 6 | * to deal in the Software without restriction, including without limitation |
| Anna Bridge |
186:707f6e361f3e | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Anna Bridge |
186:707f6e361f3e | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Anna Bridge |
186:707f6e361f3e | 9 | * Software is furnished to do so, subject to the following conditions: |
| Anna Bridge |
186:707f6e361f3e | 10 | * |
| Anna Bridge |
186:707f6e361f3e | 11 | * The above copyright notice and this permission notice shall be included |
| Anna Bridge |
186:707f6e361f3e | 12 | * in all copies or substantial portions of the Software. |
| Anna Bridge |
186:707f6e361f3e | 13 | * |
| Anna Bridge |
186:707f6e361f3e | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Anna Bridge |
186:707f6e361f3e | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Anna Bridge |
186:707f6e361f3e | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Anna Bridge |
186:707f6e361f3e | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Anna Bridge |
186:707f6e361f3e | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Anna Bridge |
186:707f6e361f3e | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Anna Bridge |
186:707f6e361f3e | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Anna Bridge |
186:707f6e361f3e | 21 | * |
| Anna Bridge |
186:707f6e361f3e | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Anna Bridge |
186:707f6e361f3e | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Anna Bridge |
186:707f6e361f3e | 24 | * Products, Inc. Branding Policy. |
| Anna Bridge |
186:707f6e361f3e | 25 | * |
| Anna Bridge |
186:707f6e361f3e | 26 | * The mere transfer of this software does not imply any licenses |
| Anna Bridge |
186:707f6e361f3e | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Anna Bridge |
186:707f6e361f3e | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Anna Bridge |
186:707f6e361f3e | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Anna Bridge |
186:707f6e361f3e | 30 | * ownership rights. |
| Anna Bridge |
186:707f6e361f3e | 31 | * |
| Anna Bridge |
186:707f6e361f3e | 32 | * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $ |
| Anna Bridge |
186:707f6e361f3e | 33 | * $Revision: 21839 $ |
| Anna Bridge |
186:707f6e361f3e | 34 | * |
| Anna Bridge |
186:707f6e361f3e | 35 | ******************************************************************************/ |
| Anna Bridge |
186:707f6e361f3e | 36 | |
| Anna Bridge |
186:707f6e361f3e | 37 | #ifndef _MXC_PT_REGS_H_ |
| Anna Bridge |
186:707f6e361f3e | 38 | #define _MXC_PT_REGS_H_ |
| Anna Bridge |
186:707f6e361f3e | 39 | |
| Anna Bridge |
186:707f6e361f3e | 40 | #ifdef __cplusplus |
| Anna Bridge |
186:707f6e361f3e | 41 | extern "C" { |
| Anna Bridge |
186:707f6e361f3e | 42 | #endif |
| Anna Bridge |
186:707f6e361f3e | 43 | |
| Anna Bridge |
186:707f6e361f3e | 44 | #include <stdint.h> |
| Anna Bridge |
186:707f6e361f3e | 45 | |
| Anna Bridge |
186:707f6e361f3e | 46 | /* |
| Anna Bridge |
186:707f6e361f3e | 47 | If types are not defined elsewhere (CMSIS) define them here |
| Anna Bridge |
186:707f6e361f3e | 48 | */ |
| Anna Bridge |
186:707f6e361f3e | 49 | #ifndef __IO |
| Anna Bridge |
186:707f6e361f3e | 50 | #define __IO volatile |
| Anna Bridge |
186:707f6e361f3e | 51 | #endif |
| Anna Bridge |
186:707f6e361f3e | 52 | #ifndef __I |
| Anna Bridge |
186:707f6e361f3e | 53 | #define __I volatile const |
| Anna Bridge |
186:707f6e361f3e | 54 | #endif |
| Anna Bridge |
186:707f6e361f3e | 55 | #ifndef __O |
| Anna Bridge |
186:707f6e361f3e | 56 | #define __O volatile |
| Anna Bridge |
186:707f6e361f3e | 57 | #endif |
| Anna Bridge |
186:707f6e361f3e | 58 | #ifndef __RO |
| Anna Bridge |
186:707f6e361f3e | 59 | #define __RO volatile const |
| Anna Bridge |
186:707f6e361f3e | 60 | #endif |
| Anna Bridge |
186:707f6e361f3e | 61 | |
| Anna Bridge |
186:707f6e361f3e | 62 | |
| Anna Bridge |
186:707f6e361f3e | 63 | /* |
| Anna Bridge |
186:707f6e361f3e | 64 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Anna Bridge |
186:707f6e361f3e | 65 | access to each register in module. |
| Anna Bridge |
186:707f6e361f3e | 66 | */ |
| Anna Bridge |
186:707f6e361f3e | 67 | |
| Anna Bridge |
186:707f6e361f3e | 68 | /* Offset Register Description |
| Anna Bridge |
186:707f6e361f3e | 69 | ============= ============================================================================ */ |
| Anna Bridge |
186:707f6e361f3e | 70 | typedef struct { |
| Anna Bridge |
186:707f6e361f3e | 71 | __IO uint32_t enable; /* 0x0000 Global Enable/Disable Controls for All Pulse Trains */ |
| Anna Bridge |
186:707f6e361f3e | 72 | __IO uint32_t resync; /* 0x0004 Global Resync (All Pulse Trains) Control */ |
| Anna Bridge |
186:707f6e361f3e | 73 | __IO uint32_t intfl; /* 0x0008 Pulse Train Interrupt Flags */ |
| Anna Bridge |
186:707f6e361f3e | 74 | __IO uint32_t inten; /* 0x000C Pulse Train Interrupt Enable/Disable */ |
| Anna Bridge |
186:707f6e361f3e | 75 | } mxc_ptg_regs_t; |
| Anna Bridge |
186:707f6e361f3e | 76 | |
| Anna Bridge |
186:707f6e361f3e | 77 | |
| Anna Bridge |
186:707f6e361f3e | 78 | /* Offset Register Description |
| Anna Bridge |
186:707f6e361f3e | 79 | ============= ============================================================================ */ |
| Anna Bridge |
186:707f6e361f3e | 80 | typedef struct { |
| Anna Bridge |
186:707f6e361f3e | 81 | __IO uint32_t rate_length; /* 0x0000 Pulse Train Configuration */ |
| Anna Bridge |
186:707f6e361f3e | 82 | __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */ |
| Anna Bridge |
186:707f6e361f3e | 83 | __IO uint32_t loop; /* 0x0008 Pulse Train Loop Configuration */ |
| Anna Bridge |
186:707f6e361f3e | 84 | __IO uint32_t restart; /* 0x000C Pulse Train Auto-Restart Configuration */ |
| Anna Bridge |
186:707f6e361f3e | 85 | } mxc_pt_regs_t; |
| Anna Bridge |
186:707f6e361f3e | 86 | |
| Anna Bridge |
186:707f6e361f3e | 87 | |
| Anna Bridge |
186:707f6e361f3e | 88 | /* |
| Anna Bridge |
186:707f6e361f3e | 89 | Register offsets for module PT. |
| Anna Bridge |
186:707f6e361f3e | 90 | */ |
| Anna Bridge |
186:707f6e361f3e | 91 | |
| Anna Bridge |
186:707f6e361f3e | 92 | #define MXC_R_PTG_OFFS_ENABLE ((uint32_t)0x00000000UL) |
| Anna Bridge |
186:707f6e361f3e | 93 | #define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) |
| Anna Bridge |
186:707f6e361f3e | 94 | #define MXC_R_PTG_OFFS_INTFL ((uint32_t)0x00000008UL) |
| Anna Bridge |
186:707f6e361f3e | 95 | #define MXC_R_PTG_OFFS_INTEN ((uint32_t)0x0000000CUL) |
| Anna Bridge |
186:707f6e361f3e | 96 | #define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) |
| Anna Bridge |
186:707f6e361f3e | 97 | #define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) |
| Anna Bridge |
186:707f6e361f3e | 98 | #define MXC_R_PT_OFFS_LOOP ((uint32_t)0x00000008UL) |
| Anna Bridge |
186:707f6e361f3e | 99 | #define MXC_R_PT_OFFS_RESTART ((uint32_t)0x0000000CUL) |
| Anna Bridge |
186:707f6e361f3e | 100 | |
| Anna Bridge |
186:707f6e361f3e | 101 | |
| Anna Bridge |
186:707f6e361f3e | 102 | /* |
| Anna Bridge |
186:707f6e361f3e | 103 | Field positions and masks for module PT. |
| Anna Bridge |
186:707f6e361f3e | 104 | */ |
| Anna Bridge |
186:707f6e361f3e | 105 | |
| Anna Bridge |
186:707f6e361f3e | 106 | #define MXC_F_PT_ENABLE_PT0_POS 0 |
| Anna Bridge |
186:707f6e361f3e | 107 | #define MXC_F_PT_ENABLE_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT0_POS)) |
| Anna Bridge |
186:707f6e361f3e | 108 | #define MXC_F_PT_ENABLE_PT1_POS 1 |
| Anna Bridge |
186:707f6e361f3e | 109 | #define MXC_F_PT_ENABLE_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT1_POS)) |
| Anna Bridge |
186:707f6e361f3e | 110 | #define MXC_F_PT_ENABLE_PT2_POS 2 |
| Anna Bridge |
186:707f6e361f3e | 111 | #define MXC_F_PT_ENABLE_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT2_POS)) |
| Anna Bridge |
186:707f6e361f3e | 112 | #define MXC_F_PT_ENABLE_PT3_POS 3 |
| Anna Bridge |
186:707f6e361f3e | 113 | #define MXC_F_PT_ENABLE_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT3_POS)) |
| Anna Bridge |
186:707f6e361f3e | 114 | #define MXC_F_PT_ENABLE_PT4_POS 4 |
| Anna Bridge |
186:707f6e361f3e | 115 | #define MXC_F_PT_ENABLE_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT4_POS)) |
| Anna Bridge |
186:707f6e361f3e | 116 | #define MXC_F_PT_ENABLE_PT5_POS 5 |
| Anna Bridge |
186:707f6e361f3e | 117 | #define MXC_F_PT_ENABLE_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT5_POS)) |
| Anna Bridge |
186:707f6e361f3e | 118 | #define MXC_F_PT_ENABLE_PT6_POS 6 |
| Anna Bridge |
186:707f6e361f3e | 119 | #define MXC_F_PT_ENABLE_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT6_POS)) |
| Anna Bridge |
186:707f6e361f3e | 120 | #define MXC_F_PT_ENABLE_PT7_POS 7 |
| Anna Bridge |
186:707f6e361f3e | 121 | #define MXC_F_PT_ENABLE_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT7_POS)) |
| Anna Bridge |
186:707f6e361f3e | 122 | #define MXC_F_PT_ENABLE_PT8_POS 8 |
| Anna Bridge |
186:707f6e361f3e | 123 | #define MXC_F_PT_ENABLE_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT8_POS)) |
| Anna Bridge |
186:707f6e361f3e | 124 | #define MXC_F_PT_ENABLE_PT9_POS 9 |
| Anna Bridge |
186:707f6e361f3e | 125 | #define MXC_F_PT_ENABLE_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT9_POS)) |
| Anna Bridge |
186:707f6e361f3e | 126 | #define MXC_F_PT_ENABLE_PT10_POS 10 |
| Anna Bridge |
186:707f6e361f3e | 127 | #define MXC_F_PT_ENABLE_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT10_POS)) |
| Anna Bridge |
186:707f6e361f3e | 128 | #define MXC_F_PT_ENABLE_PT11_POS 11 |
| Anna Bridge |
186:707f6e361f3e | 129 | #define MXC_F_PT_ENABLE_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT11_POS)) |
| Anna Bridge |
186:707f6e361f3e | 130 | #define MXC_F_PT_ENABLE_PT12_POS 12 |
| Anna Bridge |
186:707f6e361f3e | 131 | #define MXC_F_PT_ENABLE_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT12_POS)) |
| Anna Bridge |
186:707f6e361f3e | 132 | #define MXC_F_PT_ENABLE_PT13_POS 13 |
| Anna Bridge |
186:707f6e361f3e | 133 | #define MXC_F_PT_ENABLE_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT13_POS)) |
| Anna Bridge |
186:707f6e361f3e | 134 | #define MXC_F_PT_ENABLE_PT14_POS 14 |
| Anna Bridge |
186:707f6e361f3e | 135 | #define MXC_F_PT_ENABLE_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT14_POS)) |
| Anna Bridge |
186:707f6e361f3e | 136 | #define MXC_F_PT_ENABLE_PT15_POS 15 |
| Anna Bridge |
186:707f6e361f3e | 137 | #define MXC_F_PT_ENABLE_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT15_POS)) |
| Anna Bridge |
186:707f6e361f3e | 138 | |
| Anna Bridge |
186:707f6e361f3e | 139 | #define MXC_F_PT_RESYNC_PT0_POS 0 |
| Anna Bridge |
186:707f6e361f3e | 140 | #define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) |
| Anna Bridge |
186:707f6e361f3e | 141 | #define MXC_F_PT_RESYNC_PT1_POS 1 |
| Anna Bridge |
186:707f6e361f3e | 142 | #define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) |
| Anna Bridge |
186:707f6e361f3e | 143 | #define MXC_F_PT_RESYNC_PT2_POS 2 |
| Anna Bridge |
186:707f6e361f3e | 144 | #define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) |
| Anna Bridge |
186:707f6e361f3e | 145 | #define MXC_F_PT_RESYNC_PT3_POS 3 |
| Anna Bridge |
186:707f6e361f3e | 146 | #define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) |
| Anna Bridge |
186:707f6e361f3e | 147 | #define MXC_F_PT_RESYNC_PT4_POS 4 |
| Anna Bridge |
186:707f6e361f3e | 148 | #define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) |
| Anna Bridge |
186:707f6e361f3e | 149 | #define MXC_F_PT_RESYNC_PT5_POS 5 |
| Anna Bridge |
186:707f6e361f3e | 150 | #define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) |
| Anna Bridge |
186:707f6e361f3e | 151 | #define MXC_F_PT_RESYNC_PT6_POS 6 |
| Anna Bridge |
186:707f6e361f3e | 152 | #define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) |
| Anna Bridge |
186:707f6e361f3e | 153 | #define MXC_F_PT_RESYNC_PT7_POS 7 |
| Anna Bridge |
186:707f6e361f3e | 154 | #define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) |
| Anna Bridge |
186:707f6e361f3e | 155 | #define MXC_F_PT_RESYNC_PT8_POS 8 |
| Anna Bridge |
186:707f6e361f3e | 156 | #define MXC_F_PT_RESYNC_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT8_POS)) |
| Anna Bridge |
186:707f6e361f3e | 157 | #define MXC_F_PT_RESYNC_PT9_POS 9 |
| Anna Bridge |
186:707f6e361f3e | 158 | #define MXC_F_PT_RESYNC_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT9_POS)) |
| Anna Bridge |
186:707f6e361f3e | 159 | #define MXC_F_PT_RESYNC_PT10_POS 10 |
| Anna Bridge |
186:707f6e361f3e | 160 | #define MXC_F_PT_RESYNC_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT10_POS)) |
| Anna Bridge |
186:707f6e361f3e | 161 | #define MXC_F_PT_RESYNC_PT11_POS 11 |
| Anna Bridge |
186:707f6e361f3e | 162 | #define MXC_F_PT_RESYNC_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT11_POS)) |
| Anna Bridge |
186:707f6e361f3e | 163 | #define MXC_F_PT_RESYNC_PT12_POS 12 |
| Anna Bridge |
186:707f6e361f3e | 164 | #define MXC_F_PT_RESYNC_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT12_POS)) |
| Anna Bridge |
186:707f6e361f3e | 165 | #define MXC_F_PT_RESYNC_PT13_POS 13 |
| Anna Bridge |
186:707f6e361f3e | 166 | #define MXC_F_PT_RESYNC_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT13_POS)) |
| Anna Bridge |
186:707f6e361f3e | 167 | #define MXC_F_PT_RESYNC_PT14_POS 14 |
| Anna Bridge |
186:707f6e361f3e | 168 | #define MXC_F_PT_RESYNC_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT14_POS)) |
| Anna Bridge |
186:707f6e361f3e | 169 | #define MXC_F_PT_RESYNC_PT15_POS 15 |
| Anna Bridge |
186:707f6e361f3e | 170 | #define MXC_F_PT_RESYNC_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT15_POS)) |
| Anna Bridge |
186:707f6e361f3e | 171 | |
| Anna Bridge |
186:707f6e361f3e | 172 | #define MXC_F_PT_INTFL_PT0_POS 0 |
| Anna Bridge |
186:707f6e361f3e | 173 | #define MXC_F_PT_INTFL_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT0_POS)) |
| Anna Bridge |
186:707f6e361f3e | 174 | #define MXC_F_PT_INTFL_PT1_POS 1 |
| Anna Bridge |
186:707f6e361f3e | 175 | #define MXC_F_PT_INTFL_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT1_POS)) |
| Anna Bridge |
186:707f6e361f3e | 176 | #define MXC_F_PT_INTFL_PT2_POS 2 |
| Anna Bridge |
186:707f6e361f3e | 177 | #define MXC_F_PT_INTFL_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT2_POS)) |
| Anna Bridge |
186:707f6e361f3e | 178 | #define MXC_F_PT_INTFL_PT3_POS 3 |
| Anna Bridge |
186:707f6e361f3e | 179 | #define MXC_F_PT_INTFL_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT3_POS)) |
| Anna Bridge |
186:707f6e361f3e | 180 | #define MXC_F_PT_INTFL_PT4_POS 4 |
| Anna Bridge |
186:707f6e361f3e | 181 | #define MXC_F_PT_INTFL_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT4_POS)) |
| Anna Bridge |
186:707f6e361f3e | 182 | #define MXC_F_PT_INTFL_PT5_POS 5 |
| Anna Bridge |
186:707f6e361f3e | 183 | #define MXC_F_PT_INTFL_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT5_POS)) |
| Anna Bridge |
186:707f6e361f3e | 184 | #define MXC_F_PT_INTFL_PT6_POS 6 |
| Anna Bridge |
186:707f6e361f3e | 185 | #define MXC_F_PT_INTFL_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT6_POS)) |
| Anna Bridge |
186:707f6e361f3e | 186 | #define MXC_F_PT_INTFL_PT7_POS 7 |
| Anna Bridge |
186:707f6e361f3e | 187 | #define MXC_F_PT_INTFL_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT7_POS)) |
| Anna Bridge |
186:707f6e361f3e | 188 | #define MXC_F_PT_INTFL_PT8_POS 8 |
| Anna Bridge |
186:707f6e361f3e | 189 | #define MXC_F_PT_INTFL_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT8_POS)) |
| Anna Bridge |
186:707f6e361f3e | 190 | #define MXC_F_PT_INTFL_PT9_POS 9 |
| Anna Bridge |
186:707f6e361f3e | 191 | #define MXC_F_PT_INTFL_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT9_POS)) |
| Anna Bridge |
186:707f6e361f3e | 192 | #define MXC_F_PT_INTFL_PT10_POS 10 |
| Anna Bridge |
186:707f6e361f3e | 193 | #define MXC_F_PT_INTFL_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT10_POS)) |
| Anna Bridge |
186:707f6e361f3e | 194 | #define MXC_F_PT_INTFL_PT11_POS 11 |
| Anna Bridge |
186:707f6e361f3e | 195 | #define MXC_F_PT_INTFL_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT11_POS)) |
| Anna Bridge |
186:707f6e361f3e | 196 | #define MXC_F_PT_INTFL_PT12_POS 12 |
| Anna Bridge |
186:707f6e361f3e | 197 | #define MXC_F_PT_INTFL_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT12_POS)) |
| Anna Bridge |
186:707f6e361f3e | 198 | #define MXC_F_PT_INTFL_PT13_POS 13 |
| Anna Bridge |
186:707f6e361f3e | 199 | #define MXC_F_PT_INTFL_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT13_POS)) |
| Anna Bridge |
186:707f6e361f3e | 200 | #define MXC_F_PT_INTFL_PT14_POS 14 |
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186:707f6e361f3e | 201 | #define MXC_F_PT_INTFL_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT14_POS)) |
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186:707f6e361f3e | 202 | #define MXC_F_PT_INTFL_PT15_POS 15 |
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186:707f6e361f3e | 203 | #define MXC_F_PT_INTFL_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT15_POS)) |
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186:707f6e361f3e | 204 | |
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186:707f6e361f3e | 205 | #define MXC_F_PT_INTEN_PT0_POS 0 |
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186:707f6e361f3e | 206 | #define MXC_F_PT_INTEN_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT0_POS)) |
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186:707f6e361f3e | 207 | #define MXC_F_PT_INTEN_PT1_POS 1 |
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186:707f6e361f3e | 208 | #define MXC_F_PT_INTEN_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT1_POS)) |
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186:707f6e361f3e | 209 | #define MXC_F_PT_INTEN_PT2_POS 2 |
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186:707f6e361f3e | 210 | #define MXC_F_PT_INTEN_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT2_POS)) |
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186:707f6e361f3e | 211 | #define MXC_F_PT_INTEN_PT3_POS 3 |
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186:707f6e361f3e | 212 | #define MXC_F_PT_INTEN_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT3_POS)) |
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186:707f6e361f3e | 213 | #define MXC_F_PT_INTEN_PT4_POS 4 |
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186:707f6e361f3e | 214 | #define MXC_F_PT_INTEN_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT4_POS)) |
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186:707f6e361f3e | 215 | #define MXC_F_PT_INTEN_PT5_POS 5 |
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186:707f6e361f3e | 216 | #define MXC_F_PT_INTEN_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT5_POS)) |
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186:707f6e361f3e | 217 | #define MXC_F_PT_INTEN_PT6_POS 6 |
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186:707f6e361f3e | 218 | #define MXC_F_PT_INTEN_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT6_POS)) |
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186:707f6e361f3e | 219 | #define MXC_F_PT_INTEN_PT7_POS 7 |
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186:707f6e361f3e | 220 | #define MXC_F_PT_INTEN_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT7_POS)) |
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186:707f6e361f3e | 221 | #define MXC_F_PT_INTEN_PT8_POS 8 |
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186:707f6e361f3e | 222 | #define MXC_F_PT_INTEN_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT8_POS)) |
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186:707f6e361f3e | 223 | #define MXC_F_PT_INTEN_PT9_POS 9 |
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186:707f6e361f3e | 224 | #define MXC_F_PT_INTEN_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT9_POS)) |
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186:707f6e361f3e | 225 | #define MXC_F_PT_INTEN_PT10_POS 10 |
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186:707f6e361f3e | 226 | #define MXC_F_PT_INTEN_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT10_POS)) |
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186:707f6e361f3e | 227 | #define MXC_F_PT_INTEN_PT11_POS 11 |
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186:707f6e361f3e | 228 | #define MXC_F_PT_INTEN_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT11_POS)) |
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186:707f6e361f3e | 229 | #define MXC_F_PT_INTEN_PT12_POS 12 |
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186:707f6e361f3e | 230 | #define MXC_F_PT_INTEN_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT12_POS)) |
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186:707f6e361f3e | 231 | #define MXC_F_PT_INTEN_PT13_POS 13 |
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186:707f6e361f3e | 232 | #define MXC_F_PT_INTEN_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT13_POS)) |
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186:707f6e361f3e | 233 | #define MXC_F_PT_INTEN_PT14_POS 14 |
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186:707f6e361f3e | 234 | #define MXC_F_PT_INTEN_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT14_POS)) |
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186:707f6e361f3e | 235 | #define MXC_F_PT_INTEN_PT15_POS 15 |
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186:707f6e361f3e | 236 | #define MXC_F_PT_INTEN_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT15_POS)) |
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186:707f6e361f3e | 237 | |
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186:707f6e361f3e | 238 | #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 |
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186:707f6e361f3e | 239 | #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) |
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186:707f6e361f3e | 240 | #define MXC_F_PT_RATE_LENGTH_MODE_POS 27 |
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186:707f6e361f3e | 241 | #define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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186:707f6e361f3e | 242 | |
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186:707f6e361f3e | 243 | #define MXC_F_PT_LOOP_COUNT_POS 0 |
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186:707f6e361f3e | 244 | #define MXC_F_PT_LOOP_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_PT_LOOP_COUNT_POS)) |
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186:707f6e361f3e | 245 | #define MXC_F_PT_LOOP_DELAY_POS 16 |
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186:707f6e361f3e | 246 | #define MXC_F_PT_LOOP_DELAY ((uint32_t)(0x00000FFFUL << MXC_F_PT_LOOP_DELAY_POS)) |
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186:707f6e361f3e | 247 | |
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186:707f6e361f3e | 248 | #define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 |
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186:707f6e361f3e | 249 | #define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) |
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186:707f6e361f3e | 250 | #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 |
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186:707f6e361f3e | 251 | #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) |
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186:707f6e361f3e | 252 | #define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 |
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186:707f6e361f3e | 253 | #define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) |
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186:707f6e361f3e | 254 | #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 |
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186:707f6e361f3e | 255 | #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) |
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186:707f6e361f3e | 256 | |
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186:707f6e361f3e | 257 | |
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186:707f6e361f3e | 258 | |
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186:707f6e361f3e | 259 | /* |
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186:707f6e361f3e | 260 | Field values and shifted values for module PT. |
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186:707f6e361f3e | 261 | */ |
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186:707f6e361f3e | 262 | |
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186:707f6e361f3e | 263 | #define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(0x00000000UL)) |
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186:707f6e361f3e | 264 | #define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x00000001UL)) |
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186:707f6e361f3e | 265 | #define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(0x00000002UL)) |
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186:707f6e361f3e | 266 | #define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(0x00000003UL)) |
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186:707f6e361f3e | 267 | #define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(0x00000004UL)) |
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186:707f6e361f3e | 268 | #define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(0x00000005UL)) |
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186:707f6e361f3e | 269 | #define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(0x00000006UL)) |
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186:707f6e361f3e | 270 | #define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(0x00000007UL)) |
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186:707f6e361f3e | 271 | #define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(0x00000008UL)) |
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186:707f6e361f3e | 272 | #define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(0x00000009UL)) |
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186:707f6e361f3e | 273 | #define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(0x0000000AUL)) |
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186:707f6e361f3e | 274 | #define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(0x0000000BUL)) |
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186:707f6e361f3e | 275 | #define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(0x0000000CUL)) |
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186:707f6e361f3e | 276 | #define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(0x0000000DUL)) |
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186:707f6e361f3e | 277 | #define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(0x0000000EUL)) |
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186:707f6e361f3e | 278 | #define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(0x0000000FUL)) |
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186:707f6e361f3e | 279 | #define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(0x00000010UL)) |
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186:707f6e361f3e | 280 | #define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(0x00000011UL)) |
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186:707f6e361f3e | 281 | #define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(0x00000012UL)) |
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186:707f6e361f3e | 282 | #define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(0x00000013UL)) |
| Anna Bridge |
186:707f6e361f3e | 283 | #define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(0x00000014UL)) |
| Anna Bridge |
186:707f6e361f3e | 284 | #define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(0x00000015UL)) |
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186:707f6e361f3e | 285 | #define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(0x00000016UL)) |
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186:707f6e361f3e | 286 | #define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(0x00000017UL)) |
| Anna Bridge |
186:707f6e361f3e | 287 | #define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(0x00000018UL)) |
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186:707f6e361f3e | 288 | #define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(0x00000019UL)) |
| Anna Bridge |
186:707f6e361f3e | 289 | #define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(0x0000001AUL)) |
| Anna Bridge |
186:707f6e361f3e | 290 | #define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(0x0000001BUL)) |
| Anna Bridge |
186:707f6e361f3e | 291 | #define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(0x0000001CUL)) |
| Anna Bridge |
186:707f6e361f3e | 292 | #define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(0x0000001DUL)) |
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186:707f6e361f3e | 293 | #define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(0x0000001EUL)) |
| Anna Bridge |
186:707f6e361f3e | 294 | #define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(0x0000001FUL)) |
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186:707f6e361f3e | 295 | |
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186:707f6e361f3e | 296 | #define MXC_S_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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186:707f6e361f3e | 297 | #define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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186:707f6e361f3e | 298 | #define MXC_S_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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186:707f6e361f3e | 299 | #define MXC_S_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 300 | #define MXC_S_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 301 | #define MXC_S_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 302 | #define MXC_S_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 303 | #define MXC_S_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 304 | #define MXC_S_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 305 | #define MXC_S_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 306 | #define MXC_S_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 307 | #define MXC_S_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 308 | #define MXC_S_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 309 | #define MXC_S_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 310 | #define MXC_S_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 311 | #define MXC_S_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 312 | #define MXC_S_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 313 | #define MXC_S_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 314 | #define MXC_S_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 315 | #define MXC_S_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 316 | #define MXC_S_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 317 | #define MXC_S_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 318 | #define MXC_S_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 319 | #define MXC_S_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 320 | #define MXC_S_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 321 | #define MXC_S_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 322 | #define MXC_S_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 323 | #define MXC_S_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 324 | #define MXC_S_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 325 | #define MXC_S_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 326 | #define MXC_S_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
| Anna Bridge |
186:707f6e361f3e | 327 | #define MXC_S_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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186:707f6e361f3e | 328 | |
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186:707f6e361f3e | 329 | |
| Anna Bridge |
186:707f6e361f3e | 330 | |
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186:707f6e361f3e | 331 | #ifdef __cplusplus |
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186:707f6e361f3e | 332 | } |
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186:707f6e361f3e | 333 | #endif |
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186:707f6e361f3e | 334 | |
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186:707f6e361f3e | 335 | #endif /* _MXC_PT_REGS_H_ */ |
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186:707f6e361f3e | 336 |
