mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Maxim/TARGET_MAX32620C/device/pmu_regs.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 186:707f6e361f3e 1 /*******************************************************************************
Anna Bridge 186:707f6e361f3e 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
Anna Bridge 186:707f6e361f3e 3 *
Anna Bridge 186:707f6e361f3e 4 * Permission is hereby granted, free of charge, to any person obtaining a
Anna Bridge 186:707f6e361f3e 5 * copy of this software and associated documentation files (the "Software"),
Anna Bridge 186:707f6e361f3e 6 * to deal in the Software without restriction, including without limitation
Anna Bridge 186:707f6e361f3e 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Anna Bridge 186:707f6e361f3e 8 * and/or sell copies of the Software, and to permit persons to whom the
Anna Bridge 186:707f6e361f3e 9 * Software is furnished to do so, subject to the following conditions:
Anna Bridge 186:707f6e361f3e 10 *
Anna Bridge 186:707f6e361f3e 11 * The above copyright notice and this permission notice shall be included
Anna Bridge 186:707f6e361f3e 12 * in all copies or substantial portions of the Software.
Anna Bridge 186:707f6e361f3e 13 *
Anna Bridge 186:707f6e361f3e 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Anna Bridge 186:707f6e361f3e 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Anna Bridge 186:707f6e361f3e 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Anna Bridge 186:707f6e361f3e 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Anna Bridge 186:707f6e361f3e 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Anna Bridge 186:707f6e361f3e 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Anna Bridge 186:707f6e361f3e 20 * OTHER DEALINGS IN THE SOFTWARE.
Anna Bridge 186:707f6e361f3e 21 *
Anna Bridge 186:707f6e361f3e 22 * Except as contained in this notice, the name of Maxim Integrated
Anna Bridge 186:707f6e361f3e 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Anna Bridge 186:707f6e361f3e 24 * Products, Inc. Branding Policy.
Anna Bridge 186:707f6e361f3e 25 *
Anna Bridge 186:707f6e361f3e 26 * The mere transfer of this software does not imply any licenses
Anna Bridge 186:707f6e361f3e 27 * of trade secrets, proprietary technology, copyrights, patents,
Anna Bridge 186:707f6e361f3e 28 * trademarks, maskwork rights, or any other form of intellectual
Anna Bridge 186:707f6e361f3e 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Anna Bridge 186:707f6e361f3e 30 * ownership rights.
Anna Bridge 186:707f6e361f3e 31 *
Anna Bridge 186:707f6e361f3e 32 * $Date: 2016-04-25 15:50:53 -0500 (Mon, 25 Apr 2016) $
Anna Bridge 186:707f6e361f3e 33 * $Revision: 22510 $
Anna Bridge 186:707f6e361f3e 34 *
Anna Bridge 186:707f6e361f3e 35 ******************************************************************************/
Anna Bridge 186:707f6e361f3e 36
Anna Bridge 186:707f6e361f3e 37 #ifndef _MXC_PMU_REGS_H_
Anna Bridge 186:707f6e361f3e 38 #define _MXC_PMU_REGS_H_
Anna Bridge 186:707f6e361f3e 39
Anna Bridge 186:707f6e361f3e 40 #ifdef __cplusplus
Anna Bridge 186:707f6e361f3e 41 extern "C" {
Anna Bridge 186:707f6e361f3e 42 #endif
Anna Bridge 186:707f6e361f3e 43
Anna Bridge 186:707f6e361f3e 44 #include <stdint.h>
Anna Bridge 186:707f6e361f3e 45
Anna Bridge 186:707f6e361f3e 46 /*
Anna Bridge 186:707f6e361f3e 47 If types are not defined elsewhere (CMSIS) define them here
Anna Bridge 186:707f6e361f3e 48 */
Anna Bridge 186:707f6e361f3e 49 #ifndef __IO
Anna Bridge 186:707f6e361f3e 50 #define __IO volatile
Anna Bridge 186:707f6e361f3e 51 #endif
Anna Bridge 186:707f6e361f3e 52 #ifndef __I
Anna Bridge 186:707f6e361f3e 53 #define __I volatile const
Anna Bridge 186:707f6e361f3e 54 #endif
Anna Bridge 186:707f6e361f3e 55 #ifndef __O
Anna Bridge 186:707f6e361f3e 56 #define __O volatile
Anna Bridge 186:707f6e361f3e 57 #endif
Anna Bridge 186:707f6e361f3e 58 #ifndef __RO
Anna Bridge 186:707f6e361f3e 59 #define __RO volatile const
Anna Bridge 186:707f6e361f3e 60 #endif
Anna Bridge 186:707f6e361f3e 61
Anna Bridge 186:707f6e361f3e 62 /*
Anna Bridge 186:707f6e361f3e 63 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
Anna Bridge 186:707f6e361f3e 64 access to each register in module.
Anna Bridge 186:707f6e361f3e 65 */
Anna Bridge 186:707f6e361f3e 66
Anna Bridge 186:707f6e361f3e 67 /* Offset Register Description
Anna Bridge 186:707f6e361f3e 68 ============= ============================================================================ */
Anna Bridge 186:707f6e361f3e 69 typedef struct {
Anna Bridge 186:707f6e361f3e 70 __IO uint32_t dscadr; /* 0x0000 PMU Channel Next Descriptor Address */
Anna Bridge 186:707f6e361f3e 71 __IO uint32_t cfg; /* 0x0004 PMU Channel Configuration */
Anna Bridge 186:707f6e361f3e 72 __IO uint32_t loop; /* 0x0008 PMU Channel Loop Counters */
Anna Bridge 186:707f6e361f3e 73 __RO uint32_t rsv00C[5]; /* 0x000C-0x001C */
Anna Bridge 186:707f6e361f3e 74 } mxc_pmu_regs_t;
Anna Bridge 186:707f6e361f3e 75
Anna Bridge 186:707f6e361f3e 76
Anna Bridge 186:707f6e361f3e 77 /*
Anna Bridge 186:707f6e361f3e 78 Register offsets for module PMU.
Anna Bridge 186:707f6e361f3e 79 */
Anna Bridge 186:707f6e361f3e 80
Anna Bridge 186:707f6e361f3e 81 #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL)
Anna Bridge 186:707f6e361f3e 82 #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL)
Anna Bridge 186:707f6e361f3e 83 #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL)
Anna Bridge 186:707f6e361f3e 84
Anna Bridge 186:707f6e361f3e 85
Anna Bridge 186:707f6e361f3e 86 /*
Anna Bridge 186:707f6e361f3e 87 Field positions and masks for module PMU.
Anna Bridge 186:707f6e361f3e 88 */
Anna Bridge 186:707f6e361f3e 89
Anna Bridge 186:707f6e361f3e 90 #define MXC_F_PMU_CFG_ENABLE_POS 0
Anna Bridge 186:707f6e361f3e 91 #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
Anna Bridge 186:707f6e361f3e 92 #define MXC_F_PMU_CFG_LL_STOPPED_POS 2
Anna Bridge 186:707f6e361f3e 93 #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
Anna Bridge 186:707f6e361f3e 94 #define MXC_F_PMU_CFG_MANUAL_POS 3
Anna Bridge 186:707f6e361f3e 95 #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
Anna Bridge 186:707f6e361f3e 96 #define MXC_F_PMU_CFG_BUS_ERROR_POS 4
Anna Bridge 186:707f6e361f3e 97 #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
Anna Bridge 186:707f6e361f3e 98 #define MXC_F_PMU_CFG_TO_STAT_POS 6
Anna Bridge 186:707f6e361f3e 99 #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
Anna Bridge 186:707f6e361f3e 100 #define MXC_F_PMU_CFG_TO_SEL_POS 11
Anna Bridge 186:707f6e361f3e 101 #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
Anna Bridge 186:707f6e361f3e 102 #define MXC_F_PMU_CFG_PS_SEL_POS 14
Anna Bridge 186:707f6e361f3e 103 #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
Anna Bridge 186:707f6e361f3e 104 #define MXC_F_PMU_CFG_INTERRUPT_POS 16
Anna Bridge 186:707f6e361f3e 105 #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
Anna Bridge 186:707f6e361f3e 106 #define MXC_F_PMU_CFG_INT_EN_POS 17
Anna Bridge 186:707f6e361f3e 107 #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
Anna Bridge 186:707f6e361f3e 108 #define MXC_F_PMU_CFG_BURST_SIZE_POS 24
Anna Bridge 186:707f6e361f3e 109 #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
Anna Bridge 186:707f6e361f3e 110
Anna Bridge 186:707f6e361f3e 111 #define MXC_F_PMU_LOOP_COUNTER_0_POS 0
Anna Bridge 186:707f6e361f3e 112 #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
Anna Bridge 186:707f6e361f3e 113 #define MXC_F_PMU_LOOP_COUNTER_1_POS 16
Anna Bridge 186:707f6e361f3e 114 #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
Anna Bridge 186:707f6e361f3e 115
Anna Bridge 186:707f6e361f3e 116 /*
Anna Bridge 186:707f6e361f3e 117 Field values
Anna Bridge 186:707f6e361f3e 118 */
Anna Bridge 186:707f6e361f3e 119
Anna Bridge 186:707f6e361f3e 120 #define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL))
Anna Bridge 186:707f6e361f3e 121 #define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL))
Anna Bridge 186:707f6e361f3e 122 #define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL))
Anna Bridge 186:707f6e361f3e 123 #define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL))
Anna Bridge 186:707f6e361f3e 124 #define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL))
Anna Bridge 186:707f6e361f3e 125 #define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL))
Anna Bridge 186:707f6e361f3e 126 #define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL))
Anna Bridge 186:707f6e361f3e 127 #define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL))
Anna Bridge 186:707f6e361f3e 128
Anna Bridge 186:707f6e361f3e 129 #define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL))
Anna Bridge 186:707f6e361f3e 130 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL))
Anna Bridge 186:707f6e361f3e 131 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL))
Anna Bridge 186:707f6e361f3e 132 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL))
Anna Bridge 186:707f6e361f3e 133
Anna Bridge 186:707f6e361f3e 134 /* Op codes */
Anna Bridge 186:707f6e361f3e 135 #define PMU_MOVE_OP 0
Anna Bridge 186:707f6e361f3e 136 #define PMU_WRITE_OP 1
Anna Bridge 186:707f6e361f3e 137 #define PMU_WAIT_OP 2
Anna Bridge 186:707f6e361f3e 138 #define PMU_JUMP_OP 3
Anna Bridge 186:707f6e361f3e 139 #define PMU_LOOP_OP 4
Anna Bridge 186:707f6e361f3e 140 #define PMU_POLL_OP 5
Anna Bridge 186:707f6e361f3e 141 #define PMU_BRANCH_OP 6
Anna Bridge 186:707f6e361f3e 142 #define PMU_TRANSFER_OP 7
Anna Bridge 186:707f6e361f3e 143
Anna Bridge 186:707f6e361f3e 144 /* Bit values used in all decroptiors */
Anna Bridge 186:707f6e361f3e 145 #define PMU_NO_INTERRUPT 0 /* Interrupt flag is NOT set at end of channel execution */
Anna Bridge 186:707f6e361f3e 146 #define PMU_INTERRUPT 1 /* Interrupt flag is set at end of channel execution */
Anna Bridge 186:707f6e361f3e 147
Anna Bridge 186:707f6e361f3e 148 #define PMU_NO_STOP 0 /* Do not stop channel after this descriptor ends */
Anna Bridge 186:707f6e361f3e 149 #define PMU_STOP 1 /* Halt PMU channel after this descriptor ends */
Anna Bridge 186:707f6e361f3e 150
Anna Bridge 186:707f6e361f3e 151 /* Interrupt and Stop bit positions */
Anna Bridge 186:707f6e361f3e 152 #define PMU_INT_POS 3
Anna Bridge 186:707f6e361f3e 153 #define PMU_STOP_POS 4
Anna Bridge 186:707f6e361f3e 154
Anna Bridge 186:707f6e361f3e 155 /* MOVE descriptor bit values */
Anna Bridge 186:707f6e361f3e 156 #define PMU_MOVE_READ_8_BIT 0 /* Read size = 8 */
Anna Bridge 186:707f6e361f3e 157 #define PMU_MOVE_READ_16_BIT 1 /* Read size = 16 */
Anna Bridge 186:707f6e361f3e 158 #define PMU_MOVE_READ_32_BIT 2 /* Read size = 32 */
Anna Bridge 186:707f6e361f3e 159
Anna Bridge 186:707f6e361f3e 160 #define PMU_MOVE_READ_NO_INC 0 /* read address not incremented */
Anna Bridge 186:707f6e361f3e 161 #define PMU_MOVE_READ_INC 1 /* Auto-Increment read address */
Anna Bridge 186:707f6e361f3e 162
Anna Bridge 186:707f6e361f3e 163 #define PMU_MOVE_WRITE_8_BIT 0 /* Write Size = 8 */
Anna Bridge 186:707f6e361f3e 164 #define PMU_MOVE_WRITE_16_BIT 1 /* Write Size = 16 */
Anna Bridge 186:707f6e361f3e 165 #define PMU_MOVE_WRITE_32_BIT 2 /* Write Size = 32 */
Anna Bridge 186:707f6e361f3e 166
Anna Bridge 186:707f6e361f3e 167 #define PMU_MOVE_WRITE_NO_INC 0 /* Write address not incremented */
Anna Bridge 186:707f6e361f3e 168 #define PMU_MOVE_WRITE_INC 1 /* Auto_Increment write address */
Anna Bridge 186:707f6e361f3e 169
Anna Bridge 186:707f6e361f3e 170 #define PMU_MOVE_NO_CONT 0 /* MOVE does not rely on previous MOVE */
Anna Bridge 186:707f6e361f3e 171 #define PMU_MOVE_CONT 1 /* MOVE continues from read/write address */
Anna Bridge 186:707f6e361f3e 172 /* and INC values defined in previous MOVE */
Anna Bridge 186:707f6e361f3e 173
Anna Bridge 186:707f6e361f3e 174 /* MOVE bit positions */
Anna Bridge 186:707f6e361f3e 175 #define PMU_MOVE_READS_POS 5
Anna Bridge 186:707f6e361f3e 176 #define PMU_MOVE_READI_POS 7
Anna Bridge 186:707f6e361f3e 177 #define PMU_MOVE_WRITES_POS 8
Anna Bridge 186:707f6e361f3e 178 #define PMU_MOVE_WRITEI_POS 10
Anna Bridge 186:707f6e361f3e 179 #define PMU_MOVE_CONT_POS 11
Anna Bridge 186:707f6e361f3e 180 #define PMU_MOVE_LEN_POS 12
Anna Bridge 186:707f6e361f3e 181
Anna Bridge 186:707f6e361f3e 182 /* WRITE descriptor bit values */
Anna Bridge 186:707f6e361f3e 183 #define PMU_WRITE_MASKED_WRITE_VALUE 0 /* Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */
Anna Bridge 186:707f6e361f3e 184 #define PMU_WRITE_PLUS_1 1 /* Value = READ_VALUE + 1 */
Anna Bridge 186:707f6e361f3e 185 #define PMU_WRITE_MINUS_1 2 /* Value = READ_VALUE - 1 */
Anna Bridge 186:707f6e361f3e 186 #define PMU_WRITE_SHIFT_RT_1 3 /* Value = READ_VALUE >> 1 */
Anna Bridge 186:707f6e361f3e 187 #define PMU_WRITE_SHIFT_LT_1 4 /* Value = READ_VALUE << 1 */
Anna Bridge 186:707f6e361f3e 188 #define PMU_WRITE_ROTATE_RT_1 5 /* Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */
Anna Bridge 186:707f6e361f3e 189 #define PMU_WRITE_ROTATE_LT_1 6 /* Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */
Anna Bridge 186:707f6e361f3e 190 #define PMU_WRITE_NOT_READ_VAL 7 /* Value = ~READ_VALUE */
Anna Bridge 186:707f6e361f3e 191 #define PMU_WRITE_XOR_MASK 8 /* Value = READ_VALUE XOR WRITE_MASK */
Anna Bridge 186:707f6e361f3e 192 #define PMU_WRITE_OR_MASK 9 /* Value = READ_VALUE | WRITE_MASK */
Anna Bridge 186:707f6e361f3e 193 #define PMU_WRITE_AND_MASK 10 /* Value = READ_VALUE & WRITE_MASK */
Anna Bridge 186:707f6e361f3e 194
Anna Bridge 186:707f6e361f3e 195 /* WRITE bit positions */
Anna Bridge 186:707f6e361f3e 196 #define PMU_WRITE_METHOD_POS 8
Anna Bridge 186:707f6e361f3e 197
Anna Bridge 186:707f6e361f3e 198 /* WAIT descriptor bit values */
Anna Bridge 186:707f6e361f3e 199 #define PMU_WAIT_SEL_0 0 /* Select the interrupt source */
Anna Bridge 186:707f6e361f3e 200 #define PMU_WAIT_SEL_1 1
Anna Bridge 186:707f6e361f3e 201
Anna Bridge 186:707f6e361f3e 202 /* WAIT bit positions */
Anna Bridge 186:707f6e361f3e 203 #define PMU_WAIT_WAIT_POS 5
Anna Bridge 186:707f6e361f3e 204 #define PMU_WAIT_SEL_POS 6
Anna Bridge 186:707f6e361f3e 205
Anna Bridge 186:707f6e361f3e 206 /* LOOP descriptor bit values */
Anna Bridge 186:707f6e361f3e 207 #define PMU_LOOP_SEL_COUNTER0 0 /* select Counter0 to count down from */
Anna Bridge 186:707f6e361f3e 208 #define PMU_LOOP_SEL_COUNTER1 1 /* select Counter1 to count down from */
Anna Bridge 186:707f6e361f3e 209
Anna Bridge 186:707f6e361f3e 210 /* LOOP bit positions */
Anna Bridge 186:707f6e361f3e 211 #define PMU_LOOP_SEL_COUNTER_POS 5
Anna Bridge 186:707f6e361f3e 212
Anna Bridge 186:707f6e361f3e 213 /* POLL descriptor bit values */
Anna Bridge 186:707f6e361f3e 214 #define PMU_POLL_OR 0 /* polling ends when at least one mask bit matches expected data */
Anna Bridge 186:707f6e361f3e 215 #define PMU_POLL_AND 1 /* polling ends when all mask bits matches expected data */
Anna Bridge 186:707f6e361f3e 216
Anna Bridge 186:707f6e361f3e 217 /* POLL bit positions */
Anna Bridge 186:707f6e361f3e 218 #define PMU_POLL_AND_POS 7
Anna Bridge 186:707f6e361f3e 219
Anna Bridge 186:707f6e361f3e 220 /* BRANCH descriptor bit values */
Anna Bridge 186:707f6e361f3e 221 #define PMU_BRANCH_OR 0 /* branch when any mask bit = or != expected data (based on = or != branch type) */
Anna Bridge 186:707f6e361f3e 222 #define PMU_BRANCH_AND 1 /* branch when all mask bit = or != expected data (based on = or != branch type) */
Anna Bridge 186:707f6e361f3e 223
Anna Bridge 186:707f6e361f3e 224 #define PMU_BRANCH_TYPE_NOT_EQUAL 0 /* Branch when polled data != expected data */
Anna Bridge 186:707f6e361f3e 225 #define PMU_BRANCH_TYPE_EQUAL 1 /* Branch when polled data = expected data */
Anna Bridge 186:707f6e361f3e 226 #define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /* Branch when polled data <= expected data */
Anna Bridge 186:707f6e361f3e 227 #define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /* Branch when polled data >= expected data */
Anna Bridge 186:707f6e361f3e 228 #define PMU_BRANCH_TYPE_LESSER 4 /* Branch when polled data < expected data */
Anna Bridge 186:707f6e361f3e 229 #define PMU_BRANCH_TYPE_GREATER 5 /* Branch when polled data > expected data */
Anna Bridge 186:707f6e361f3e 230
Anna Bridge 186:707f6e361f3e 231 /* BRANCH bit positions */
Anna Bridge 186:707f6e361f3e 232 #define PMU_BRANCH_AND_POS 7
Anna Bridge 186:707f6e361f3e 233 #define PMU_BRANCH_TYPE_POS 8
Anna Bridge 186:707f6e361f3e 234
Anna Bridge 186:707f6e361f3e 235 /* TRANSFER descriptor bit values */
Anna Bridge 186:707f6e361f3e 236 #define PMU_TX_READ_8_BIT 0 /* Read size = 8 */
Anna Bridge 186:707f6e361f3e 237 #define PMU_TX_READ_16_BIT 1 /* Read size = 16 */
Anna Bridge 186:707f6e361f3e 238 #define PMU_TX_READ_32_BIT 2 /* Read size = 32 */
Anna Bridge 186:707f6e361f3e 239
Anna Bridge 186:707f6e361f3e 240 #define PMU_TX_READ_NO_INC 0 /* read address not incremented */
Anna Bridge 186:707f6e361f3e 241 #define PMU_TX_READ_INC 1 /* Auto-Increment read address */
Anna Bridge 186:707f6e361f3e 242
Anna Bridge 186:707f6e361f3e 243 #define PMU_TX_WRITE_8_BIT 0 /* Write Size = 8 */
Anna Bridge 186:707f6e361f3e 244 #define PMU_TX_WRITE_16_BIT 1 /* Write Size = 16 */
Anna Bridge 186:707f6e361f3e 245 #define PMU_TX_WRITE_32_BIT 2 /* Write Size = 32 */
Anna Bridge 186:707f6e361f3e 246
Anna Bridge 186:707f6e361f3e 247 #define PMU_TX_WRITE_NO_INC 0 /* Write address not incremented */
Anna Bridge 186:707f6e361f3e 248 #define PMU_TX_WRITE_INC 1 /* Auto_Increment write address */
Anna Bridge 186:707f6e361f3e 249
Anna Bridge 186:707f6e361f3e 250 /* TRANSFER bit positions */
Anna Bridge 186:707f6e361f3e 251 #define PMU_TX_READS_POS 5
Anna Bridge 186:707f6e361f3e 252 #define PMU_TX_READI_POS 7
Anna Bridge 186:707f6e361f3e 253 #define PMU_TX_WRITES_POS 8
Anna Bridge 186:707f6e361f3e 254 #define PMU_TX_WRITEI_POS 10
Anna Bridge 186:707f6e361f3e 255 #define PMU_TX_LEN_POS 12
Anna Bridge 186:707f6e361f3e 256 #define PMU_TX_BS_POS 26
Anna Bridge 186:707f6e361f3e 257
Anna Bridge 186:707f6e361f3e 258 /* PMU interrupt sources for the WAIT opcode */
Anna Bridge 186:707f6e361f3e 259 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
Anna Bridge 186:707f6e361f3e 260 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
Anna Bridge 186:707f6e361f3e 261 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
Anna Bridge 186:707f6e361f3e 262 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
Anna Bridge 186:707f6e361f3e 263 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
Anna Bridge 186:707f6e361f3e 264 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
Anna Bridge 186:707f6e361f3e 265 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
Anna Bridge 186:707f6e361f3e 266 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
Anna Bridge 186:707f6e361f3e 267 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
Anna Bridge 186:707f6e361f3e 268 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
Anna Bridge 186:707f6e361f3e 269 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
Anna Bridge 186:707f6e361f3e 270 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
Anna Bridge 186:707f6e361f3e 271 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
Anna Bridge 186:707f6e361f3e 272 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
Anna Bridge 186:707f6e361f3e 273 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
Anna Bridge 186:707f6e361f3e 274 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
Anna Bridge 186:707f6e361f3e 275 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16))
Anna Bridge 186:707f6e361f3e 276 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17))
Anna Bridge 186:707f6e361f3e 277 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18))
Anna Bridge 186:707f6e361f3e 278 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19))
Anna Bridge 186:707f6e361f3e 279 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20))
Anna Bridge 186:707f6e361f3e 280 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21))
Anna Bridge 186:707f6e361f3e 281 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22))
Anna Bridge 186:707f6e361f3e 282 #define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23))
Anna Bridge 186:707f6e361f3e 283 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24))
Anna Bridge 186:707f6e361f3e 284 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25))
Anna Bridge 186:707f6e361f3e 285 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26))
Anna Bridge 186:707f6e361f3e 286 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27))
Anna Bridge 186:707f6e361f3e 287 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28))
Anna Bridge 186:707f6e361f3e 288 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29))
Anna Bridge 186:707f6e361f3e 289 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30))
Anna Bridge 186:707f6e361f3e 290 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31))
Anna Bridge 186:707f6e361f3e 291 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0))
Anna Bridge 186:707f6e361f3e 292 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1))
Anna Bridge 186:707f6e361f3e 293 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2))
Anna Bridge 186:707f6e361f3e 294 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3))
Anna Bridge 186:707f6e361f3e 295 #define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4))
Anna Bridge 186:707f6e361f3e 296 #define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5))
Anna Bridge 186:707f6e361f3e 297 #define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6))
Anna Bridge 186:707f6e361f3e 298 #define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7))
Anna Bridge 186:707f6e361f3e 299 #define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8))
Anna Bridge 186:707f6e361f3e 300 #define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9))
Anna Bridge 186:707f6e361f3e 301 #define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10))
Anna Bridge 186:707f6e361f3e 302 #define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11))
Anna Bridge 186:707f6e361f3e 303 #define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12))
Anna Bridge 186:707f6e361f3e 304 #define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13))
Anna Bridge 186:707f6e361f3e 305 #define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14))
Anna Bridge 186:707f6e361f3e 306 #define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15))
Anna Bridge 186:707f6e361f3e 307 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16))
Anna Bridge 186:707f6e361f3e 308 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17))
Anna Bridge 186:707f6e361f3e 309 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18))
Anna Bridge 186:707f6e361f3e 310 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19))
Anna Bridge 186:707f6e361f3e 311 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20))
Anna Bridge 186:707f6e361f3e 312 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21))
Anna Bridge 186:707f6e361f3e 313 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22))
Anna Bridge 186:707f6e361f3e 314 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23))
Anna Bridge 186:707f6e361f3e 315 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24))
Anna Bridge 186:707f6e361f3e 316 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25))
Anna Bridge 186:707f6e361f3e 317 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26))
Anna Bridge 186:707f6e361f3e 318 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27))
Anna Bridge 186:707f6e361f3e 319 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28))
Anna Bridge 186:707f6e361f3e 320 #define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29))
Anna Bridge 186:707f6e361f3e 321 #define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30))
Anna Bridge 186:707f6e361f3e 322 #define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31))
Anna Bridge 186:707f6e361f3e 323 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0))
Anna Bridge 186:707f6e361f3e 324 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1))
Anna Bridge 186:707f6e361f3e 325 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2))
Anna Bridge 186:707f6e361f3e 326 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3))
Anna Bridge 186:707f6e361f3e 327 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4))
Anna Bridge 186:707f6e361f3e 328 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5))
Anna Bridge 186:707f6e361f3e 329 #define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6))
Anna Bridge 186:707f6e361f3e 330 #define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7))
Anna Bridge 186:707f6e361f3e 331 #define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8))
Anna Bridge 186:707f6e361f3e 332 #define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9))
Anna Bridge 186:707f6e361f3e 333 #define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10))
Anna Bridge 186:707f6e361f3e 334 #define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11))
Anna Bridge 186:707f6e361f3e 335 #define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12))
Anna Bridge 186:707f6e361f3e 336 #define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13))
Anna Bridge 186:707f6e361f3e 337 #define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14))
Anna Bridge 186:707f6e361f3e 338 #define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15))
Anna Bridge 186:707f6e361f3e 339 #define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16))
Anna Bridge 186:707f6e361f3e 340 #define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17))
Anna Bridge 186:707f6e361f3e 341 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18))
Anna Bridge 186:707f6e361f3e 342 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19))
Anna Bridge 186:707f6e361f3e 343 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20))
Anna Bridge 186:707f6e361f3e 344 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21))
Anna Bridge 186:707f6e361f3e 345 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22))
Anna Bridge 186:707f6e361f3e 346 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23))
Anna Bridge 186:707f6e361f3e 347 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24))
Anna Bridge 186:707f6e361f3e 348 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25))
Anna Bridge 186:707f6e361f3e 349 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26))
Anna Bridge 186:707f6e361f3e 350 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27))
Anna Bridge 186:707f6e361f3e 351 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28))
Anna Bridge 186:707f6e361f3e 352 #define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29))
Anna Bridge 186:707f6e361f3e 353 #define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30))
Anna Bridge 186:707f6e361f3e 354 #define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31))
Anna Bridge 186:707f6e361f3e 355 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0))
Anna Bridge 186:707f6e361f3e 356 #define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1))
Anna Bridge 186:707f6e361f3e 357 #define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2))
Anna Bridge 186:707f6e361f3e 358 #define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3))
Anna Bridge 186:707f6e361f3e 359 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4))
Anna Bridge 186:707f6e361f3e 360
Anna Bridge 186:707f6e361f3e 361 /* PMU interrupt sources for the TRANSFER opcode */
Anna Bridge 186:707f6e361f3e 362 #define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
Anna Bridge 186:707f6e361f3e 363 #define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
Anna Bridge 186:707f6e361f3e 364 #define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
Anna Bridge 186:707f6e361f3e 365 #define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
Anna Bridge 186:707f6e361f3e 366 #define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
Anna Bridge 186:707f6e361f3e 367 #define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
Anna Bridge 186:707f6e361f3e 368 #define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
Anna Bridge 186:707f6e361f3e 369 #define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
Anna Bridge 186:707f6e361f3e 370 #define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
Anna Bridge 186:707f6e361f3e 371 #define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
Anna Bridge 186:707f6e361f3e 372 #define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
Anna Bridge 186:707f6e361f3e 373 #define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
Anna Bridge 186:707f6e361f3e 374 #define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
Anna Bridge 186:707f6e361f3e 375 #define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
Anna Bridge 186:707f6e361f3e 376 #define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
Anna Bridge 186:707f6e361f3e 377 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
Anna Bridge 186:707f6e361f3e 378 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16))
Anna Bridge 186:707f6e361f3e 379 #define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17))
Anna Bridge 186:707f6e361f3e 380 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18))
Anna Bridge 186:707f6e361f3e 381 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19))
Anna Bridge 186:707f6e361f3e 382 #define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20))
Anna Bridge 186:707f6e361f3e 383 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21))
Anna Bridge 186:707f6e361f3e 384 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22))
Anna Bridge 186:707f6e361f3e 385 #define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23))
Anna Bridge 186:707f6e361f3e 386 #define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24))
Anna Bridge 186:707f6e361f3e 387
Anna Bridge 186:707f6e361f3e 388
Anna Bridge 186:707f6e361f3e 389 #ifdef __cplusplus
Anna Bridge 186:707f6e361f3e 390 }
Anna Bridge 186:707f6e361f3e 391 #endif
Anna Bridge 186:707f6e361f3e 392
Anna Bridge 186:707f6e361f3e 393 #endif /* _MXC_PMU_REGS_H_ */
Anna Bridge 186:707f6e361f3e 394