mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include <stddef.h>
<> 144:ef7eb2e8f9f7 35 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 36 #include "gpio_irq_api.h"
<> 144:ef7eb2e8f9f7 37 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #define NUM_PORTS 8
<> 144:ef7eb2e8f9f7 40 #define NUM_PINS_PER_PORT 8
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 static uint32_t ids[NUM_PORTS][NUM_PINS_PER_PORT] = {{0}};
<> 144:ef7eb2e8f9f7 43 static gpio_irq_handler irq_handler;
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 static void handle_irq(unsigned int port)
<> 144:ef7eb2e8f9f7 46 {
<> 144:ef7eb2e8f9f7 47 uint32_t intfl, in_val;
<> 144:ef7eb2e8f9f7 48 uint32_t mask;
<> 144:ef7eb2e8f9f7 49 unsigned int pin;
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /* Read pin state */
<> 144:ef7eb2e8f9f7 52 in_val = MXC_GPIO->in_val[port];
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /* Read interrupts */
<> 144:ef7eb2e8f9f7 55 intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 mask = 1;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 for (pin = 0; pin < NUM_PINS_PER_PORT; pin++) {
<> 144:ef7eb2e8f9f7 60 if (intfl & mask) {
<> 144:ef7eb2e8f9f7 61 if (ids[port][pin]) {
<> 144:ef7eb2e8f9f7 62 if (in_val & mask) {
<> 144:ef7eb2e8f9f7 63 irq_handler(ids[port][pin], IRQ_RISE);
<> 144:ef7eb2e8f9f7 64 } else {
<> 144:ef7eb2e8f9f7 65 irq_handler(ids[port][pin], IRQ_FALL);
<> 144:ef7eb2e8f9f7 66 }
<> 144:ef7eb2e8f9f7 67 }
<> 144:ef7eb2e8f9f7 68 MXC_GPIO->intfl[port] = mask; /* clear interrupt */
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70 mask <<= 1;
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72 }
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 void gpio_irq_0(void) { handle_irq(0); }
<> 144:ef7eb2e8f9f7 75 void gpio_irq_1(void) { handle_irq(1); }
<> 144:ef7eb2e8f9f7 76 void gpio_irq_2(void) { handle_irq(2); }
<> 144:ef7eb2e8f9f7 77 void gpio_irq_3(void) { handle_irq(3); }
<> 144:ef7eb2e8f9f7 78 void gpio_irq_4(void) { handle_irq(4); }
<> 144:ef7eb2e8f9f7 79 void gpio_irq_5(void) { handle_irq(5); }
<> 144:ef7eb2e8f9f7 80 void gpio_irq_6(void) { handle_irq(6); }
<> 144:ef7eb2e8f9f7 81 void gpio_irq_7(void) { handle_irq(7); }
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 84 {
<> 144:ef7eb2e8f9f7 85 if (name == NC)
<> 144:ef7eb2e8f9f7 86 return -1;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint8_t port = PINNAME_TO_PORT(name);
<> 144:ef7eb2e8f9f7 89 uint8_t pin = PINNAME_TO_PIN(name);
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 if ((port > NUM_PORTS) || (pin > NUM_PINS_PER_PORT)) {
<> 144:ef7eb2e8f9f7 92 return 1;
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 obj->port = port;
<> 144:ef7eb2e8f9f7 96 obj->pin = pin;
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 irq_handler = handler;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 ids[port][pin] = id;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* register handlers */
<> 144:ef7eb2e8f9f7 103 NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
<> 144:ef7eb2e8f9f7 104 NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
<> 144:ef7eb2e8f9f7 105 NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
<> 144:ef7eb2e8f9f7 106 NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
<> 144:ef7eb2e8f9f7 107 NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
<> 144:ef7eb2e8f9f7 108 NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
<> 144:ef7eb2e8f9f7 109 NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
<> 144:ef7eb2e8f9f7 110 NVIC_SetVector(GPIO_P7_IRQn, (uint32_t)gpio_irq_7);
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* disable the interrupt locally */
<> 144:ef7eb2e8f9f7 113 MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* clear a pending request */
<> 144:ef7eb2e8f9f7 116 MXC_GPIO->intfl[port] = 1 << pin;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* enable the requested interrupt */
<> 144:ef7eb2e8f9f7 119 MXC_GPIO->inten[port] |= (1 << pin);
<> 144:ef7eb2e8f9f7 120 NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 return 0;
<> 144:ef7eb2e8f9f7 123 }
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 void gpio_irq_free(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 126 {
<> 144:ef7eb2e8f9f7 127 /* disable interrupt */
<> 144:ef7eb2e8f9f7 128 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 129 MXC_GPIO->int_mode[obj->port] &= ~(0xF << (obj->pin*4));
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 ids[obj->port][obj->pin] = 0;
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
<> 144:ef7eb2e8f9f7 137 uint32_t curr_mode = (int_mode >> (obj->pin*4)) & 0x3; /* only supporting edge interrupts */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 uint32_t new_mode = curr_mode;
<> 144:ef7eb2e8f9f7 140 if (event == IRQ_FALL) {
<> 144:ef7eb2e8f9f7 141 if (enable) {
<> 144:ef7eb2e8f9f7 142 new_mode |= 0x1;
<> 144:ef7eb2e8f9f7 143 } else {
<> 144:ef7eb2e8f9f7 144 new_mode &= ~0x1;
<> 144:ef7eb2e8f9f7 145 }
<> 144:ef7eb2e8f9f7 146 } else if (event == IRQ_RISE) {
<> 144:ef7eb2e8f9f7 147 if (enable) {
<> 144:ef7eb2e8f9f7 148 new_mode |= 0x2;
<> 144:ef7eb2e8f9f7 149 } else {
<> 144:ef7eb2e8f9f7 150 new_mode &= ~0x2;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 int_mode &= ~(0xF << (obj->pin*4));
<> 144:ef7eb2e8f9f7 155 int_mode |= (new_mode << (obj->pin*4));
<> 144:ef7eb2e8f9f7 156 MXC_GPIO->int_mode[obj->port] = int_mode;
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 void gpio_irq_enable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
<> 144:ef7eb2e8f9f7 162 }
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 void gpio_irq_disable(gpio_irq_t *obj)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
<> 144:ef7eb2e8f9f7 167 }