mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_GigaDevice/TARGET_GD32F30X/spi_api.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 189:f392fc9709a3 | 1 | /* mbed Microcontroller Library |
AnnaBridge | 189:f392fc9709a3 | 2 | * Copyright (c) 2018 GigaDevice Semiconductor Inc. |
AnnaBridge | 189:f392fc9709a3 | 3 | * |
AnnaBridge | 189:f392fc9709a3 | 4 | * SPDX-License-Identifier: Apache-2.0 |
AnnaBridge | 189:f392fc9709a3 | 5 | * |
AnnaBridge | 189:f392fc9709a3 | 6 | * Licensed under the Apache License, Version 2.0 (the "License"); |
AnnaBridge | 189:f392fc9709a3 | 7 | * you may not use this file except in compliance with the License. |
AnnaBridge | 189:f392fc9709a3 | 8 | * You may obtain a copy of the License at |
AnnaBridge | 189:f392fc9709a3 | 9 | * |
AnnaBridge | 189:f392fc9709a3 | 10 | * http://www.apache.org/licenses/LICENSE-2.0 |
AnnaBridge | 189:f392fc9709a3 | 11 | * |
AnnaBridge | 189:f392fc9709a3 | 12 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 189:f392fc9709a3 | 13 | * distributed under the License is distributed on an "AS IS" BASIS, |
AnnaBridge | 189:f392fc9709a3 | 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 189:f392fc9709a3 | 15 | * See the License for the specific language governing permissions and |
AnnaBridge | 189:f392fc9709a3 | 16 | * limitations under the License. |
AnnaBridge | 189:f392fc9709a3 | 17 | */ |
AnnaBridge | 189:f392fc9709a3 | 18 | #include "mbed_assert.h" |
AnnaBridge | 189:f392fc9709a3 | 19 | #include "mbed_error.h" |
AnnaBridge | 189:f392fc9709a3 | 20 | #include "spi_api.h" |
AnnaBridge | 189:f392fc9709a3 | 21 | |
AnnaBridge | 189:f392fc9709a3 | 22 | #if DEVICE_SPI |
AnnaBridge | 189:f392fc9709a3 | 23 | #include "cmsis.h" |
AnnaBridge | 189:f392fc9709a3 | 24 | #include "pinmap.h" |
AnnaBridge | 189:f392fc9709a3 | 25 | #include "PeripheralPins.h" |
AnnaBridge | 189:f392fc9709a3 | 26 | |
AnnaBridge | 189:f392fc9709a3 | 27 | #define SPI_S(obj) (( struct spi_s *)(obj)) |
AnnaBridge | 189:f392fc9709a3 | 28 | |
AnnaBridge | 189:f392fc9709a3 | 29 | /** Get the frequency of SPI clock source |
AnnaBridge | 189:f392fc9709a3 | 30 | * |
AnnaBridge | 189:f392fc9709a3 | 31 | * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral |
AnnaBridge | 189:f392fc9709a3 | 32 | * @param[out] spi_freq The SPI clock source freguency |
AnnaBridge | 189:f392fc9709a3 | 33 | * @param[in] obj The SPI object |
AnnaBridge | 189:f392fc9709a3 | 34 | */ |
AnnaBridge | 189:f392fc9709a3 | 35 | static int dev_spi_clock_source_frequency_get(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 36 | { |
AnnaBridge | 189:f392fc9709a3 | 37 | int spi_freq = 0; |
AnnaBridge | 189:f392fc9709a3 | 38 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 39 | |
AnnaBridge | 189:f392fc9709a3 | 40 | switch ((int)spiobj->spi) { |
AnnaBridge | 189:f392fc9709a3 | 41 | case SPI0: |
AnnaBridge | 189:f392fc9709a3 | 42 | /* clock source is APB2 */ |
AnnaBridge | 189:f392fc9709a3 | 43 | spi_freq = rcu_clock_freq_get(CK_APB2); |
AnnaBridge | 189:f392fc9709a3 | 44 | break; |
AnnaBridge | 189:f392fc9709a3 | 45 | case SPI1: |
AnnaBridge | 189:f392fc9709a3 | 46 | /* clock source is APB1 */ |
AnnaBridge | 189:f392fc9709a3 | 47 | spi_freq = rcu_clock_freq_get(CK_APB1); |
AnnaBridge | 189:f392fc9709a3 | 48 | break; |
AnnaBridge | 189:f392fc9709a3 | 49 | case SPI2: |
AnnaBridge | 189:f392fc9709a3 | 50 | /* clock source is APB1 */ |
AnnaBridge | 189:f392fc9709a3 | 51 | spi_freq = rcu_clock_freq_get(CK_APB1); |
AnnaBridge | 189:f392fc9709a3 | 52 | break; |
AnnaBridge | 189:f392fc9709a3 | 53 | default: |
AnnaBridge | 189:f392fc9709a3 | 54 | error("SPI clock source frequency get error"); |
AnnaBridge | 189:f392fc9709a3 | 55 | break; |
AnnaBridge | 189:f392fc9709a3 | 56 | } |
AnnaBridge | 189:f392fc9709a3 | 57 | return spi_freq; |
AnnaBridge | 189:f392fc9709a3 | 58 | } |
AnnaBridge | 189:f392fc9709a3 | 59 | |
AnnaBridge | 189:f392fc9709a3 | 60 | /** Initialize the SPI structure |
AnnaBridge | 189:f392fc9709a3 | 61 | * |
AnnaBridge | 189:f392fc9709a3 | 62 | * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral |
AnnaBridge | 189:f392fc9709a3 | 63 | * @param[out] obj The SPI object to initialize |
AnnaBridge | 189:f392fc9709a3 | 64 | */ |
AnnaBridge | 189:f392fc9709a3 | 65 | static void dev_spi_struct_init(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 66 | { |
AnnaBridge | 189:f392fc9709a3 | 67 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 68 | |
AnnaBridge | 189:f392fc9709a3 | 69 | spi_disable(spiobj->spi); |
AnnaBridge | 189:f392fc9709a3 | 70 | spi_para_init(spiobj->spi, &obj->spi_struct); |
AnnaBridge | 189:f392fc9709a3 | 71 | spi_enable(spiobj->spi); |
AnnaBridge | 189:f392fc9709a3 | 72 | } |
AnnaBridge | 189:f392fc9709a3 | 73 | |
AnnaBridge | 189:f392fc9709a3 | 74 | /** Initialize the SPI peripheral |
AnnaBridge | 189:f392fc9709a3 | 75 | * |
AnnaBridge | 189:f392fc9709a3 | 76 | * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral |
AnnaBridge | 189:f392fc9709a3 | 77 | * @param[out] obj The SPI object to initialize |
AnnaBridge | 189:f392fc9709a3 | 78 | * @param[in] mosi The pin to use for MOSI |
AnnaBridge | 189:f392fc9709a3 | 79 | * @param[in] miso The pin to use for MISO |
AnnaBridge | 189:f392fc9709a3 | 80 | * @param[in] sclk The pin to use for SCLK |
AnnaBridge | 189:f392fc9709a3 | 81 | * @param[in] ssel The pin to use for SSEL |
AnnaBridge | 189:f392fc9709a3 | 82 | */ |
AnnaBridge | 189:f392fc9709a3 | 83 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) |
AnnaBridge | 189:f392fc9709a3 | 84 | { |
AnnaBridge | 189:f392fc9709a3 | 85 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 86 | |
AnnaBridge | 189:f392fc9709a3 | 87 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
AnnaBridge | 189:f392fc9709a3 | 88 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
AnnaBridge | 189:f392fc9709a3 | 89 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
AnnaBridge | 189:f392fc9709a3 | 90 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
AnnaBridge | 189:f392fc9709a3 | 91 | |
AnnaBridge | 189:f392fc9709a3 | 92 | /* return SPIName according to PinName */ |
AnnaBridge | 189:f392fc9709a3 | 93 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
AnnaBridge | 189:f392fc9709a3 | 94 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
AnnaBridge | 189:f392fc9709a3 | 95 | |
AnnaBridge | 189:f392fc9709a3 | 96 | spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); |
AnnaBridge | 189:f392fc9709a3 | 97 | MBED_ASSERT(spiobj->spi != (SPIName)NC); |
AnnaBridge | 189:f392fc9709a3 | 98 | |
AnnaBridge | 189:f392fc9709a3 | 99 | /* Set iqr type */ |
AnnaBridge | 189:f392fc9709a3 | 100 | if (spiobj->spi == SPI0) { |
AnnaBridge | 189:f392fc9709a3 | 101 | rcu_periph_clock_enable(RCU_SPI0); |
AnnaBridge | 189:f392fc9709a3 | 102 | spiobj->spi_irq = SPI0_IRQn; |
AnnaBridge | 189:f392fc9709a3 | 103 | } |
AnnaBridge | 189:f392fc9709a3 | 104 | if (spiobj->spi == SPI1) { |
AnnaBridge | 189:f392fc9709a3 | 105 | rcu_periph_clock_enable(RCU_SPI1); |
AnnaBridge | 189:f392fc9709a3 | 106 | spiobj->spi_irq = SPI1_IRQn; |
AnnaBridge | 189:f392fc9709a3 | 107 | } |
AnnaBridge | 189:f392fc9709a3 | 108 | if (spiobj->spi == SPI2) { |
AnnaBridge | 189:f392fc9709a3 | 109 | rcu_periph_clock_enable(RCU_SPI2); |
AnnaBridge | 189:f392fc9709a3 | 110 | spiobj->spi_irq = SPI2_IRQn; |
AnnaBridge | 189:f392fc9709a3 | 111 | } |
AnnaBridge | 189:f392fc9709a3 | 112 | |
AnnaBridge | 189:f392fc9709a3 | 113 | /* config GPIO mode of SPI pins */ |
AnnaBridge | 189:f392fc9709a3 | 114 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
AnnaBridge | 189:f392fc9709a3 | 115 | pinmap_pinout(miso, PinMap_SPI_MISO); |
AnnaBridge | 189:f392fc9709a3 | 116 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
AnnaBridge | 189:f392fc9709a3 | 117 | spiobj->pin_miso = miso; |
AnnaBridge | 189:f392fc9709a3 | 118 | spiobj->pin_mosi = mosi; |
AnnaBridge | 189:f392fc9709a3 | 119 | spiobj->pin_sclk = sclk; |
AnnaBridge | 189:f392fc9709a3 | 120 | spiobj->pin_ssel = ssel; |
AnnaBridge | 189:f392fc9709a3 | 121 | if (ssel != NC) { |
AnnaBridge | 189:f392fc9709a3 | 122 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
AnnaBridge | 189:f392fc9709a3 | 123 | spiobj->spi_struct.nss = SPI_NSS_HARD; |
AnnaBridge | 189:f392fc9709a3 | 124 | } else { |
AnnaBridge | 189:f392fc9709a3 | 125 | spiobj->spi_struct.nss = SPI_NSS_SOFT; |
AnnaBridge | 189:f392fc9709a3 | 126 | } |
AnnaBridge | 189:f392fc9709a3 | 127 | |
AnnaBridge | 189:f392fc9709a3 | 128 | /* Default values */ |
AnnaBridge | 189:f392fc9709a3 | 129 | spiobj->spi_struct.device_mode = SPI_MASTER; |
AnnaBridge | 189:f392fc9709a3 | 130 | spiobj->spi_struct.prescale = SPI_PSC_256; |
AnnaBridge | 189:f392fc9709a3 | 131 | spiobj->spi_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; |
AnnaBridge | 189:f392fc9709a3 | 132 | spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; |
AnnaBridge | 189:f392fc9709a3 | 133 | spiobj->spi_struct.frame_size = SPI_FRAMESIZE_8BIT; |
AnnaBridge | 189:f392fc9709a3 | 134 | spiobj->spi_struct.endian = SPI_ENDIAN_MSB; |
AnnaBridge | 189:f392fc9709a3 | 135 | |
AnnaBridge | 189:f392fc9709a3 | 136 | dev_spi_struct_init(obj); |
AnnaBridge | 189:f392fc9709a3 | 137 | } |
AnnaBridge | 189:f392fc9709a3 | 138 | |
AnnaBridge | 189:f392fc9709a3 | 139 | /** Release a SPI object |
AnnaBridge | 189:f392fc9709a3 | 140 | * |
AnnaBridge | 189:f392fc9709a3 | 141 | * TODO: spi_free is currently unimplemented |
AnnaBridge | 189:f392fc9709a3 | 142 | * This will require reference counting at the C++ level to be safe |
AnnaBridge | 189:f392fc9709a3 | 143 | * |
AnnaBridge | 189:f392fc9709a3 | 144 | * Return the pins owned by the SPI object to their reset state |
AnnaBridge | 189:f392fc9709a3 | 145 | * Disable the SPI peripheral |
AnnaBridge | 189:f392fc9709a3 | 146 | * Disable the SPI clock |
AnnaBridge | 189:f392fc9709a3 | 147 | * @param[in] obj The SPI object to deinitialize |
AnnaBridge | 189:f392fc9709a3 | 148 | */ |
AnnaBridge | 189:f392fc9709a3 | 149 | void spi_free(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 150 | { |
AnnaBridge | 189:f392fc9709a3 | 151 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 152 | spi_disable(spiobj->spi); |
AnnaBridge | 189:f392fc9709a3 | 153 | |
AnnaBridge | 189:f392fc9709a3 | 154 | /* Disable and deinit SPI */ |
AnnaBridge | 189:f392fc9709a3 | 155 | if (spiobj->spi == SPI0) { |
AnnaBridge | 189:f392fc9709a3 | 156 | spi_i2s_deinit(SPI0); |
AnnaBridge | 189:f392fc9709a3 | 157 | rcu_periph_clock_disable(RCU_SPI0); |
AnnaBridge | 189:f392fc9709a3 | 158 | } |
AnnaBridge | 189:f392fc9709a3 | 159 | if (spiobj->spi == SPI1) { |
AnnaBridge | 189:f392fc9709a3 | 160 | spi_i2s_deinit(SPI1); |
AnnaBridge | 189:f392fc9709a3 | 161 | rcu_periph_clock_disable(RCU_SPI1); |
AnnaBridge | 189:f392fc9709a3 | 162 | } |
AnnaBridge | 189:f392fc9709a3 | 163 | if (spiobj->spi == SPI2) { |
AnnaBridge | 189:f392fc9709a3 | 164 | spi_i2s_deinit(SPI2); |
AnnaBridge | 189:f392fc9709a3 | 165 | rcu_periph_clock_disable(RCU_SPI2); |
AnnaBridge | 189:f392fc9709a3 | 166 | } |
AnnaBridge | 189:f392fc9709a3 | 167 | /* Deinit GPIO mode of SPI pins */ |
AnnaBridge | 189:f392fc9709a3 | 168 | pin_function(spiobj->pin_miso, MODE_IN_FLOATING); |
AnnaBridge | 189:f392fc9709a3 | 169 | pin_function(spiobj->pin_mosi, MODE_IN_FLOATING); |
AnnaBridge | 189:f392fc9709a3 | 170 | pin_function(spiobj->pin_sclk, MODE_IN_FLOATING); |
AnnaBridge | 189:f392fc9709a3 | 171 | if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { |
AnnaBridge | 189:f392fc9709a3 | 172 | pin_function(spiobj->pin_ssel, MODE_IN_FLOATING); |
AnnaBridge | 189:f392fc9709a3 | 173 | } |
AnnaBridge | 189:f392fc9709a3 | 174 | } |
AnnaBridge | 189:f392fc9709a3 | 175 | |
AnnaBridge | 189:f392fc9709a3 | 176 | /** Configure the SPI format |
AnnaBridge | 189:f392fc9709a3 | 177 | * |
AnnaBridge | 189:f392fc9709a3 | 178 | * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. |
AnnaBridge | 189:f392fc9709a3 | 179 | * The default bit order is MSB. |
AnnaBridge | 189:f392fc9709a3 | 180 | * @param[in,out] obj The SPI object to configure |
AnnaBridge | 189:f392fc9709a3 | 181 | * @param[in] bits The number of bits per frame |
AnnaBridge | 189:f392fc9709a3 | 182 | * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) |
AnnaBridge | 189:f392fc9709a3 | 183 | * @param[in] slave Zero for master mode or non-zero for slave mode |
AnnaBridge | 189:f392fc9709a3 | 184 | */ |
AnnaBridge | 189:f392fc9709a3 | 185 | void spi_format(spi_t *obj, int bits, int mode, int slave) |
AnnaBridge | 189:f392fc9709a3 | 186 | { |
AnnaBridge | 189:f392fc9709a3 | 187 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 188 | |
AnnaBridge | 189:f392fc9709a3 | 189 | spiobj->spi_struct.frame_size = (bits == 16) ? SPI_FRAMESIZE_16BIT : SPI_FRAMESIZE_8BIT; |
AnnaBridge | 189:f392fc9709a3 | 190 | /* Config polarity and phase of SPI */ |
AnnaBridge | 189:f392fc9709a3 | 191 | switch (mode) { |
AnnaBridge | 189:f392fc9709a3 | 192 | case 0: |
AnnaBridge | 189:f392fc9709a3 | 193 | spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; |
AnnaBridge | 189:f392fc9709a3 | 194 | break; |
AnnaBridge | 189:f392fc9709a3 | 195 | case 1: |
AnnaBridge | 189:f392fc9709a3 | 196 | spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; |
AnnaBridge | 189:f392fc9709a3 | 197 | break; |
AnnaBridge | 189:f392fc9709a3 | 198 | case 2: |
AnnaBridge | 189:f392fc9709a3 | 199 | spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; |
AnnaBridge | 189:f392fc9709a3 | 200 | break; |
AnnaBridge | 189:f392fc9709a3 | 201 | default: |
AnnaBridge | 189:f392fc9709a3 | 202 | spiobj->spi_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; |
AnnaBridge | 189:f392fc9709a3 | 203 | |
AnnaBridge | 189:f392fc9709a3 | 204 | break; |
AnnaBridge | 189:f392fc9709a3 | 205 | } |
AnnaBridge | 189:f392fc9709a3 | 206 | |
AnnaBridge | 189:f392fc9709a3 | 207 | if (spiobj->spi_struct.nss != SPI_NSS_SOFT) { |
AnnaBridge | 189:f392fc9709a3 | 208 | spiobj->spi_struct.nss = SPI_NSS_HARD; |
AnnaBridge | 189:f392fc9709a3 | 209 | spi_nss_output_enable(spiobj->spi); |
AnnaBridge | 189:f392fc9709a3 | 210 | } |
AnnaBridge | 189:f392fc9709a3 | 211 | /* Select SPI as master or slave */ |
AnnaBridge | 189:f392fc9709a3 | 212 | spiobj->spi_struct.device_mode = (slave) ? SPI_SLAVE : SPI_MASTER; |
AnnaBridge | 189:f392fc9709a3 | 213 | |
AnnaBridge | 189:f392fc9709a3 | 214 | dev_spi_struct_init(obj); |
AnnaBridge | 189:f392fc9709a3 | 215 | } |
AnnaBridge | 189:f392fc9709a3 | 216 | |
AnnaBridge | 189:f392fc9709a3 | 217 | static const uint16_t baudrate_prescaler_table[] = {SPI_PSC_2, |
AnnaBridge | 189:f392fc9709a3 | 218 | SPI_PSC_4, |
AnnaBridge | 189:f392fc9709a3 | 219 | SPI_PSC_8, |
AnnaBridge | 189:f392fc9709a3 | 220 | SPI_PSC_16, |
AnnaBridge | 189:f392fc9709a3 | 221 | SPI_PSC_32, |
AnnaBridge | 189:f392fc9709a3 | 222 | SPI_PSC_64, |
AnnaBridge | 189:f392fc9709a3 | 223 | SPI_PSC_128, |
AnnaBridge | 189:f392fc9709a3 | 224 | SPI_PSC_256 |
AnnaBridge | 189:f392fc9709a3 | 225 | }; |
AnnaBridge | 189:f392fc9709a3 | 226 | |
AnnaBridge | 189:f392fc9709a3 | 227 | /** Set the SPI baud rate |
AnnaBridge | 189:f392fc9709a3 | 228 | * |
AnnaBridge | 189:f392fc9709a3 | 229 | * Actual frequency may differ from the desired frequency due to available dividers and bus clock |
AnnaBridge | 189:f392fc9709a3 | 230 | * Configures the SPI peripheral's baud rate |
AnnaBridge | 189:f392fc9709a3 | 231 | * @param[in,out] obj The SPI object to configure |
AnnaBridge | 189:f392fc9709a3 | 232 | * @param[in] hz The baud rate in Hz |
AnnaBridge | 189:f392fc9709a3 | 233 | */ |
AnnaBridge | 189:f392fc9709a3 | 234 | void spi_frequency(spi_t *obj, int hz) |
AnnaBridge | 189:f392fc9709a3 | 235 | { |
AnnaBridge | 189:f392fc9709a3 | 236 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 237 | int spi_hz = 0; |
AnnaBridge | 189:f392fc9709a3 | 238 | uint8_t prescaler_rank = 0; |
AnnaBridge | 189:f392fc9709a3 | 239 | uint8_t last_index = (sizeof(baudrate_prescaler_table) / sizeof(baudrate_prescaler_table[0])) - 1; |
AnnaBridge | 189:f392fc9709a3 | 240 | |
AnnaBridge | 189:f392fc9709a3 | 241 | spi_hz = dev_spi_clock_source_frequency_get(obj) / 2; |
AnnaBridge | 189:f392fc9709a3 | 242 | |
AnnaBridge | 189:f392fc9709a3 | 243 | /* Config SPI prescaler according to input frequency*/ |
AnnaBridge | 189:f392fc9709a3 | 244 | while ((spi_hz > hz) && (prescaler_rank < last_index)) { |
AnnaBridge | 189:f392fc9709a3 | 245 | spi_hz = spi_hz / 2; |
AnnaBridge | 189:f392fc9709a3 | 246 | prescaler_rank++; |
AnnaBridge | 189:f392fc9709a3 | 247 | } |
AnnaBridge | 189:f392fc9709a3 | 248 | |
AnnaBridge | 189:f392fc9709a3 | 249 | spiobj->spi_struct.prescale = baudrate_prescaler_table[prescaler_rank]; |
AnnaBridge | 189:f392fc9709a3 | 250 | dev_spi_struct_init(obj); |
AnnaBridge | 189:f392fc9709a3 | 251 | } |
AnnaBridge | 189:f392fc9709a3 | 252 | |
AnnaBridge | 189:f392fc9709a3 | 253 | /** Write a block out in master mode and receive a value |
AnnaBridge | 189:f392fc9709a3 | 254 | * |
AnnaBridge | 189:f392fc9709a3 | 255 | * The total number of bytes sent and received will be the maximum of |
AnnaBridge | 189:f392fc9709a3 | 256 | * tx_length and rx_length. The bytes written will be padded with the |
AnnaBridge | 189:f392fc9709a3 | 257 | * value 0xff. |
AnnaBridge | 189:f392fc9709a3 | 258 | * |
AnnaBridge | 189:f392fc9709a3 | 259 | * @param[in] obj The SPI peripheral to use for sending |
AnnaBridge | 189:f392fc9709a3 | 260 | * @param[in] tx_buffer Pointer to the byte-array of data to write to the device |
AnnaBridge | 189:f392fc9709a3 | 261 | * @param[in] tx_length Number of bytes to write, may be zero |
AnnaBridge | 189:f392fc9709a3 | 262 | * @param[in] rx_buffer Pointer to the byte-array of data to read from the device |
AnnaBridge | 189:f392fc9709a3 | 263 | * @param[in] rx_length Number of bytes to read, may be zero |
AnnaBridge | 189:f392fc9709a3 | 264 | * @param[in] write_fill Default data transmitted while performing a read |
AnnaBridge | 189:f392fc9709a3 | 265 | * @returns |
AnnaBridge | 189:f392fc9709a3 | 266 | * The number of bytes written and read from the device. This is |
AnnaBridge | 189:f392fc9709a3 | 267 | * maximum of tx_length and rx_length. |
AnnaBridge | 189:f392fc9709a3 | 268 | */ |
AnnaBridge | 189:f392fc9709a3 | 269 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) |
AnnaBridge | 189:f392fc9709a3 | 270 | { |
AnnaBridge | 189:f392fc9709a3 | 271 | int total = (tx_length > rx_length) ? tx_length : rx_length; |
AnnaBridge | 189:f392fc9709a3 | 272 | |
AnnaBridge | 189:f392fc9709a3 | 273 | for (int i = 0; i < total; i++) { |
AnnaBridge | 189:f392fc9709a3 | 274 | char out = (i < tx_length) ? tx_buffer[i] : write_fill; |
AnnaBridge | 189:f392fc9709a3 | 275 | char in = spi_master_write(obj, out); |
AnnaBridge | 189:f392fc9709a3 | 276 | if (i < rx_length) { |
AnnaBridge | 189:f392fc9709a3 | 277 | rx_buffer[i] = in; |
AnnaBridge | 189:f392fc9709a3 | 278 | } |
AnnaBridge | 189:f392fc9709a3 | 279 | } |
AnnaBridge | 189:f392fc9709a3 | 280 | |
AnnaBridge | 189:f392fc9709a3 | 281 | return total; |
AnnaBridge | 189:f392fc9709a3 | 282 | } |
AnnaBridge | 189:f392fc9709a3 | 283 | |
AnnaBridge | 189:f392fc9709a3 | 284 | /** Write a byte out in master mode and receive a value |
AnnaBridge | 189:f392fc9709a3 | 285 | * |
AnnaBridge | 189:f392fc9709a3 | 286 | * @param[in] obj The SPI peripheral to use for sending |
AnnaBridge | 189:f392fc9709a3 | 287 | * @param[in] value The value to send |
AnnaBridge | 189:f392fc9709a3 | 288 | * @return Returns the value received during send |
AnnaBridge | 189:f392fc9709a3 | 289 | */ |
AnnaBridge | 189:f392fc9709a3 | 290 | int spi_master_write(spi_t *obj, int value) |
AnnaBridge | 189:f392fc9709a3 | 291 | { |
AnnaBridge | 189:f392fc9709a3 | 292 | int count = 0; |
AnnaBridge | 189:f392fc9709a3 | 293 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 294 | |
AnnaBridge | 189:f392fc9709a3 | 295 | /* wait the SPI transmit buffer is empty */ |
AnnaBridge | 189:f392fc9709a3 | 296 | while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)) && (count++ < 1000)); |
AnnaBridge | 189:f392fc9709a3 | 297 | if (count >= 1000) { |
AnnaBridge | 189:f392fc9709a3 | 298 | return -1; |
AnnaBridge | 189:f392fc9709a3 | 299 | } else { |
AnnaBridge | 189:f392fc9709a3 | 300 | spi_i2s_data_transmit(spiobj->spi, value); |
AnnaBridge | 189:f392fc9709a3 | 301 | } |
AnnaBridge | 189:f392fc9709a3 | 302 | |
AnnaBridge | 189:f392fc9709a3 | 303 | count = 0; |
AnnaBridge | 189:f392fc9709a3 | 304 | /* wait the SPI receive buffer is not empty */ |
AnnaBridge | 189:f392fc9709a3 | 305 | while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); |
AnnaBridge | 189:f392fc9709a3 | 306 | if (count >= 1000) { |
AnnaBridge | 189:f392fc9709a3 | 307 | return -1; |
AnnaBridge | 189:f392fc9709a3 | 308 | } else { |
AnnaBridge | 189:f392fc9709a3 | 309 | return spi_i2s_data_receive(spiobj->spi); |
AnnaBridge | 189:f392fc9709a3 | 310 | } |
AnnaBridge | 189:f392fc9709a3 | 311 | } |
AnnaBridge | 189:f392fc9709a3 | 312 | |
AnnaBridge | 189:f392fc9709a3 | 313 | /** Check if a value is available to read |
AnnaBridge | 189:f392fc9709a3 | 314 | * |
AnnaBridge | 189:f392fc9709a3 | 315 | * @param[in] obj The SPI peripheral to check |
AnnaBridge | 189:f392fc9709a3 | 316 | * @return non-zero if a value is available |
AnnaBridge | 189:f392fc9709a3 | 317 | */ |
AnnaBridge | 189:f392fc9709a3 | 318 | int spi_slave_receive(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 319 | { |
AnnaBridge | 189:f392fc9709a3 | 320 | int status; |
AnnaBridge | 189:f392fc9709a3 | 321 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 322 | /* check whether or not the SPI receive buffer is empty */ |
AnnaBridge | 189:f392fc9709a3 | 323 | status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE) != RESET) ? 1 : 0); |
AnnaBridge | 189:f392fc9709a3 | 324 | return status; |
AnnaBridge | 189:f392fc9709a3 | 325 | } |
AnnaBridge | 189:f392fc9709a3 | 326 | |
AnnaBridge | 189:f392fc9709a3 | 327 | /** Get a received value out of the SPI receive buffer in slave mode |
AnnaBridge | 189:f392fc9709a3 | 328 | * |
AnnaBridge | 189:f392fc9709a3 | 329 | * Blocks until a value is available |
AnnaBridge | 189:f392fc9709a3 | 330 | * @param[in] obj The SPI peripheral to read |
AnnaBridge | 189:f392fc9709a3 | 331 | * @return The value received |
AnnaBridge | 189:f392fc9709a3 | 332 | */ |
AnnaBridge | 189:f392fc9709a3 | 333 | int spi_slave_read(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 334 | { |
AnnaBridge | 189:f392fc9709a3 | 335 | int count = 0; |
AnnaBridge | 189:f392fc9709a3 | 336 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 337 | /* wait the SPI receive buffer is not empty */ |
AnnaBridge | 189:f392fc9709a3 | 338 | while ((RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_RBNE)) && (count++ < 1000)); |
AnnaBridge | 189:f392fc9709a3 | 339 | if (count >= 1000) { |
AnnaBridge | 189:f392fc9709a3 | 340 | return -1; |
AnnaBridge | 189:f392fc9709a3 | 341 | } else { |
AnnaBridge | 189:f392fc9709a3 | 342 | return spi_i2s_data_receive(spiobj->spi); |
AnnaBridge | 189:f392fc9709a3 | 343 | } |
AnnaBridge | 189:f392fc9709a3 | 344 | } |
AnnaBridge | 189:f392fc9709a3 | 345 | |
AnnaBridge | 189:f392fc9709a3 | 346 | /** Write a value to the SPI peripheral in slave mode |
AnnaBridge | 189:f392fc9709a3 | 347 | * |
AnnaBridge | 189:f392fc9709a3 | 348 | * Blocks until the SPI peripheral can be written to |
AnnaBridge | 189:f392fc9709a3 | 349 | * @param[in] obj The SPI peripheral to write |
AnnaBridge | 189:f392fc9709a3 | 350 | * @param[in] value The value to write |
AnnaBridge | 189:f392fc9709a3 | 351 | */ |
AnnaBridge | 189:f392fc9709a3 | 352 | void spi_slave_write(spi_t *obj, int value) |
AnnaBridge | 189:f392fc9709a3 | 353 | { |
AnnaBridge | 189:f392fc9709a3 | 354 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 355 | /* wait the SPI transmit buffer is empty */ |
AnnaBridge | 189:f392fc9709a3 | 356 | while (RESET == spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TBE)); |
AnnaBridge | 189:f392fc9709a3 | 357 | spi_i2s_data_transmit(spiobj->spi, value); |
AnnaBridge | 189:f392fc9709a3 | 358 | } |
AnnaBridge | 189:f392fc9709a3 | 359 | |
AnnaBridge | 189:f392fc9709a3 | 360 | /** Checks if the specified SPI peripheral is in use |
AnnaBridge | 189:f392fc9709a3 | 361 | * |
AnnaBridge | 189:f392fc9709a3 | 362 | * @param[in] obj The SPI peripheral to check |
AnnaBridge | 189:f392fc9709a3 | 363 | * @return non-zero if the peripheral is currently transmitting |
AnnaBridge | 189:f392fc9709a3 | 364 | */ |
AnnaBridge | 189:f392fc9709a3 | 365 | int spi_busy(spi_t *obj) |
AnnaBridge | 189:f392fc9709a3 | 366 | { |
AnnaBridge | 189:f392fc9709a3 | 367 | int status; |
AnnaBridge | 189:f392fc9709a3 | 368 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 189:f392fc9709a3 | 369 | /* check whether or not the SPI is busy */ |
AnnaBridge | 189:f392fc9709a3 | 370 | status = ((spi_i2s_flag_get(spiobj->spi, SPI_FLAG_TRANS) != RESET) ? 1 : 0); |
AnnaBridge | 189:f392fc9709a3 | 371 | return status; |
AnnaBridge | 189:f392fc9709a3 | 372 | } |
AnnaBridge | 189:f392fc9709a3 | 373 | |
AnnaBridge | 189:f392fc9709a3 | 374 | #endif |