mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_GigaDevice/TARGET_GD32F30X/sleep.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2018 GigaDevice Semiconductor Inc.
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 5 *
AnnaBridge 189:f392fc9709a3 6 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 7 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 8 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 13 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 15 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 16 * limitations under the License.
AnnaBridge 189:f392fc9709a3 17 */
AnnaBridge 189:f392fc9709a3 18 #if DEVICE_SLEEP
AnnaBridge 189:f392fc9709a3 19
AnnaBridge 189:f392fc9709a3 20 #include "sleep_api.h"
AnnaBridge 189:f392fc9709a3 21 #include "us_ticker_api.h"
AnnaBridge 189:f392fc9709a3 22 #include "mbed_critical.h"
AnnaBridge 189:f392fc9709a3 23 #include "mbed_error.h"
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 extern void ticker_timer_data_save(void);
AnnaBridge 189:f392fc9709a3 26 extern void ticker_timer_data_restore(void);
AnnaBridge 189:f392fc9709a3 27 extern int serial_busy_state_check(void);
AnnaBridge 189:f392fc9709a3 28
AnnaBridge 189:f392fc9709a3 29 /*!
AnnaBridge 189:f392fc9709a3 30 \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
AnnaBridge 189:f392fc9709a3 31 \param[in] none
AnnaBridge 189:f392fc9709a3 32 \param[out] none
AnnaBridge 189:f392fc9709a3 33 \retval none
AnnaBridge 189:f392fc9709a3 34 */
AnnaBridge 189:f392fc9709a3 35 static void system_clock_120m_hxtal(void)
AnnaBridge 189:f392fc9709a3 36 {
AnnaBridge 189:f392fc9709a3 37 uint32_t timeout = 0U;
AnnaBridge 189:f392fc9709a3 38 uint32_t stab_flag = 0U;
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 /* enable HXTAL */
AnnaBridge 189:f392fc9709a3 41 RCU_CTL |= RCU_CTL_HXTALEN;
AnnaBridge 189:f392fc9709a3 42
AnnaBridge 189:f392fc9709a3 43 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
AnnaBridge 189:f392fc9709a3 44 do {
AnnaBridge 189:f392fc9709a3 45 timeout++;
AnnaBridge 189:f392fc9709a3 46 stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
AnnaBridge 189:f392fc9709a3 47 } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
AnnaBridge 189:f392fc9709a3 48
AnnaBridge 189:f392fc9709a3 49 /* if fail */
AnnaBridge 189:f392fc9709a3 50 if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
AnnaBridge 189:f392fc9709a3 51 while (1) {
AnnaBridge 189:f392fc9709a3 52 }
AnnaBridge 189:f392fc9709a3 53 }
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 RCU_APB1EN |= RCU_APB1EN_PMUEN;
AnnaBridge 189:f392fc9709a3 56 PMU_CTL |= PMU_CTL_LDOVS;
AnnaBridge 189:f392fc9709a3 57
AnnaBridge 189:f392fc9709a3 58 /* HXTAL is stable */
AnnaBridge 189:f392fc9709a3 59 /* AHB = SYSCLK */
AnnaBridge 189:f392fc9709a3 60 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
AnnaBridge 189:f392fc9709a3 61 /* APB2 = AHB/1 */
AnnaBridge 189:f392fc9709a3 62 RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
AnnaBridge 189:f392fc9709a3 63 /* APB1 = AHB/2 */
AnnaBridge 189:f392fc9709a3 64 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
AnnaBridge 189:f392fc9709a3 65
AnnaBridge 189:f392fc9709a3 66 #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
AnnaBridge 189:f392fc9709a3 67 /* select HXTAL/2 as clock source */
AnnaBridge 189:f392fc9709a3 68 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
AnnaBridge 189:f392fc9709a3 69 RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
AnnaBridge 189:f392fc9709a3 70
AnnaBridge 189:f392fc9709a3 71 /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */
AnnaBridge 189:f392fc9709a3 72 RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
AnnaBridge 189:f392fc9709a3 73 RCU_CFG0 |= RCU_PLL_MUL30;
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 #elif defined(GD32F30X_CL)
AnnaBridge 189:f392fc9709a3 76 /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
AnnaBridge 189:f392fc9709a3 77 RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
AnnaBridge 189:f392fc9709a3 78 RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
AnnaBridge 189:f392fc9709a3 79
AnnaBridge 189:f392fc9709a3 80 /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
AnnaBridge 189:f392fc9709a3 81 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
AnnaBridge 189:f392fc9709a3 82 RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 /* enable PLL1 */
AnnaBridge 189:f392fc9709a3 85 RCU_CTL |= RCU_CTL_PLL1EN;
AnnaBridge 189:f392fc9709a3 86 /* wait till PLL1 is ready */
AnnaBridge 189:f392fc9709a3 87 while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) {
AnnaBridge 189:f392fc9709a3 88 }
AnnaBridge 189:f392fc9709a3 89 #endif /* GD32F30X_HD and GD32F30X_XD */
AnnaBridge 189:f392fc9709a3 90
AnnaBridge 189:f392fc9709a3 91 /* enable PLL */
AnnaBridge 189:f392fc9709a3 92 RCU_CTL |= RCU_CTL_PLLEN;
AnnaBridge 189:f392fc9709a3 93
AnnaBridge 189:f392fc9709a3 94 /* wait until PLL is stable */
AnnaBridge 189:f392fc9709a3 95 while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
AnnaBridge 189:f392fc9709a3 96 }
AnnaBridge 189:f392fc9709a3 97
AnnaBridge 189:f392fc9709a3 98 /* enable the high-drive to extend the clock frequency to 120 MHz */
AnnaBridge 189:f392fc9709a3 99 PMU_CTL |= PMU_CTL_HDEN;
AnnaBridge 189:f392fc9709a3 100 while (0U == (PMU_CS & PMU_CS_HDRF)) {
AnnaBridge 189:f392fc9709a3 101 }
AnnaBridge 189:f392fc9709a3 102
AnnaBridge 189:f392fc9709a3 103 /* select the high-drive mode */
AnnaBridge 189:f392fc9709a3 104 PMU_CTL |= PMU_CTL_HDS;
AnnaBridge 189:f392fc9709a3 105 while (0U == (PMU_CS & PMU_CS_HDSRF)) {
AnnaBridge 189:f392fc9709a3 106 }
AnnaBridge 189:f392fc9709a3 107
AnnaBridge 189:f392fc9709a3 108 /* select PLL as system clock */
AnnaBridge 189:f392fc9709a3 109 RCU_CFG0 &= ~RCU_CFG0_SCS;
AnnaBridge 189:f392fc9709a3 110 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
AnnaBridge 189:f392fc9709a3 111
AnnaBridge 189:f392fc9709a3 112 /* wait until PLL is selected as system clock */
AnnaBridge 189:f392fc9709a3 113 while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
AnnaBridge 189:f392fc9709a3 114 }
AnnaBridge 189:f392fc9709a3 115 }
AnnaBridge 189:f392fc9709a3 116
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 /** Send the microcontroller to sleep
AnnaBridge 189:f392fc9709a3 119 *
AnnaBridge 189:f392fc9709a3 120 * The processor is setup ready for sleep, and sent to sleep. In this mode, the
AnnaBridge 189:f392fc9709a3 121 * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
AnnaBridge 189:f392fc9709a3 122 * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
AnnaBridge 189:f392fc9709a3 123 * memory state are maintained, and the peripherals continue to work and can generate interrupts.
AnnaBridge 189:f392fc9709a3 124 *
AnnaBridge 189:f392fc9709a3 125 * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
AnnaBridge 189:f392fc9709a3 126 *
AnnaBridge 189:f392fc9709a3 127 * The wake-up time shall be less than 10 us.
AnnaBridge 189:f392fc9709a3 128 *
AnnaBridge 189:f392fc9709a3 129 */
AnnaBridge 189:f392fc9709a3 130 void hal_sleep(void)
AnnaBridge 189:f392fc9709a3 131 {
AnnaBridge 189:f392fc9709a3 132 /* Disable Interrupts */
AnnaBridge 189:f392fc9709a3 133 core_util_critical_section_enter();
AnnaBridge 189:f392fc9709a3 134
AnnaBridge 189:f392fc9709a3 135 /* Enter SLEEP mode */
AnnaBridge 189:f392fc9709a3 136 pmu_to_sleepmode(WFI_CMD);
AnnaBridge 189:f392fc9709a3 137
AnnaBridge 189:f392fc9709a3 138 /* Enable Interrupts */
AnnaBridge 189:f392fc9709a3 139 core_util_critical_section_exit();
AnnaBridge 189:f392fc9709a3 140 }
AnnaBridge 189:f392fc9709a3 141
AnnaBridge 189:f392fc9709a3 142
AnnaBridge 189:f392fc9709a3 143 /** Send the microcontroller to deep sleep
AnnaBridge 189:f392fc9709a3 144 *
AnnaBridge 189:f392fc9709a3 145 * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
AnnaBridge 189:f392fc9709a3 146 * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks.
AnnaBridge 189:f392fc9709a3 147 * All state is still maintained.
AnnaBridge 189:f392fc9709a3 148 *
AnnaBridge 189:f392fc9709a3 149 * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer.
AnnaBridge 189:f392fc9709a3 150 *
AnnaBridge 189:f392fc9709a3 151 * The wake-up time shall be less than 10 ms.
AnnaBridge 189:f392fc9709a3 152 */
AnnaBridge 189:f392fc9709a3 153 void hal_deepsleep(void)
AnnaBridge 189:f392fc9709a3 154 {
AnnaBridge 189:f392fc9709a3 155 if (0 != serial_busy_state_check()) {
AnnaBridge 189:f392fc9709a3 156 return;
AnnaBridge 189:f392fc9709a3 157 }
AnnaBridge 189:f392fc9709a3 158
AnnaBridge 189:f392fc9709a3 159 /* Disable Interrupts */
AnnaBridge 189:f392fc9709a3 160 core_util_critical_section_enter();
AnnaBridge 189:f392fc9709a3 161
AnnaBridge 189:f392fc9709a3 162 ticker_timer_data_save();
AnnaBridge 189:f392fc9709a3 163
AnnaBridge 189:f392fc9709a3 164 /* Enter DEEP SLEEP mode */
AnnaBridge 189:f392fc9709a3 165 rcu_periph_clock_enable(RCU_PMU);
AnnaBridge 189:f392fc9709a3 166 pmu_to_deepsleepmode(PMU_LDO_NORMAL, WFI_CMD);
AnnaBridge 189:f392fc9709a3 167
AnnaBridge 189:f392fc9709a3 168 /* Reconfigure the PLL after weak up */
AnnaBridge 189:f392fc9709a3 169 system_clock_120m_hxtal();
AnnaBridge 189:f392fc9709a3 170
AnnaBridge 189:f392fc9709a3 171 ticker_timer_data_restore();
AnnaBridge 189:f392fc9709a3 172
AnnaBridge 189:f392fc9709a3 173 /* Enable Interrupts */
AnnaBridge 189:f392fc9709a3 174 core_util_critical_section_exit();
AnnaBridge 189:f392fc9709a3 175 }
AnnaBridge 189:f392fc9709a3 176
AnnaBridge 189:f392fc9709a3 177 #endif /* DEVICE_SLEEP */