mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_GigaDevice/TARGET_GD32F30X/mbed_overrides.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2018 GigaDevice Semiconductor Inc.
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 5 *
AnnaBridge 189:f392fc9709a3 6 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 7 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 8 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 13 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 15 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 16 * limitations under the License.
AnnaBridge 189:f392fc9709a3 17 */
AnnaBridge 189:f392fc9709a3 18 #include "gd32f30x.h"
AnnaBridge 189:f392fc9709a3 19 #include "cmsis.h"
AnnaBridge 189:f392fc9709a3 20 #include "hal_tick.h"
AnnaBridge 189:f392fc9709a3 21
AnnaBridge 189:f392fc9709a3 22 int mbed_sdk_inited = 0;
AnnaBridge 189:f392fc9709a3 23
AnnaBridge 189:f392fc9709a3 24 /*!
AnnaBridge 189:f392fc9709a3 25 \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
AnnaBridge 189:f392fc9709a3 26 \param[in] none
AnnaBridge 189:f392fc9709a3 27 \param[out] none
AnnaBridge 189:f392fc9709a3 28 \retval none
AnnaBridge 189:f392fc9709a3 29 */
AnnaBridge 189:f392fc9709a3 30 #if TICKER_TIMER_WIDTH_BIT == 16
AnnaBridge 189:f392fc9709a3 31 extern void ticker_16bits_timer_init(void);
AnnaBridge 189:f392fc9709a3 32 #else
AnnaBridge 189:f392fc9709a3 33 extern void ticker_32bits_timer_init(void);
AnnaBridge 189:f392fc9709a3 34 #endif
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 /*!
AnnaBridge 189:f392fc9709a3 37 \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
AnnaBridge 189:f392fc9709a3 38 \param[in] none
AnnaBridge 189:f392fc9709a3 39 \param[out] none
AnnaBridge 189:f392fc9709a3 40 \retval none
AnnaBridge 189:f392fc9709a3 41 */
AnnaBridge 189:f392fc9709a3 42 static void system_clock_120m_hxtal(void)
AnnaBridge 189:f392fc9709a3 43 {
AnnaBridge 189:f392fc9709a3 44 uint32_t timeout = 0U;
AnnaBridge 189:f392fc9709a3 45 uint32_t stab_flag = 0U;
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 /* enable HXTAL */
AnnaBridge 189:f392fc9709a3 48 RCU_CTL |= RCU_CTL_HXTALEN;
AnnaBridge 189:f392fc9709a3 49
AnnaBridge 189:f392fc9709a3 50 /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
AnnaBridge 189:f392fc9709a3 51 do {
AnnaBridge 189:f392fc9709a3 52 timeout++;
AnnaBridge 189:f392fc9709a3 53 stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
AnnaBridge 189:f392fc9709a3 54 } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
AnnaBridge 189:f392fc9709a3 55
AnnaBridge 189:f392fc9709a3 56 /* if fail */
AnnaBridge 189:f392fc9709a3 57 if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
AnnaBridge 189:f392fc9709a3 58 while (1) {
AnnaBridge 189:f392fc9709a3 59 }
AnnaBridge 189:f392fc9709a3 60 }
AnnaBridge 189:f392fc9709a3 61
AnnaBridge 189:f392fc9709a3 62 RCU_APB1EN |= RCU_APB1EN_PMUEN;
AnnaBridge 189:f392fc9709a3 63 PMU_CTL |= PMU_CTL_LDOVS;
AnnaBridge 189:f392fc9709a3 64
AnnaBridge 189:f392fc9709a3 65 /* HXTAL is stable */
AnnaBridge 189:f392fc9709a3 66 /* AHB = SYSCLK */
AnnaBridge 189:f392fc9709a3 67 RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
AnnaBridge 189:f392fc9709a3 68 /* APB2 = AHB/1 */
AnnaBridge 189:f392fc9709a3 69 RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
AnnaBridge 189:f392fc9709a3 70 /* APB1 = AHB/2 */
AnnaBridge 189:f392fc9709a3 71 RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
AnnaBridge 189:f392fc9709a3 72
AnnaBridge 189:f392fc9709a3 73 #if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
AnnaBridge 189:f392fc9709a3 74 /* select HXTAL/2 as clock source */
AnnaBridge 189:f392fc9709a3 75 RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0);
AnnaBridge 189:f392fc9709a3 76 RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0);
AnnaBridge 189:f392fc9709a3 77
AnnaBridge 189:f392fc9709a3 78 /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */
AnnaBridge 189:f392fc9709a3 79 RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
AnnaBridge 189:f392fc9709a3 80 RCU_CFG0 |= RCU_PLL_MUL30;
AnnaBridge 189:f392fc9709a3 81
AnnaBridge 189:f392fc9709a3 82 #elif defined(GD32F30X_CL)
AnnaBridge 189:f392fc9709a3 83 /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
AnnaBridge 189:f392fc9709a3 84 RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
AnnaBridge 189:f392fc9709a3 85 RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
AnnaBridge 189:f392fc9709a3 86
AnnaBridge 189:f392fc9709a3 87 /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
AnnaBridge 189:f392fc9709a3 88 RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
AnnaBridge 189:f392fc9709a3 89 RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
AnnaBridge 189:f392fc9709a3 90
AnnaBridge 189:f392fc9709a3 91 /* enable PLL1 */
AnnaBridge 189:f392fc9709a3 92 RCU_CTL |= RCU_CTL_PLL1EN;
AnnaBridge 189:f392fc9709a3 93 /* wait till PLL1 is ready */
AnnaBridge 189:f392fc9709a3 94 while ((RCU_CTL & RCU_CTL_PLL1STB) == 0U) {
AnnaBridge 189:f392fc9709a3 95 }
AnnaBridge 189:f392fc9709a3 96 #endif /* GD32F30X_HD and GD32F30X_XD */
AnnaBridge 189:f392fc9709a3 97
AnnaBridge 189:f392fc9709a3 98 /* enable PLL */
AnnaBridge 189:f392fc9709a3 99 RCU_CTL |= RCU_CTL_PLLEN;
AnnaBridge 189:f392fc9709a3 100
AnnaBridge 189:f392fc9709a3 101 /* wait until PLL is stable */
AnnaBridge 189:f392fc9709a3 102 while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
AnnaBridge 189:f392fc9709a3 103 }
AnnaBridge 189:f392fc9709a3 104
AnnaBridge 189:f392fc9709a3 105 /* enable the high-drive to extend the clock frequency to 120 MHz */
AnnaBridge 189:f392fc9709a3 106 PMU_CTL |= PMU_CTL_HDEN;
AnnaBridge 189:f392fc9709a3 107 while (0U == (PMU_CS & PMU_CS_HDRF)) {
AnnaBridge 189:f392fc9709a3 108 }
AnnaBridge 189:f392fc9709a3 109
AnnaBridge 189:f392fc9709a3 110 /* select the high-drive mode */
AnnaBridge 189:f392fc9709a3 111 PMU_CTL |= PMU_CTL_HDS;
AnnaBridge 189:f392fc9709a3 112 while (0U == (PMU_CS & PMU_CS_HDSRF)) {
AnnaBridge 189:f392fc9709a3 113 }
AnnaBridge 189:f392fc9709a3 114
AnnaBridge 189:f392fc9709a3 115 /* select PLL as system clock */
AnnaBridge 189:f392fc9709a3 116 RCU_CFG0 &= ~RCU_CFG0_SCS;
AnnaBridge 189:f392fc9709a3 117 RCU_CFG0 |= RCU_CKSYSSRC_PLL;
AnnaBridge 189:f392fc9709a3 118
AnnaBridge 189:f392fc9709a3 119 /* wait until PLL is selected as system clock */
AnnaBridge 189:f392fc9709a3 120 while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
AnnaBridge 189:f392fc9709a3 121 }
AnnaBridge 189:f392fc9709a3 122 }
AnnaBridge 189:f392fc9709a3 123
AnnaBridge 189:f392fc9709a3 124 /**
AnnaBridge 189:f392fc9709a3 125 * SDK hook for running code before ctors or OS
AnnaBridge 189:f392fc9709a3 126 *
AnnaBridge 189:f392fc9709a3 127 * This is a weak function which can be overridden by a target's
AnnaBridge 189:f392fc9709a3 128 * SDK to allow code to run after ram is initialized but before
AnnaBridge 189:f392fc9709a3 129 * the OS has been started or constructors have run.
AnnaBridge 189:f392fc9709a3 130 *
AnnaBridge 189:f392fc9709a3 131 * Preconditions:
AnnaBridge 189:f392fc9709a3 132 * - Ram is initialized
AnnaBridge 189:f392fc9709a3 133 * - NVIC is setup
AnnaBridge 189:f392fc9709a3 134 */
AnnaBridge 189:f392fc9709a3 135 /**
AnnaBridge 189:f392fc9709a3 136 * This function is called after RAM initialization and before main.
AnnaBridge 189:f392fc9709a3 137 */
AnnaBridge 189:f392fc9709a3 138 void mbed_sdk_init()
AnnaBridge 189:f392fc9709a3 139 {
AnnaBridge 189:f392fc9709a3 140 /* Update the SystemCoreClock */
AnnaBridge 189:f392fc9709a3 141 SystemCoreClockUpdate();
AnnaBridge 189:f392fc9709a3 142 nvic_priority_group_set(NVIC_PRIGROUP_PRE4_SUB0);
AnnaBridge 189:f392fc9709a3 143
AnnaBridge 189:f392fc9709a3 144 /* configure 1ms tick */
AnnaBridge 189:f392fc9709a3 145 #if TICKER_TIMER_WIDTH_BIT == 16
AnnaBridge 189:f392fc9709a3 146 ticker_16bits_timer_init();
AnnaBridge 189:f392fc9709a3 147 #else
AnnaBridge 189:f392fc9709a3 148 ticker_32bits_timer_init();
AnnaBridge 189:f392fc9709a3 149 #endif
AnnaBridge 189:f392fc9709a3 150
AnnaBridge 189:f392fc9709a3 151 system_clock_120m_hxtal();
AnnaBridge 189:f392fc9709a3 152
AnnaBridge 189:f392fc9709a3 153 SystemCoreClockUpdate();
AnnaBridge 189:f392fc9709a3 154
AnnaBridge 189:f392fc9709a3 155 mbed_sdk_inited = 1;
AnnaBridge 189:f392fc9709a3 156 }