mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_GigaDevice/TARGET_GD32E10X/pinmap.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2018 GigaDevice Semiconductor Inc.
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 5 *
AnnaBridge 189:f392fc9709a3 6 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 7 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 8 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 13 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 15 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 16 * limitations under the License.
AnnaBridge 189:f392fc9709a3 17 */
AnnaBridge 189:f392fc9709a3 18 #include "mbed_assert.h"
AnnaBridge 189:f392fc9709a3 19 #include "pinmap.h"
AnnaBridge 189:f392fc9709a3 20 #include "PortNames.h"
AnnaBridge 189:f392fc9709a3 21 #include "mbed_error.h"
AnnaBridge 189:f392fc9709a3 22
AnnaBridge 189:f392fc9709a3 23 extern uint32_t gpio_clock_enable(uint32_t port_idx);
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 extern const int GD_GPIO_REMAP[];
AnnaBridge 189:f392fc9709a3 26 extern const int GD_GPIO_MODE[];
AnnaBridge 189:f392fc9709a3 27 extern const int GD_GPIO_SPEED[];
AnnaBridge 189:f392fc9709a3 28
AnnaBridge 189:f392fc9709a3 29 static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin);
AnnaBridge 189:f392fc9709a3 30
AnnaBridge 189:f392fc9709a3 31 /** Configure pin (mode, speed, reamp function )
AnnaBridge 189:f392fc9709a3 32 *
AnnaBridge 189:f392fc9709a3 33 * @param pin gpio pin name
AnnaBridge 189:f392fc9709a3 34 * @param function gpio pin mode, speed, remap function
AnnaBridge 189:f392fc9709a3 35 */
AnnaBridge 189:f392fc9709a3 36 void pin_function(PinName pin, int function)
AnnaBridge 189:f392fc9709a3 37 {
AnnaBridge 189:f392fc9709a3 38 MBED_ASSERT(pin != (PinName)NC);
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 uint32_t mode = GD_PIN_MODE_GET(function);
AnnaBridge 189:f392fc9709a3 41 uint32_t remap = GD_PIN_REMAP_GET(function);
AnnaBridge 189:f392fc9709a3 42 uint32_t speed = GD_PIN_SPEED_GET(function);
AnnaBridge 189:f392fc9709a3 43 uint32_t port = GD_PORT_GET(pin);
AnnaBridge 189:f392fc9709a3 44 uint32_t gd_pin = 1 << GD_PIN_GET(pin);
AnnaBridge 189:f392fc9709a3 45
AnnaBridge 189:f392fc9709a3 46 uint32_t gpio = gpio_clock_enable(port);
AnnaBridge 189:f392fc9709a3 47 gpio_para_init(gpio, GD_GPIO_MODE[mode], GD_GPIO_SPEED[speed], gd_pin);
AnnaBridge 189:f392fc9709a3 48
AnnaBridge 189:f392fc9709a3 49 if (remap != 0) {
AnnaBridge 189:f392fc9709a3 50 rcu_periph_clock_enable(RCU_AF);
AnnaBridge 189:f392fc9709a3 51 gpio_pin_remap_config(GD_GPIO_REMAP[remap], ENABLE);
AnnaBridge 189:f392fc9709a3 52 }
AnnaBridge 189:f392fc9709a3 53 }
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /** Only configure pin mode
AnnaBridge 189:f392fc9709a3 56 *
AnnaBridge 189:f392fc9709a3 57 * @param pin gpio pin name
AnnaBridge 189:f392fc9709a3 58 * @param function gpio pin mode
AnnaBridge 189:f392fc9709a3 59 */
AnnaBridge 189:f392fc9709a3 60 void pin_mode(PinName pin, PinMode mode)
AnnaBridge 189:f392fc9709a3 61 {
AnnaBridge 189:f392fc9709a3 62 MBED_ASSERT(pin != (PinName)NC);
AnnaBridge 189:f392fc9709a3 63 uint32_t port = GD_PORT_GET(pin);
AnnaBridge 189:f392fc9709a3 64 uint32_t gd_pin = 1 << GD_PIN_GET(pin);
AnnaBridge 189:f392fc9709a3 65
AnnaBridge 189:f392fc9709a3 66 uint32_t gpio = gpio_clock_enable(port);
AnnaBridge 189:f392fc9709a3 67 if (mode != PullNone) {
AnnaBridge 189:f392fc9709a3 68 gpio_mode_set(gpio, GD_GPIO_MODE[mode], gd_pin);
AnnaBridge 189:f392fc9709a3 69 }
AnnaBridge 189:f392fc9709a3 70 }
AnnaBridge 189:f392fc9709a3 71
AnnaBridge 189:f392fc9709a3 72 /** configure gpio pin mode
AnnaBridge 189:f392fc9709a3 73 *
AnnaBridge 189:f392fc9709a3 74 * @param gpio_periph gpio port name
AnnaBridge 189:f392fc9709a3 75 * @param mode gpio pin mode
AnnaBridge 189:f392fc9709a3 76 * @param pin gpio pin number
AnnaBridge 189:f392fc9709a3 77 */
AnnaBridge 189:f392fc9709a3 78 static void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pin)
AnnaBridge 189:f392fc9709a3 79 {
AnnaBridge 189:f392fc9709a3 80 uint16_t i;
AnnaBridge 189:f392fc9709a3 81 uint32_t temp_mode = 0U;
AnnaBridge 189:f392fc9709a3 82 uint32_t reg = 0U;
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 /* GPIO mode configuration */
AnnaBridge 189:f392fc9709a3 85 temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU));
AnnaBridge 189:f392fc9709a3 86
AnnaBridge 189:f392fc9709a3 87 /* configure the eight low port pins with GPIO_CTL0 */
AnnaBridge 189:f392fc9709a3 88 for (i = 0U; i < 8U; i++) {
AnnaBridge 189:f392fc9709a3 89 if ((1U << i) & pin) {
AnnaBridge 189:f392fc9709a3 90 reg = GPIO_CTL0(gpio_periph);
AnnaBridge 189:f392fc9709a3 91
AnnaBridge 189:f392fc9709a3 92 /* set the specified pin mode bits */
AnnaBridge 189:f392fc9709a3 93 reg |= GPIO_MODE_SET(i, temp_mode);
AnnaBridge 189:f392fc9709a3 94
AnnaBridge 189:f392fc9709a3 95 /* set IPD or IPU */
AnnaBridge 189:f392fc9709a3 96 if (GPIO_MODE_IPD == mode) {
AnnaBridge 189:f392fc9709a3 97 /* reset the corresponding OCTL bit */
AnnaBridge 189:f392fc9709a3 98 GPIO_BC(gpio_periph) = (uint32_t)pin;
AnnaBridge 189:f392fc9709a3 99 } else {
AnnaBridge 189:f392fc9709a3 100 /* set the corresponding OCTL bit */
AnnaBridge 189:f392fc9709a3 101 if (GPIO_MODE_IPU == mode) {
AnnaBridge 189:f392fc9709a3 102 GPIO_BOP(gpio_periph) = (uint32_t)pin;
AnnaBridge 189:f392fc9709a3 103 }
AnnaBridge 189:f392fc9709a3 104 }
AnnaBridge 189:f392fc9709a3 105
AnnaBridge 189:f392fc9709a3 106 /* set GPIO_CTL0 register */
AnnaBridge 189:f392fc9709a3 107 GPIO_CTL0(gpio_periph) = reg;
AnnaBridge 189:f392fc9709a3 108 }
AnnaBridge 189:f392fc9709a3 109 }
AnnaBridge 189:f392fc9709a3 110 /* configure the eight high port pins with GPIO_CTL1 */
AnnaBridge 189:f392fc9709a3 111 for (i = 8U; i < 16U; i++) {
AnnaBridge 189:f392fc9709a3 112 if ((1U << i) & pin) {
AnnaBridge 189:f392fc9709a3 113 reg = GPIO_CTL1(gpio_periph);
AnnaBridge 189:f392fc9709a3 114
AnnaBridge 189:f392fc9709a3 115 /* set the specified pin mode bits */
AnnaBridge 189:f392fc9709a3 116 reg |= GPIO_MODE_SET(i - 8U, temp_mode);
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 /* set IPD or IPU */
AnnaBridge 189:f392fc9709a3 119 if (GPIO_MODE_IPD == mode) {
AnnaBridge 189:f392fc9709a3 120 /* reset the corresponding OCTL bit */
AnnaBridge 189:f392fc9709a3 121 GPIO_BC(gpio_periph) = (uint32_t)pin;
AnnaBridge 189:f392fc9709a3 122 } else {
AnnaBridge 189:f392fc9709a3 123 /* set the corresponding OCTL bit */
AnnaBridge 189:f392fc9709a3 124 if (GPIO_MODE_IPU == mode) {
AnnaBridge 189:f392fc9709a3 125 GPIO_BOP(gpio_periph) = (uint32_t)pin;
AnnaBridge 189:f392fc9709a3 126 }
AnnaBridge 189:f392fc9709a3 127 }
AnnaBridge 189:f392fc9709a3 128
AnnaBridge 189:f392fc9709a3 129 /* set GPIO_CTL1 register */
AnnaBridge 189:f392fc9709a3 130 GPIO_CTL1(gpio_periph) = reg;
AnnaBridge 189:f392fc9709a3 131 }
AnnaBridge 189:f392fc9709a3 132 }
AnnaBridge 189:f392fc9709a3 133 }
AnnaBridge 189:f392fc9709a3 134
AnnaBridge 189:f392fc9709a3 135