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mbed library sources. Supersedes mbed-src.

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targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/system_MKL25Z4.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 ** ###################################################################
<> 144:ef7eb2e8f9f7 3 ** Processor: MKL25Z128VLK4
<> 144:ef7eb2e8f9f7 4 ** Compilers: ARM Compiler
<> 144:ef7eb2e8f9f7 5 ** Freescale C/C++ for Embedded ARM
<> 144:ef7eb2e8f9f7 6 ** GNU C Compiler
<> 144:ef7eb2e8f9f7 7 ** IAR ANSI C/C++ Compiler for ARM
<> 144:ef7eb2e8f9f7 8 **
<> 144:ef7eb2e8f9f7 9 ** Reference manual: KL25RM, Rev.1, Jun 2012
<> 144:ef7eb2e8f9f7 10 ** Version: rev. 1.1, 2012-06-21
<> 144:ef7eb2e8f9f7 11 **
<> 144:ef7eb2e8f9f7 12 ** Abstract:
<> 144:ef7eb2e8f9f7 13 ** Provides a system configuration function and a global variable that
<> 144:ef7eb2e8f9f7 14 ** contains the system frequency. It configures the device and initializes
<> 144:ef7eb2e8f9f7 15 ** the oscillator (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 16 **
<> 144:ef7eb2e8f9f7 17 ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
<> 144:ef7eb2e8f9f7 18 **
<> 144:ef7eb2e8f9f7 19 ** http: www.freescale.com
<> 144:ef7eb2e8f9f7 20 ** mail: support@freescale.com
<> 144:ef7eb2e8f9f7 21 **
<> 144:ef7eb2e8f9f7 22 ** Revisions:
<> 144:ef7eb2e8f9f7 23 ** - rev. 1.0 (2012-06-13)
<> 144:ef7eb2e8f9f7 24 ** Initial version.
<> 144:ef7eb2e8f9f7 25 ** - rev. 1.1 (2012-06-21)
<> 144:ef7eb2e8f9f7 26 ** Update according to reference manual rev. 1.
<> 144:ef7eb2e8f9f7 27 **
<> 144:ef7eb2e8f9f7 28 ** ###################################################################
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 /**
<> 144:ef7eb2e8f9f7 32 * @file MKL25Z4
<> 144:ef7eb2e8f9f7 33 * @version 1.1
<> 144:ef7eb2e8f9f7 34 * @date 2012-06-21
<> 144:ef7eb2e8f9f7 35 * @brief Device specific configuration file for MKL25Z4 (implementation file)
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 * Provides a system configuration function and a global variable that contains
<> 144:ef7eb2e8f9f7 38 * the system frequency. It configures the device and initializes the oscillator
<> 144:ef7eb2e8f9f7 39 * (PLL) that is part of the microcontroller device.
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #include <stdint.h>
<> 144:ef7eb2e8f9f7 43 #include "MKL25Z4.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #define DISABLE_WDOG 1
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #define CLOCK_SETUP 1
<> 144:ef7eb2e8f9f7 48 /* Predefined clock setups
<> 144:ef7eb2e8f9f7 49 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
<> 144:ef7eb2e8f9f7 50 Reference clock source for MCG module is the slow internal clock source 32.768kHz
<> 144:ef7eb2e8f9f7 51 Core clock = 41.94MHz, BusClock = 13.98MHz
<> 144:ef7eb2e8f9f7 52 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
<> 144:ef7eb2e8f9f7 53 Reference clock source for MCG module is an external crystal 8MHz
<> 144:ef7eb2e8f9f7 54 Core clock = 48MHz, BusClock = 24MHz
<> 144:ef7eb2e8f9f7 55 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
<> 144:ef7eb2e8f9f7 56 Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
<> 144:ef7eb2e8f9f7 57 Core clock = 8MHz, BusClock = 8MHz
<> 144:ef7eb2e8f9f7 58 3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
<> 144:ef7eb2e8f9f7 59 Reference clock source for MCG module is an external crystal 32.768kHz
<> 144:ef7eb2e8f9f7 60 Core clock = 47.97MHz, BusClock = 23.98MHz
<> 144:ef7eb2e8f9f7 61 This setup sets the RTC to be driven by the MCU clock directly without the need of an external source.
<> 144:ef7eb2e8f9f7 62 RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time
<> 144:ef7eb2e8f9f7 63 accuracy durring the reset period. RTC will reset on power down.
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 67 Define clock source values
<> 144:ef7eb2e8f9f7 68 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 69 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 70 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 71 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 72 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 73 #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
<> 144:ef7eb2e8f9f7 74 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 75 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 76 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 77 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 78 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
<> 144:ef7eb2e8f9f7 79 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 80 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 81 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 82 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 83 #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
<> 144:ef7eb2e8f9f7 84 #elif (CLOCK_SETUP == 3)
<> 144:ef7eb2e8f9f7 85 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 86 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 87 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
<> 144:ef7eb2e8f9f7 88 #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
<> 144:ef7eb2e8f9f7 89 #endif /* (CLOCK_SETUP == 3) */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 92 -- Core clock
<> 144:ef7eb2e8f9f7 93 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 98 -- SystemInit()
<> 144:ef7eb2e8f9f7 99 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 void SystemInit (void) {
<> 144:ef7eb2e8f9f7 102 #if (DISABLE_WDOG)
<> 144:ef7eb2e8f9f7 103 /* Disable the WDOG module */
<> 144:ef7eb2e8f9f7 104 /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
<> 144:ef7eb2e8f9f7 105 SIM->COPC = (uint32_t)0x00u;
<> 144:ef7eb2e8f9f7 106 #endif /* (DISABLE_WDOG) */
<> 144:ef7eb2e8f9f7 107 #if (CLOCK_SETUP == 0)
<> 144:ef7eb2e8f9f7 108 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 109 SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
<> 144:ef7eb2e8f9f7 110 /* Switch to FEI Mode */
<> 144:ef7eb2e8f9f7 111 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 112 MCG->C1 = (uint8_t)0x06U;
<> 144:ef7eb2e8f9f7 113 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 114 MCG->C2 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 115 /* MCG->C4: DMX32=0,DRST_DRS=1 */
<> 144:ef7eb2e8f9f7 116 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
<> 144:ef7eb2e8f9f7 117 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 118 OSC0->CR = (uint8_t)0x80U;
<> 144:ef7eb2e8f9f7 119 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 120 MCG->C5 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 121 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 122 MCG->C6 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 123 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
<> 144:ef7eb2e8f9f7 126 }
<> 144:ef7eb2e8f9f7 127 #elif (CLOCK_SETUP == 1)
<> 144:ef7eb2e8f9f7 128 /* SIM->SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 129 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
<> 144:ef7eb2e8f9f7 130 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 131 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
<> 144:ef7eb2e8f9f7 132 /* PORTA->PCR18: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 133 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 134 /* PORTA->PCR19: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 135 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 136 /* Switch to FBE Mode */
<> 144:ef7eb2e8f9f7 137 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
<> 144:ef7eb2e8f9f7 138 OSC0->CR = (uint8_t)0x89U;
<> 144:ef7eb2e8f9f7 139 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 140 MCG->C2 = (uint8_t)0x24U;
<> 144:ef7eb2e8f9f7 141 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 142 MCG->C1 = (uint8_t)0x9AU;
<> 144:ef7eb2e8f9f7 143 /* MCG->C4: DMX32=0,DRST_DRS=0 */
<> 144:ef7eb2e8f9f7 144 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
<> 144:ef7eb2e8f9f7 145 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
<> 144:ef7eb2e8f9f7 146 MCG->C5 = (uint8_t)0x01U;
<> 144:ef7eb2e8f9f7 147 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 148 MCG->C6 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 149 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 152 }
<> 144:ef7eb2e8f9f7 153 /* Switch to PBE Mode */
<> 144:ef7eb2e8f9f7 154 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 155 MCG->C6 = (uint8_t)0x40U;
<> 144:ef7eb2e8f9f7 156 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
<> 144:ef7eb2e8f9f7 159 }
<> 144:ef7eb2e8f9f7 160 /* Switch to PEE Mode */
<> 144:ef7eb2e8f9f7 161 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 162 MCG->C1 = (uint8_t)0x1AU;
<> 144:ef7eb2e8f9f7 163 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165 #elif (CLOCK_SETUP == 2)
<> 144:ef7eb2e8f9f7 166 /* SIM->SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 167 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
<> 144:ef7eb2e8f9f7 168 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 169 SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
<> 144:ef7eb2e8f9f7 170 /* PORTA->PCR18: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 171 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 172 /* PORTA->PCR19: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 173 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
<> 144:ef7eb2e8f9f7 174 /* Switch to FBE Mode */
<> 144:ef7eb2e8f9f7 175 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
<> 144:ef7eb2e8f9f7 176 OSC0->CR = (uint8_t)0x89U;
<> 144:ef7eb2e8f9f7 177 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 178 MCG->C2 = (uint8_t)0x24U;
<> 144:ef7eb2e8f9f7 179 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 180 MCG->C1 = (uint8_t)0x9AU;
<> 144:ef7eb2e8f9f7 181 /* MCG->C4: DMX32=0,DRST_DRS=0 */
<> 144:ef7eb2e8f9f7 182 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
<> 144:ef7eb2e8f9f7 183 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
<> 144:ef7eb2e8f9f7 184 MCG->C5 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 185 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
<> 144:ef7eb2e8f9f7 186 MCG->C6 = (uint8_t)0x00U;
<> 144:ef7eb2e8f9f7 187 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191 /* Switch to BLPE Mode */
<> 144:ef7eb2e8f9f7 192 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
<> 144:ef7eb2e8f9f7 193 MCG->C2 = (uint8_t)0x26U;
<> 144:ef7eb2e8f9f7 194 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
<> 144:ef7eb2e8f9f7 195 }
<> 144:ef7eb2e8f9f7 196 #elif (CLOCK_SETUP == 3)
<> 144:ef7eb2e8f9f7 197 /* SIM->SCGC5: PORTA=1 */
<> 144:ef7eb2e8f9f7 198 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
<> 144:ef7eb2e8f9f7 199 /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
<> 144:ef7eb2e8f9f7 200 SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
<> 144:ef7eb2e8f9f7 201 /* PORTA->PCR[3]: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 202 PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 203 /* PORTA->PCR[4]: ISF=0,MUX=0 */
<> 144:ef7eb2e8f9f7 204 PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
<> 144:ef7eb2e8f9f7 205 /* Switch to FEE Mode */
<> 144:ef7eb2e8f9f7 206 /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
<> 144:ef7eb2e8f9f7 207 MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
<> 144:ef7eb2e8f9f7 208 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
<> 144:ef7eb2e8f9f7 209 OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK;
<> 144:ef7eb2e8f9f7 210 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
<> 144:ef7eb2e8f9f7 211 MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
<> 144:ef7eb2e8f9f7 212 /* MCG->C4: DMX32=1,DRST_DRS=1 */
<> 144:ef7eb2e8f9f7 213 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
<> 144:ef7eb2e8f9f7 214 MCG_C4_DRST_DRS(0x02)
<> 144:ef7eb2e8f9f7 215 )) | (uint8_t)(
<> 144:ef7eb2e8f9f7 216 MCG_C4_DMX32_MASK |
<> 144:ef7eb2e8f9f7 217 MCG_C4_DRST_DRS(0x01)
<> 144:ef7eb2e8f9f7 218 ));
<> 144:ef7eb2e8f9f7 219 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223 #endif /* (CLOCK_SETUP == 3) */
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* ----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 227 -- SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 228 ---------------------------------------------------------------------------- */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 void SystemCoreClockUpdate (void) {
<> 144:ef7eb2e8f9f7 231 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
<> 144:ef7eb2e8f9f7 232 uint8_t Divider;
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 235 /* Output of FLL or PLL is selected */
<> 144:ef7eb2e8f9f7 236 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 237 /* FLL is selected */
<> 144:ef7eb2e8f9f7 238 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 239 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 240 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 241 Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
<> 144:ef7eb2e8f9f7 242 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
<> 144:ef7eb2e8f9f7 243 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
<> 144:ef7eb2e8f9f7 244 MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
<> 144:ef7eb2e8f9f7 245 } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
<> 144:ef7eb2e8f9f7 246 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 247 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
<> 144:ef7eb2e8f9f7 248 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 249 /* Select correct multiplier to calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 250 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
<> 144:ef7eb2e8f9f7 251 case 0x0u:
<> 144:ef7eb2e8f9f7 252 MCGOUTClock *= 640u;
<> 144:ef7eb2e8f9f7 253 break;
<> 144:ef7eb2e8f9f7 254 case 0x20u:
<> 144:ef7eb2e8f9f7 255 MCGOUTClock *= 1280u;
<> 144:ef7eb2e8f9f7 256 break;
<> 144:ef7eb2e8f9f7 257 case 0x40u:
<> 144:ef7eb2e8f9f7 258 MCGOUTClock *= 1920u;
<> 144:ef7eb2e8f9f7 259 break;
<> 144:ef7eb2e8f9f7 260 case 0x60u:
<> 144:ef7eb2e8f9f7 261 MCGOUTClock *= 2560u;
<> 144:ef7eb2e8f9f7 262 break;
<> 144:ef7eb2e8f9f7 263 case 0x80u:
<> 144:ef7eb2e8f9f7 264 MCGOUTClock *= 732u;
<> 144:ef7eb2e8f9f7 265 break;
<> 144:ef7eb2e8f9f7 266 case 0xA0u:
<> 144:ef7eb2e8f9f7 267 MCGOUTClock *= 1464u;
<> 144:ef7eb2e8f9f7 268 break;
<> 144:ef7eb2e8f9f7 269 case 0xC0u:
<> 144:ef7eb2e8f9f7 270 MCGOUTClock *= 2197u;
<> 144:ef7eb2e8f9f7 271 break;
<> 144:ef7eb2e8f9f7 272 case 0xE0u:
<> 144:ef7eb2e8f9f7 273 MCGOUTClock *= 2929u;
<> 144:ef7eb2e8f9f7 274 break;
<> 144:ef7eb2e8f9f7 275 default:
<> 144:ef7eb2e8f9f7 276 break;
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 279 /* PLL is selected */
<> 144:ef7eb2e8f9f7 280 Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
<> 144:ef7eb2e8f9f7 281 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
<> 144:ef7eb2e8f9f7 282 Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
<> 144:ef7eb2e8f9f7 283 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
<> 144:ef7eb2e8f9f7 284 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 285 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
<> 144:ef7eb2e8f9f7 286 /* Internal reference clock is selected */
<> 144:ef7eb2e8f9f7 287 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
<> 144:ef7eb2e8f9f7 288 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
<> 144:ef7eb2e8f9f7 289 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 290 MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
<> 144:ef7eb2e8f9f7 291 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
<> 144:ef7eb2e8f9f7 292 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
<> 144:ef7eb2e8f9f7 293 /* External reference clock is selected */
<> 144:ef7eb2e8f9f7 294 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
<> 144:ef7eb2e8f9f7 295 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 296 /* Reserved value */
<> 144:ef7eb2e8f9f7 297 return;
<> 144:ef7eb2e8f9f7 298 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
<> 144:ef7eb2e8f9f7 299 SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
<> 144:ef7eb2e8f9f7 300 }