mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/analogin_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /*
AnnaBridge 189:f392fc9709a3 2 * mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 3 * Copyright (c) 2017-2018 Future Electronics
AnnaBridge 189:f392fc9709a3 4 *
AnnaBridge 189:f392fc9709a3 5 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 6 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 7 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 12 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 14 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 15 * limitations under the License.
AnnaBridge 189:f392fc9709a3 16 */
AnnaBridge 189:f392fc9709a3 17
AnnaBridge 189:f392fc9709a3 18 #include "device.h"
AnnaBridge 189:f392fc9709a3 19 #include "analogin_api.h"
AnnaBridge 189:f392fc9709a3 20 #include "cy_sar.h"
AnnaBridge 189:f392fc9709a3 21 #include "psoc6_utils.h"
AnnaBridge 189:f392fc9709a3 22 #include "mbed_assert.h"
AnnaBridge 189:f392fc9709a3 23 #include "mbed_error.h"
AnnaBridge 189:f392fc9709a3 24 #include "pinmap.h"
AnnaBridge 189:f392fc9709a3 25 #include "PeripheralPins.h"
AnnaBridge 189:f392fc9709a3 26 #include "platform/mbed_error.h"
AnnaBridge 189:f392fc9709a3 27
AnnaBridge 189:f392fc9709a3 28 #if DEVICE_ANALOGIN
AnnaBridge 189:f392fc9709a3 29
AnnaBridge 189:f392fc9709a3 30 const uint16_t ADC_MAX_VALUE = 0x0fff;
AnnaBridge 189:f392fc9709a3 31
AnnaBridge 189:f392fc9709a3 32 const uint32_t SAR_BASE_CLOCK_HZ = 18000000; // 18 MHz or less
AnnaBridge 189:f392fc9709a3 33
AnnaBridge 189:f392fc9709a3 34 /** Default SAR channel configuration.
AnnaBridge 189:f392fc9709a3 35 * Notice, that because dynamic SAR MUX switching is disabled,
AnnaBridge 189:f392fc9709a3 36 * per-channel MUX configuration is ignored, thus not configured here.
AnnaBridge 189:f392fc9709a3 37 */
AnnaBridge 189:f392fc9709a3 38 #define DEFAULT_CHANNEL_CONFIG ( \
AnnaBridge 189:f392fc9709a3 39 CY_SAR_CHAN_SINGLE_ENDED | \
AnnaBridge 189:f392fc9709a3 40 CY_SAR_CHAN_AVG_ENABLE | \
AnnaBridge 189:f392fc9709a3 41 CY_SAR_CHAN_SAMPLE_TIME_0 \
AnnaBridge 189:f392fc9709a3 42 )
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44
AnnaBridge 189:f392fc9709a3 45 /** Global SAR configuration data, modified as channels are configured.
AnnaBridge 189:f392fc9709a3 46 */
AnnaBridge 189:f392fc9709a3 47 static cy_stc_sar_config_t sar_config = {
AnnaBridge 189:f392fc9709a3 48 .ctrl = CY_SAR_VREF_SEL_VDDA_DIV_2 |
AnnaBridge 189:f392fc9709a3 49 CY_SAR_NEG_SEL_VREF |
AnnaBridge 189:f392fc9709a3 50 CY_SAR_CTRL_COMP_DLY_12 |
AnnaBridge 189:f392fc9709a3 51 CY_SAR_COMP_PWR_50 |
AnnaBridge 189:f392fc9709a3 52 CY_SAR_SARSEQ_SWITCH_DISABLE, /**< Control register */
AnnaBridge 189:f392fc9709a3 53 .sampleCtrl = CY_SAR_RIGHT_ALIGN |
AnnaBridge 189:f392fc9709a3 54 CY_SAR_SINGLE_ENDED_UNSIGNED |
AnnaBridge 189:f392fc9709a3 55 CY_SAR_AVG_CNT_16 |
AnnaBridge 189:f392fc9709a3 56 CY_SAR_AVG_MODE_SEQUENTIAL_FIXED |
AnnaBridge 189:f392fc9709a3 57 CY_SAR_TRIGGER_MODE_FW_ONLY, /**< Sample control register */
AnnaBridge 189:f392fc9709a3 58 .sampleTime01 = (4uL << CY_SAR_SAMPLE_TIME0_SHIFT) |
AnnaBridge 189:f392fc9709a3 59 (4uL << CY_SAR_SAMPLE_TIME1_SHIFT), /**< Sample time in ADC clocks for ST0 and ST1 */
AnnaBridge 189:f392fc9709a3 60 .sampleTime23 = (4uL << CY_SAR_SAMPLE_TIME2_SHIFT) |
AnnaBridge 189:f392fc9709a3 61 (4uL << CY_SAR_SAMPLE_TIME3_SHIFT), /**< Sample time in ADC clocks for ST2 and ST3 */
AnnaBridge 189:f392fc9709a3 62 .rangeThres = 0, /**< Range detect threshold register for all channels (unused)*/
AnnaBridge 189:f392fc9709a3 63 .rangeCond = 0, /**< Range detect mode for all channels (unused)*/
AnnaBridge 189:f392fc9709a3 64 .chanEn = 0, /**< Enable bits for the channels */
AnnaBridge 189:f392fc9709a3 65 .chanConfig = { /**< Channel configuration registers */
AnnaBridge 189:f392fc9709a3 66 DEFAULT_CHANNEL_CONFIG, // chn 0
AnnaBridge 189:f392fc9709a3 67 DEFAULT_CHANNEL_CONFIG, // chn 1
AnnaBridge 189:f392fc9709a3 68 DEFAULT_CHANNEL_CONFIG, // chn 2
AnnaBridge 189:f392fc9709a3 69 DEFAULT_CHANNEL_CONFIG, // chn 3
AnnaBridge 189:f392fc9709a3 70 DEFAULT_CHANNEL_CONFIG, // chn 4
AnnaBridge 189:f392fc9709a3 71 DEFAULT_CHANNEL_CONFIG, // chn 5
AnnaBridge 189:f392fc9709a3 72 DEFAULT_CHANNEL_CONFIG, // chn 6
AnnaBridge 189:f392fc9709a3 73 DEFAULT_CHANNEL_CONFIG, // chn 7
AnnaBridge 189:f392fc9709a3 74 DEFAULT_CHANNEL_CONFIG, // chn 8
AnnaBridge 189:f392fc9709a3 75 DEFAULT_CHANNEL_CONFIG, // chn 9
AnnaBridge 189:f392fc9709a3 76 DEFAULT_CHANNEL_CONFIG, // chn 10
AnnaBridge 189:f392fc9709a3 77 DEFAULT_CHANNEL_CONFIG, // chn 11
AnnaBridge 189:f392fc9709a3 78 DEFAULT_CHANNEL_CONFIG, // chn 12
AnnaBridge 189:f392fc9709a3 79 DEFAULT_CHANNEL_CONFIG, // chn 13
AnnaBridge 189:f392fc9709a3 80 DEFAULT_CHANNEL_CONFIG, // chn 14
AnnaBridge 189:f392fc9709a3 81 DEFAULT_CHANNEL_CONFIG, // chn 15
AnnaBridge 189:f392fc9709a3 82 },
AnnaBridge 189:f392fc9709a3 83 .intrMask = 0, /**< Interrupt enable mask */
AnnaBridge 189:f392fc9709a3 84 .satIntrMask = 0, /**< Saturate interrupt mask register */
AnnaBridge 189:f392fc9709a3 85 .rangeIntrMask = 0, /**< Range interrupt mask register */
AnnaBridge 189:f392fc9709a3 86 .muxSwitch = 0, /**< SARMUX firmware switches to connect analog signals to SAR */
AnnaBridge 189:f392fc9709a3 87 .muxSwitchSqCtrl = 0, /**< SARMUX Switch SAR sequencer control */
AnnaBridge 189:f392fc9709a3 88 .configRouting = false, /**< Configure or ignore routing related registers (muxSwitch, muxSwitchSqCtrl) */
AnnaBridge 189:f392fc9709a3 89 .vrefMvValue = 0, /**< Reference voltage in millivolts used in counts to volts conversion */
AnnaBridge 189:f392fc9709a3 90 };
AnnaBridge 189:f392fc9709a3 91
AnnaBridge 189:f392fc9709a3 92 static bool sar_initialized = false;
AnnaBridge 189:f392fc9709a3 93
AnnaBridge 189:f392fc9709a3 94
AnnaBridge 189:f392fc9709a3 95 static void sar_init(analogin_t *obj)
AnnaBridge 189:f392fc9709a3 96 {
AnnaBridge 189:f392fc9709a3 97 if (!sar_initialized) {
AnnaBridge 189:f392fc9709a3 98 uint32_t sar_clock_divider = CY_INVALID_DIVIDER;
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 sar_initialized = true;
AnnaBridge 189:f392fc9709a3 101 // Allocate and setup clock.
AnnaBridge 189:f392fc9709a3 102 sar_clock_divider = cy_clk_allocate_divider(CY_SYSCLK_DIV_8_BIT);
AnnaBridge 189:f392fc9709a3 103 if (sar_clock_divider == CY_INVALID_DIVIDER) {
AnnaBridge 189:f392fc9709a3 104 error("SAR clock divider allocation failed.");
AnnaBridge 189:f392fc9709a3 105 return;
AnnaBridge 189:f392fc9709a3 106 }
AnnaBridge 189:f392fc9709a3 107 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT,
AnnaBridge 189:f392fc9709a3 108 sar_clock_divider,
AnnaBridge 189:f392fc9709a3 109 ((CY_CLK_PERICLK_FREQ_HZ + SAR_BASE_CLOCK_HZ / 2) / SAR_BASE_CLOCK_HZ) - 1);
AnnaBridge 189:f392fc9709a3 110 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
AnnaBridge 189:f392fc9709a3 111 Cy_SysClk_PeriphAssignDivider(obj->clock, CY_SYSCLK_DIV_8_BIT, sar_clock_divider);
AnnaBridge 189:f392fc9709a3 112
AnnaBridge 189:f392fc9709a3 113 Cy_SAR_Init(obj->base, &sar_config);
AnnaBridge 189:f392fc9709a3 114 Cy_SAR_Enable(obj->base);
AnnaBridge 189:f392fc9709a3 115 }
AnnaBridge 189:f392fc9709a3 116 }
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 void analogin_init(analogin_t *obj, PinName pin)
AnnaBridge 189:f392fc9709a3 119 {
AnnaBridge 189:f392fc9709a3 120 uint32_t sar = 0;
AnnaBridge 189:f392fc9709a3 121 uint32_t sar_function = 0;
AnnaBridge 189:f392fc9709a3 122
AnnaBridge 189:f392fc9709a3 123 MBED_ASSERT(obj);
AnnaBridge 189:f392fc9709a3 124 MBED_ASSERT(pin != (PinName)NC);
AnnaBridge 189:f392fc9709a3 125
AnnaBridge 189:f392fc9709a3 126
AnnaBridge 189:f392fc9709a3 127 sar = pinmap_peripheral(pin, PinMap_ADC);
AnnaBridge 189:f392fc9709a3 128 if (sar != (uint32_t)NC) {
AnnaBridge 189:f392fc9709a3 129 if (cy_reserve_io_pin(pin)) {
AnnaBridge 189:f392fc9709a3 130 error("ANALOG IN pin reservation conflict.");
AnnaBridge 189:f392fc9709a3 131 }
AnnaBridge 189:f392fc9709a3 132 obj->base = (SAR_Type*)CY_PERIPHERAL_BASE(sar);
AnnaBridge 189:f392fc9709a3 133 obj->pin = pin;
AnnaBridge 189:f392fc9709a3 134 obj->channel_mask = 1 << CY_PIN(pin);
AnnaBridge 189:f392fc9709a3 135
AnnaBridge 189:f392fc9709a3 136 // Configure clock.
AnnaBridge 189:f392fc9709a3 137 sar_function = pinmap_function(pin, PinMap_ADC);
AnnaBridge 189:f392fc9709a3 138 obj->clock = CY_PIN_CLOCK(sar_function);
AnnaBridge 189:f392fc9709a3 139 sar_init(obj);
AnnaBridge 189:f392fc9709a3 140 pin_function(pin, sar_function);
AnnaBridge 189:f392fc9709a3 141 } else {
AnnaBridge 189:f392fc9709a3 142 error("ANALOG IN pinout mismatch.");
AnnaBridge 189:f392fc9709a3 143 }
AnnaBridge 189:f392fc9709a3 144 }
AnnaBridge 189:f392fc9709a3 145
AnnaBridge 189:f392fc9709a3 146 float analogin_read(analogin_t *obj)
AnnaBridge 189:f392fc9709a3 147 {
AnnaBridge 189:f392fc9709a3 148 uint16_t result = analogin_read_u16(obj);
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 return (float)result * (1.0 / ADC_MAX_VALUE);
AnnaBridge 189:f392fc9709a3 151 }
AnnaBridge 189:f392fc9709a3 152
AnnaBridge 189:f392fc9709a3 153 uint16_t analogin_read_u16(analogin_t *obj)
AnnaBridge 189:f392fc9709a3 154 {
AnnaBridge 189:f392fc9709a3 155 uint32_t result = 0;
AnnaBridge 189:f392fc9709a3 156
AnnaBridge 189:f392fc9709a3 157 Cy_SAR_SetChanMask(obj->base, obj->channel_mask);
AnnaBridge 189:f392fc9709a3 158 Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_CLOSE);
AnnaBridge 189:f392fc9709a3 159 Cy_SAR_StartConvert(obj->base, CY_SAR_START_CONVERT_SINGLE_SHOT);
AnnaBridge 189:f392fc9709a3 160 if (Cy_SAR_IsEndConversion(obj->base, CY_SAR_WAIT_FOR_RESULT) == CY_SAR_SUCCESS) {
AnnaBridge 189:f392fc9709a3 161 result = Cy_SAR_GetResult32(obj->base, CY_PIN(obj->pin));
AnnaBridge 189:f392fc9709a3 162 } else {
AnnaBridge 189:f392fc9709a3 163 error("ANALOG IN: measurement failed!");
AnnaBridge 189:f392fc9709a3 164 }
AnnaBridge 189:f392fc9709a3 165 Cy_SAR_SetAnalogSwitch(obj->base, CY_SAR_MUX_SWITCH0, obj->channel_mask, CY_SAR_SWITCH_OPEN);
AnnaBridge 189:f392fc9709a3 166 // We are running 16x oversampling extending results to 16 bits.
AnnaBridge 189:f392fc9709a3 167 return (uint16_t)(result);
AnnaBridge 189:f392fc9709a3 168 }
AnnaBridge 189:f392fc9709a3 169
AnnaBridge 189:f392fc9709a3 170 #endif // DEVICE_ANALOGIN
AnnaBridge 189:f392fc9709a3 171