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mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 2 | * File Name: cycfg_pins.h |
| AnnaBridge | 189:f392fc9709a3 | 3 | * |
| AnnaBridge | 189:f392fc9709a3 | 4 | * Description: |
| AnnaBridge | 189:f392fc9709a3 | 5 | * Pin configuration |
| AnnaBridge | 189:f392fc9709a3 | 6 | * This file was automatically generated and should not be modified. |
| AnnaBridge | 189:f392fc9709a3 | 7 | * |
| AnnaBridge | 189:f392fc9709a3 | 8 | ******************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 9 | * Copyright 2017-2019 Cypress Semiconductor Corporation |
| AnnaBridge | 189:f392fc9709a3 | 10 | * SPDX-License-Identifier: Apache-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| AnnaBridge | 189:f392fc9709a3 | 13 | * you may not use this file except in compliance with the License. |
| AnnaBridge | 189:f392fc9709a3 | 14 | * You may obtain a copy of the License at |
| AnnaBridge | 189:f392fc9709a3 | 15 | * |
| AnnaBridge | 189:f392fc9709a3 | 16 | * http://www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 17 | * |
| AnnaBridge | 189:f392fc9709a3 | 18 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 189:f392fc9709a3 | 19 | * distributed under the License is distributed on an "AS IS" BASIS, |
| AnnaBridge | 189:f392fc9709a3 | 20 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * See the License for the specific language governing permissions and |
| AnnaBridge | 189:f392fc9709a3 | 22 | * limitations under the License. |
| AnnaBridge | 189:f392fc9709a3 | 23 | ********************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 24 | |
| AnnaBridge | 189:f392fc9709a3 | 25 | #if !defined(CYCFG_PINS_H) |
| AnnaBridge | 189:f392fc9709a3 | 26 | #define CYCFG_PINS_H |
| AnnaBridge | 189:f392fc9709a3 | 27 | |
| AnnaBridge | 189:f392fc9709a3 | 28 | #include "cycfg_notices.h" |
| AnnaBridge | 189:f392fc9709a3 | 29 | #include "cy_gpio.h" |
| AnnaBridge | 189:f392fc9709a3 | 30 | #include "cycfg_connectivity.h" |
| AnnaBridge | 189:f392fc9709a3 | 31 | |
| AnnaBridge | 189:f392fc9709a3 | 32 | #if defined(__cplusplus) |
| AnnaBridge | 189:f392fc9709a3 | 33 | extern "C" { |
| AnnaBridge | 189:f392fc9709a3 | 34 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | #define WCO_IN_PORT GPIO_PRT0 |
| AnnaBridge | 189:f392fc9709a3 | 37 | #define WCO_IN_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define WCO_IN_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 39 | #define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 40 | #define WCO_IN_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 41 | #ifndef ioss_0_port_0_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 42 | #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 43 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 44 | #define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 45 | #define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 46 | #define WCO_OUT_PORT GPIO_PRT0 |
| AnnaBridge | 189:f392fc9709a3 | 47 | #define WCO_OUT_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 48 | #define WCO_OUT_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 49 | #define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 50 | #define WCO_OUT_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 51 | #ifndef ioss_0_port_0_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 52 | #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 53 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 54 | #define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 55 | #define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 56 | #define LED_RED_PORT GPIO_PRT0 |
| AnnaBridge | 189:f392fc9709a3 | 57 | #define LED_RED_PIN 3U |
| AnnaBridge | 189:f392fc9709a3 | 58 | #define LED_RED_NUM 3U |
| AnnaBridge | 189:f392fc9709a3 | 59 | #define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 60 | #define LED_RED_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 61 | #ifndef ioss_0_port_0_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 62 | #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 63 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 64 | #define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 65 | #define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 66 | #define SW2_PORT GPIO_PRT0 |
| AnnaBridge | 189:f392fc9709a3 | 67 | #define SW2_PIN 4U |
| AnnaBridge | 189:f392fc9709a3 | 68 | #define SW2_NUM 4U |
| AnnaBridge | 189:f392fc9709a3 | 69 | #define SW2_DRIVEMODE CY_GPIO_DM_PULLUP |
| AnnaBridge | 189:f392fc9709a3 | 70 | #define SW2_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 71 | #ifndef ioss_0_port_0_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 72 | #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 73 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 74 | #define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 75 | #define SW2_IRQ ioss_interrupts_gpio_0_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 76 | #define LED_BLUE_PORT GPIO_PRT11 |
| AnnaBridge | 189:f392fc9709a3 | 77 | #define LED_BLUE_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 78 | #define LED_BLUE_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 79 | #define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 80 | #define LED_BLUE_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 81 | #ifndef ioss_0_port_11_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 82 | #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 83 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 84 | #define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 85 | #define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 86 | #define QSPI_SS0_PORT GPIO_PRT11 |
| AnnaBridge | 189:f392fc9709a3 | 87 | #define QSPI_SS0_PIN 2U |
| AnnaBridge | 189:f392fc9709a3 | 88 | #define QSPI_SS0_NUM 2U |
| AnnaBridge | 189:f392fc9709a3 | 89 | #define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 90 | #define QSPI_SS0_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 91 | #ifndef ioss_0_port_11_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 92 | #define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 93 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 94 | #define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 95 | #define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 96 | #define QSPI_DATA3_PORT GPIO_PRT11 |
| AnnaBridge | 189:f392fc9709a3 | 97 | #define QSPI_DATA3_PIN 3U |
| AnnaBridge | 189:f392fc9709a3 | 98 | #define QSPI_DATA3_NUM 3U |
| AnnaBridge | 189:f392fc9709a3 | 99 | #define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 100 | #define QSPI_DATA3_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 101 | #ifndef ioss_0_port_11_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 102 | #define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 103 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 105 | #define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 106 | #define QSPI_DATA2_PORT GPIO_PRT11 |
| AnnaBridge | 189:f392fc9709a3 | 107 | #define QSPI_DATA2_PIN 4U |
| AnnaBridge | 189:f392fc9709a3 | 108 | #define QSPI_DATA2_NUM 4U |
| AnnaBridge | 189:f392fc9709a3 | 109 | #define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 110 | #define QSPI_DATA2_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 111 | #ifndef ioss_0_port_11_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 112 | #define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 113 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 115 | #define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 116 | #define QSPI_DATA1_PORT GPIO_PRT11 |
| AnnaBridge | 189:f392fc9709a3 | 117 | #define QSPI_DATA1_PIN 5U |
| AnnaBridge | 189:f392fc9709a3 | 118 | #define QSPI_DATA1_NUM 5U |
| AnnaBridge | 189:f392fc9709a3 | 119 | #define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 120 | #define QSPI_DATA1_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 121 | #ifndef ioss_0_port_11_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 122 | #define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 123 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 125 | #define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 126 | #define QSPI_DATA0_PORT GPIO_PRT11 |
| AnnaBridge | 189:f392fc9709a3 | 127 | #define QSPI_DATA0_PIN 6U |
| AnnaBridge | 189:f392fc9709a3 | 128 | #define QSPI_DATA0_NUM 6U |
| AnnaBridge | 189:f392fc9709a3 | 129 | #define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 130 | #define QSPI_DATA0_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 131 | #ifndef ioss_0_port_11_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 132 | #define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 133 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 134 | #define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 135 | #define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 136 | #define QSPI_SPI_CLOCK_PORT GPIO_PRT11 |
| AnnaBridge | 189:f392fc9709a3 | 137 | #define QSPI_SPI_CLOCK_PIN 7U |
| AnnaBridge | 189:f392fc9709a3 | 138 | #define QSPI_SPI_CLOCK_NUM 7U |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 141 | #ifndef ioss_0_port_11_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 143 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 144 | #define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 146 | #define LED9_PORT GPIO_PRT13 |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define LED9_PIN 7U |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define LED9_NUM 7U |
| AnnaBridge | 189:f392fc9709a3 | 149 | #define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 150 | #define LED9_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 151 | #ifndef ioss_0_port_13_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 152 | #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 153 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 155 | #define LED9_IRQ ioss_interrupts_gpio_13_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 156 | #define ioss_0_port_14_pin_0_PORT GPIO_PRT14 |
| AnnaBridge | 189:f392fc9709a3 | 157 | #define ioss_0_port_14_pin_0_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 158 | #define ioss_0_port_14_pin_0_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 159 | #define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 160 | #define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 161 | #ifndef ioss_0_port_14_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 162 | #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 163 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 164 | #define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 165 | #define ioss_0_port_14_pin_1_PORT GPIO_PRT14 |
| AnnaBridge | 189:f392fc9709a3 | 166 | #define ioss_0_port_14_pin_1_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 167 | #define ioss_0_port_14_pin_1_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 168 | #define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 169 | #define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 170 | #ifndef ioss_0_port_14_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 171 | #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 172 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 173 | #define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 174 | #define CSD_TX_PORT GPIO_PRT1 |
| AnnaBridge | 189:f392fc9709a3 | 175 | #define CSD_TX_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 176 | #define CSD_TX_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 177 | #define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 178 | #define CSD_TX_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 179 | #ifndef ioss_0_port_1_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 180 | #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 181 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 182 | #define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 183 | #define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 184 | #define LED_GREEN_PORT GPIO_PRT1 |
| AnnaBridge | 189:f392fc9709a3 | 185 | #define LED_GREEN_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 186 | #define LED_GREEN_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 187 | #define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 188 | #define LED_GREEN_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 189 | #ifndef ioss_0_port_1_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 190 | #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 191 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 192 | #define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 193 | #define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 194 | #define LED8_PORT GPIO_PRT1 |
| AnnaBridge | 189:f392fc9709a3 | 195 | #define LED8_PIN 5U |
| AnnaBridge | 189:f392fc9709a3 | 196 | #define LED8_NUM 5U |
| AnnaBridge | 189:f392fc9709a3 | 197 | #define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 198 | #define LED8_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 199 | #ifndef ioss_0_port_1_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 200 | #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 201 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 202 | #define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 203 | #define LED8_IRQ ioss_interrupts_gpio_1_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 204 | #define SDHC0_DAT0_PORT GPIO_PRT2 |
| AnnaBridge | 189:f392fc9709a3 | 205 | #define SDHC0_DAT0_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 206 | #define SDHC0_DAT0_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 207 | #define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 208 | #define SDHC0_DAT0_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 209 | #ifndef ioss_0_port_2_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 210 | #define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 211 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 212 | #define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 213 | #define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 214 | #define SDHC0_DAT1_PORT GPIO_PRT2 |
| AnnaBridge | 189:f392fc9709a3 | 215 | #define SDHC0_DAT1_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 216 | #define SDHC0_DAT1_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 217 | #define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 218 | #define SDHC0_DAT1_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 219 | #ifndef ioss_0_port_2_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 220 | #define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 221 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 222 | #define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 223 | #define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 224 | #define SDHC0_DAT2_PORT GPIO_PRT2 |
| AnnaBridge | 189:f392fc9709a3 | 225 | #define SDHC0_DAT2_PIN 2U |
| AnnaBridge | 189:f392fc9709a3 | 226 | #define SDHC0_DAT2_NUM 2U |
| AnnaBridge | 189:f392fc9709a3 | 227 | #define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 228 | #define SDHC0_DAT2_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 229 | #ifndef ioss_0_port_2_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 230 | #define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 231 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 232 | #define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 233 | #define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 234 | #define SDHC0_DAT3_PORT GPIO_PRT2 |
| AnnaBridge | 189:f392fc9709a3 | 235 | #define SDHC0_DAT3_PIN 3U |
| AnnaBridge | 189:f392fc9709a3 | 236 | #define SDHC0_DAT3_NUM 3U |
| AnnaBridge | 189:f392fc9709a3 | 237 | #define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 238 | #define SDHC0_DAT3_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 239 | #ifndef ioss_0_port_2_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 240 | #define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 241 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 242 | #define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 243 | #define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 244 | #define SDHC0_CMD_PORT GPIO_PRT2 |
| AnnaBridge | 189:f392fc9709a3 | 245 | #define SDHC0_CMD_PIN 4U |
| AnnaBridge | 189:f392fc9709a3 | 246 | #define SDHC0_CMD_NUM 4U |
| AnnaBridge | 189:f392fc9709a3 | 247 | #define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG |
| AnnaBridge | 189:f392fc9709a3 | 248 | #define SDHC0_CMD_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 249 | #ifndef ioss_0_port_2_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 250 | #define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 251 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 252 | #define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 253 | #define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 254 | #define SDHC0_CLK_PORT GPIO_PRT2 |
| AnnaBridge | 189:f392fc9709a3 | 255 | #define SDHC0_CLK_PIN 5U |
| AnnaBridge | 189:f392fc9709a3 | 256 | #define SDHC0_CLK_NUM 5U |
| AnnaBridge | 189:f392fc9709a3 | 257 | #define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 258 | #define SDHC0_CLK_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 259 | #ifndef ioss_0_port_2_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 260 | #define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 261 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 262 | #define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 263 | #define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 264 | #define ENABLE_WIFI_PORT GPIO_PRT2 |
| AnnaBridge | 189:f392fc9709a3 | 265 | #define ENABLE_WIFI_PIN 6U |
| AnnaBridge | 189:f392fc9709a3 | 266 | #define ENABLE_WIFI_NUM 6U |
| AnnaBridge | 189:f392fc9709a3 | 267 | #define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 268 | #define ENABLE_WIFI_INIT_DRIVESTATE 0 |
| AnnaBridge | 189:f392fc9709a3 | 269 | #ifndef ioss_0_port_2_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 270 | #define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 271 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 272 | #define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 273 | #define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 274 | #define BT_UART_RX_PORT GPIO_PRT3 |
| AnnaBridge | 189:f392fc9709a3 | 275 | #define BT_UART_RX_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 276 | #define BT_UART_RX_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 277 | #define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ |
| AnnaBridge | 189:f392fc9709a3 | 278 | #define BT_UART_RX_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 279 | #ifndef ioss_0_port_3_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 280 | #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 281 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 282 | #define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 283 | #define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 284 | #define BT_UART_TX_PORT GPIO_PRT3 |
| AnnaBridge | 189:f392fc9709a3 | 285 | #define BT_UART_TX_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 286 | #define BT_UART_TX_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 287 | #define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 288 | #define BT_UART_TX_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 289 | #ifndef ioss_0_port_3_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 290 | #define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 291 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 292 | #define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 293 | #define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 294 | #define BT_UART_RTS_PORT GPIO_PRT3 |
| AnnaBridge | 189:f392fc9709a3 | 295 | #define BT_UART_RTS_PIN 2U |
| AnnaBridge | 189:f392fc9709a3 | 296 | #define BT_UART_RTS_NUM 2U |
| AnnaBridge | 189:f392fc9709a3 | 297 | #define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 298 | #define BT_UART_RTS_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 299 | #ifndef ioss_0_port_3_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 300 | #define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 301 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 302 | #define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 303 | #define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 304 | #define BT_UART_CTS_PORT GPIO_PRT3 |
| AnnaBridge | 189:f392fc9709a3 | 305 | #define BT_UART_CTS_PIN 3U |
| AnnaBridge | 189:f392fc9709a3 | 306 | #define BT_UART_CTS_NUM 3U |
| AnnaBridge | 189:f392fc9709a3 | 307 | #define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ |
| AnnaBridge | 189:f392fc9709a3 | 308 | #define BT_UART_CTS_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 309 | #ifndef ioss_0_port_3_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 310 | #define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 311 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 312 | #define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 313 | #define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 314 | #define BT_POWER_PORT GPIO_PRT3 |
| AnnaBridge | 189:f392fc9709a3 | 315 | #define BT_POWER_PIN 4U |
| AnnaBridge | 189:f392fc9709a3 | 316 | #define BT_POWER_NUM 4U |
| AnnaBridge | 189:f392fc9709a3 | 317 | #define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 318 | #define BT_POWER_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 319 | #ifndef ioss_0_port_3_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 320 | #define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 321 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 322 | #define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 323 | #define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 324 | #define BT_HOST_WAKE_PORT GPIO_PRT3 |
| AnnaBridge | 189:f392fc9709a3 | 325 | #define BT_HOST_WAKE_PIN 5U |
| AnnaBridge | 189:f392fc9709a3 | 326 | #define BT_HOST_WAKE_NUM 5U |
| AnnaBridge | 189:f392fc9709a3 | 327 | #define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 328 | #define BT_HOST_WAKE_INIT_DRIVESTATE 0 |
| AnnaBridge | 189:f392fc9709a3 | 329 | #ifndef ioss_0_port_3_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 330 | #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 331 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 332 | #define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 333 | #define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 334 | #define BT_DEVICE_WAKE_PORT GPIO_PRT4 |
| AnnaBridge | 189:f392fc9709a3 | 335 | #define BT_DEVICE_WAKE_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 336 | #define BT_DEVICE_WAKE_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 337 | #define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 338 | #define BT_DEVICE_WAKE_INIT_DRIVESTATE 0 |
| AnnaBridge | 189:f392fc9709a3 | 339 | #ifndef ioss_0_port_4_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 340 | #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 341 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 342 | #define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 343 | #define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 344 | #define UART_RX_PORT GPIO_PRT5 |
| AnnaBridge | 189:f392fc9709a3 | 345 | #define UART_RX_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 346 | #define UART_RX_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 347 | #define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ |
| AnnaBridge | 189:f392fc9709a3 | 348 | #define UART_RX_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 349 | #ifndef ioss_0_port_5_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 350 | #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 351 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 352 | #define UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 353 | #define UART_RX_IRQ ioss_interrupts_gpio_5_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 354 | #define UART_TX_PORT GPIO_PRT5 |
| AnnaBridge | 189:f392fc9709a3 | 355 | #define UART_TX_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 356 | #define UART_TX_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 357 | #define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 358 | #define UART_TX_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 359 | #ifndef ioss_0_port_5_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 360 | #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 361 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 362 | #define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 363 | #define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 364 | #define EZI2C_SCL_PORT GPIO_PRT6 |
| AnnaBridge | 189:f392fc9709a3 | 365 | #define EZI2C_SCL_PIN 0U |
| AnnaBridge | 189:f392fc9709a3 | 366 | #define EZI2C_SCL_NUM 0U |
| AnnaBridge | 189:f392fc9709a3 | 367 | #define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW |
| AnnaBridge | 189:f392fc9709a3 | 368 | #define EZI2C_SCL_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 369 | #ifndef ioss_0_port_6_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 370 | #define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 371 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 372 | #define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 373 | #define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 374 | #define EZI2C_SDA_PORT GPIO_PRT6 |
| AnnaBridge | 189:f392fc9709a3 | 375 | #define EZI2C_SDA_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 376 | #define EZI2C_SDA_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 377 | #define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW |
| AnnaBridge | 189:f392fc9709a3 | 378 | #define EZI2C_SDA_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 379 | #ifndef ioss_0_port_6_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 380 | #define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 381 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 382 | #define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 383 | #define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 384 | #define SWO_PORT GPIO_PRT6 |
| AnnaBridge | 189:f392fc9709a3 | 385 | #define SWO_PIN 4U |
| AnnaBridge | 189:f392fc9709a3 | 386 | #define SWO_NUM 4U |
| AnnaBridge | 189:f392fc9709a3 | 387 | #define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF |
| AnnaBridge | 189:f392fc9709a3 | 388 | #define SWO_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 389 | #ifndef ioss_0_port_6_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 390 | #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 391 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 392 | #define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 393 | #define SWO_IRQ ioss_interrupts_gpio_6_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 394 | #define SWDIO_PORT GPIO_PRT6 |
| AnnaBridge | 189:f392fc9709a3 | 395 | #define SWDIO_PIN 6U |
| AnnaBridge | 189:f392fc9709a3 | 396 | #define SWDIO_NUM 6U |
| AnnaBridge | 189:f392fc9709a3 | 397 | #define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP |
| AnnaBridge | 189:f392fc9709a3 | 398 | #define SWDIO_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 399 | #ifndef ioss_0_port_6_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 400 | #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 401 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 402 | #define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 403 | #define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 404 | #define SWDCK_PORT GPIO_PRT6 |
| AnnaBridge | 189:f392fc9709a3 | 405 | #define SWDCK_PIN 7U |
| AnnaBridge | 189:f392fc9709a3 | 406 | #define SWDCK_NUM 7U |
| AnnaBridge | 189:f392fc9709a3 | 407 | #define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN |
| AnnaBridge | 189:f392fc9709a3 | 408 | #define SWDCK_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 409 | #ifndef ioss_0_port_6_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 410 | #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 411 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 412 | #define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 413 | #define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 414 | #define CINA_PORT GPIO_PRT7 |
| AnnaBridge | 189:f392fc9709a3 | 415 | #define CINA_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 416 | #define CINA_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 417 | #define CINA_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 418 | #define CINA_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 419 | #ifndef ioss_0_port_7_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 420 | #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 421 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 422 | #define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 423 | #define CINA_IRQ ioss_interrupts_gpio_7_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 424 | #define CINB_PORT GPIO_PRT7 |
| AnnaBridge | 189:f392fc9709a3 | 425 | #define CINB_PIN 2U |
| AnnaBridge | 189:f392fc9709a3 | 426 | #define CINB_NUM 2U |
| AnnaBridge | 189:f392fc9709a3 | 427 | #define CINB_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 428 | #define CINB_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 429 | #ifndef ioss_0_port_7_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 430 | #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 431 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 432 | #define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 433 | #define CINB_IRQ ioss_interrupts_gpio_7_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 434 | #define CMOD_PORT GPIO_PRT7 |
| AnnaBridge | 189:f392fc9709a3 | 435 | #define CMOD_PIN 7U |
| AnnaBridge | 189:f392fc9709a3 | 436 | #define CMOD_NUM 7U |
| AnnaBridge | 189:f392fc9709a3 | 437 | #define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 438 | #define CMOD_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 439 | #ifndef ioss_0_port_7_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 440 | #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 441 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 442 | #define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 443 | #define CMOD_IRQ ioss_interrupts_gpio_7_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 444 | #define CSD_BTN0_PORT GPIO_PRT8 |
| AnnaBridge | 189:f392fc9709a3 | 445 | #define CSD_BTN0_PIN 1U |
| AnnaBridge | 189:f392fc9709a3 | 446 | #define CSD_BTN0_NUM 1U |
| AnnaBridge | 189:f392fc9709a3 | 447 | #define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 448 | #define CSD_BTN0_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 449 | #ifndef ioss_0_port_8_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 450 | #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 451 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 452 | #define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 453 | #define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 454 | #define CSD_BTN1_PORT GPIO_PRT8 |
| AnnaBridge | 189:f392fc9709a3 | 455 | #define CSD_BTN1_PIN 2U |
| AnnaBridge | 189:f392fc9709a3 | 456 | #define CSD_BTN1_NUM 2U |
| AnnaBridge | 189:f392fc9709a3 | 457 | #define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 458 | #define CSD_BTN1_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 459 | #ifndef ioss_0_port_8_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 460 | #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 461 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 462 | #define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 463 | #define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 464 | #define CSD_SLD0_PORT GPIO_PRT8 |
| AnnaBridge | 189:f392fc9709a3 | 465 | #define CSD_SLD0_PIN 3U |
| AnnaBridge | 189:f392fc9709a3 | 466 | #define CSD_SLD0_NUM 3U |
| AnnaBridge | 189:f392fc9709a3 | 467 | #define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 468 | #define CSD_SLD0_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 469 | #ifndef ioss_0_port_8_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 470 | #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 471 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 472 | #define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 473 | #define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 474 | #define CSD_SLD1_PORT GPIO_PRT8 |
| AnnaBridge | 189:f392fc9709a3 | 475 | #define CSD_SLD1_PIN 4U |
| AnnaBridge | 189:f392fc9709a3 | 476 | #define CSD_SLD1_NUM 4U |
| AnnaBridge | 189:f392fc9709a3 | 477 | #define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 478 | #define CSD_SLD1_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 479 | #ifndef ioss_0_port_8_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 480 | #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 481 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 482 | #define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 483 | #define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 484 | #define CSD_SLD2_PORT GPIO_PRT8 |
| AnnaBridge | 189:f392fc9709a3 | 485 | #define CSD_SLD2_PIN 5U |
| AnnaBridge | 189:f392fc9709a3 | 486 | #define CSD_SLD2_NUM 5U |
| AnnaBridge | 189:f392fc9709a3 | 487 | #define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 488 | #define CSD_SLD2_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 489 | #ifndef ioss_0_port_8_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 490 | #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 491 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 492 | #define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 493 | #define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 494 | #define CSD_SLD3_PORT GPIO_PRT8 |
| AnnaBridge | 189:f392fc9709a3 | 495 | #define CSD_SLD3_PIN 6U |
| AnnaBridge | 189:f392fc9709a3 | 496 | #define CSD_SLD3_NUM 6U |
| AnnaBridge | 189:f392fc9709a3 | 497 | #define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 498 | #define CSD_SLD3_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 499 | #ifndef ioss_0_port_8_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 500 | #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 501 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 502 | #define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 503 | #define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 504 | #define CSD_SLD4_PORT GPIO_PRT8 |
| AnnaBridge | 189:f392fc9709a3 | 505 | #define CSD_SLD4_PIN 7U |
| AnnaBridge | 189:f392fc9709a3 | 506 | #define CSD_SLD4_NUM 7U |
| AnnaBridge | 189:f392fc9709a3 | 507 | #define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG |
| AnnaBridge | 189:f392fc9709a3 | 508 | #define CSD_SLD4_INIT_DRIVESTATE 1 |
| AnnaBridge | 189:f392fc9709a3 | 509 | #ifndef ioss_0_port_8_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 510 | #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO |
| AnnaBridge | 189:f392fc9709a3 | 511 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 512 | #define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM |
| AnnaBridge | 189:f392fc9709a3 | 513 | #define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn |
| AnnaBridge | 189:f392fc9709a3 | 514 | |
| AnnaBridge | 189:f392fc9709a3 | 515 | extern const cy_stc_gpio_pin_config_t WCO_IN_config; |
| AnnaBridge | 189:f392fc9709a3 | 516 | extern const cy_stc_gpio_pin_config_t WCO_OUT_config; |
| AnnaBridge | 189:f392fc9709a3 | 517 | extern const cy_stc_gpio_pin_config_t LED_RED_config; |
| AnnaBridge | 189:f392fc9709a3 | 518 | extern const cy_stc_gpio_pin_config_t SW2_config; |
| AnnaBridge | 189:f392fc9709a3 | 519 | extern const cy_stc_gpio_pin_config_t LED_BLUE_config; |
| AnnaBridge | 189:f392fc9709a3 | 520 | extern const cy_stc_gpio_pin_config_t QSPI_SS0_config; |
| AnnaBridge | 189:f392fc9709a3 | 521 | extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config; |
| AnnaBridge | 189:f392fc9709a3 | 522 | extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config; |
| AnnaBridge | 189:f392fc9709a3 | 523 | extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config; |
| AnnaBridge | 189:f392fc9709a3 | 524 | extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config; |
| AnnaBridge | 189:f392fc9709a3 | 525 | extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config; |
| AnnaBridge | 189:f392fc9709a3 | 526 | extern const cy_stc_gpio_pin_config_t LED9_config; |
| AnnaBridge | 189:f392fc9709a3 | 527 | extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config; |
| AnnaBridge | 189:f392fc9709a3 | 528 | extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config; |
| AnnaBridge | 189:f392fc9709a3 | 529 | extern const cy_stc_gpio_pin_config_t CSD_TX_config; |
| AnnaBridge | 189:f392fc9709a3 | 530 | extern const cy_stc_gpio_pin_config_t LED_GREEN_config; |
| AnnaBridge | 189:f392fc9709a3 | 531 | extern const cy_stc_gpio_pin_config_t LED8_config; |
| AnnaBridge | 189:f392fc9709a3 | 532 | extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config; |
| AnnaBridge | 189:f392fc9709a3 | 533 | extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config; |
| AnnaBridge | 189:f392fc9709a3 | 534 | extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config; |
| AnnaBridge | 189:f392fc9709a3 | 535 | extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config; |
| AnnaBridge | 189:f392fc9709a3 | 536 | extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config; |
| AnnaBridge | 189:f392fc9709a3 | 537 | extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config; |
| AnnaBridge | 189:f392fc9709a3 | 538 | extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config; |
| AnnaBridge | 189:f392fc9709a3 | 539 | extern const cy_stc_gpio_pin_config_t BT_UART_RX_config; |
| AnnaBridge | 189:f392fc9709a3 | 540 | extern const cy_stc_gpio_pin_config_t BT_UART_TX_config; |
| AnnaBridge | 189:f392fc9709a3 | 541 | extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config; |
| AnnaBridge | 189:f392fc9709a3 | 542 | extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config; |
| AnnaBridge | 189:f392fc9709a3 | 543 | extern const cy_stc_gpio_pin_config_t BT_POWER_config; |
| AnnaBridge | 189:f392fc9709a3 | 544 | extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config; |
| AnnaBridge | 189:f392fc9709a3 | 545 | extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config; |
| AnnaBridge | 189:f392fc9709a3 | 546 | extern const cy_stc_gpio_pin_config_t UART_RX_config; |
| AnnaBridge | 189:f392fc9709a3 | 547 | extern const cy_stc_gpio_pin_config_t UART_TX_config; |
| AnnaBridge | 189:f392fc9709a3 | 548 | extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config; |
| AnnaBridge | 189:f392fc9709a3 | 549 | extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config; |
| AnnaBridge | 189:f392fc9709a3 | 550 | extern const cy_stc_gpio_pin_config_t SWO_config; |
| AnnaBridge | 189:f392fc9709a3 | 551 | extern const cy_stc_gpio_pin_config_t SWDIO_config; |
| AnnaBridge | 189:f392fc9709a3 | 552 | extern const cy_stc_gpio_pin_config_t SWDCK_config; |
| AnnaBridge | 189:f392fc9709a3 | 553 | extern const cy_stc_gpio_pin_config_t CINA_config; |
| AnnaBridge | 189:f392fc9709a3 | 554 | extern const cy_stc_gpio_pin_config_t CINB_config; |
| AnnaBridge | 189:f392fc9709a3 | 555 | extern const cy_stc_gpio_pin_config_t CMOD_config; |
| AnnaBridge | 189:f392fc9709a3 | 556 | extern const cy_stc_gpio_pin_config_t CSD_BTN0_config; |
| AnnaBridge | 189:f392fc9709a3 | 557 | extern const cy_stc_gpio_pin_config_t CSD_BTN1_config; |
| AnnaBridge | 189:f392fc9709a3 | 558 | extern const cy_stc_gpio_pin_config_t CSD_SLD0_config; |
| AnnaBridge | 189:f392fc9709a3 | 559 | extern const cy_stc_gpio_pin_config_t CSD_SLD1_config; |
| AnnaBridge | 189:f392fc9709a3 | 560 | extern const cy_stc_gpio_pin_config_t CSD_SLD2_config; |
| AnnaBridge | 189:f392fc9709a3 | 561 | extern const cy_stc_gpio_pin_config_t CSD_SLD3_config; |
| AnnaBridge | 189:f392fc9709a3 | 562 | extern const cy_stc_gpio_pin_config_t CSD_SLD4_config; |
| AnnaBridge | 189:f392fc9709a3 | 563 | |
| AnnaBridge | 189:f392fc9709a3 | 564 | void init_cycfg_pins(void); |
| AnnaBridge | 189:f392fc9709a3 | 565 | |
| AnnaBridge | 189:f392fc9709a3 | 566 | #if defined(__cplusplus) |
| AnnaBridge | 189:f392fc9709a3 | 567 | } |
| AnnaBridge | 189:f392fc9709a3 | 568 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 569 | |
| AnnaBridge | 189:f392fc9709a3 | 570 | |
| AnnaBridge | 189:f392fc9709a3 | 571 | #endif /* CYCFG_PINS_H */ |
