mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 2 * File Name: cycfg_peripherals.c
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * Description:
AnnaBridge 189:f392fc9709a3 5 * Peripheral Hardware Block configuration
AnnaBridge 189:f392fc9709a3 6 * This file was automatically generated and should not be modified.
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 ********************************************************************************
AnnaBridge 189:f392fc9709a3 9 * Copyright 2017-2019 Cypress Semiconductor Corporation
AnnaBridge 189:f392fc9709a3 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 13 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 14 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 15 *
AnnaBridge 189:f392fc9709a3 16 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 17 *
AnnaBridge 189:f392fc9709a3 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 19 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 21 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 22 * limitations under the License.
AnnaBridge 189:f392fc9709a3 23 ********************************************************************************/
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 #include "cycfg_peripherals.h"
AnnaBridge 189:f392fc9709a3 26
AnnaBridge 189:f392fc9709a3 27 #define PWM_INPUT_DISABLED 0x7U
AnnaBridge 189:f392fc9709a3 28 #define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
AnnaBridge 189:f392fc9709a3 29 CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
AnnaBridge 189:f392fc9709a3 30 CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
AnnaBridge 189:f392fc9709a3 31 CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
AnnaBridge 189:f392fc9709a3 32 CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
AnnaBridge 189:f392fc9709a3 33 CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \
AnnaBridge 189:f392fc9709a3 34 CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \
AnnaBridge 189:f392fc9709a3 35 CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
AnnaBridge 189:f392fc9709a3 36 CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
AnnaBridge 189:f392fc9709a3 37 CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
AnnaBridge 189:f392fc9709a3 38 CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
AnnaBridge 189:f392fc9709a3 39 CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
AnnaBridge 189:f392fc9709a3 40 CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
AnnaBridge 189:f392fc9709a3 41
AnnaBridge 189:f392fc9709a3 42 cy_stc_csd_context_t cy_csd_0_context =
AnnaBridge 189:f392fc9709a3 43 {
AnnaBridge 189:f392fc9709a3 44 .lockKey = CY_CSD_NONE_KEY,
AnnaBridge 189:f392fc9709a3 45 };
AnnaBridge 189:f392fc9709a3 46 const cy_stc_scb_uart_config_t BT_UART_config =
AnnaBridge 189:f392fc9709a3 47 {
AnnaBridge 189:f392fc9709a3 48 .uartMode = CY_SCB_UART_STANDARD,
AnnaBridge 189:f392fc9709a3 49 .enableMutliProcessorMode = false,
AnnaBridge 189:f392fc9709a3 50 .smartCardRetryOnNack = false,
AnnaBridge 189:f392fc9709a3 51 .irdaInvertRx = false,
AnnaBridge 189:f392fc9709a3 52 .irdaEnableLowPowerReceiver = false,
AnnaBridge 189:f392fc9709a3 53 .oversample = 8,
AnnaBridge 189:f392fc9709a3 54 .enableMsbFirst = false,
AnnaBridge 189:f392fc9709a3 55 .dataWidth = 8UL,
AnnaBridge 189:f392fc9709a3 56 .parity = CY_SCB_UART_PARITY_NONE,
AnnaBridge 189:f392fc9709a3 57 .stopBits = CY_SCB_UART_STOP_BITS_1,
AnnaBridge 189:f392fc9709a3 58 .enableInputFilter = false,
AnnaBridge 189:f392fc9709a3 59 .breakWidth = 11UL,
AnnaBridge 189:f392fc9709a3 60 .dropOnFrameError = false,
AnnaBridge 189:f392fc9709a3 61 .dropOnParityError = false,
AnnaBridge 189:f392fc9709a3 62 .receiverAddress = 0x0UL,
AnnaBridge 189:f392fc9709a3 63 .receiverAddressMask = 0x0UL,
AnnaBridge 189:f392fc9709a3 64 .acceptAddrInFifo = false,
AnnaBridge 189:f392fc9709a3 65 .enableCts = true,
AnnaBridge 189:f392fc9709a3 66 .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
AnnaBridge 189:f392fc9709a3 67 .rtsRxFifoLevel = 63,
AnnaBridge 189:f392fc9709a3 68 .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
AnnaBridge 189:f392fc9709a3 69 .rxFifoTriggerLevel = 1UL,
AnnaBridge 189:f392fc9709a3 70 .rxFifoIntEnableMask = 0UL,
AnnaBridge 189:f392fc9709a3 71 .txFifoTriggerLevel = 63UL,
AnnaBridge 189:f392fc9709a3 72 .txFifoIntEnableMask = 0UL,
AnnaBridge 189:f392fc9709a3 73 };
AnnaBridge 189:f392fc9709a3 74 const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
AnnaBridge 189:f392fc9709a3 75 {
AnnaBridge 189:f392fc9709a3 76 .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
AnnaBridge 189:f392fc9709a3 77 .slaveAddress1 = 8U,
AnnaBridge 189:f392fc9709a3 78 .slaveAddress2 = 0U,
AnnaBridge 189:f392fc9709a3 79 .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
AnnaBridge 189:f392fc9709a3 80 .enableWakeFromSleep = false,
AnnaBridge 189:f392fc9709a3 81 };
AnnaBridge 189:f392fc9709a3 82 const cy_stc_scb_uart_config_t KITPROG_UART_config =
AnnaBridge 189:f392fc9709a3 83 {
AnnaBridge 189:f392fc9709a3 84 .uartMode = CY_SCB_UART_STANDARD,
AnnaBridge 189:f392fc9709a3 85 .enableMutliProcessorMode = false,
AnnaBridge 189:f392fc9709a3 86 .smartCardRetryOnNack = false,
AnnaBridge 189:f392fc9709a3 87 .irdaInvertRx = false,
AnnaBridge 189:f392fc9709a3 88 .irdaEnableLowPowerReceiver = false,
AnnaBridge 189:f392fc9709a3 89 .oversample = 8,
AnnaBridge 189:f392fc9709a3 90 .enableMsbFirst = false,
AnnaBridge 189:f392fc9709a3 91 .dataWidth = 8UL,
AnnaBridge 189:f392fc9709a3 92 .parity = CY_SCB_UART_PARITY_NONE,
AnnaBridge 189:f392fc9709a3 93 .stopBits = CY_SCB_UART_STOP_BITS_1,
AnnaBridge 189:f392fc9709a3 94 .enableInputFilter = false,
AnnaBridge 189:f392fc9709a3 95 .breakWidth = 11UL,
AnnaBridge 189:f392fc9709a3 96 .dropOnFrameError = false,
AnnaBridge 189:f392fc9709a3 97 .dropOnParityError = false,
AnnaBridge 189:f392fc9709a3 98 .receiverAddress = 0x0UL,
AnnaBridge 189:f392fc9709a3 99 .receiverAddressMask = 0x0UL,
AnnaBridge 189:f392fc9709a3 100 .acceptAddrInFifo = false,
AnnaBridge 189:f392fc9709a3 101 .enableCts = false,
AnnaBridge 189:f392fc9709a3 102 .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
AnnaBridge 189:f392fc9709a3 103 .rtsRxFifoLevel = 0UL,
AnnaBridge 189:f392fc9709a3 104 .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
AnnaBridge 189:f392fc9709a3 105 .rxFifoTriggerLevel = 63UL,
AnnaBridge 189:f392fc9709a3 106 .rxFifoIntEnableMask = 0UL,
AnnaBridge 189:f392fc9709a3 107 .txFifoTriggerLevel = 63UL,
AnnaBridge 189:f392fc9709a3 108 .txFifoIntEnableMask = 0UL,
AnnaBridge 189:f392fc9709a3 109 };
AnnaBridge 189:f392fc9709a3 110 const cy_stc_smif_config_t QSPI_config =
AnnaBridge 189:f392fc9709a3 111 {
AnnaBridge 189:f392fc9709a3 112 .mode = (uint32_t)CY_SMIF_NORMAL,
AnnaBridge 189:f392fc9709a3 113 .deselectDelay = QSPI_DESELECT_DELAY,
AnnaBridge 189:f392fc9709a3 114 .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
AnnaBridge 189:f392fc9709a3 115 .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
AnnaBridge 189:f392fc9709a3 116 };
AnnaBridge 189:f392fc9709a3 117 const cy_stc_mcwdt_config_t MCWDT0_config =
AnnaBridge 189:f392fc9709a3 118 {
AnnaBridge 189:f392fc9709a3 119 .c0Match = 32768U,
AnnaBridge 189:f392fc9709a3 120 .c1Match = 32768U,
AnnaBridge 189:f392fc9709a3 121 .c0Mode = CY_MCWDT_MODE_NONE,
AnnaBridge 189:f392fc9709a3 122 .c1Mode = CY_MCWDT_MODE_NONE,
AnnaBridge 189:f392fc9709a3 123 .c2ToggleBit = 16U,
AnnaBridge 189:f392fc9709a3 124 .c2Mode = CY_MCWDT_MODE_NONE,
AnnaBridge 189:f392fc9709a3 125 .c0ClearOnMatch = false,
AnnaBridge 189:f392fc9709a3 126 .c1ClearOnMatch = false,
AnnaBridge 189:f392fc9709a3 127 .c0c1Cascade = true,
AnnaBridge 189:f392fc9709a3 128 .c1c2Cascade = false,
AnnaBridge 189:f392fc9709a3 129 };
AnnaBridge 189:f392fc9709a3 130 const cy_stc_rtc_config_t RTC_config =
AnnaBridge 189:f392fc9709a3 131 {
AnnaBridge 189:f392fc9709a3 132 .sec = 0U,
AnnaBridge 189:f392fc9709a3 133 .min = 0U,
AnnaBridge 189:f392fc9709a3 134 .hour = 12U,
AnnaBridge 189:f392fc9709a3 135 .amPm = CY_RTC_AM,
AnnaBridge 189:f392fc9709a3 136 .hrFormat = CY_RTC_24_HOURS,
AnnaBridge 189:f392fc9709a3 137 .dayOfWeek = CY_RTC_SUNDAY,
AnnaBridge 189:f392fc9709a3 138 .date = 1U,
AnnaBridge 189:f392fc9709a3 139 .month = CY_RTC_JANUARY,
AnnaBridge 189:f392fc9709a3 140 .year = 0U,
AnnaBridge 189:f392fc9709a3 141 };
AnnaBridge 189:f392fc9709a3 142 const cy_stc_tcpwm_pwm_config_t PWM_config =
AnnaBridge 189:f392fc9709a3 143 {
AnnaBridge 189:f392fc9709a3 144 .pwmMode = CY_TCPWM_PWM_MODE_PWM,
AnnaBridge 189:f392fc9709a3 145 .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
AnnaBridge 189:f392fc9709a3 146 .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
AnnaBridge 189:f392fc9709a3 147 .deadTimeClocks = 0,
AnnaBridge 189:f392fc9709a3 148 .runMode = CY_TCPWM_PWM_CONTINUOUS,
AnnaBridge 189:f392fc9709a3 149 .period0 = 32000,
AnnaBridge 189:f392fc9709a3 150 .period1 = 32768,
AnnaBridge 189:f392fc9709a3 151 .enablePeriodSwap = false,
AnnaBridge 189:f392fc9709a3 152 .compare0 = 16384,
AnnaBridge 189:f392fc9709a3 153 .compare1 = 16384,
AnnaBridge 189:f392fc9709a3 154 .enableCompareSwap = false,
AnnaBridge 189:f392fc9709a3 155 .interruptSources = CY_TCPWM_INT_NONE,
AnnaBridge 189:f392fc9709a3 156 .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
AnnaBridge 189:f392fc9709a3 157 .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
AnnaBridge 189:f392fc9709a3 158 .killMode = CY_TCPWM_PWM_STOP_ON_KILL,
AnnaBridge 189:f392fc9709a3 159 .swapInputMode = PWM_INPUT_DISABLED & 0x3U,
AnnaBridge 189:f392fc9709a3 160 .swapInput = CY_TCPWM_INPUT_0,
AnnaBridge 189:f392fc9709a3 161 .reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
AnnaBridge 189:f392fc9709a3 162 .reloadInput = CY_TCPWM_INPUT_0,
AnnaBridge 189:f392fc9709a3 163 .startInputMode = PWM_INPUT_DISABLED & 0x3U,
AnnaBridge 189:f392fc9709a3 164 .startInput = CY_TCPWM_INPUT_0,
AnnaBridge 189:f392fc9709a3 165 .killInputMode = PWM_INPUT_DISABLED & 0x3U,
AnnaBridge 189:f392fc9709a3 166 .killInput = CY_TCPWM_INPUT_0,
AnnaBridge 189:f392fc9709a3 167 .countInputMode = PWM_INPUT_DISABLED & 0x3U,
AnnaBridge 189:f392fc9709a3 168 .countInput = CY_TCPWM_INPUT_1,
AnnaBridge 189:f392fc9709a3 169 };
AnnaBridge 189:f392fc9709a3 170 const cy_stc_usbfs_dev_drv_config_t USBUART_config =
AnnaBridge 189:f392fc9709a3 171 {
AnnaBridge 189:f392fc9709a3 172 .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
AnnaBridge 189:f392fc9709a3 173 .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
AnnaBridge 189:f392fc9709a3 174 .epBuffer = NULL,
AnnaBridge 189:f392fc9709a3 175 .epBufferSize = 0U,
AnnaBridge 189:f392fc9709a3 176 .dmaConfig[0] = NULL,
AnnaBridge 189:f392fc9709a3 177 .dmaConfig[1] = NULL,
AnnaBridge 189:f392fc9709a3 178 .dmaConfig[2] = NULL,
AnnaBridge 189:f392fc9709a3 179 .dmaConfig[3] = NULL,
AnnaBridge 189:f392fc9709a3 180 .dmaConfig[4] = NULL,
AnnaBridge 189:f392fc9709a3 181 .dmaConfig[5] = NULL,
AnnaBridge 189:f392fc9709a3 182 .dmaConfig[6] = NULL,
AnnaBridge 189:f392fc9709a3 183 .dmaConfig[7] = NULL,
AnnaBridge 189:f392fc9709a3 184 .enableLpm = false,
AnnaBridge 189:f392fc9709a3 185 .intrLevelSel = USBUART_INTR_LVL_SEL,
AnnaBridge 189:f392fc9709a3 186 };
AnnaBridge 189:f392fc9709a3 187
AnnaBridge 189:f392fc9709a3 188
AnnaBridge 189:f392fc9709a3 189 void init_cycfg_peripherals(void)
AnnaBridge 189:f392fc9709a3 190 {
AnnaBridge 189:f392fc9709a3 191 Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
AnnaBridge 189:f392fc9709a3 192
AnnaBridge 189:f392fc9709a3 193 Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
AnnaBridge 189:f392fc9709a3 194
AnnaBridge 189:f392fc9709a3 195 Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
AnnaBridge 189:f392fc9709a3 196
AnnaBridge 189:f392fc9709a3 197 Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
AnnaBridge 189:f392fc9709a3 198
AnnaBridge 189:f392fc9709a3 199 Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
AnnaBridge 189:f392fc9709a3 200
AnnaBridge 189:f392fc9709a3 201 Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
AnnaBridge 189:f392fc9709a3 202
AnnaBridge 189:f392fc9709a3 203 Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
AnnaBridge 189:f392fc9709a3 204 }