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mbed library sources. Supersedes mbed-src.

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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 2 * File Name: cycfg_dmas.c
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * Description:
AnnaBridge 189:f392fc9709a3 5 * DMA configuration
AnnaBridge 189:f392fc9709a3 6 * This file was automatically generated and should not be modified.
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 ********************************************************************************
AnnaBridge 189:f392fc9709a3 9 * Copyright 2017-2019 Cypress Semiconductor Corporation
AnnaBridge 189:f392fc9709a3 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 13 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 14 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 15 *
AnnaBridge 189:f392fc9709a3 16 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 17 *
AnnaBridge 189:f392fc9709a3 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 19 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 21 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 22 * limitations under the License.
AnnaBridge 189:f392fc9709a3 23 ********************************************************************************/
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 #include "cycfg_dmas.h"
AnnaBridge 189:f392fc9709a3 26
AnnaBridge 189:f392fc9709a3 27 const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config =
AnnaBridge 189:f392fc9709a3 28 {
AnnaBridge 189:f392fc9709a3 29 .retrigger = CY_DMA_RETRIG_IM,
AnnaBridge 189:f392fc9709a3 30 .interruptType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 31 .triggerOutType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 32 .channelState = CY_DMA_CHANNEL_DISABLED,
AnnaBridge 189:f392fc9709a3 33 .triggerInType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 34 .dataSize = CY_DMA_BYTE,
AnnaBridge 189:f392fc9709a3 35 .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 36 .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 37 .descriptorType = CY_DMA_1D_TRANSFER,
AnnaBridge 189:f392fc9709a3 38 .srcAddress = NULL,
AnnaBridge 189:f392fc9709a3 39 .dstAddress = NULL,
AnnaBridge 189:f392fc9709a3 40 .srcXincrement = 0,
AnnaBridge 189:f392fc9709a3 41 .dstXincrement = 1,
AnnaBridge 189:f392fc9709a3 42 .xCount = 6,
AnnaBridge 189:f392fc9709a3 43 .srcYincrement = 0,
AnnaBridge 189:f392fc9709a3 44 .dstYincrement = 0,
AnnaBridge 189:f392fc9709a3 45 .yCount = 1,
AnnaBridge 189:f392fc9709a3 46 .nextDescriptor = NULL,
AnnaBridge 189:f392fc9709a3 47 };
AnnaBridge 189:f392fc9709a3 48 cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 =
AnnaBridge 189:f392fc9709a3 49 {
AnnaBridge 189:f392fc9709a3 50 .ctl = 0UL,
AnnaBridge 189:f392fc9709a3 51 .src = 0UL,
AnnaBridge 189:f392fc9709a3 52 .dst = 0UL,
AnnaBridge 189:f392fc9709a3 53 .xCtl = 0UL,
AnnaBridge 189:f392fc9709a3 54 .yCtl = 0UL,
AnnaBridge 189:f392fc9709a3 55 .nextPtr = 0UL,
AnnaBridge 189:f392fc9709a3 56 };
AnnaBridge 189:f392fc9709a3 57 const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
AnnaBridge 189:f392fc9709a3 58 {
AnnaBridge 189:f392fc9709a3 59 .descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
AnnaBridge 189:f392fc9709a3 60 .preemptable = true,
AnnaBridge 189:f392fc9709a3 61 .priority = 1,
AnnaBridge 189:f392fc9709a3 62 .enable = false,
AnnaBridge 189:f392fc9709a3 63 .bufferable = false,
AnnaBridge 189:f392fc9709a3 64 };
AnnaBridge 189:f392fc9709a3 65 const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
AnnaBridge 189:f392fc9709a3 66 {
AnnaBridge 189:f392fc9709a3 67 .retrigger = CY_DMA_RETRIG_16CYC,
AnnaBridge 189:f392fc9709a3 68 .interruptType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 69 .triggerOutType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 70 .channelState = CY_DMA_CHANNEL_DISABLED,
AnnaBridge 189:f392fc9709a3 71 .triggerInType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 72 .dataSize = CY_DMA_BYTE,
AnnaBridge 189:f392fc9709a3 73 .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 74 .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 75 .descriptorType = CY_DMA_1D_TRANSFER,
AnnaBridge 189:f392fc9709a3 76 .srcAddress = NULL,
AnnaBridge 189:f392fc9709a3 77 .dstAddress = NULL,
AnnaBridge 189:f392fc9709a3 78 .srcXincrement = 1,
AnnaBridge 189:f392fc9709a3 79 .dstXincrement = 0,
AnnaBridge 189:f392fc9709a3 80 .xCount = 5,
AnnaBridge 189:f392fc9709a3 81 .srcYincrement = 0,
AnnaBridge 189:f392fc9709a3 82 .dstYincrement = 0,
AnnaBridge 189:f392fc9709a3 83 .yCount = 1,
AnnaBridge 189:f392fc9709a3 84 .nextDescriptor = NULL,
AnnaBridge 189:f392fc9709a3 85 };
AnnaBridge 189:f392fc9709a3 86 cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 =
AnnaBridge 189:f392fc9709a3 87 {
AnnaBridge 189:f392fc9709a3 88 .ctl = 0UL,
AnnaBridge 189:f392fc9709a3 89 .src = 0UL,
AnnaBridge 189:f392fc9709a3 90 .dst = 0UL,
AnnaBridge 189:f392fc9709a3 91 .xCtl = 0UL,
AnnaBridge 189:f392fc9709a3 92 .yCtl = 0UL,
AnnaBridge 189:f392fc9709a3 93 .nextPtr = 0UL,
AnnaBridge 189:f392fc9709a3 94 };
AnnaBridge 189:f392fc9709a3 95 const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
AnnaBridge 189:f392fc9709a3 96 {
AnnaBridge 189:f392fc9709a3 97 .descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
AnnaBridge 189:f392fc9709a3 98 .preemptable = true,
AnnaBridge 189:f392fc9709a3 99 .priority = 1,
AnnaBridge 189:f392fc9709a3 100 .enable = false,
AnnaBridge 189:f392fc9709a3 101 .bufferable = false,
AnnaBridge 189:f392fc9709a3 102 };
AnnaBridge 189:f392fc9709a3 103 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
AnnaBridge 189:f392fc9709a3 104 {
AnnaBridge 189:f392fc9709a3 105 .retrigger = CY_DMA_RETRIG_4CYC,
AnnaBridge 189:f392fc9709a3 106 .interruptType = CY_DMA_DESCR,
AnnaBridge 189:f392fc9709a3 107 .triggerOutType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 108 .channelState = CY_DMA_CHANNEL_DISABLED,
AnnaBridge 189:f392fc9709a3 109 .triggerInType = CY_DMA_X_LOOP,
AnnaBridge 189:f392fc9709a3 110 .dataSize = CY_DMA_HALFWORD,
AnnaBridge 189:f392fc9709a3 111 .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 112 .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 113 .descriptorType = CY_DMA_2D_TRANSFER,
AnnaBridge 189:f392fc9709a3 114 .srcAddress = NULL,
AnnaBridge 189:f392fc9709a3 115 .dstAddress = NULL,
AnnaBridge 189:f392fc9709a3 116 .srcXincrement = 2,
AnnaBridge 189:f392fc9709a3 117 .dstXincrement = 0,
AnnaBridge 189:f392fc9709a3 118 .xCount = 10,
AnnaBridge 189:f392fc9709a3 119 .srcYincrement = 10,
AnnaBridge 189:f392fc9709a3 120 .dstYincrement = 0,
AnnaBridge 189:f392fc9709a3 121 .yCount = 2,
AnnaBridge 189:f392fc9709a3 122 .nextDescriptor = NULL,
AnnaBridge 189:f392fc9709a3 123 };
AnnaBridge 189:f392fc9709a3 124 cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 =
AnnaBridge 189:f392fc9709a3 125 {
AnnaBridge 189:f392fc9709a3 126 .ctl = 0UL,
AnnaBridge 189:f392fc9709a3 127 .src = 0UL,
AnnaBridge 189:f392fc9709a3 128 .dst = 0UL,
AnnaBridge 189:f392fc9709a3 129 .xCtl = 0UL,
AnnaBridge 189:f392fc9709a3 130 .yCtl = 0UL,
AnnaBridge 189:f392fc9709a3 131 .nextPtr = 0UL,
AnnaBridge 189:f392fc9709a3 132 };
AnnaBridge 189:f392fc9709a3 133 const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
AnnaBridge 189:f392fc9709a3 134 {
AnnaBridge 189:f392fc9709a3 135 .descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
AnnaBridge 189:f392fc9709a3 136 .preemptable = false,
AnnaBridge 189:f392fc9709a3 137 .priority = 0,
AnnaBridge 189:f392fc9709a3 138 .enable = false,
AnnaBridge 189:f392fc9709a3 139 .bufferable = false,
AnnaBridge 189:f392fc9709a3 140 };
AnnaBridge 189:f392fc9709a3 141 const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
AnnaBridge 189:f392fc9709a3 142 {
AnnaBridge 189:f392fc9709a3 143 .retrigger = CY_DMA_RETRIG_IM,
AnnaBridge 189:f392fc9709a3 144 .interruptType = CY_DMA_DESCR,
AnnaBridge 189:f392fc9709a3 145 .triggerOutType = CY_DMA_1ELEMENT,
AnnaBridge 189:f392fc9709a3 146 .channelState = CY_DMA_CHANNEL_DISABLED,
AnnaBridge 189:f392fc9709a3 147 .triggerInType = CY_DMA_X_LOOP,
AnnaBridge 189:f392fc9709a3 148 .dataSize = CY_DMA_HALFWORD,
AnnaBridge 189:f392fc9709a3 149 .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 150 .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
AnnaBridge 189:f392fc9709a3 151 .descriptorType = CY_DMA_2D_TRANSFER,
AnnaBridge 189:f392fc9709a3 152 .srcAddress = NULL,
AnnaBridge 189:f392fc9709a3 153 .dstAddress = NULL,
AnnaBridge 189:f392fc9709a3 154 .srcXincrement = 0,
AnnaBridge 189:f392fc9709a3 155 .dstXincrement = 2,
AnnaBridge 189:f392fc9709a3 156 .xCount = 10,
AnnaBridge 189:f392fc9709a3 157 .srcYincrement = 0,
AnnaBridge 189:f392fc9709a3 158 .dstYincrement = 10,
AnnaBridge 189:f392fc9709a3 159 .yCount = 2,
AnnaBridge 189:f392fc9709a3 160 .nextDescriptor = NULL,
AnnaBridge 189:f392fc9709a3 161 };
AnnaBridge 189:f392fc9709a3 162 cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 =
AnnaBridge 189:f392fc9709a3 163 {
AnnaBridge 189:f392fc9709a3 164 .ctl = 0UL,
AnnaBridge 189:f392fc9709a3 165 .src = 0UL,
AnnaBridge 189:f392fc9709a3 166 .dst = 0UL,
AnnaBridge 189:f392fc9709a3 167 .xCtl = 0UL,
AnnaBridge 189:f392fc9709a3 168 .yCtl = 0UL,
AnnaBridge 189:f392fc9709a3 169 .nextPtr = 0UL,
AnnaBridge 189:f392fc9709a3 170 };
AnnaBridge 189:f392fc9709a3 171 const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
AnnaBridge 189:f392fc9709a3 172 {
AnnaBridge 189:f392fc9709a3 173 .descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
AnnaBridge 189:f392fc9709a3 174 .preemptable = false,
AnnaBridge 189:f392fc9709a3 175 .priority = 0,
AnnaBridge 189:f392fc9709a3 176 .enable = false,
AnnaBridge 189:f392fc9709a3 177 .bufferable = false,
AnnaBridge 189:f392fc9709a3 178 };
AnnaBridge 189:f392fc9709a3 179