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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6_cm4.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /***************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 2 | * \file system_psoc6_cm4.c |
| AnnaBridge | 189:f392fc9709a3 | 3 | * \version 2.30 |
| AnnaBridge | 189:f392fc9709a3 | 4 | * |
| AnnaBridge | 189:f392fc9709a3 | 5 | * The device system-source file. |
| AnnaBridge | 189:f392fc9709a3 | 6 | * |
| AnnaBridge | 189:f392fc9709a3 | 7 | ******************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 8 | * \copyright |
| AnnaBridge | 189:f392fc9709a3 | 9 | * Copyright 2016-2019 Cypress Semiconductor Corporation |
| AnnaBridge | 189:f392fc9709a3 | 10 | * SPDX-License-Identifier: Apache-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| AnnaBridge | 189:f392fc9709a3 | 13 | * you may not use this file except in compliance with the License. |
| AnnaBridge | 189:f392fc9709a3 | 14 | * You may obtain a copy of the License at |
| AnnaBridge | 189:f392fc9709a3 | 15 | * |
| AnnaBridge | 189:f392fc9709a3 | 16 | * http://www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 17 | * |
| AnnaBridge | 189:f392fc9709a3 | 18 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 189:f392fc9709a3 | 19 | * distributed under the License is distributed on an "AS IS" BASIS, |
| AnnaBridge | 189:f392fc9709a3 | 20 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * See the License for the specific language governing permissions and |
| AnnaBridge | 189:f392fc9709a3 | 22 | * limitations under the License. |
| AnnaBridge | 189:f392fc9709a3 | 23 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 24 | |
| AnnaBridge | 189:f392fc9709a3 | 25 | #include <stdint.h> |
| AnnaBridge | 189:f392fc9709a3 | 26 | #include <stdbool.h> |
| AnnaBridge | 189:f392fc9709a3 | 27 | #include "cy_device.h" |
| AnnaBridge | 189:f392fc9709a3 | 28 | #include "device.h" |
| AnnaBridge | 189:f392fc9709a3 | 29 | #include "system_psoc6.h" |
| AnnaBridge | 189:f392fc9709a3 | 30 | #include "cy_device_headers.h" |
| AnnaBridge | 189:f392fc9709a3 | 31 | #include "psoc6_utils.h" |
| AnnaBridge | 189:f392fc9709a3 | 32 | #include "cy_syslib.h" |
| AnnaBridge | 189:f392fc9709a3 | 33 | #include "cy_wdt.h" |
| AnnaBridge | 189:f392fc9709a3 | 34 | #include "cycfg.h" |
| AnnaBridge | 189:f392fc9709a3 | 35 | |
| AnnaBridge | 189:f392fc9709a3 | 36 | #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) |
| AnnaBridge | 189:f392fc9709a3 | 37 | #include "cy_ipc_sema.h" |
| AnnaBridge | 189:f392fc9709a3 | 38 | #include "cy_ipc_pipe.h" |
| AnnaBridge | 189:f392fc9709a3 | 39 | #include "cy_ipc_drv.h" |
| AnnaBridge | 189:f392fc9709a3 | 40 | |
| AnnaBridge | 189:f392fc9709a3 | 41 | #if defined(CY_DEVICE_PSOC6ABLE2) |
| AnnaBridge | 189:f392fc9709a3 | 42 | #include "cy_flash.h" |
| AnnaBridge | 189:f392fc9709a3 | 43 | #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ |
| AnnaBridge | 189:f392fc9709a3 | 44 | #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ |
| AnnaBridge | 189:f392fc9709a3 | 45 | |
| AnnaBridge | 189:f392fc9709a3 | 46 | |
| AnnaBridge | 189:f392fc9709a3 | 47 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 48 | * SystemCoreClockUpdate() |
| AnnaBridge | 189:f392fc9709a3 | 49 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 50 | |
| AnnaBridge | 189:f392fc9709a3 | 51 | /** Default HFClk frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 52 | #define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) |
| AnnaBridge | 189:f392fc9709a3 | 53 | |
| AnnaBridge | 189:f392fc9709a3 | 54 | /** Default PeriClk frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 55 | #define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) |
| AnnaBridge | 189:f392fc9709a3 | 56 | |
| AnnaBridge | 189:f392fc9709a3 | 57 | /** Default SlowClk system core frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 58 | #define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) |
| AnnaBridge | 189:f392fc9709a3 | 59 | |
| AnnaBridge | 189:f392fc9709a3 | 60 | /** IMO frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 61 | #define CY_CLK_IMO_FREQ_HZ (8000000UL) |
| AnnaBridge | 189:f392fc9709a3 | 62 | |
| AnnaBridge | 189:f392fc9709a3 | 63 | /** HVILO frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 64 | #define CY_CLK_HVILO_FREQ_HZ (32000UL) |
| AnnaBridge | 189:f392fc9709a3 | 65 | |
| AnnaBridge | 189:f392fc9709a3 | 66 | /** PILO frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 67 | #define CY_CLK_PILO_FREQ_HZ (32768UL) |
| AnnaBridge | 189:f392fc9709a3 | 68 | |
| AnnaBridge | 189:f392fc9709a3 | 69 | /** WCO frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 70 | #define CY_CLK_WCO_FREQ_HZ (32768UL) |
| AnnaBridge | 189:f392fc9709a3 | 71 | |
| AnnaBridge | 189:f392fc9709a3 | 72 | /** ALTLF frequency in Hz */ |
| AnnaBridge | 189:f392fc9709a3 | 73 | #define CY_CLK_ALTLF_FREQ_HZ (32768UL) |
| AnnaBridge | 189:f392fc9709a3 | 74 | |
| AnnaBridge | 189:f392fc9709a3 | 75 | |
| AnnaBridge | 189:f392fc9709a3 | 76 | /** |
| AnnaBridge | 189:f392fc9709a3 | 77 | * Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, |
| AnnaBridge | 189:f392fc9709a3 | 78 | * which is the system clock frequency supplied to the SysTick timer and the |
| AnnaBridge | 189:f392fc9709a3 | 79 | * processor core clock. |
| AnnaBridge | 189:f392fc9709a3 | 80 | * This variable implements CMSIS Core global variable. |
| AnnaBridge | 189:f392fc9709a3 | 81 | * Refer to the [CMSIS documentation] |
| AnnaBridge | 189:f392fc9709a3 | 82 | * (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") |
| AnnaBridge | 189:f392fc9709a3 | 83 | * for more details. |
| AnnaBridge | 189:f392fc9709a3 | 84 | * This variable can be used by debuggers to query the frequency |
| AnnaBridge | 189:f392fc9709a3 | 85 | * of the debug timer or to configure the trace clock speed. |
| AnnaBridge | 189:f392fc9709a3 | 86 | * |
| AnnaBridge | 189:f392fc9709a3 | 87 | * \attention Compilers must be configured to avoid removing this variable in case |
| AnnaBridge | 189:f392fc9709a3 | 88 | * the application program is not using it. Debugging systems require the variable |
| AnnaBridge | 189:f392fc9709a3 | 89 | * to be physically present in memory so that it can be examined to configure the debugger. */ |
| AnnaBridge | 189:f392fc9709a3 | 90 | uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; |
| AnnaBridge | 189:f392fc9709a3 | 91 | |
| AnnaBridge | 189:f392fc9709a3 | 92 | /** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ |
| AnnaBridge | 189:f392fc9709a3 | 93 | uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; |
| AnnaBridge | 189:f392fc9709a3 | 94 | |
| AnnaBridge | 189:f392fc9709a3 | 95 | /** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ |
| AnnaBridge | 189:f392fc9709a3 | 96 | uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; |
| AnnaBridge | 189:f392fc9709a3 | 97 | |
| AnnaBridge | 189:f392fc9709a3 | 98 | /** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ |
| AnnaBridge | 189:f392fc9709a3 | 99 | #if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) |
| AnnaBridge | 189:f392fc9709a3 | 100 | uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 101 | #endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ |
| AnnaBridge | 189:f392fc9709a3 | 102 | |
| AnnaBridge | 189:f392fc9709a3 | 103 | /* SCB->CPACR */ |
| AnnaBridge | 189:f392fc9709a3 | 104 | #define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) |
| AnnaBridge | 189:f392fc9709a3 | 105 | |
| AnnaBridge | 189:f392fc9709a3 | 106 | |
| AnnaBridge | 189:f392fc9709a3 | 107 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 108 | * SystemInit() |
| AnnaBridge | 189:f392fc9709a3 | 109 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 110 | |
| AnnaBridge | 189:f392fc9709a3 | 111 | /* CLK_FLL_CONFIG default values */ |
| AnnaBridge | 189:f392fc9709a3 | 112 | #define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) |
| AnnaBridge | 189:f392fc9709a3 | 113 | #define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) |
| AnnaBridge | 189:f392fc9709a3 | 114 | #define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) |
| AnnaBridge | 189:f392fc9709a3 | 115 | #define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) |
| AnnaBridge | 189:f392fc9709a3 | 116 | |
| AnnaBridge | 189:f392fc9709a3 | 117 | |
| AnnaBridge | 189:f392fc9709a3 | 118 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 119 | * SystemCoreClockUpdate (void) |
| AnnaBridge | 189:f392fc9709a3 | 120 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 121 | |
| AnnaBridge | 189:f392fc9709a3 | 122 | /* Do not use these definitions directly in your application */ |
| AnnaBridge | 189:f392fc9709a3 | 123 | #define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) |
| AnnaBridge | 189:f392fc9709a3 | 124 | #define CY_DELAY_1K_THRESHOLD (1000u) |
| AnnaBridge | 189:f392fc9709a3 | 125 | #define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) |
| AnnaBridge | 189:f392fc9709a3 | 126 | #define CY_DELAY_1M_THRESHOLD (1000000u) |
| AnnaBridge | 189:f392fc9709a3 | 127 | #define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) |
| AnnaBridge | 189:f392fc9709a3 | 128 | uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; |
| AnnaBridge | 189:f392fc9709a3 | 129 | |
| AnnaBridge | 189:f392fc9709a3 | 130 | uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / |
| AnnaBridge | 189:f392fc9709a3 | 131 | CY_DELAY_1K_THRESHOLD; |
| AnnaBridge | 189:f392fc9709a3 | 132 | |
| AnnaBridge | 189:f392fc9709a3 | 133 | uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / |
| AnnaBridge | 189:f392fc9709a3 | 134 | CY_DELAY_1M_THRESHOLD); |
| AnnaBridge | 189:f392fc9709a3 | 135 | |
| AnnaBridge | 189:f392fc9709a3 | 136 | uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * |
| AnnaBridge | 189:f392fc9709a3 | 137 | ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); |
| AnnaBridge | 189:f392fc9709a3 | 138 | |
| AnnaBridge | 189:f392fc9709a3 | 139 | #define CY_ROOT_PATH_SRC_IMO (0UL) |
| AnnaBridge | 189:f392fc9709a3 | 140 | #define CY_ROOT_PATH_SRC_EXT (1UL) |
| AnnaBridge | 189:f392fc9709a3 | 141 | #if (SRSS_ECO_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 142 | #define CY_ROOT_PATH_SRC_ECO (2UL) |
| AnnaBridge | 189:f392fc9709a3 | 143 | #endif /* (SRSS_ECO_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 144 | #if (SRSS_ALTHF_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 145 | #define CY_ROOT_PATH_SRC_ALTHF (3UL) |
| AnnaBridge | 189:f392fc9709a3 | 146 | #endif /* (SRSS_ALTHF_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 147 | #define CY_ROOT_PATH_SRC_DSI_MUX (4UL) |
| AnnaBridge | 189:f392fc9709a3 | 148 | #define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) |
| AnnaBridge | 189:f392fc9709a3 | 149 | #define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) |
| AnnaBridge | 189:f392fc9709a3 | 150 | #if (SRSS_ALTLF_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 151 | #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) |
| AnnaBridge | 189:f392fc9709a3 | 152 | #endif /* (SRSS_ALTLF_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 153 | #if (SRSS_PILO_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 154 | #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) |
| AnnaBridge | 189:f392fc9709a3 | 155 | #endif /* (SRSS_PILO_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 156 | |
| AnnaBridge | 189:f392fc9709a3 | 157 | |
| AnnaBridge | 189:f392fc9709a3 | 158 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 159 | * Function Name: SystemInit |
| AnnaBridge | 189:f392fc9709a3 | 160 | ****************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 161 | * \cond |
| AnnaBridge | 189:f392fc9709a3 | 162 | * Initializes the system: |
| AnnaBridge | 189:f392fc9709a3 | 163 | * - Restores FLL registers to the default state for single core devices. |
| AnnaBridge | 189:f392fc9709a3 | 164 | * - Unlocks and disables WDT. |
| AnnaBridge | 189:f392fc9709a3 | 165 | * - Calls Cy_PDL_Init() function to define the driver library. |
| AnnaBridge | 189:f392fc9709a3 | 166 | * - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. |
| AnnaBridge | 189:f392fc9709a3 | 167 | * - Calls \ref SystemCoreClockUpdate(). |
| AnnaBridge | 189:f392fc9709a3 | 168 | * \endcond |
| AnnaBridge | 189:f392fc9709a3 | 169 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 170 | void SystemInit(void) |
| AnnaBridge | 189:f392fc9709a3 | 171 | { |
| AnnaBridge | 189:f392fc9709a3 | 172 | Cy_PDL_Init(CY_DEVICE_CFG); |
| AnnaBridge | 189:f392fc9709a3 | 173 | |
| AnnaBridge | 189:f392fc9709a3 | 174 | #ifdef __CM0P_PRESENT |
| AnnaBridge | 189:f392fc9709a3 | 175 | #if (__CM0P_PRESENT == 0) |
| AnnaBridge | 189:f392fc9709a3 | 176 | /* Restore FLL registers to the default state as they are not restored by the ROM code */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | uint32_t copy = SRSS->CLK_FLL_CONFIG; |
| AnnaBridge | 189:f392fc9709a3 | 178 | copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; |
| AnnaBridge | 189:f392fc9709a3 | 179 | SRSS->CLK_FLL_CONFIG = copy; |
| AnnaBridge | 189:f392fc9709a3 | 180 | |
| AnnaBridge | 189:f392fc9709a3 | 181 | copy = SRSS->CLK_ROOT_SELECT[0u]; |
| AnnaBridge | 189:f392fc9709a3 | 182 | copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ |
| AnnaBridge | 189:f392fc9709a3 | 183 | SRSS->CLK_ROOT_SELECT[0u] = copy; |
| AnnaBridge | 189:f392fc9709a3 | 184 | |
| AnnaBridge | 189:f392fc9709a3 | 185 | SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; |
| AnnaBridge | 189:f392fc9709a3 | 186 | SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; |
| AnnaBridge | 189:f392fc9709a3 | 187 | SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; |
| AnnaBridge | 189:f392fc9709a3 | 188 | SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; |
| AnnaBridge | 189:f392fc9709a3 | 189 | |
| AnnaBridge | 189:f392fc9709a3 | 190 | /* Unlock and disable WDT */ |
| AnnaBridge | 189:f392fc9709a3 | 191 | Cy_WDT_Unlock(); |
| AnnaBridge | 189:f392fc9709a3 | 192 | Cy_WDT_Disable(); |
| AnnaBridge | 189:f392fc9709a3 | 193 | #endif /* (__CM0P_PRESENT == 0) */ |
| AnnaBridge | 189:f392fc9709a3 | 194 | #endif /* __CM0P_PRESENT */ |
| AnnaBridge | 189:f392fc9709a3 | 195 | |
| AnnaBridge | 189:f392fc9709a3 | 196 | Cy_SystemInit(); |
| AnnaBridge | 189:f392fc9709a3 | 197 | SystemCoreClockUpdate(); |
| AnnaBridge | 189:f392fc9709a3 | 198 | |
| AnnaBridge | 189:f392fc9709a3 | 199 | #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) |
| AnnaBridge | 189:f392fc9709a3 | 200 | |
| AnnaBridge | 189:f392fc9709a3 | 201 | #ifdef __CM0P_PRESENT |
| AnnaBridge | 189:f392fc9709a3 | 202 | #if (__CM0P_PRESENT == 0) |
| AnnaBridge | 189:f392fc9709a3 | 203 | /* Allocate and initialize semaphores for the system operations. */ |
| AnnaBridge | 189:f392fc9709a3 | 204 | static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; |
| AnnaBridge | 189:f392fc9709a3 | 205 | (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); |
| AnnaBridge | 189:f392fc9709a3 | 206 | #else |
| AnnaBridge | 189:f392fc9709a3 | 207 | (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); |
| AnnaBridge | 189:f392fc9709a3 | 208 | #endif /* (__CM0P_PRESENT) */ |
| AnnaBridge | 189:f392fc9709a3 | 209 | #else |
| AnnaBridge | 189:f392fc9709a3 | 210 | (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); |
| AnnaBridge | 189:f392fc9709a3 | 211 | #endif /* __CM0P_PRESENT */ |
| AnnaBridge | 189:f392fc9709a3 | 212 | |
| AnnaBridge | 189:f392fc9709a3 | 213 | |
| AnnaBridge | 189:f392fc9709a3 | 214 | /******************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 215 | * |
| AnnaBridge | 189:f392fc9709a3 | 216 | * Initializes the system pipes. The system pipes are used by BLE and Flash. |
| AnnaBridge | 189:f392fc9709a3 | 217 | * |
| AnnaBridge | 189:f392fc9709a3 | 218 | * If the default startup file is not used, or SystemInit() is not called in your |
| AnnaBridge | 189:f392fc9709a3 | 219 | * project, call the following three functions prior to executing any flash or |
| AnnaBridge | 189:f392fc9709a3 | 220 | * EmEEPROM write or erase operation: |
| AnnaBridge | 189:f392fc9709a3 | 221 | * -# Cy_IPC_Sema_Init() |
| AnnaBridge | 189:f392fc9709a3 | 222 | * -# Cy_IPC_Pipe_Config() |
| AnnaBridge | 189:f392fc9709a3 | 223 | * -# Cy_IPC_Pipe_Init() |
| AnnaBridge | 189:f392fc9709a3 | 224 | * -# Cy_Flash_Init() |
| AnnaBridge | 189:f392fc9709a3 | 225 | * |
| AnnaBridge | 189:f392fc9709a3 | 226 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 227 | /* Create an array of endpoint structures */ |
| AnnaBridge | 189:f392fc9709a3 | 228 | static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; |
| AnnaBridge | 189:f392fc9709a3 | 229 | |
| AnnaBridge | 189:f392fc9709a3 | 230 | Cy_IPC_Pipe_Config(systemIpcPipeEpArray); |
| AnnaBridge | 189:f392fc9709a3 | 231 | |
| AnnaBridge | 189:f392fc9709a3 | 232 | static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; |
| AnnaBridge | 189:f392fc9709a3 | 233 | |
| AnnaBridge | 189:f392fc9709a3 | 234 | static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = |
| AnnaBridge | 189:f392fc9709a3 | 235 | { |
| AnnaBridge | 189:f392fc9709a3 | 236 | /* .ep0ConfigData */ |
| AnnaBridge | 189:f392fc9709a3 | 237 | { |
| AnnaBridge | 189:f392fc9709a3 | 238 | /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, |
| AnnaBridge | 189:f392fc9709a3 | 239 | /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, |
| AnnaBridge | 189:f392fc9709a3 | 240 | /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, |
| AnnaBridge | 189:f392fc9709a3 | 241 | /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, |
| AnnaBridge | 189:f392fc9709a3 | 242 | /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 |
| AnnaBridge | 189:f392fc9709a3 | 243 | }, |
| AnnaBridge | 189:f392fc9709a3 | 244 | /* .ep1ConfigData */ |
| AnnaBridge | 189:f392fc9709a3 | 245 | { |
| AnnaBridge | 189:f392fc9709a3 | 246 | /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, |
| AnnaBridge | 189:f392fc9709a3 | 247 | /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, |
| AnnaBridge | 189:f392fc9709a3 | 248 | /* .ipcNotifierMuxNumber */ 0u, |
| AnnaBridge | 189:f392fc9709a3 | 249 | /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, |
| AnnaBridge | 189:f392fc9709a3 | 250 | /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 |
| AnnaBridge | 189:f392fc9709a3 | 251 | }, |
| AnnaBridge | 189:f392fc9709a3 | 252 | /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, |
| AnnaBridge | 189:f392fc9709a3 | 253 | /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, |
| AnnaBridge | 189:f392fc9709a3 | 254 | /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 |
| AnnaBridge | 189:f392fc9709a3 | 255 | }; |
| AnnaBridge | 189:f392fc9709a3 | 256 | |
| AnnaBridge | 189:f392fc9709a3 | 257 | if (cy_device->flashPipeRequired != 0u) |
| AnnaBridge | 189:f392fc9709a3 | 258 | { |
| AnnaBridge | 189:f392fc9709a3 | 259 | Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); |
| AnnaBridge | 189:f392fc9709a3 | 260 | } |
| AnnaBridge | 189:f392fc9709a3 | 261 | |
| AnnaBridge | 189:f392fc9709a3 | 262 | #if defined(CY_DEVICE_PSOC6ABLE2) |
| AnnaBridge | 189:f392fc9709a3 | 263 | Cy_Flash_Init(); |
| AnnaBridge | 189:f392fc9709a3 | 264 | #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ |
| AnnaBridge | 189:f392fc9709a3 | 265 | |
| AnnaBridge | 189:f392fc9709a3 | 266 | #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ |
| AnnaBridge | 189:f392fc9709a3 | 267 | } |
| AnnaBridge | 189:f392fc9709a3 | 268 | |
| AnnaBridge | 189:f392fc9709a3 | 269 | |
| AnnaBridge | 189:f392fc9709a3 | 270 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 271 | * Function Name: mbed_sdk_init |
| AnnaBridge | 189:f392fc9709a3 | 272 | ****************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 273 | * |
| AnnaBridge | 189:f392fc9709a3 | 274 | * Mbed's post-memory-initialization function. |
| AnnaBridge | 189:f392fc9709a3 | 275 | * Used here to initialize common parts of the Cypress libraries. |
| AnnaBridge | 189:f392fc9709a3 | 276 | * |
| AnnaBridge | 189:f392fc9709a3 | 277 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 278 | void mbed_sdk_init(void) |
| AnnaBridge | 189:f392fc9709a3 | 279 | { |
| AnnaBridge | 189:f392fc9709a3 | 280 | /* Initialize shared resource manager */ |
| AnnaBridge | 189:f392fc9709a3 | 281 | cy_srm_initialize(); |
| AnnaBridge | 189:f392fc9709a3 | 282 | |
| AnnaBridge | 189:f392fc9709a3 | 283 | /* Initialize system and clocks. */ |
| AnnaBridge | 189:f392fc9709a3 | 284 | /* Placed here as it must be done after proper LIBC initialization. */ |
| AnnaBridge | 189:f392fc9709a3 | 285 | SystemInit(); |
| AnnaBridge | 189:f392fc9709a3 | 286 | |
| AnnaBridge | 189:f392fc9709a3 | 287 | /* Set up the device based on configurator selections */ |
| AnnaBridge | 189:f392fc9709a3 | 288 | init_cycfg_all(); |
| AnnaBridge | 189:f392fc9709a3 | 289 | |
| AnnaBridge | 189:f392fc9709a3 | 290 | /* Enable global interrupts */ |
| AnnaBridge | 189:f392fc9709a3 | 291 | __enable_irq(); |
| AnnaBridge | 189:f392fc9709a3 | 292 | } |
| AnnaBridge | 189:f392fc9709a3 | 293 | |
| AnnaBridge | 189:f392fc9709a3 | 294 | |
| AnnaBridge | 189:f392fc9709a3 | 295 | |
| AnnaBridge | 189:f392fc9709a3 | 296 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 297 | * Function Name: Cy_SystemInit |
| AnnaBridge | 189:f392fc9709a3 | 298 | ****************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 299 | * |
| AnnaBridge | 189:f392fc9709a3 | 300 | * The function is called during device startup. Once project compiled as part of |
| AnnaBridge | 189:f392fc9709a3 | 301 | * the PSoC Creator project, the Cy_SystemInit() function is generated by the |
| AnnaBridge | 189:f392fc9709a3 | 302 | * PSoC Creator. |
| AnnaBridge | 189:f392fc9709a3 | 303 | * |
| AnnaBridge | 189:f392fc9709a3 | 304 | * The function generated by PSoC Creator performs all of the necessary device |
| AnnaBridge | 189:f392fc9709a3 | 305 | * configuration based on the design settings. This includes settings from the |
| AnnaBridge | 189:f392fc9709a3 | 306 | * Design Wide Resources (DWR) such as Clocks and Pins as well as any component |
| AnnaBridge | 189:f392fc9709a3 | 307 | * configuration that is necessary. |
| AnnaBridge | 189:f392fc9709a3 | 308 | * |
| AnnaBridge | 189:f392fc9709a3 | 309 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 310 | __WEAK void Cy_SystemInit(void) |
| AnnaBridge | 189:f392fc9709a3 | 311 | { |
| AnnaBridge | 189:f392fc9709a3 | 312 | /* Empty weak function. The actual implementation to be in the PSoC Creator |
| AnnaBridge | 189:f392fc9709a3 | 313 | * generated strong function. |
| AnnaBridge | 189:f392fc9709a3 | 314 | */ |
| AnnaBridge | 189:f392fc9709a3 | 315 | } |
| AnnaBridge | 189:f392fc9709a3 | 316 | |
| AnnaBridge | 189:f392fc9709a3 | 317 | |
| AnnaBridge | 189:f392fc9709a3 | 318 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 319 | * Function Name: SystemCoreClockUpdate |
| AnnaBridge | 189:f392fc9709a3 | 320 | ****************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 321 | * |
| AnnaBridge | 189:f392fc9709a3 | 322 | * Gets core clock frequency and updates \ref SystemCoreClock, \ref |
| AnnaBridge | 189:f392fc9709a3 | 323 | * cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. |
| AnnaBridge | 189:f392fc9709a3 | 324 | * |
| AnnaBridge | 189:f392fc9709a3 | 325 | * Updates global variables used by the \ref Cy_SysLib_Delay(), \ref |
| AnnaBridge | 189:f392fc9709a3 | 326 | * Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). |
| AnnaBridge | 189:f392fc9709a3 | 327 | * |
| AnnaBridge | 189:f392fc9709a3 | 328 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 329 | void SystemCoreClockUpdate (void) |
| AnnaBridge | 189:f392fc9709a3 | 330 | { |
| AnnaBridge | 189:f392fc9709a3 | 331 | uint32_t srcFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 332 | uint32_t pathFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 333 | uint32_t fastClkDiv; |
| AnnaBridge | 189:f392fc9709a3 | 334 | uint32_t periClkDiv; |
| AnnaBridge | 189:f392fc9709a3 | 335 | uint32_t rootPath; |
| AnnaBridge | 189:f392fc9709a3 | 336 | uint32_t srcClk; |
| AnnaBridge | 189:f392fc9709a3 | 337 | |
| AnnaBridge | 189:f392fc9709a3 | 338 | /* Get root path clock for the high-frequency clock # 0 */ |
| AnnaBridge | 189:f392fc9709a3 | 339 | rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); |
| AnnaBridge | 189:f392fc9709a3 | 340 | |
| AnnaBridge | 189:f392fc9709a3 | 341 | /* Get source of the root path clock */ |
| AnnaBridge | 189:f392fc9709a3 | 342 | srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); |
| AnnaBridge | 189:f392fc9709a3 | 343 | |
| AnnaBridge | 189:f392fc9709a3 | 344 | /* Get frequency of the source */ |
| AnnaBridge | 189:f392fc9709a3 | 345 | switch (srcClk) |
| AnnaBridge | 189:f392fc9709a3 | 346 | { |
| AnnaBridge | 189:f392fc9709a3 | 347 | case CY_ROOT_PATH_SRC_IMO: |
| AnnaBridge | 189:f392fc9709a3 | 348 | srcFreqHz = CY_CLK_IMO_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 349 | break; |
| AnnaBridge | 189:f392fc9709a3 | 350 | |
| AnnaBridge | 189:f392fc9709a3 | 351 | case CY_ROOT_PATH_SRC_EXT: |
| AnnaBridge | 189:f392fc9709a3 | 352 | srcFreqHz = CY_CLK_EXT_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 353 | break; |
| AnnaBridge | 189:f392fc9709a3 | 354 | |
| AnnaBridge | 189:f392fc9709a3 | 355 | #if (SRSS_ECO_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 356 | case CY_ROOT_PATH_SRC_ECO: |
| AnnaBridge | 189:f392fc9709a3 | 357 | srcFreqHz = CY_CLK_ECO_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 358 | break; |
| AnnaBridge | 189:f392fc9709a3 | 359 | #endif /* (SRSS_ECO_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 360 | |
| AnnaBridge | 189:f392fc9709a3 | 361 | #if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 362 | case CY_ROOT_PATH_SRC_ALTHF: |
| AnnaBridge | 189:f392fc9709a3 | 363 | srcFreqHz = cy_BleEcoClockFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 364 | break; |
| AnnaBridge | 189:f392fc9709a3 | 365 | #endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 366 | |
| AnnaBridge | 189:f392fc9709a3 | 367 | case CY_ROOT_PATH_SRC_DSI_MUX: |
| AnnaBridge | 189:f392fc9709a3 | 368 | { |
| AnnaBridge | 189:f392fc9709a3 | 369 | uint32_t dsi_src; |
| AnnaBridge | 189:f392fc9709a3 | 370 | dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); |
| AnnaBridge | 189:f392fc9709a3 | 371 | switch (dsi_src) |
| AnnaBridge | 189:f392fc9709a3 | 372 | { |
| AnnaBridge | 189:f392fc9709a3 | 373 | case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: |
| AnnaBridge | 189:f392fc9709a3 | 374 | srcFreqHz = CY_CLK_HVILO_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 375 | break; |
| AnnaBridge | 189:f392fc9709a3 | 376 | |
| AnnaBridge | 189:f392fc9709a3 | 377 | case CY_ROOT_PATH_SRC_DSI_MUX_WCO: |
| AnnaBridge | 189:f392fc9709a3 | 378 | srcFreqHz = CY_CLK_WCO_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 379 | break; |
| AnnaBridge | 189:f392fc9709a3 | 380 | |
| AnnaBridge | 189:f392fc9709a3 | 381 | #if (SRSS_ALTLF_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 382 | case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: |
| AnnaBridge | 189:f392fc9709a3 | 383 | srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 384 | break; |
| AnnaBridge | 189:f392fc9709a3 | 385 | #endif /* (SRSS_ALTLF_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 386 | |
| AnnaBridge | 189:f392fc9709a3 | 387 | #if (SRSS_PILO_PRESENT == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 388 | case CY_ROOT_PATH_SRC_DSI_MUX_PILO: |
| AnnaBridge | 189:f392fc9709a3 | 389 | srcFreqHz = CY_CLK_PILO_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 390 | break; |
| AnnaBridge | 189:f392fc9709a3 | 391 | #endif /* (SRSS_PILO_PRESENT == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 392 | |
| AnnaBridge | 189:f392fc9709a3 | 393 | default: |
| AnnaBridge | 189:f392fc9709a3 | 394 | srcFreqHz = CY_CLK_HVILO_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 395 | break; |
| AnnaBridge | 189:f392fc9709a3 | 396 | } |
| AnnaBridge | 189:f392fc9709a3 | 397 | } |
| AnnaBridge | 189:f392fc9709a3 | 398 | break; |
| AnnaBridge | 189:f392fc9709a3 | 399 | |
| AnnaBridge | 189:f392fc9709a3 | 400 | default: |
| AnnaBridge | 189:f392fc9709a3 | 401 | srcFreqHz = CY_CLK_EXT_FREQ_HZ; |
| AnnaBridge | 189:f392fc9709a3 | 402 | break; |
| AnnaBridge | 189:f392fc9709a3 | 403 | } |
| AnnaBridge | 189:f392fc9709a3 | 404 | |
| AnnaBridge | 189:f392fc9709a3 | 405 | if (rootPath == 0UL) |
| AnnaBridge | 189:f392fc9709a3 | 406 | { |
| AnnaBridge | 189:f392fc9709a3 | 407 | /* FLL */ |
| AnnaBridge | 189:f392fc9709a3 | 408 | bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); |
| AnnaBridge | 189:f392fc9709a3 | 409 | bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); |
| AnnaBridge | 189:f392fc9709a3 | 410 | bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || |
| AnnaBridge | 189:f392fc9709a3 | 411 | (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); |
| AnnaBridge | 189:f392fc9709a3 | 412 | if ((fllOutputAuto && fllLocked) || fllOutputOutput) |
| AnnaBridge | 189:f392fc9709a3 | 413 | { |
| AnnaBridge | 189:f392fc9709a3 | 414 | uint32_t fllMult; |
| AnnaBridge | 189:f392fc9709a3 | 415 | uint32_t refDiv; |
| AnnaBridge | 189:f392fc9709a3 | 416 | uint32_t outputDiv; |
| AnnaBridge | 189:f392fc9709a3 | 417 | |
| AnnaBridge | 189:f392fc9709a3 | 418 | fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); |
| AnnaBridge | 189:f392fc9709a3 | 419 | refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); |
| AnnaBridge | 189:f392fc9709a3 | 420 | outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; |
| AnnaBridge | 189:f392fc9709a3 | 421 | |
| AnnaBridge | 189:f392fc9709a3 | 422 | pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; |
| AnnaBridge | 189:f392fc9709a3 | 423 | } |
| AnnaBridge | 189:f392fc9709a3 | 424 | else |
| AnnaBridge | 189:f392fc9709a3 | 425 | { |
| AnnaBridge | 189:f392fc9709a3 | 426 | pathFreqHz = srcFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 427 | } |
| AnnaBridge | 189:f392fc9709a3 | 428 | } |
| AnnaBridge | 189:f392fc9709a3 | 429 | else if ((rootPath == 1UL) || (rootPath == 2UL)) |
| AnnaBridge | 189:f392fc9709a3 | 430 | { |
| AnnaBridge | 189:f392fc9709a3 | 431 | /* PLL */ |
| AnnaBridge | 189:f392fc9709a3 | 432 | bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); |
| AnnaBridge | 189:f392fc9709a3 | 433 | bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); |
| AnnaBridge | 189:f392fc9709a3 | 434 | bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || |
| AnnaBridge | 189:f392fc9709a3 | 435 | (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); |
| AnnaBridge | 189:f392fc9709a3 | 436 | if ((pllOutputAuto && pllLocked) || pllOutputOutput) |
| AnnaBridge | 189:f392fc9709a3 | 437 | { |
| AnnaBridge | 189:f392fc9709a3 | 438 | uint32_t feedbackDiv; |
| AnnaBridge | 189:f392fc9709a3 | 439 | uint32_t referenceDiv; |
| AnnaBridge | 189:f392fc9709a3 | 440 | uint32_t outputDiv; |
| AnnaBridge | 189:f392fc9709a3 | 441 | |
| AnnaBridge | 189:f392fc9709a3 | 442 | feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); |
| AnnaBridge | 189:f392fc9709a3 | 443 | referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); |
| AnnaBridge | 189:f392fc9709a3 | 444 | outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); |
| AnnaBridge | 189:f392fc9709a3 | 445 | |
| AnnaBridge | 189:f392fc9709a3 | 446 | pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; |
| AnnaBridge | 189:f392fc9709a3 | 447 | |
| AnnaBridge | 189:f392fc9709a3 | 448 | } |
| AnnaBridge | 189:f392fc9709a3 | 449 | else |
| AnnaBridge | 189:f392fc9709a3 | 450 | { |
| AnnaBridge | 189:f392fc9709a3 | 451 | pathFreqHz = srcFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 452 | } |
| AnnaBridge | 189:f392fc9709a3 | 453 | } |
| AnnaBridge | 189:f392fc9709a3 | 454 | else |
| AnnaBridge | 189:f392fc9709a3 | 455 | { |
| AnnaBridge | 189:f392fc9709a3 | 456 | /* Direct */ |
| AnnaBridge | 189:f392fc9709a3 | 457 | pathFreqHz = srcFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 458 | } |
| AnnaBridge | 189:f392fc9709a3 | 459 | |
| AnnaBridge | 189:f392fc9709a3 | 460 | /* Get frequency after hf_clk pre-divider */ |
| AnnaBridge | 189:f392fc9709a3 | 461 | pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); |
| AnnaBridge | 189:f392fc9709a3 | 462 | cy_Hfclk0FreqHz = pathFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 463 | |
| AnnaBridge | 189:f392fc9709a3 | 464 | /* Fast Clock Divider */ |
| AnnaBridge | 189:f392fc9709a3 | 465 | fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); |
| AnnaBridge | 189:f392fc9709a3 | 466 | |
| AnnaBridge | 189:f392fc9709a3 | 467 | /* Peripheral Clock Divider */ |
| AnnaBridge | 189:f392fc9709a3 | 468 | periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); |
| AnnaBridge | 189:f392fc9709a3 | 469 | cy_PeriClkFreqHz = pathFreqHz / periClkDiv; |
| AnnaBridge | 189:f392fc9709a3 | 470 | |
| AnnaBridge | 189:f392fc9709a3 | 471 | pathFreqHz = pathFreqHz / fastClkDiv; |
| AnnaBridge | 189:f392fc9709a3 | 472 | SystemCoreClock = pathFreqHz; |
| AnnaBridge | 189:f392fc9709a3 | 473 | |
| AnnaBridge | 189:f392fc9709a3 | 474 | /* Sets clock frequency for Delay API */ |
| AnnaBridge | 189:f392fc9709a3 | 475 | cy_delayFreqHz = SystemCoreClock; |
| AnnaBridge | 189:f392fc9709a3 | 476 | cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); |
| AnnaBridge | 189:f392fc9709a3 | 477 | cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; |
| AnnaBridge | 189:f392fc9709a3 | 478 | cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; |
| AnnaBridge | 189:f392fc9709a3 | 479 | } |
| AnnaBridge | 189:f392fc9709a3 | 480 | |
| AnnaBridge | 189:f392fc9709a3 | 481 | |
| AnnaBridge | 189:f392fc9709a3 | 482 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 483 | * Function Name: Cy_SystemInitFpuEnable |
| AnnaBridge | 189:f392fc9709a3 | 484 | ****************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 485 | * |
| AnnaBridge | 189:f392fc9709a3 | 486 | * Enables the FPU if it is used. The function is called from the startup file. |
| AnnaBridge | 189:f392fc9709a3 | 487 | * |
| AnnaBridge | 189:f392fc9709a3 | 488 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 489 | void Cy_SystemInitFpuEnable(void) |
| AnnaBridge | 189:f392fc9709a3 | 490 | { |
| AnnaBridge | 189:f392fc9709a3 | 491 | #if defined (__FPU_USED) && (__FPU_USED == 1U) |
| AnnaBridge | 189:f392fc9709a3 | 492 | uint32_t interruptState; |
| AnnaBridge | 189:f392fc9709a3 | 493 | interruptState = Cy_SysLib_EnterCriticalSection(); |
| AnnaBridge | 189:f392fc9709a3 | 494 | SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; |
| AnnaBridge | 189:f392fc9709a3 | 495 | __DSB(); |
| AnnaBridge | 189:f392fc9709a3 | 496 | __ISB(); |
| AnnaBridge | 189:f392fc9709a3 | 497 | Cy_SysLib_ExitCriticalSection(interruptState); |
| AnnaBridge | 189:f392fc9709a3 | 498 | #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ |
| AnnaBridge | 189:f392fc9709a3 | 499 | } |
| AnnaBridge | 189:f392fc9709a3 | 500 | |
| AnnaBridge | 189:f392fc9709a3 | 501 | |
| AnnaBridge | 189:f392fc9709a3 | 502 | #if !defined(CY_IPC_DEFAULT_CFG_DISABLE) |
| AnnaBridge | 189:f392fc9709a3 | 503 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 504 | * Function Name: Cy_SysIpcPipeIsrCm4 |
| AnnaBridge | 189:f392fc9709a3 | 505 | ****************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 506 | * |
| AnnaBridge | 189:f392fc9709a3 | 507 | * This is the interrupt service routine for the system pipe. |
| AnnaBridge | 189:f392fc9709a3 | 508 | * |
| AnnaBridge | 189:f392fc9709a3 | 509 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 510 | void Cy_SysIpcPipeIsrCm4(void) |
| AnnaBridge | 189:f392fc9709a3 | 511 | { |
| AnnaBridge | 189:f392fc9709a3 | 512 | Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); |
| AnnaBridge | 189:f392fc9709a3 | 513 | } |
| AnnaBridge | 189:f392fc9709a3 | 514 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 515 | |
| AnnaBridge | 189:f392fc9709a3 | 516 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 517 | * Function Name: Cy_MemorySymbols |
| AnnaBridge | 189:f392fc9709a3 | 518 | ****************************************************************************//** |
| AnnaBridge | 189:f392fc9709a3 | 519 | * |
| AnnaBridge | 189:f392fc9709a3 | 520 | * The intention of the function is to declare boundaries of the memories for the |
| AnnaBridge | 189:f392fc9709a3 | 521 | * MDK compilers. For the rest of the supported compilers, this is done using |
| AnnaBridge | 189:f392fc9709a3 | 522 | * linker configuration files. The following symbols used by the cymcuelftool. |
| AnnaBridge | 189:f392fc9709a3 | 523 | * |
| AnnaBridge | 189:f392fc9709a3 | 524 | *******************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 525 | #if defined (__ARMCC_VERSION) |
| AnnaBridge | 189:f392fc9709a3 | 526 | __asm void Cy_MemorySymbols(void) |
| AnnaBridge | 189:f392fc9709a3 | 527 | { |
| AnnaBridge | 189:f392fc9709a3 | 528 | /* Flash */ |
| AnnaBridge | 189:f392fc9709a3 | 529 | EXPORT __cy_memory_0_start |
| AnnaBridge | 189:f392fc9709a3 | 530 | EXPORT __cy_memory_0_length |
| AnnaBridge | 189:f392fc9709a3 | 531 | EXPORT __cy_memory_0_row_size |
| AnnaBridge | 189:f392fc9709a3 | 532 | |
| AnnaBridge | 189:f392fc9709a3 | 533 | /* Working Flash */ |
| AnnaBridge | 189:f392fc9709a3 | 534 | EXPORT __cy_memory_1_start |
| AnnaBridge | 189:f392fc9709a3 | 535 | EXPORT __cy_memory_1_length |
| AnnaBridge | 189:f392fc9709a3 | 536 | EXPORT __cy_memory_1_row_size |
| AnnaBridge | 189:f392fc9709a3 | 537 | |
| AnnaBridge | 189:f392fc9709a3 | 538 | /* Supervisory Flash */ |
| AnnaBridge | 189:f392fc9709a3 | 539 | EXPORT __cy_memory_2_start |
| AnnaBridge | 189:f392fc9709a3 | 540 | EXPORT __cy_memory_2_length |
| AnnaBridge | 189:f392fc9709a3 | 541 | EXPORT __cy_memory_2_row_size |
| AnnaBridge | 189:f392fc9709a3 | 542 | |
| AnnaBridge | 189:f392fc9709a3 | 543 | /* XIP */ |
| AnnaBridge | 189:f392fc9709a3 | 544 | EXPORT __cy_memory_3_start |
| AnnaBridge | 189:f392fc9709a3 | 545 | EXPORT __cy_memory_3_length |
| AnnaBridge | 189:f392fc9709a3 | 546 | EXPORT __cy_memory_3_row_size |
| AnnaBridge | 189:f392fc9709a3 | 547 | |
| AnnaBridge | 189:f392fc9709a3 | 548 | /* eFuse */ |
| AnnaBridge | 189:f392fc9709a3 | 549 | EXPORT __cy_memory_4_start |
| AnnaBridge | 189:f392fc9709a3 | 550 | EXPORT __cy_memory_4_length |
| AnnaBridge | 189:f392fc9709a3 | 551 | EXPORT __cy_memory_4_row_size |
| AnnaBridge | 189:f392fc9709a3 | 552 | |
| AnnaBridge | 189:f392fc9709a3 | 553 | /* Flash */ |
| AnnaBridge | 189:f392fc9709a3 | 554 | __cy_memory_0_start EQU __cpp(CY_FLASH_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 555 | __cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) |
| AnnaBridge | 189:f392fc9709a3 | 556 | __cy_memory_0_row_size EQU 0x200 |
| AnnaBridge | 189:f392fc9709a3 | 557 | |
| AnnaBridge | 189:f392fc9709a3 | 558 | /* Flash region for EEPROM emulation */ |
| AnnaBridge | 189:f392fc9709a3 | 559 | __cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 560 | __cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) |
| AnnaBridge | 189:f392fc9709a3 | 561 | __cy_memory_1_row_size EQU 0x200 |
| AnnaBridge | 189:f392fc9709a3 | 562 | |
| AnnaBridge | 189:f392fc9709a3 | 563 | /* Supervisory Flash */ |
| AnnaBridge | 189:f392fc9709a3 | 564 | __cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 565 | __cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) |
| AnnaBridge | 189:f392fc9709a3 | 566 | __cy_memory_2_row_size EQU 0x200 |
| AnnaBridge | 189:f392fc9709a3 | 567 | |
| AnnaBridge | 189:f392fc9709a3 | 568 | /* XIP */ |
| AnnaBridge | 189:f392fc9709a3 | 569 | __cy_memory_3_start EQU __cpp(CY_XIP_BASE) |
| AnnaBridge | 189:f392fc9709a3 | 570 | __cy_memory_3_length EQU __cpp(CY_XIP_SIZE) |
| AnnaBridge | 189:f392fc9709a3 | 571 | __cy_memory_3_row_size EQU 0x200 |
| AnnaBridge | 189:f392fc9709a3 | 572 | |
| AnnaBridge | 189:f392fc9709a3 | 573 | /* eFuse */ |
| AnnaBridge | 189:f392fc9709a3 | 574 | __cy_memory_4_start EQU __cpp(0x90700000) |
| AnnaBridge | 189:f392fc9709a3 | 575 | __cy_memory_4_length EQU __cpp(0x100000) |
| AnnaBridge | 189:f392fc9709a3 | 576 | __cy_memory_4_row_size EQU __cpp(1) |
| AnnaBridge | 189:f392fc9709a3 | 577 | } |
| AnnaBridge | 189:f392fc9709a3 | 578 | |
| AnnaBridge | 189:f392fc9709a3 | 579 | #endif /* defined (__ARMCC_VERSION) */ |
| AnnaBridge | 189:f392fc9709a3 | 580 | |
| AnnaBridge | 189:f392fc9709a3 | 581 | |
| AnnaBridge | 189:f392fc9709a3 | 582 | /* [] END OF FILE */ |
