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mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /* |
| AnnaBridge | 189:f392fc9709a3 | 2 | * mbed Microcontroller Library |
| AnnaBridge | 189:f392fc9709a3 | 3 | * Copyright (c) 2017-2018 Future Electronics |
| AnnaBridge | 189:f392fc9709a3 | 4 | * Copyright (c) 2019 Cypress Semiconductor Corporation |
| AnnaBridge | 189:f392fc9709a3 | 5 | * SPDX-License-Identifier: Apache-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 6 | * |
| AnnaBridge | 189:f392fc9709a3 | 7 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| AnnaBridge | 189:f392fc9709a3 | 8 | * you may not use this file except in compliance with the License. |
| AnnaBridge | 189:f392fc9709a3 | 9 | * You may obtain a copy of the License at |
| AnnaBridge | 189:f392fc9709a3 | 10 | * |
| AnnaBridge | 189:f392fc9709a3 | 11 | * http://www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 12 | * |
| AnnaBridge | 189:f392fc9709a3 | 13 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 189:f392fc9709a3 | 14 | * distributed under the License is distributed on an "AS IS" BASIS, |
| AnnaBridge | 189:f392fc9709a3 | 15 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 189:f392fc9709a3 | 16 | * See the License for the specific language governing permissions and |
| AnnaBridge | 189:f392fc9709a3 | 17 | * limitations under the License. |
| AnnaBridge | 189:f392fc9709a3 | 18 | */ |
| AnnaBridge | 189:f392fc9709a3 | 19 | |
| AnnaBridge | 189:f392fc9709a3 | 20 | #include "PeripheralNames.h" |
| AnnaBridge | 189:f392fc9709a3 | 21 | #include "PeripheralPins.h" |
| AnnaBridge | 189:f392fc9709a3 | 22 | #include "pinmap.h" |
| AnnaBridge | 189:f392fc9709a3 | 23 | |
| AnnaBridge | 189:f392fc9709a3 | 24 | #if DEVICE_SERIAL |
| AnnaBridge | 189:f392fc9709a3 | 25 | //*** SERIAL *** |
| AnnaBridge | 189:f392fc9709a3 | 26 | const PinMap PinMap_UART_RX[] = { |
| AnnaBridge | 189:f392fc9709a3 | 27 | {P0_2, UART_0, CY_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 28 | {P1_0, UART_7, CY_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 29 | {P5_0, UART_5, CY_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 30 | {P6_0, UART_3, CY_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 31 | {P6_4, UART_6, CY_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 32 | {P7_0, UART_4, CY_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 33 | {P8_0, UART_4, CY_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 34 | {P9_0, UART_2, CY_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 35 | {P10_0, UART_1, CY_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 36 | {P11_0, UART_5, CY_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 37 | {P12_0, UART_6, CY_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 38 | {P13_0, UART_6, CY_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 39 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 40 | }; |
| AnnaBridge | 189:f392fc9709a3 | 41 | const PinMap PinMap_UART_TX[] = { |
| AnnaBridge | 189:f392fc9709a3 | 42 | {P0_3, UART_0, CY_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 43 | {P1_1, UART_7, CY_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 44 | {P5_1, UART_5, CY_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 45 | {P6_1, UART_3, CY_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 46 | {P6_5, UART_6, CY_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 47 | {P7_1, UART_4, CY_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 48 | {P8_1, UART_4, CY_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 49 | {P9_1, UART_2, CY_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 50 | {P10_1, UART_1, CY_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 51 | {P11_1, UART_5, CY_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 52 | {P12_1, UART_6, CY_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 53 | {P13_1, UART_6, CY_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 54 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 55 | }; |
| AnnaBridge | 189:f392fc9709a3 | 56 | const PinMap PinMap_UART_RTS[] = { |
| AnnaBridge | 189:f392fc9709a3 | 57 | {P0_4, UART_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 58 | {P1_2, UART_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 59 | {P5_2, UART_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 60 | {P6_2, UART_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 61 | {P6_6, UART_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 62 | {P7_2, UART_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 63 | {P8_2, UART_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 64 | {P9_2, UART_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 65 | {P10_2, UART_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 66 | {P11_2, UART_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 67 | {P12_2, UART_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 68 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 69 | }; |
| AnnaBridge | 189:f392fc9709a3 | 70 | const PinMap PinMap_UART_CTS[] = { |
| AnnaBridge | 189:f392fc9709a3 | 71 | {P0_5, UART_0, CY_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 72 | {P1_3, UART_7, CY_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 73 | {P5_3, UART_5, CY_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 74 | {P6_3, UART_3, CY_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 75 | {P6_7, UART_6, CY_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 76 | {P7_3, UART_4, CY_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 77 | {P8_3, UART_4, CY_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 78 | {P9_3, UART_2, CY_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 79 | {P10_3, UART_1, CY_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 80 | {P11_3, UART_5, CY_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 81 | {P12_3, UART_6, CY_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 82 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 83 | }; |
| AnnaBridge | 189:f392fc9709a3 | 84 | #endif // DEVICE_SERIAL |
| AnnaBridge | 189:f392fc9709a3 | 85 | |
| AnnaBridge | 189:f392fc9709a3 | 86 | |
| AnnaBridge | 189:f392fc9709a3 | 87 | #if DEVICE_I2C |
| AnnaBridge | 189:f392fc9709a3 | 88 | //*** I2C *** |
| AnnaBridge | 189:f392fc9709a3 | 89 | const PinMap PinMap_I2C_SCL[] = { |
| AnnaBridge | 189:f392fc9709a3 | 90 | {P0_2, I2C_0, CY_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 91 | {P1_0, I2C_7, CY_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 92 | {P5_0, I2C_5, CY_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 93 | {P6_0, I2C_3, CY_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 94 | {P6_4, I2C_6, CY_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 95 | {P7_0, I2C_4, CY_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 96 | {P8_0, I2C_4, CY_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 97 | {P9_0, I2C_2, CY_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 98 | {P10_0, I2C_1, CY_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 99 | {P11_0, I2C_5, CY_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 100 | {P12_0, I2C_6, CY_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 101 | {P13_0, I2C_6, CY_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 102 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 103 | }; |
| AnnaBridge | 189:f392fc9709a3 | 104 | const PinMap PinMap_I2C_SDA[] = { |
| AnnaBridge | 189:f392fc9709a3 | 105 | {P0_3, I2C_0, CY_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 106 | {P1_1, I2C_7, CY_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 107 | {P5_1, I2C_5, CY_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 108 | {P6_1, I2C_3, CY_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 109 | {P6_5, I2C_6, CY_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 110 | {P7_1, I2C_4, CY_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 111 | {P8_1, I2C_4, CY_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 112 | {P9_1, I2C_2, CY_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 113 | {P10_1, I2C_1, CY_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 114 | {P11_1, I2C_5, CY_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 115 | {P12_1, I2C_6, CY_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 116 | {P13_1, I2C_6, CY_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 117 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 118 | }; |
| AnnaBridge | 189:f392fc9709a3 | 119 | #endif // DEVICE_I2C |
| AnnaBridge | 189:f392fc9709a3 | 120 | |
| AnnaBridge | 189:f392fc9709a3 | 121 | #if DEVICE_SPI |
| AnnaBridge | 189:f392fc9709a3 | 122 | //*** SPI *** |
| AnnaBridge | 189:f392fc9709a3 | 123 | const PinMap PinMap_SPI_MOSI[] = { |
| AnnaBridge | 189:f392fc9709a3 | 124 | {P0_2, SPI_0, CY_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 125 | {P1_0, SPI_7, CY_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 126 | {P5_0, SPI_5, CY_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 127 | {P6_0, SPI_3, CY_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 128 | {P6_4, SPI_6, CY_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 129 | {P7_0, SPI_4, CY_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 130 | {P8_0, SPI_4, CY_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 131 | {P9_0, SPI_2, CY_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 132 | {P10_0, SPI_1, CY_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 133 | {P11_0, SPI_5, CY_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 134 | {P12_0, SPI_6, CY_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 135 | {P13_0, SPI_6, CY_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 136 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 137 | }; |
| AnnaBridge | 189:f392fc9709a3 | 138 | const PinMap PinMap_SPI_MISO[] = { |
| AnnaBridge | 189:f392fc9709a3 | 139 | {P0_3, SPI_0, CY_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 140 | {P1_1, SPI_7, CY_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 141 | {P5_1, SPI_5, CY_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 142 | {P6_1, SPI_3, CY_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 143 | {P6_5, SPI_6, CY_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 144 | {P7_1, SPI_4, CY_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 145 | {P8_1, SPI_4, CY_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 146 | {P9_1, SPI_2, CY_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 147 | {P10_1, SPI_1, CY_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 148 | {P11_1, SPI_5, CY_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 149 | {P12_1, SPI_6, CY_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 150 | {P13_1, SPI_6, CY_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 151 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 152 | }; |
| AnnaBridge | 189:f392fc9709a3 | 153 | const PinMap PinMap_SPI_SCLK[] = { |
| AnnaBridge | 189:f392fc9709a3 | 154 | {P0_4, SPI_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 155 | {P1_2, SPI_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 156 | {P5_2, SPI_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 157 | {P6_2, SPI_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 158 | {P6_6, SPI_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 159 | {P7_2, SPI_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 160 | |
| AnnaBridge | 189:f392fc9709a3 | 161 | {P8_2, SPI_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 162 | {P9_2, SPI_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 163 | {P10_2, SPI_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 164 | {P11_2, SPI_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 165 | {P12_2, SPI_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 166 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 167 | }; |
| AnnaBridge | 189:f392fc9709a3 | 168 | const PinMap PinMap_SPI_SSEL[] = { |
| AnnaBridge | 189:f392fc9709a3 | 169 | {P0_5, SPI_0, CY_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0, PCLK_SCB0_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 170 | {P1_3, SPI_7, CY_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0, PCLK_SCB7_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 171 | {P5_3, SPI_5, CY_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 172 | {P6_3, SPI_3, CY_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0, PCLK_SCB3_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 173 | {P6_7, SPI_6, CY_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 174 | {P7_3, SPI_4, CY_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 175 | {P8_3, SPI_4, CY_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 176 | {P9_3, SPI_2, CY_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0, PCLK_SCB2_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 177 | {P10_3, SPI_1, CY_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0, PCLK_SCB1_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 178 | {P11_3, SPI_5, CY_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 179 | {P12_3, SPI_6, CY_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)}, |
| AnnaBridge | 189:f392fc9709a3 | 180 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 181 | }; |
| AnnaBridge | 189:f392fc9709a3 | 182 | #endif // DEVICE_SPI |
| AnnaBridge | 189:f392fc9709a3 | 183 | |
| AnnaBridge | 189:f392fc9709a3 | 184 | #if DEVICE_PWMOUT |
| AnnaBridge | 189:f392fc9709a3 | 185 | //*** PWM *** |
| AnnaBridge | 189:f392fc9709a3 | 186 | const PinMap PinMap_PWM_OUT[] = { |
| AnnaBridge | 189:f392fc9709a3 | 187 | // 16-bit PWM outputs |
| AnnaBridge | 189:f392fc9709a3 | 188 | {P0_0, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 189 | {P0_2, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 190 | {P0_4, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 191 | {P1_0, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 192 | {P1_2, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)}, |
| AnnaBridge | 189:f392fc9709a3 | 193 | {P1_4, PWM_16b_13, CY_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)}, |
| AnnaBridge | 189:f392fc9709a3 | 194 | {P5_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 195 | {P5_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 196 | {P5_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 197 | {P5_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 198 | {P6_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)}, |
| AnnaBridge | 189:f392fc9709a3 | 199 | {P6_2, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9, PCLK_TCPWM1_CLOCKS9)}, |
| AnnaBridge | 189:f392fc9709a3 | 200 | {P6_4, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10, PCLK_TCPWM1_CLOCKS10)}, |
| AnnaBridge | 189:f392fc9709a3 | 201 | {P6_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)}, |
| AnnaBridge | 189:f392fc9709a3 | 202 | {P7_0, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)}, |
| AnnaBridge | 189:f392fc9709a3 | 203 | {P7_2, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)}, |
| AnnaBridge | 189:f392fc9709a3 | 204 | {P7_4, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14, PCLK_TCPWM1_CLOCKS14)}, |
| AnnaBridge | 189:f392fc9709a3 | 205 | {P7_6, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15, PCLK_TCPWM1_CLOCKS15)}, |
| AnnaBridge | 189:f392fc9709a3 | 206 | {P8_0, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16, PCLK_TCPWM1_CLOCKS16)}, |
| AnnaBridge | 189:f392fc9709a3 | 207 | {P8_2, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17, PCLK_TCPWM1_CLOCKS17)}, |
| AnnaBridge | 189:f392fc9709a3 | 208 | {P8_4, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18, PCLK_TCPWM1_CLOCKS18)}, |
| AnnaBridge | 189:f392fc9709a3 | 209 | {P8_6, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19, PCLK_TCPWM1_CLOCKS19)}, |
| AnnaBridge | 189:f392fc9709a3 | 210 | {P9_0, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20, PCLK_TCPWM1_CLOCKS20)}, |
| AnnaBridge | 189:f392fc9709a3 | 211 | {P9_2, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21, PCLK_TCPWM1_CLOCKS21)}, |
| AnnaBridge | 189:f392fc9709a3 | 212 | {P9_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 213 | {P9_6, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 214 | {P10_0, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22, PCLK_TCPWM1_CLOCKS22)}, |
| AnnaBridge | 189:f392fc9709a3 | 215 | {P10_2, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23, PCLK_TCPWM1_CLOCKS23)}, |
| AnnaBridge | 189:f392fc9709a3 | 216 | {P10_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 217 | {P10_6, PWM_16b_2, CY_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 218 | {P11_0, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 219 | {P11_2, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 220 | {P11_4, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 221 | {P12_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 222 | {P12_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 223 | {P12_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 224 | {P12_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 225 | {P13_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)}, |
| AnnaBridge | 189:f392fc9709a3 | 226 | {P13_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)}, |
| AnnaBridge | 189:f392fc9709a3 | 227 | // 16-bit PWM inverted outputs |
| AnnaBridge | 189:f392fc9709a3 | 228 | {P0_1, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 229 | {P0_3, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 230 | {P0_5, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 231 | {P1_1, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 232 | {P1_3, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)}, |
| AnnaBridge | 189:f392fc9709a3 | 233 | {P1_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)}, |
| AnnaBridge | 189:f392fc9709a3 | 234 | {P5_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 235 | {P5_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 236 | {P5_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 237 | {P6_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)}, |
| AnnaBridge | 189:f392fc9709a3 | 238 | {P6_3, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9, PCLK_TCPWM1_CLOCKS9)}, |
| AnnaBridge | 189:f392fc9709a3 | 239 | {P6_5, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10, PCLK_TCPWM1_CLOCKS10)}, |
| AnnaBridge | 189:f392fc9709a3 | 240 | {P6_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)}, |
| AnnaBridge | 189:f392fc9709a3 | 241 | {P7_1, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)}, |
| AnnaBridge | 189:f392fc9709a3 | 242 | {P7_3, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13, PCLK_TCPWM1_CLOCKS13)}, |
| AnnaBridge | 189:f392fc9709a3 | 243 | {P7_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)}, |
| AnnaBridge | 189:f392fc9709a3 | 244 | {P7_7, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15, PCLK_TCPWM1_CLOCKS15)}, |
| AnnaBridge | 189:f392fc9709a3 | 245 | {P8_1, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16, PCLK_TCPWM1_CLOCKS16)}, |
| AnnaBridge | 189:f392fc9709a3 | 246 | {P8_3, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17, PCLK_TCPWM1_CLOCKS17)}, |
| AnnaBridge | 189:f392fc9709a3 | 247 | {P8_5, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18, PCLK_TCPWM1_CLOCKS18)}, |
| AnnaBridge | 189:f392fc9709a3 | 248 | {P8_7, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19, PCLK_TCPWM1_CLOCKS19)}, |
| AnnaBridge | 189:f392fc9709a3 | 249 | {P9_1, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20, PCLK_TCPWM1_CLOCKS20)}, |
| AnnaBridge | 189:f392fc9709a3 | 250 | {P9_3, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21, PCLK_TCPWM1_CLOCKS21)}, |
| AnnaBridge | 189:f392fc9709a3 | 251 | {P9_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 252 | {P9_7, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 253 | {P10_1, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22, PCLK_TCPWM1_CLOCKS22)}, |
| AnnaBridge | 189:f392fc9709a3 | 254 | {P10_3, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23, PCLK_TCPWM1_CLOCKS23)}, |
| AnnaBridge | 189:f392fc9709a3 | 255 | {P10_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 256 | {P11_1, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 257 | {P11_3, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 258 | {P11_5, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 259 | {P12_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 260 | {P12_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 261 | {P12_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 262 | {P12_7, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7, PCLK_TCPWM1_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 263 | {P13_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)}, |
| AnnaBridge | 189:f392fc9709a3 | 264 | {P13_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)}, |
| AnnaBridge | 189:f392fc9709a3 | 265 | // 32-bit PWM outputs |
| AnnaBridge | 189:f392fc9709a3 | 266 | {PWM32(P0_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 267 | {PWM32(P0_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 268 | {PWM32(P0_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 269 | {PWM32(P1_0), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 270 | {PWM32(P1_2), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 271 | {PWM32(P1_4), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 272 | {PWM32(P5_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 273 | {PWM32(P5_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 274 | {PWM32(P5_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 275 | {PWM32(P5_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 276 | {PWM32(P6_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 277 | {PWM32(P6_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 278 | {PWM32(P6_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 279 | {PWM32(P6_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 280 | {PWM32(P7_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 281 | {PWM32(P7_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 282 | {PWM32(P7_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 283 | {PWM32(P7_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 284 | {PWM32(P8_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 285 | {PWM32(P8_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 286 | {PWM32(P8_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 287 | {PWM32(P8_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 288 | {PWM32(P9_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 289 | {PWM32(P9_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 290 | {PWM32(P9_4), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 291 | {PWM32(P9_6), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 292 | {PWM32(P10_0), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 293 | {PWM32(P10_2), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 294 | {PWM32(P10_4), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 295 | {PWM32(P10_6), PWM_32b_1, CY_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 296 | {PWM32(P11_0), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 297 | {PWM32(P11_2), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 298 | {PWM32(P11_4), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 299 | {PWM32(P12_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 300 | {PWM32(P12_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 301 | {PWM32(P12_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 302 | {PWM32(P12_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 303 | {PWM32(P13_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 304 | {PWM32(P13_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 305 | // 32-bit PWM inverted outputs |
| AnnaBridge | 189:f392fc9709a3 | 306 | {PWM32(P0_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 307 | {PWM32(P0_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 308 | {PWM32(P0_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 309 | {PWM32(P1_1), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 310 | {PWM32(P1_3), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 311 | {PWM32(P1_5), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 312 | {PWM32(P5_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 313 | {PWM32(P5_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 314 | {PWM32(P5_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 315 | {PWM32(P6_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 316 | {PWM32(P6_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 317 | {PWM32(P6_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 318 | {PWM32(P6_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 319 | {PWM32(P7_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 320 | {PWM32(P7_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 321 | {PWM32(P7_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 322 | {PWM32(P7_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 323 | {PWM32(P8_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 324 | {PWM32(P8_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 325 | {PWM32(P8_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 326 | {PWM32(P8_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 327 | {PWM32(P9_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 328 | {PWM32(P9_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 329 | {PWM32(P9_5), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 330 | {PWM32(P9_7), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 331 | {PWM32(P10_1), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 332 | {PWM32(P10_3), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 333 | {PWM32(P10_5), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 334 | {PWM32(P11_1), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)}, |
| AnnaBridge | 189:f392fc9709a3 | 335 | {PWM32(P11_3), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)}, |
| AnnaBridge | 189:f392fc9709a3 | 336 | {PWM32(P11_5), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 337 | {PWM32(P12_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)}, |
| AnnaBridge | 189:f392fc9709a3 | 338 | {PWM32(P12_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)}, |
| AnnaBridge | 189:f392fc9709a3 | 339 | {PWM32(P12_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)}, |
| AnnaBridge | 189:f392fc9709a3 | 340 | {PWM32(P12_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)}, |
| AnnaBridge | 189:f392fc9709a3 | 341 | {PWM32(P13_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)}, |
| AnnaBridge | 189:f392fc9709a3 | 342 | {PWM32(P13_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)}, |
| AnnaBridge | 189:f392fc9709a3 | 343 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 344 | }; |
| AnnaBridge | 189:f392fc9709a3 | 345 | #endif // DEVICE_PWMOUT |
| AnnaBridge | 189:f392fc9709a3 | 346 | |
| AnnaBridge | 189:f392fc9709a3 | 347 | #if DEVICE_ANALOGIN |
| AnnaBridge | 189:f392fc9709a3 | 348 | const PinMap PinMap_ADC[] = { |
| AnnaBridge | 189:f392fc9709a3 | 349 | {P10_0, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, |
| AnnaBridge | 189:f392fc9709a3 | 350 | {P10_1, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, |
| AnnaBridge | 189:f392fc9709a3 | 351 | {P10_2, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, |
| AnnaBridge | 189:f392fc9709a3 | 352 | {P10_3, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, |
| AnnaBridge | 189:f392fc9709a3 | 353 | {P10_4, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, |
| AnnaBridge | 189:f392fc9709a3 | 354 | {P10_5, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, |
| AnnaBridge | 189:f392fc9709a3 | 355 | {P10_6, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)}, |
| AnnaBridge | 189:f392fc9709a3 | 356 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 357 | }; |
| AnnaBridge | 189:f392fc9709a3 | 358 | #endif // DEVICE_ANALOGIN |
| AnnaBridge | 189:f392fc9709a3 | 359 | |
| AnnaBridge | 189:f392fc9709a3 | 360 | #if DEVICE_ANALOGOUT |
| AnnaBridge | 189:f392fc9709a3 | 361 | const PinMap PinMap_DAC[] = { |
| AnnaBridge | 189:f392fc9709a3 | 362 | {P9_6, DAC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)}, |
| AnnaBridge | 189:f392fc9709a3 | 363 | {P10_5, DAC_0, CY_PIN_FUNCTION(HSIOM_SEL_AMUXA, PCLK_PASS_CLOCK_CTDAC, AnalogMode, 0)}, // CTDAC connects to the P10_5 pin through the AMUXA bus |
| AnnaBridge | 189:f392fc9709a3 | 364 | {NC, NC, 0} |
| AnnaBridge | 189:f392fc9709a3 | 365 | }; |
| AnnaBridge | 189:f392fc9709a3 | 366 | #endif // DEVICE_ANALOGIN |
