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targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 189:f392fc9709a3 | 1 | /******************************************************************************* |
| AnnaBridge | 189:f392fc9709a3 | 2 | * File Name: cycfg_platform.c |
| AnnaBridge | 189:f392fc9709a3 | 3 | * |
| AnnaBridge | 189:f392fc9709a3 | 4 | * Description: |
| AnnaBridge | 189:f392fc9709a3 | 5 | * Platform configuration |
| AnnaBridge | 189:f392fc9709a3 | 6 | * This file was automatically generated and should not be modified. |
| AnnaBridge | 189:f392fc9709a3 | 7 | * |
| AnnaBridge | 189:f392fc9709a3 | 8 | ******************************************************************************** |
| AnnaBridge | 189:f392fc9709a3 | 9 | * Copyright 2017-2019 Cypress Semiconductor Corporation |
| AnnaBridge | 189:f392fc9709a3 | 10 | * SPDX-License-Identifier: Apache-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 11 | * |
| AnnaBridge | 189:f392fc9709a3 | 12 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| AnnaBridge | 189:f392fc9709a3 | 13 | * you may not use this file except in compliance with the License. |
| AnnaBridge | 189:f392fc9709a3 | 14 | * You may obtain a copy of the License at |
| AnnaBridge | 189:f392fc9709a3 | 15 | * |
| AnnaBridge | 189:f392fc9709a3 | 16 | * http://www.apache.org/licenses/LICENSE-2.0 |
| AnnaBridge | 189:f392fc9709a3 | 17 | * |
| AnnaBridge | 189:f392fc9709a3 | 18 | * Unless required by applicable law or agreed to in writing, software |
| AnnaBridge | 189:f392fc9709a3 | 19 | * distributed under the License is distributed on an "AS IS" BASIS, |
| AnnaBridge | 189:f392fc9709a3 | 20 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| AnnaBridge | 189:f392fc9709a3 | 21 | * See the License for the specific language governing permissions and |
| AnnaBridge | 189:f392fc9709a3 | 22 | * limitations under the License. |
| AnnaBridge | 189:f392fc9709a3 | 23 | ********************************************************************************/ |
| AnnaBridge | 189:f392fc9709a3 | 24 | |
| AnnaBridge | 189:f392fc9709a3 | 25 | #include "cycfg_platform.h" |
| AnnaBridge | 189:f392fc9709a3 | 26 | |
| AnnaBridge | 189:f392fc9709a3 | 27 | #define CY_CFG_SYSCLK_ECO_ERROR 1 |
| AnnaBridge | 189:f392fc9709a3 | 28 | #define CY_CFG_SYSCLK_ALTHF_ERROR 2 |
| AnnaBridge | 189:f392fc9709a3 | 29 | #define CY_CFG_SYSCLK_PLL_ERROR 3 |
| AnnaBridge | 189:f392fc9709a3 | 30 | #define CY_CFG_SYSCLK_FLL_ERROR 4 |
| AnnaBridge | 189:f392fc9709a3 | 31 | #define CY_CFG_SYSCLK_WCO_ERROR 5 |
| AnnaBridge | 189:f392fc9709a3 | 32 | #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 33 | #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 34 | #define CY_CFG_SYSCLK_FLL_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 35 | #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 36 | #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL |
| AnnaBridge | 189:f392fc9709a3 | 37 | #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 |
| AnnaBridge | 189:f392fc9709a3 | 38 | #define CY_CFG_SYSCLK_CLKHF2_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 39 | #define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL |
| AnnaBridge | 189:f392fc9709a3 | 40 | #define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 |
| AnnaBridge | 189:f392fc9709a3 | 41 | #define CY_CFG_SYSCLK_ILO_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 42 | #define CY_CFG_SYSCLK_IMO_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 43 | #define CY_CFG_SYSCLK_CLKLF_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 44 | #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 45 | #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO |
| AnnaBridge | 189:f392fc9709a3 | 46 | #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 47 | #define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO |
| AnnaBridge | 189:f392fc9709a3 | 48 | #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 49 | #define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO |
| AnnaBridge | 189:f392fc9709a3 | 50 | #define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 51 | #define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO |
| AnnaBridge | 189:f392fc9709a3 | 52 | #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 53 | #define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO |
| AnnaBridge | 189:f392fc9709a3 | 54 | #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 55 | #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 56 | #define CY_CFG_SYSCLK_WCO_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 57 | #define CY_CFG_PWR_ENABLED 1 |
| AnnaBridge | 189:f392fc9709a3 | 58 | #define CY_CFG_PWR_USING_LDO 1 |
| AnnaBridge | 189:f392fc9709a3 | 59 | #define CY_CFG_PWR_USING_PMIC 0 |
| AnnaBridge | 189:f392fc9709a3 | 60 | #define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD |
| AnnaBridge | 189:f392fc9709a3 | 61 | #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V |
| AnnaBridge | 189:f392fc9709a3 | 62 | #define CY_CFG_PWR_USING_ULP 0 |
| AnnaBridge | 189:f392fc9709a3 | 63 | |
| AnnaBridge | 189:f392fc9709a3 | 64 | static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = |
| AnnaBridge | 189:f392fc9709a3 | 65 | { |
| AnnaBridge | 189:f392fc9709a3 | 66 | .fllMult = 500U, |
| AnnaBridge | 189:f392fc9709a3 | 67 | .refDiv = 20U, |
| AnnaBridge | 189:f392fc9709a3 | 68 | .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, |
| AnnaBridge | 189:f392fc9709a3 | 69 | .enableOutputDiv = true, |
| AnnaBridge | 189:f392fc9709a3 | 70 | .lockTolerance = 10U, |
| AnnaBridge | 189:f392fc9709a3 | 71 | .igain = 9U, |
| AnnaBridge | 189:f392fc9709a3 | 72 | .pgain = 5U, |
| AnnaBridge | 189:f392fc9709a3 | 73 | .settlingCount = 8U, |
| AnnaBridge | 189:f392fc9709a3 | 74 | .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, |
| AnnaBridge | 189:f392fc9709a3 | 75 | .cco_Freq = 355U, |
| AnnaBridge | 189:f392fc9709a3 | 76 | }; |
| AnnaBridge | 189:f392fc9709a3 | 77 | |
| AnnaBridge | 189:f392fc9709a3 | 78 | __WEAK void cycfg_ClockStartupError(uint32_t error) |
| AnnaBridge | 189:f392fc9709a3 | 79 | { |
| AnnaBridge | 189:f392fc9709a3 | 80 | (void)error; /* Suppress the compiler warning */ |
| AnnaBridge | 189:f392fc9709a3 | 81 | while(1); |
| AnnaBridge | 189:f392fc9709a3 | 82 | } |
| AnnaBridge | 189:f392fc9709a3 | 83 | __STATIC_INLINE void Cy_SysClk_ClkBakInit() |
| AnnaBridge | 189:f392fc9709a3 | 84 | { |
| AnnaBridge | 189:f392fc9709a3 | 85 | Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); |
| AnnaBridge | 189:f392fc9709a3 | 86 | } |
| AnnaBridge | 189:f392fc9709a3 | 87 | __STATIC_INLINE void Cy_SysClk_ClkFastInit() |
| AnnaBridge | 189:f392fc9709a3 | 88 | { |
| AnnaBridge | 189:f392fc9709a3 | 89 | Cy_SysClk_ClkFastSetDivider(0U); |
| AnnaBridge | 189:f392fc9709a3 | 90 | } |
| AnnaBridge | 189:f392fc9709a3 | 91 | __STATIC_INLINE void Cy_SysClk_FllInit() |
| AnnaBridge | 189:f392fc9709a3 | 92 | { |
| AnnaBridge | 189:f392fc9709a3 | 93 | if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) |
| AnnaBridge | 189:f392fc9709a3 | 94 | { |
| AnnaBridge | 189:f392fc9709a3 | 95 | cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); |
| AnnaBridge | 189:f392fc9709a3 | 96 | } |
| AnnaBridge | 189:f392fc9709a3 | 97 | if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) |
| AnnaBridge | 189:f392fc9709a3 | 98 | { |
| AnnaBridge | 189:f392fc9709a3 | 99 | cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); |
| AnnaBridge | 189:f392fc9709a3 | 100 | } |
| AnnaBridge | 189:f392fc9709a3 | 101 | } |
| AnnaBridge | 189:f392fc9709a3 | 102 | __STATIC_INLINE void Cy_SysClk_ClkHf0Init() |
| AnnaBridge | 189:f392fc9709a3 | 103 | { |
| AnnaBridge | 189:f392fc9709a3 | 104 | Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); |
| AnnaBridge | 189:f392fc9709a3 | 105 | Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); |
| AnnaBridge | 189:f392fc9709a3 | 106 | } |
| AnnaBridge | 189:f392fc9709a3 | 107 | __STATIC_INLINE void Cy_SysClk_ClkHf2Init() |
| AnnaBridge | 189:f392fc9709a3 | 108 | { |
| AnnaBridge | 189:f392fc9709a3 | 109 | Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH); |
| AnnaBridge | 189:f392fc9709a3 | 110 | Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2); |
| AnnaBridge | 189:f392fc9709a3 | 111 | Cy_SysClk_ClkHfEnable(2U); |
| AnnaBridge | 189:f392fc9709a3 | 112 | } |
| AnnaBridge | 189:f392fc9709a3 | 113 | __STATIC_INLINE void Cy_SysClk_IloInit() |
| AnnaBridge | 189:f392fc9709a3 | 114 | { |
| AnnaBridge | 189:f392fc9709a3 | 115 | /* The WDT is unlocked in the default startup code */ |
| AnnaBridge | 189:f392fc9709a3 | 116 | Cy_SysClk_IloEnable(); |
| AnnaBridge | 189:f392fc9709a3 | 117 | Cy_SysClk_IloHibernateOn(true); |
| AnnaBridge | 189:f392fc9709a3 | 118 | } |
| AnnaBridge | 189:f392fc9709a3 | 119 | __STATIC_INLINE void Cy_SysClk_ClkLfInit() |
| AnnaBridge | 189:f392fc9709a3 | 120 | { |
| AnnaBridge | 189:f392fc9709a3 | 121 | /* The WDT is unlocked in the default startup code */ |
| AnnaBridge | 189:f392fc9709a3 | 122 | Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); |
| AnnaBridge | 189:f392fc9709a3 | 123 | } |
| AnnaBridge | 189:f392fc9709a3 | 124 | __STATIC_INLINE void Cy_SysClk_ClkPath0Init() |
| AnnaBridge | 189:f392fc9709a3 | 125 | { |
| AnnaBridge | 189:f392fc9709a3 | 126 | Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); |
| AnnaBridge | 189:f392fc9709a3 | 127 | } |
| AnnaBridge | 189:f392fc9709a3 | 128 | __STATIC_INLINE void Cy_SysClk_ClkPath1Init() |
| AnnaBridge | 189:f392fc9709a3 | 129 | { |
| AnnaBridge | 189:f392fc9709a3 | 130 | Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); |
| AnnaBridge | 189:f392fc9709a3 | 131 | } |
| AnnaBridge | 189:f392fc9709a3 | 132 | __STATIC_INLINE void Cy_SysClk_ClkPath2Init() |
| AnnaBridge | 189:f392fc9709a3 | 133 | { |
| AnnaBridge | 189:f392fc9709a3 | 134 | Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); |
| AnnaBridge | 189:f392fc9709a3 | 135 | } |
| AnnaBridge | 189:f392fc9709a3 | 136 | __STATIC_INLINE void Cy_SysClk_ClkPath3Init() |
| AnnaBridge | 189:f392fc9709a3 | 137 | { |
| AnnaBridge | 189:f392fc9709a3 | 138 | Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); |
| AnnaBridge | 189:f392fc9709a3 | 139 | } |
| AnnaBridge | 189:f392fc9709a3 | 140 | __STATIC_INLINE void Cy_SysClk_ClkPath4Init() |
| AnnaBridge | 189:f392fc9709a3 | 141 | { |
| AnnaBridge | 189:f392fc9709a3 | 142 | Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); |
| AnnaBridge | 189:f392fc9709a3 | 143 | } |
| AnnaBridge | 189:f392fc9709a3 | 144 | __STATIC_INLINE void Cy_SysClk_ClkPeriInit() |
| AnnaBridge | 189:f392fc9709a3 | 145 | { |
| AnnaBridge | 189:f392fc9709a3 | 146 | Cy_SysClk_ClkPeriSetDivider(1U); |
| AnnaBridge | 189:f392fc9709a3 | 147 | } |
| AnnaBridge | 189:f392fc9709a3 | 148 | __STATIC_INLINE void Cy_SysClk_ClkSlowInit() |
| AnnaBridge | 189:f392fc9709a3 | 149 | { |
| AnnaBridge | 189:f392fc9709a3 | 150 | Cy_SysClk_ClkSlowSetDivider(0U); |
| AnnaBridge | 189:f392fc9709a3 | 151 | } |
| AnnaBridge | 189:f392fc9709a3 | 152 | __STATIC_INLINE void Cy_SysClk_WcoInit() |
| AnnaBridge | 189:f392fc9709a3 | 153 | { |
| AnnaBridge | 189:f392fc9709a3 | 154 | (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); |
| AnnaBridge | 189:f392fc9709a3 | 155 | (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); |
| AnnaBridge | 189:f392fc9709a3 | 156 | if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) |
| AnnaBridge | 189:f392fc9709a3 | 157 | { |
| AnnaBridge | 189:f392fc9709a3 | 158 | cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); |
| AnnaBridge | 189:f392fc9709a3 | 159 | } |
| AnnaBridge | 189:f392fc9709a3 | 160 | } |
| AnnaBridge | 189:f392fc9709a3 | 161 | |
| AnnaBridge | 189:f392fc9709a3 | 162 | |
| AnnaBridge | 189:f392fc9709a3 | 163 | void init_cycfg_platform(void) |
| AnnaBridge | 189:f392fc9709a3 | 164 | { |
| AnnaBridge | 189:f392fc9709a3 | 165 | /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ |
| AnnaBridge | 189:f392fc9709a3 | 166 | Cy_SysLib_SetWaitStates(false, 150UL); |
| AnnaBridge | 189:f392fc9709a3 | 167 | #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD) |
| AnnaBridge | 189:f392fc9709a3 | 168 | if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) |
| AnnaBridge | 189:f392fc9709a3 | 169 | { |
| AnnaBridge | 189:f392fc9709a3 | 170 | Cy_SysLib_ResetBackupDomain(); |
| AnnaBridge | 189:f392fc9709a3 | 171 | Cy_SysClk_IloDisable(); |
| AnnaBridge | 189:f392fc9709a3 | 172 | Cy_SysClk_IloInit(); |
| AnnaBridge | 189:f392fc9709a3 | 173 | } |
| AnnaBridge | 189:f392fc9709a3 | 174 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 175 | #ifdef CY_CFG_PWR_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 176 | /* Configure power mode */ |
| AnnaBridge | 189:f392fc9709a3 | 177 | #if CY_CFG_PWR_USING_LDO |
| AnnaBridge | 189:f392fc9709a3 | 178 | Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE); |
| AnnaBridge | 189:f392fc9709a3 | 179 | #else |
| AnnaBridge | 189:f392fc9709a3 | 180 | Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE); |
| AnnaBridge | 189:f392fc9709a3 | 181 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 182 | /* Configure PMIC */ |
| AnnaBridge | 189:f392fc9709a3 | 183 | Cy_SysPm_UnlockPmic(); |
| AnnaBridge | 189:f392fc9709a3 | 184 | #if CY_CFG_PWR_USING_PMIC |
| AnnaBridge | 189:f392fc9709a3 | 185 | Cy_SysPm_PmicEnableOutput(); |
| AnnaBridge | 189:f392fc9709a3 | 186 | #else |
| AnnaBridge | 189:f392fc9709a3 | 187 | Cy_SysPm_PmicDisableOutput(); |
| AnnaBridge | 189:f392fc9709a3 | 188 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 189 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 190 | |
| AnnaBridge | 189:f392fc9709a3 | 191 | /* Reset the core clock path to default and disable all the FLLs/PLLs */ |
| AnnaBridge | 189:f392fc9709a3 | 192 | Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); |
| AnnaBridge | 189:f392fc9709a3 | 193 | Cy_SysClk_ClkFastSetDivider(0U); |
| AnnaBridge | 189:f392fc9709a3 | 194 | Cy_SysClk_ClkPeriSetDivider(1U); |
| AnnaBridge | 189:f392fc9709a3 | 195 | Cy_SysClk_ClkSlowSetDivider(0U); |
| AnnaBridge | 189:f392fc9709a3 | 196 | Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1); |
| AnnaBridge | 189:f392fc9709a3 | 197 | Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); |
| AnnaBridge | 189:f392fc9709a3 | 198 | |
| AnnaBridge | 189:f392fc9709a3 | 199 | if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && |
| AnnaBridge | 189:f392fc9709a3 | 200 | (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) |
| AnnaBridge | 189:f392fc9709a3 | 201 | { |
| AnnaBridge | 189:f392fc9709a3 | 202 | Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); |
| AnnaBridge | 189:f392fc9709a3 | 203 | } |
| AnnaBridge | 189:f392fc9709a3 | 204 | |
| AnnaBridge | 189:f392fc9709a3 | 205 | Cy_SysClk_FllDisable(); |
| AnnaBridge | 189:f392fc9709a3 | 206 | Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); |
| AnnaBridge | 189:f392fc9709a3 | 207 | Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); |
| AnnaBridge | 189:f392fc9709a3 | 208 | #ifdef CY_IP_MXBLESS |
| AnnaBridge | 189:f392fc9709a3 | 209 | (void)Cy_BLE_EcoReset(); |
| AnnaBridge | 189:f392fc9709a3 | 210 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 211 | |
| AnnaBridge | 189:f392fc9709a3 | 212 | #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 213 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2); |
| AnnaBridge | 189:f392fc9709a3 | 214 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 215 | |
| AnnaBridge | 189:f392fc9709a3 | 216 | #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 217 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3); |
| AnnaBridge | 189:f392fc9709a3 | 218 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 219 | |
| AnnaBridge | 189:f392fc9709a3 | 220 | #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 221 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4); |
| AnnaBridge | 189:f392fc9709a3 | 222 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 223 | |
| AnnaBridge | 189:f392fc9709a3 | 224 | #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 225 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5); |
| AnnaBridge | 189:f392fc9709a3 | 226 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 227 | |
| AnnaBridge | 189:f392fc9709a3 | 228 | #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 229 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6); |
| AnnaBridge | 189:f392fc9709a3 | 230 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 231 | |
| AnnaBridge | 189:f392fc9709a3 | 232 | #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 233 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7); |
| AnnaBridge | 189:f392fc9709a3 | 234 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 235 | |
| AnnaBridge | 189:f392fc9709a3 | 236 | #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 237 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8); |
| AnnaBridge | 189:f392fc9709a3 | 238 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 239 | |
| AnnaBridge | 189:f392fc9709a3 | 240 | #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 241 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9); |
| AnnaBridge | 189:f392fc9709a3 | 242 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 243 | |
| AnnaBridge | 189:f392fc9709a3 | 244 | #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 245 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10); |
| AnnaBridge | 189:f392fc9709a3 | 246 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 247 | |
| AnnaBridge | 189:f392fc9709a3 | 248 | #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 249 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11); |
| AnnaBridge | 189:f392fc9709a3 | 250 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 251 | |
| AnnaBridge | 189:f392fc9709a3 | 252 | #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 253 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12); |
| AnnaBridge | 189:f392fc9709a3 | 254 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 255 | |
| AnnaBridge | 189:f392fc9709a3 | 256 | #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 257 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13); |
| AnnaBridge | 189:f392fc9709a3 | 258 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 259 | |
| AnnaBridge | 189:f392fc9709a3 | 260 | #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 261 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14); |
| AnnaBridge | 189:f392fc9709a3 | 262 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 263 | |
| AnnaBridge | 189:f392fc9709a3 | 264 | #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE |
| AnnaBridge | 189:f392fc9709a3 | 265 | (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15); |
| AnnaBridge | 189:f392fc9709a3 | 266 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 267 | |
| AnnaBridge | 189:f392fc9709a3 | 268 | /* Enable all source clocks */ |
| AnnaBridge | 189:f392fc9709a3 | 269 | #ifdef CY_CFG_SYSCLK_PILO_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 270 | Cy_SysClk_PiloInit(); |
| AnnaBridge | 189:f392fc9709a3 | 271 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 272 | |
| AnnaBridge | 189:f392fc9709a3 | 273 | #ifdef CY_CFG_SYSCLK_WCO_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 274 | Cy_SysClk_WcoInit(); |
| AnnaBridge | 189:f392fc9709a3 | 275 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 276 | |
| AnnaBridge | 189:f392fc9709a3 | 277 | #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 278 | Cy_SysClk_ClkLfInit(); |
| AnnaBridge | 189:f392fc9709a3 | 279 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 280 | |
| AnnaBridge | 189:f392fc9709a3 | 281 | #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 282 | Cy_SysClk_AltHfInit(); |
| AnnaBridge | 189:f392fc9709a3 | 283 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 284 | |
| AnnaBridge | 189:f392fc9709a3 | 285 | #ifdef CY_CFG_SYSCLK_ECO_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 286 | Cy_SysClk_EcoInit(); |
| AnnaBridge | 189:f392fc9709a3 | 287 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 288 | |
| AnnaBridge | 189:f392fc9709a3 | 289 | #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 290 | Cy_SysClk_ExtClkInit(); |
| AnnaBridge | 189:f392fc9709a3 | 291 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 292 | |
| AnnaBridge | 189:f392fc9709a3 | 293 | /* Configure CPU clock dividers */ |
| AnnaBridge | 189:f392fc9709a3 | 294 | #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 295 | Cy_SysClk_ClkFastInit(); |
| AnnaBridge | 189:f392fc9709a3 | 296 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 297 | |
| AnnaBridge | 189:f392fc9709a3 | 298 | #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 299 | Cy_SysClk_ClkPeriInit(); |
| AnnaBridge | 189:f392fc9709a3 | 300 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 301 | |
| AnnaBridge | 189:f392fc9709a3 | 302 | #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 303 | Cy_SysClk_ClkSlowInit(); |
| AnnaBridge | 189:f392fc9709a3 | 304 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 305 | |
| AnnaBridge | 189:f392fc9709a3 | 306 | #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) |
| AnnaBridge | 189:f392fc9709a3 | 307 | /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ |
| AnnaBridge | 189:f392fc9709a3 | 308 | Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); |
| AnnaBridge | 189:f392fc9709a3 | 309 | Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); |
| AnnaBridge | 189:f392fc9709a3 | 310 | #else |
| AnnaBridge | 189:f392fc9709a3 | 311 | #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 312 | Cy_SysClk_ClkPath1Init(); |
| AnnaBridge | 189:f392fc9709a3 | 313 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 314 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 315 | |
| AnnaBridge | 189:f392fc9709a3 | 316 | /* Configure Path Clocks */ |
| AnnaBridge | 189:f392fc9709a3 | 317 | #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 318 | Cy_SysClk_ClkPath0Init(); |
| AnnaBridge | 189:f392fc9709a3 | 319 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 320 | #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 321 | Cy_SysClk_ClkPath2Init(); |
| AnnaBridge | 189:f392fc9709a3 | 322 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 323 | #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 324 | Cy_SysClk_ClkPath3Init(); |
| AnnaBridge | 189:f392fc9709a3 | 325 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 326 | #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 327 | Cy_SysClk_ClkPath4Init(); |
| AnnaBridge | 189:f392fc9709a3 | 328 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 329 | #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 330 | Cy_SysClk_ClkPath5Init(); |
| AnnaBridge | 189:f392fc9709a3 | 331 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 332 | #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 333 | Cy_SysClk_ClkPath6Init(); |
| AnnaBridge | 189:f392fc9709a3 | 334 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 335 | #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 336 | Cy_SysClk_ClkPath7Init(); |
| AnnaBridge | 189:f392fc9709a3 | 337 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 338 | #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 339 | Cy_SysClk_ClkPath8Init(); |
| AnnaBridge | 189:f392fc9709a3 | 340 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 341 | #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 342 | Cy_SysClk_ClkPath9Init(); |
| AnnaBridge | 189:f392fc9709a3 | 343 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 344 | #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 345 | Cy_SysClk_ClkPath10Init(); |
| AnnaBridge | 189:f392fc9709a3 | 346 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 347 | #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 348 | Cy_SysClk_ClkPath11Init(); |
| AnnaBridge | 189:f392fc9709a3 | 349 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 350 | #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 351 | Cy_SysClk_ClkPath12Init(); |
| AnnaBridge | 189:f392fc9709a3 | 352 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 353 | #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 354 | Cy_SysClk_ClkPath13Init(); |
| AnnaBridge | 189:f392fc9709a3 | 355 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 356 | #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 357 | Cy_SysClk_ClkPath14Init(); |
| AnnaBridge | 189:f392fc9709a3 | 358 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 359 | #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 360 | Cy_SysClk_ClkPath15Init(); |
| AnnaBridge | 189:f392fc9709a3 | 361 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 362 | |
| AnnaBridge | 189:f392fc9709a3 | 363 | /* Configure and enable FLL */ |
| AnnaBridge | 189:f392fc9709a3 | 364 | #ifdef CY_CFG_SYSCLK_FLL_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 365 | Cy_SysClk_FllInit(); |
| AnnaBridge | 189:f392fc9709a3 | 366 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 367 | |
| AnnaBridge | 189:f392fc9709a3 | 368 | Cy_SysClk_ClkHf0Init(); |
| AnnaBridge | 189:f392fc9709a3 | 369 | |
| AnnaBridge | 189:f392fc9709a3 | 370 | #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) |
| AnnaBridge | 189:f392fc9709a3 | 371 | #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 372 | /* Apply the ClkPath1 user setting */ |
| AnnaBridge | 189:f392fc9709a3 | 373 | Cy_SysClk_ClkPath1Init(); |
| AnnaBridge | 189:f392fc9709a3 | 374 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 375 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 376 | |
| AnnaBridge | 189:f392fc9709a3 | 377 | /* Configure and enable PLLs */ |
| AnnaBridge | 189:f392fc9709a3 | 378 | #ifdef CY_CFG_SYSCLK_PLL0_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 379 | Cy_SysClk_Pll0Init(); |
| AnnaBridge | 189:f392fc9709a3 | 380 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 381 | #ifdef CY_CFG_SYSCLK_PLL1_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 382 | Cy_SysClk_Pll1Init(); |
| AnnaBridge | 189:f392fc9709a3 | 383 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 384 | #ifdef CY_CFG_SYSCLK_PLL2_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 385 | Cy_SysClk_Pll2Init(); |
| AnnaBridge | 189:f392fc9709a3 | 386 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 387 | #ifdef CY_CFG_SYSCLK_PLL3_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 388 | Cy_SysClk_Pll3Init(); |
| AnnaBridge | 189:f392fc9709a3 | 389 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 390 | #ifdef CY_CFG_SYSCLK_PLL4_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 391 | Cy_SysClk_Pll4Init(); |
| AnnaBridge | 189:f392fc9709a3 | 392 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 393 | #ifdef CY_CFG_SYSCLK_PLL5_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 394 | Cy_SysClk_Pll5Init(); |
| AnnaBridge | 189:f392fc9709a3 | 395 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 396 | #ifdef CY_CFG_SYSCLK_PLL6_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 397 | Cy_SysClk_Pll6Init(); |
| AnnaBridge | 189:f392fc9709a3 | 398 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 399 | #ifdef CY_CFG_SYSCLK_PLL7_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 400 | Cy_SysClk_Pll7Init(); |
| AnnaBridge | 189:f392fc9709a3 | 401 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 402 | #ifdef CY_CFG_SYSCLK_PLL8_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 403 | Cy_SysClk_Pll8Init(); |
| AnnaBridge | 189:f392fc9709a3 | 404 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 405 | #ifdef CY_CFG_SYSCLK_PLL9_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 406 | Cy_SysClk_Pll9Init(); |
| AnnaBridge | 189:f392fc9709a3 | 407 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 408 | #ifdef CY_CFG_SYSCLK_PLL10_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 409 | Cy_SysClk_Pll10Init(); |
| AnnaBridge | 189:f392fc9709a3 | 410 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 411 | #ifdef CY_CFG_SYSCLK_PLL11_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 412 | Cy_SysClk_Pll11Init(); |
| AnnaBridge | 189:f392fc9709a3 | 413 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 414 | #ifdef CY_CFG_SYSCLK_PLL12_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 415 | Cy_SysClk_Pll12Init(); |
| AnnaBridge | 189:f392fc9709a3 | 416 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 417 | #ifdef CY_CFG_SYSCLK_PLL13_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 418 | Cy_SysClk_Pll13Init(); |
| AnnaBridge | 189:f392fc9709a3 | 419 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 420 | #ifdef CY_CFG_SYSCLK_PLL14_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 421 | Cy_SysClk_Pll14Init(); |
| AnnaBridge | 189:f392fc9709a3 | 422 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 423 | |
| AnnaBridge | 189:f392fc9709a3 | 424 | /* Configure HF clocks */ |
| AnnaBridge | 189:f392fc9709a3 | 425 | #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 426 | Cy_SysClk_ClkHf1Init(); |
| AnnaBridge | 189:f392fc9709a3 | 427 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 428 | #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 429 | Cy_SysClk_ClkHf2Init(); |
| AnnaBridge | 189:f392fc9709a3 | 430 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 431 | #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 432 | Cy_SysClk_ClkHf3Init(); |
| AnnaBridge | 189:f392fc9709a3 | 433 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 434 | #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 435 | Cy_SysClk_ClkHf4Init(); |
| AnnaBridge | 189:f392fc9709a3 | 436 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 437 | #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 438 | Cy_SysClk_ClkHf5Init(); |
| AnnaBridge | 189:f392fc9709a3 | 439 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 440 | #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 441 | Cy_SysClk_ClkHf6Init(); |
| AnnaBridge | 189:f392fc9709a3 | 442 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 443 | #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 444 | Cy_SysClk_ClkHf7Init(); |
| AnnaBridge | 189:f392fc9709a3 | 445 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 446 | #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 447 | Cy_SysClk_ClkHf8Init(); |
| AnnaBridge | 189:f392fc9709a3 | 448 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 449 | #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 450 | Cy_SysClk_ClkHf9Init(); |
| AnnaBridge | 189:f392fc9709a3 | 451 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 452 | #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 453 | Cy_SysClk_ClkHf10Init(); |
| AnnaBridge | 189:f392fc9709a3 | 454 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 455 | #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 456 | Cy_SysClk_ClkHf11Init(); |
| AnnaBridge | 189:f392fc9709a3 | 457 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 458 | #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 459 | Cy_SysClk_ClkHf12Init(); |
| AnnaBridge | 189:f392fc9709a3 | 460 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 461 | #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 462 | Cy_SysClk_ClkHf13Init(); |
| AnnaBridge | 189:f392fc9709a3 | 463 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 464 | #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 465 | Cy_SysClk_ClkHf14Init(); |
| AnnaBridge | 189:f392fc9709a3 | 466 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 467 | #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 468 | Cy_SysClk_ClkHf15Init(); |
| AnnaBridge | 189:f392fc9709a3 | 469 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 470 | |
| AnnaBridge | 189:f392fc9709a3 | 471 | /* Configure miscellaneous clocks */ |
| AnnaBridge | 189:f392fc9709a3 | 472 | #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 473 | Cy_SysClk_ClkTimerInit(); |
| AnnaBridge | 189:f392fc9709a3 | 474 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 475 | |
| AnnaBridge | 189:f392fc9709a3 | 476 | #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 477 | Cy_SysClk_ClkAltSysTickInit(); |
| AnnaBridge | 189:f392fc9709a3 | 478 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 479 | |
| AnnaBridge | 189:f392fc9709a3 | 480 | #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 481 | Cy_SysClk_ClkPumpInit(); |
| AnnaBridge | 189:f392fc9709a3 | 482 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 483 | |
| AnnaBridge | 189:f392fc9709a3 | 484 | #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 485 | Cy_SysClk_ClkBakInit(); |
| AnnaBridge | 189:f392fc9709a3 | 486 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 487 | |
| AnnaBridge | 189:f392fc9709a3 | 488 | /* Configure default enabled clocks */ |
| AnnaBridge | 189:f392fc9709a3 | 489 | #ifdef CY_CFG_SYSCLK_ILO_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 490 | Cy_SysClk_IloInit(); |
| AnnaBridge | 189:f392fc9709a3 | 491 | #else |
| AnnaBridge | 189:f392fc9709a3 | 492 | Cy_SysClk_IloDisable(); |
| AnnaBridge | 189:f392fc9709a3 | 493 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 494 | |
| AnnaBridge | 189:f392fc9709a3 | 495 | #ifndef CY_CFG_SYSCLK_IMO_ENABLED |
| AnnaBridge | 189:f392fc9709a3 | 496 | #error the IMO must be enabled for proper chip operation |
| AnnaBridge | 189:f392fc9709a3 | 497 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 498 | |
| AnnaBridge | 189:f392fc9709a3 | 499 | /* Set accurate flash wait states */ |
| AnnaBridge | 189:f392fc9709a3 | 500 | #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) |
| AnnaBridge | 189:f392fc9709a3 | 501 | Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); |
| AnnaBridge | 189:f392fc9709a3 | 502 | #endif |
| AnnaBridge | 189:f392fc9709a3 | 503 | |
| AnnaBridge | 189:f392fc9709a3 | 504 | /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ |
| AnnaBridge | 189:f392fc9709a3 | 505 | SystemCoreClockUpdate(); |
| AnnaBridge | 189:f392fc9709a3 | 506 | } |
