mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ARM_SSG/TARGET_IOTSS/spi_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
170:19eb464bc2be 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 80:bdf1132a57cf 1 /* mbed Microcontroller Library
mbed_official 80:bdf1132a57cf 2 * Copyright (c) 2006-2015 ARM Limited
mbed_official 80:bdf1132a57cf 3 *
mbed_official 80:bdf1132a57cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 80:bdf1132a57cf 5 * you may not use this file except in compliance with the License.
mbed_official 80:bdf1132a57cf 6 * You may obtain a copy of the License at
mbed_official 80:bdf1132a57cf 7 *
mbed_official 80:bdf1132a57cf 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 80:bdf1132a57cf 9 *
mbed_official 80:bdf1132a57cf 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 80:bdf1132a57cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 80:bdf1132a57cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 80:bdf1132a57cf 13 * See the License for the specific language governing permissions and
mbed_official 80:bdf1132a57cf 14 * limitations under the License.
mbed_official 80:bdf1132a57cf 15 */
mbed_official 80:bdf1132a57cf 16 #include <math.h>
mbed_official 80:bdf1132a57cf 17
mbed_official 80:bdf1132a57cf 18 #include "spi_api.h"
mbed_official 80:bdf1132a57cf 19 #include "spi_def.h"
mbed_official 80:bdf1132a57cf 20 #include "cmsis.h"
mbed_official 80:bdf1132a57cf 21 #include "pinmap.h"
mbed_official 80:bdf1132a57cf 22 #include "mbed_error.h"
<> 160:d5399cc887bb 23 #include "mbed_wait_api.h"
mbed_official 80:bdf1132a57cf 24
mbed_official 80:bdf1132a57cf 25 static const PinMap PinMap_SPI_SCLK[] = {
mbed_official 80:bdf1132a57cf 26 {SCLK_SPI , SPI_0, 0},
mbed_official 80:bdf1132a57cf 27 {CLCD_SCLK , SPI_1, 0},
mbed_official 80:bdf1132a57cf 28 {ADC_SCLK , SPI_2, 0},
mbed_official 80:bdf1132a57cf 29 {SHIELD_0_SPI_SCK , SPI_3, 0},
mbed_official 80:bdf1132a57cf 30 {SHIELD_1_SPI_SCK , SPI_4, 0},
mbed_official 80:bdf1132a57cf 31 {NC , NC , 0}
mbed_official 80:bdf1132a57cf 32 };
mbed_official 80:bdf1132a57cf 33
mbed_official 80:bdf1132a57cf 34 static const PinMap PinMap_SPI_MOSI[] = {
mbed_official 80:bdf1132a57cf 35 {MOSI_SPI, SPI_0, 0},
mbed_official 80:bdf1132a57cf 36 {CLCD_MOSI, SPI_1, 0},
mbed_official 80:bdf1132a57cf 37 {ADC_MOSI, SPI_2, 0},
mbed_official 80:bdf1132a57cf 38 {SHIELD_0_SPI_MOSI, SPI_3, 0},
mbed_official 80:bdf1132a57cf 39 {SHIELD_1_SPI_MOSI, SPI_4, 0},
mbed_official 80:bdf1132a57cf 40 {NC , NC , 0}
mbed_official 80:bdf1132a57cf 41 };
mbed_official 80:bdf1132a57cf 42
mbed_official 80:bdf1132a57cf 43 static const PinMap PinMap_SPI_MISO[] = {
mbed_official 80:bdf1132a57cf 44 {MISO_SPI, SPI_0, 0},
mbed_official 80:bdf1132a57cf 45 {CLCD_MISO, SPI_1, 0},
mbed_official 80:bdf1132a57cf 46 {ADC_MISO, SPI_2, 0},
mbed_official 80:bdf1132a57cf 47 {SHIELD_0_SPI_MISO, SPI_3, 0},
mbed_official 80:bdf1132a57cf 48 {SHIELD_1_SPI_MISO, SPI_4, 0},
mbed_official 80:bdf1132a57cf 49 {NC , NC , 0}
mbed_official 80:bdf1132a57cf 50 };
mbed_official 80:bdf1132a57cf 51
mbed_official 80:bdf1132a57cf 52 static const PinMap PinMap_SPI_SSEL[] = {
mbed_official 80:bdf1132a57cf 53 {SSEL_SPI, SPI_0, 0},
mbed_official 80:bdf1132a57cf 54 {CLCD_SSEL, SPI_1, 0},
mbed_official 80:bdf1132a57cf 55 {ADC_SSEL, SPI_2, 0},
mbed_official 80:bdf1132a57cf 56 {SHIELD_0_SPI_nCS, SPI_3, 0},
mbed_official 80:bdf1132a57cf 57 {SHIELD_1_SPI_nCS, SPI_4, 0},
mbed_official 80:bdf1132a57cf 58 {NC , NC , 0}
mbed_official 80:bdf1132a57cf 59 };
mbed_official 80:bdf1132a57cf 60
mbed_official 80:bdf1132a57cf 61 static inline int ssp_disable(spi_t *obj);
mbed_official 80:bdf1132a57cf 62 static inline int ssp_enable(spi_t *obj);
mbed_official 80:bdf1132a57cf 63
mbed_official 80:bdf1132a57cf 64 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 80:bdf1132a57cf 65
mbed_official 80:bdf1132a57cf 66 int altfunction[4];
mbed_official 80:bdf1132a57cf 67 // determine the SPI to use
mbed_official 80:bdf1132a57cf 68 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 80:bdf1132a57cf 69 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 80:bdf1132a57cf 70 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 80:bdf1132a57cf 71 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 80:bdf1132a57cf 72 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
mbed_official 80:bdf1132a57cf 73 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
mbed_official 80:bdf1132a57cf 74 obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
mbed_official 80:bdf1132a57cf 75 if ((int)obj->spi == NC) {
mbed_official 80:bdf1132a57cf 76 error("SPI pinout mapping failed");
mbed_official 80:bdf1132a57cf 77 }
mbed_official 80:bdf1132a57cf 78
mbed_official 80:bdf1132a57cf 79 // enable power and clocking
mbed_official 80:bdf1132a57cf 80 switch ((int)obj->spi) {
mbed_official 80:bdf1132a57cf 81 case (int)SPI_0:
mbed_official 80:bdf1132a57cf 82 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 83 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 84 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 85 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 86 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 87 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 88 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 89 break;
mbed_official 80:bdf1132a57cf 90 case (int)SPI_1:
mbed_official 80:bdf1132a57cf 91 /* Configure SSP used for LCD */
mbed_official 80:bdf1132a57cf 92 obj->spi->CR1 = 0; /* Synchronous serial port disable */
mbed_official 80:bdf1132a57cf 93 obj->spi->DMACR = 0; /* Disable FIFO DMA */
mbed_official 80:bdf1132a57cf 94 obj->spi->IMSC = 0; /* Mask all FIFO/IRQ interrupts */
mbed_official 80:bdf1132a57cf 95 obj->spi->ICR = ((1ul << 0) | /* Clear SSPRORINTR interrupt */
mbed_official 80:bdf1132a57cf 96 (1ul << 1) ); /* Clear SSPRTINTR interrupt */
mbed_official 80:bdf1132a57cf 97 obj->spi->CR0 = ((7ul << 0) | /* 8 bit data size */
mbed_official 80:bdf1132a57cf 98 (0ul << 4) | /* Motorola frame format */
mbed_official 80:bdf1132a57cf 99 (0ul << 6) | /* CPOL = 0 */
mbed_official 80:bdf1132a57cf 100 (0ul << 7) | /* CPHA = 0 */
mbed_official 80:bdf1132a57cf 101 (1ul << 8) ); /* Set serial clock rate */
mbed_official 80:bdf1132a57cf 102 obj->spi->CPSR = (2ul << 0); /* set SSP clk to 6MHz (6.6MHz max) */
mbed_official 80:bdf1132a57cf 103 obj->spi->CR1 = ((1ul << 1) | /* Synchronous serial port enable */
mbed_official 80:bdf1132a57cf 104 (0ul << 2) ); /* Device configured as master */
mbed_official 80:bdf1132a57cf 105 break;
mbed_official 80:bdf1132a57cf 106 case (int)SPI_2:
mbed_official 80:bdf1132a57cf 107 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 108 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 109 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 110 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 111 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 112 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 113 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 114 break;
mbed_official 80:bdf1132a57cf 115 case (int)SPI_3:
mbed_official 80:bdf1132a57cf 116 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 117 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 118 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 119 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 120 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 121 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 122 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 123 break;
mbed_official 80:bdf1132a57cf 124 case (int)SPI_4:
mbed_official 80:bdf1132a57cf 125 obj->spi->CR1 = 0;
mbed_official 80:bdf1132a57cf 126 obj->spi->CR0 = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
mbed_official 80:bdf1132a57cf 127 obj->spi->CPSR = SSP_CPSR_DFLT;
mbed_official 80:bdf1132a57cf 128 obj->spi->IMSC = 0x8;
mbed_official 80:bdf1132a57cf 129 obj->spi->DMACR = 0;
mbed_official 80:bdf1132a57cf 130 obj->spi->CR1 = SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 131 obj->spi->ICR = 0x3;
mbed_official 80:bdf1132a57cf 132 break;
mbed_official 80:bdf1132a57cf 133 }
mbed_official 80:bdf1132a57cf 134
mbed_official 80:bdf1132a57cf 135 if(mosi != NC){ altfunction[0] = 1;}else{ altfunction[0] = 0;}
mbed_official 80:bdf1132a57cf 136 if(miso != NC){ altfunction[1] = 1;}else{ altfunction[1] = 0;}
mbed_official 80:bdf1132a57cf 137 if(sclk != NC){ altfunction[2] = 1;}else{ altfunction[2] = 0;}
mbed_official 80:bdf1132a57cf 138 if(ssel != NC){ altfunction[3] = 1;}else{ altfunction[3] = 0;}
mbed_official 80:bdf1132a57cf 139
mbed_official 80:bdf1132a57cf 140 // enable alt function
mbed_official 80:bdf1132a57cf 141 switch ((int)obj->spi) {
mbed_official 80:bdf1132a57cf 142 case (int)SPI_2:
mbed_official 80:bdf1132a57cf 143 CMSDK_GPIO1->ALTFUNCSET |= (altfunction[2]<<5 | altfunction[0]<<4 | altfunction[1]<<3 | altfunction[3]<<2);
mbed_official 80:bdf1132a57cf 144 break;
mbed_official 80:bdf1132a57cf 145 case (int)SPI_3:
mbed_official 80:bdf1132a57cf 146 CMSDK_GPIO0->ALTFUNCSET |= (altfunction[2]<<13 | altfunction[1]<<12 | altfunction[0]<<11 | altfunction[3]<<10);
mbed_official 80:bdf1132a57cf 147 break;
mbed_official 80:bdf1132a57cf 148 case (int)SPI_4:
mbed_official 80:bdf1132a57cf 149 CMSDK_GPIO4->ALTFUNCSET |= (altfunction[2]<<3 | altfunction[1]<<2 | altfunction[0]<<1 | altfunction[3]);
mbed_official 80:bdf1132a57cf 150 break;
mbed_official 80:bdf1132a57cf 151 }
mbed_official 80:bdf1132a57cf 152
mbed_official 80:bdf1132a57cf 153 // set default format and frequency
mbed_official 80:bdf1132a57cf 154 if (ssel == NC) {
mbed_official 80:bdf1132a57cf 155 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
mbed_official 80:bdf1132a57cf 156 } else {
mbed_official 80:bdf1132a57cf 157 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
mbed_official 80:bdf1132a57cf 158 }
mbed_official 80:bdf1132a57cf 159 spi_frequency(obj, 1000000);
mbed_official 80:bdf1132a57cf 160
mbed_official 80:bdf1132a57cf 161 // enable the ssp channel
mbed_official 80:bdf1132a57cf 162 ssp_enable(obj);
mbed_official 80:bdf1132a57cf 163
mbed_official 80:bdf1132a57cf 164 // pin out the spi pins
mbed_official 80:bdf1132a57cf 165 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 80:bdf1132a57cf 166 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 80:bdf1132a57cf 167 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 80:bdf1132a57cf 168 if (ssel != NC) {
mbed_official 80:bdf1132a57cf 169 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 80:bdf1132a57cf 170 }
mbed_official 80:bdf1132a57cf 171 }
mbed_official 80:bdf1132a57cf 172
mbed_official 80:bdf1132a57cf 173 void spi_free(spi_t *obj) {}
mbed_official 80:bdf1132a57cf 174
mbed_official 80:bdf1132a57cf 175 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 80:bdf1132a57cf 176 ssp_disable(obj);
mbed_official 80:bdf1132a57cf 177 if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
mbed_official 80:bdf1132a57cf 178 error("SPI format error");
mbed_official 80:bdf1132a57cf 179 }
mbed_official 80:bdf1132a57cf 180
mbed_official 80:bdf1132a57cf 181 int polarity = (mode & 0x2) ? 1 : 0;
mbed_official 80:bdf1132a57cf 182 int phase = (mode & 0x1) ? 1 : 0;
mbed_official 80:bdf1132a57cf 183
mbed_official 80:bdf1132a57cf 184 // set it up
mbed_official 80:bdf1132a57cf 185 int DSS = bits - 1; // DSS (data select size)
mbed_official 80:bdf1132a57cf 186 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
mbed_official 80:bdf1132a57cf 187 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
mbed_official 80:bdf1132a57cf 188
mbed_official 80:bdf1132a57cf 189 int FRF = 0; // FRF (frame format) = SPI
mbed_official 80:bdf1132a57cf 190 uint32_t tmp = obj->spi->CR0;
mbed_official 80:bdf1132a57cf 191 tmp &= ~(0xFFFF);
mbed_official 80:bdf1132a57cf 192 tmp |= DSS << 0
mbed_official 80:bdf1132a57cf 193 | FRF << 4
mbed_official 80:bdf1132a57cf 194 | SPO << 6
mbed_official 80:bdf1132a57cf 195 | SPH << 7;
mbed_official 80:bdf1132a57cf 196 obj->spi->CR0 = tmp;
mbed_official 80:bdf1132a57cf 197
mbed_official 80:bdf1132a57cf 198 tmp = obj->spi->CR1;
mbed_official 80:bdf1132a57cf 199 tmp &= ~(0xD);
mbed_official 80:bdf1132a57cf 200 tmp |= 0 << 0 // LBM - loop back mode - off
mbed_official 80:bdf1132a57cf 201 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
mbed_official 80:bdf1132a57cf 202 | 0 << 3; // SOD - slave output disable - na
mbed_official 80:bdf1132a57cf 203 obj->spi->CR1 = tmp;
mbed_official 80:bdf1132a57cf 204
mbed_official 80:bdf1132a57cf 205 ssp_enable(obj);
mbed_official 80:bdf1132a57cf 206 }
mbed_official 80:bdf1132a57cf 207
mbed_official 80:bdf1132a57cf 208 void spi_frequency(spi_t *obj, int hz) {
mbed_official 80:bdf1132a57cf 209 ssp_disable(obj);
mbed_official 80:bdf1132a57cf 210
mbed_official 80:bdf1132a57cf 211 uint32_t PCLK = SystemCoreClock;
mbed_official 80:bdf1132a57cf 212
mbed_official 80:bdf1132a57cf 213 int prescaler;
mbed_official 80:bdf1132a57cf 214
mbed_official 80:bdf1132a57cf 215 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
mbed_official 80:bdf1132a57cf 216 int prescale_hz = PCLK / prescaler;
mbed_official 80:bdf1132a57cf 217
mbed_official 80:bdf1132a57cf 218 // calculate the divider
mbed_official 80:bdf1132a57cf 219 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
mbed_official 80:bdf1132a57cf 220
mbed_official 80:bdf1132a57cf 221 // check we can support the divider
mbed_official 80:bdf1132a57cf 222 if (divider < 256) {
mbed_official 80:bdf1132a57cf 223 // prescaler
mbed_official 80:bdf1132a57cf 224 obj->spi->CPSR = prescaler;
mbed_official 80:bdf1132a57cf 225
mbed_official 80:bdf1132a57cf 226 // divider
mbed_official 80:bdf1132a57cf 227 obj->spi->CR0 &= ~(0xFFFF << 8);
mbed_official 80:bdf1132a57cf 228 obj->spi->CR0 |= (divider - 1) << 8;
mbed_official 80:bdf1132a57cf 229 ssp_enable(obj);
mbed_official 80:bdf1132a57cf 230 return;
mbed_official 80:bdf1132a57cf 231 }
mbed_official 80:bdf1132a57cf 232 }
mbed_official 80:bdf1132a57cf 233 error("Couldn't setup requested SPI frequency");
mbed_official 80:bdf1132a57cf 234 }
mbed_official 80:bdf1132a57cf 235
mbed_official 80:bdf1132a57cf 236 static inline int ssp_disable(spi_t *obj) {
mbed_official 80:bdf1132a57cf 237 return obj->spi->CR1 &= ~(1 << 1);
mbed_official 80:bdf1132a57cf 238 }
mbed_official 80:bdf1132a57cf 239
mbed_official 80:bdf1132a57cf 240 static inline int ssp_enable(spi_t *obj) {
mbed_official 80:bdf1132a57cf 241 return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
mbed_official 80:bdf1132a57cf 242 }
mbed_official 80:bdf1132a57cf 243
mbed_official 80:bdf1132a57cf 244 static inline int ssp_readable(spi_t *obj) {
mbed_official 80:bdf1132a57cf 245 return obj->spi->SR & (1 << 2);
mbed_official 80:bdf1132a57cf 246 }
mbed_official 80:bdf1132a57cf 247
mbed_official 80:bdf1132a57cf 248 static inline int ssp_writeable(spi_t *obj) {
mbed_official 80:bdf1132a57cf 249 return obj->spi->SR & SSP_SR_BSY_Msk;
mbed_official 80:bdf1132a57cf 250 }
mbed_official 80:bdf1132a57cf 251
mbed_official 80:bdf1132a57cf 252 static inline void ssp_write(spi_t *obj, int value) {
mbed_official 80:bdf1132a57cf 253 obj->spi->DR = value;
mbed_official 80:bdf1132a57cf 254 while (ssp_writeable(obj));
mbed_official 80:bdf1132a57cf 255 }
mbed_official 80:bdf1132a57cf 256 static inline int ssp_read(spi_t *obj) {
mbed_official 80:bdf1132a57cf 257 int read_DR = obj->spi->DR;
mbed_official 80:bdf1132a57cf 258 return read_DR;
mbed_official 80:bdf1132a57cf 259 }
mbed_official 80:bdf1132a57cf 260
mbed_official 80:bdf1132a57cf 261 static inline int ssp_busy(spi_t *obj) {
mbed_official 80:bdf1132a57cf 262 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
mbed_official 80:bdf1132a57cf 263 }
mbed_official 80:bdf1132a57cf 264
mbed_official 80:bdf1132a57cf 265 int spi_master_write(spi_t *obj, int value) {
mbed_official 80:bdf1132a57cf 266 ssp_write(obj, value);
mbed_official 80:bdf1132a57cf 267 while (obj->spi->SR & SSP_SR_BSY_Msk); /* Wait for send to finish */
mbed_official 80:bdf1132a57cf 268 return (ssp_read(obj));
mbed_official 80:bdf1132a57cf 269 }
mbed_official 80:bdf1132a57cf 270
Kojto 170:19eb464bc2be 271 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 170:19eb464bc2be 272 char *rx_buffer, int rx_length, char write_fill) {
AnnaBridge 167:e84263d55307 273 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 167:e84263d55307 274
AnnaBridge 167:e84263d55307 275 for (int i = 0; i < total; i++) {
Kojto 170:19eb464bc2be 276 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 167:e84263d55307 277 char in = spi_master_write(obj, out);
AnnaBridge 167:e84263d55307 278 if (i < rx_length) {
AnnaBridge 167:e84263d55307 279 rx_buffer[i] = in;
AnnaBridge 167:e84263d55307 280 }
AnnaBridge 167:e84263d55307 281 }
AnnaBridge 167:e84263d55307 282
AnnaBridge 167:e84263d55307 283 return total;
AnnaBridge 167:e84263d55307 284 }
AnnaBridge 167:e84263d55307 285
mbed_official 80:bdf1132a57cf 286 int spi_slave_receive(spi_t *obj) {
mbed_official 80:bdf1132a57cf 287 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
mbed_official 80:bdf1132a57cf 288 }
mbed_official 80:bdf1132a57cf 289
mbed_official 80:bdf1132a57cf 290 int spi_slave_read(spi_t *obj) {
mbed_official 80:bdf1132a57cf 291 return obj->spi->DR;
mbed_official 80:bdf1132a57cf 292 }
mbed_official 80:bdf1132a57cf 293
mbed_official 80:bdf1132a57cf 294 void spi_slave_write(spi_t *obj, int value) {
mbed_official 80:bdf1132a57cf 295 while (ssp_writeable(obj) == 0) ;
mbed_official 80:bdf1132a57cf 296 obj->spi->DR = value;
mbed_official 80:bdf1132a57cf 297 }
mbed_official 80:bdf1132a57cf 298
mbed_official 80:bdf1132a57cf 299 int spi_busy(spi_t *obj) {
mbed_official 80:bdf1132a57cf 300 return ssp_busy(obj);
mbed_official 80:bdf1132a57cf 301 }