mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 /*
<> 144:ef7eb2e8f9f7 17 * SSP interface Support
<> 144:ef7eb2e8f9f7 18 * =====================
<> 144:ef7eb2e8f9f7 19 */
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #ifndef MBED_SPI_DEF_H
<> 144:ef7eb2e8f9f7 22 #define MBED_SPI_DEF_H
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #include <stdint.h> /* standard types definitions */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #define Module_ID 0x00090108
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 typedef struct beetle_spi
<> 144:ef7eb2e8f9f7 29 {
<> 144:ef7eb2e8f9f7 30 __IO uint32_t CONFIG; /* 0x00 RW Configuration Register */
<> 144:ef7eb2e8f9f7 31 __I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/
<> 144:ef7eb2e8f9f7 32 __O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/
<> 144:ef7eb2e8f9f7 33 __O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */
<> 144:ef7eb2e8f9f7 34 __I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */
<> 144:ef7eb2e8f9f7 35 __IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */
<> 144:ef7eb2e8f9f7 36 __IO uint32_t DELAY; /* 0x18 RW Delay Register */
<> 144:ef7eb2e8f9f7 37 __O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */
<> 144:ef7eb2e8f9f7 38 __I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */
<> 144:ef7eb2e8f9f7 39 __IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */
<> 144:ef7eb2e8f9f7 40 __IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */
<> 144:ef7eb2e8f9f7 41 __IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */
<> 144:ef7eb2e8f9f7 42 uint32_t reserved[208];
<> 144:ef7eb2e8f9f7 43 __I uint32_t MID; /* 0xFC RO Module ID Register */
<> 144:ef7eb2e8f9f7 44 }SPI_TypeDef;
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 #define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */
<> 144:ef7eb2e8f9f7 48 #define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 #define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE )
<> 144:ef7eb2e8f9f7 51 #define ADC_SPI ((SPI_TypeDef *) SPI1_BASE )
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /* Configuration Register Bit Masks */
<> 144:ef7eb2e8f9f7 54 #define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select
<> 144:ef7eb2e8f9f7 55 #define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge
<> 144:ef7eb2e8f9f7 56 #define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase
<> 144:ef7eb2e8f9f7 57 #define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256)
<> 144:ef7eb2e8f9f7 58 #define CONFIG_MBRD_0 0x00008
<> 144:ef7eb2e8f9f7 59 #define CONFIG_MBRD_1 0x00010
<> 144:ef7eb2e8f9f7 60 #define CONFIG_MBRD_2 0x00020
<> 144:ef7eb2e8f9f7 61 #define CONFIG_MBRD_SHIFT 3
<> 144:ef7eb2e8f9f7 62 #define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size
<> 144:ef7eb2e8f9f7 63 #define CONFIG_TWS_0 0x00000
<> 144:ef7eb2e8f9f7 64 #define CONFIG_TWS_1 0x00040
<> 144:ef7eb2e8f9f7 65 #define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select
<> 144:ef7eb2e8f9f7 66 #define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode
<> 144:ef7eb2e8f9f7 67 #define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only)
<> 144:ef7eb2e8f9f7 68 #define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable
<> 144:ef7eb2e8f9f7 69 #define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable
<> 144:ef7eb2e8f9f7 70 #define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command
<> 144:ef7eb2e8f9f7 71 #define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable
<> 144:ef7eb2e8f9f7 72 #define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Interrupt Status Register Bit Masks */
<> 144:ef7eb2e8f9f7 75 #define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow
<> 144:ef7eb2e8f9f7 76 #define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail
<> 144:ef7eb2e8f9f7 77 #define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status)
<> 144:ef7eb2e8f9f7 78 #define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status)
<> 144:ef7eb2e8f9f7 79 #define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status)
<> 144:ef7eb2e8f9f7 80 #define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status)
<> 144:ef7eb2e8f9f7 81 #define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* Interrupt Enable Register Bit Masks */
<> 144:ef7eb2e8f9f7 84 #define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable
<> 144:ef7eb2e8f9f7 85 #define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable
<> 144:ef7eb2e8f9f7 86 #define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable
<> 144:ef7eb2e8f9f7 87 #define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable
<> 144:ef7eb2e8f9f7 88 #define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable
<> 144:ef7eb2e8f9f7 89 #define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable
<> 144:ef7eb2e8f9f7 90 #define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* Interrupt Disable Register Bit Masks */
<> 144:ef7eb2e8f9f7 93 #define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable
<> 144:ef7eb2e8f9f7 94 #define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable
<> 144:ef7eb2e8f9f7 95 #define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable
<> 144:ef7eb2e8f9f7 96 #define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable
<> 144:ef7eb2e8f9f7 97 #define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable
<> 144:ef7eb2e8f9f7 98 #define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable
<> 144:ef7eb2e8f9f7 99 #define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /* Interrupt Mask Register Bit Masks */
<> 144:ef7eb2e8f9f7 102 #define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask
<> 144:ef7eb2e8f9f7 103 #define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask
<> 144:ef7eb2e8f9f7 104 #define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask
<> 144:ef7eb2e8f9f7 105 #define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask
<> 144:ef7eb2e8f9f7 106 #define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask
<> 144:ef7eb2e8f9f7 107 #define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask
<> 144:ef7eb2e8f9f7 108 #define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* SPI Enable Register Bit Masks */
<> 144:ef7eb2e8f9f7 111 #define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Delay Register Bit Masks */
<> 144:ef7eb2e8f9f7 114 #define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init
<> 144:ef7eb2e8f9f7 115 #define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After
<> 144:ef7eb2e8f9f7 116 #define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between
<> 144:ef7eb2e8f9f7 117 #define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Transmit Data Register Bit Masks */
<> 144:ef7eb2e8f9f7 120 #define TX_DATA_TDATA 0xFF
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Receive Data Register Bit Masks */
<> 144:ef7eb2e8f9f7 123 #define RX_DATA_RDATA 0xFF
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Slave Idle Count Register Bit Masks */
<> 144:ef7eb2e8f9f7 126 #define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* TX Threshold Register Bit Masks */
<> 144:ef7eb2e8f9f7 129 #define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* RX Threshold Register Bit Masks */
<> 144:ef7eb2e8f9f7 132 #define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #endif