mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ARM_SSG/TARGET_BEETLE/i2c_def.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
149:156823d33999 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 /*
<> 144:ef7eb2e8f9f7 17 * I2C interface Support
<> 144:ef7eb2e8f9f7 18 * =====================
<> 144:ef7eb2e8f9f7 19 */
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #ifndef MBED_I2C_DEF_H
<> 144:ef7eb2e8f9f7 22 #define MBED_I2C_DEF_H
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 #include <stdint.h> /* standard types definitions */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 typedef struct beetle_i2c
<> 144:ef7eb2e8f9f7 27 {
<> 144:ef7eb2e8f9f7 28 __IO uint32_t CONTROL; /* RW Control register */
<> 144:ef7eb2e8f9f7 29 __I uint32_t STATUS; /* RO Status register */
<> 144:ef7eb2e8f9f7 30 __IO uint32_t ADDRESS; /* RW I2C address register */
<> 144:ef7eb2e8f9f7 31 __IO uint32_t DATA; /* RW I2C data register */
<> 144:ef7eb2e8f9f7 32 __IO uint32_t IRQ_STATUS; /* RO Interrupt status register ( read only but write to clear bits) */
<> 144:ef7eb2e8f9f7 33 __IO uint32_t TRANSFER_SIZE; /* RW Transfer size register */
<> 144:ef7eb2e8f9f7 34 __IO uint32_t SLAVE_MONITOR; /* RW Slave monitor pause register */
<> 144:ef7eb2e8f9f7 35 __IO uint32_t TIMEOUT; /* RW Time out register */
<> 144:ef7eb2e8f9f7 36 __I uint32_t IRQ_MASK; /* RO Interrupt mask register */
<> 144:ef7eb2e8f9f7 37 __O uint32_t IRQ_ENABLE; /* WO Interrupt enable register */
<> 144:ef7eb2e8f9f7 38 __O uint32_t IRQ_DISABLE; /* WO Interrupt disable register */
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 }I2C_TypeDef;
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #define I2C0_BASE (0x40007000ul) /* Shield Header I2C Base Address */
<> 144:ef7eb2e8f9f7 43 #define I2C1_BASE (0x4000E000ul) /* Onboard I2C Base Address */
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #define SHIELD_I2C ((I2C_TypeDef *) I2C0_BASE )
<> 144:ef7eb2e8f9f7 46 #define BOARD_I2C ((I2C_TypeDef *) I2C1_BASE )
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* Control Register Masks */
<> 144:ef7eb2e8f9f7 49 #define I2C_CTRL_RW 0x0001 /* Transfer direction */
<> 144:ef7eb2e8f9f7 50 #define I2C_CTRL_MS 0x0002 /* Mode (master / slave) */
<> 144:ef7eb2e8f9f7 51 #define I2C_CTRL_NEA 0x0004 /* Addressing mode */
<> 144:ef7eb2e8f9f7 52 #define I2C_CTRL_ACKEN 0x0008 /* ACK enable */
<> 144:ef7eb2e8f9f7 53 #define I2C_CTRL_HOLD 0x0010 /* Clock hold enable */
<> 144:ef7eb2e8f9f7 54 #define I2C_SLVMON 0x0020 /* Slave monitor mode */
<> 144:ef7eb2e8f9f7 55 #define I2C_CTRL_CLR_FIFO 0x0040 /* Force clear of FIFO */
<> 144:ef7eb2e8f9f7 56 #define I2C_CTRL_DIVISOR_B 0x3F00 /* Stage B clock divider */
<> 144:ef7eb2e8f9f7 57 #define I2C_CTRL_DIVISOR_A 0xA000 /* Stage A clock divider */
<> 144:ef7eb2e8f9f7 58 #define I2C_CTRL_DIVISORS 0xFF00 /* Combined A and B fields */
<> 144:ef7eb2e8f9f7 59 #define I2C_CTRL_DIVISOR_OFFSET 8 /* Offset of the clock divisor in
<> 144:ef7eb2e8f9f7 60 * the CONTROL register
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62 #define I2C_CTRL_DIVISOR_A_BIT_MASK 0x03
<> 144:ef7eb2e8f9f7 63 /*
<> 144:ef7eb2e8f9f7 64 * First part of the clock
<> 144:ef7eb2e8f9f7 65 * divisor in the CONTROL register
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 #define I2C_CTRL_DIVISOR_B_BIT_MASK 0x3F
<> 144:ef7eb2e8f9f7 68 /*
<> 144:ef7eb2e8f9f7 69 * Second part of the clock
<> 144:ef7eb2e8f9f7 70 * divisor in the CONTROL register
<> 144:ef7eb2e8f9f7 71 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /* Status Register Masks */
<> 144:ef7eb2e8f9f7 74 #define I2C_STATUS_RXRW 0x0008 /* Mode of transmission from master */
<> 144:ef7eb2e8f9f7 75 #define I2C_STATUS_RXDV 0x0020 /* Valid data waiting to be read */
<> 144:ef7eb2e8f9f7 76 #define I2C_STATUS_TXDV 0x0040 /* Still a data byte to be sent */
<> 144:ef7eb2e8f9f7 77 #define I2C_STATUS_RXOVF 0x0080 /* Receiver overflow */
<> 144:ef7eb2e8f9f7 78 #define I2C_STATUS_BA 0x0100 /* Bus active */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Address Register Masks */
<> 144:ef7eb2e8f9f7 81 #define I2C_ADDRESS_7BIT 0x007F
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* Interrupt Status / Enable / Disable Register Masks */
<> 144:ef7eb2e8f9f7 84 #define I2C_IRQ_COMP 0x0001 /* Transfer complete */
<> 144:ef7eb2e8f9f7 85 #define I2C_IRQ_DATA 0x0002 /* More data */
<> 144:ef7eb2e8f9f7 86 #define I2C_IRQ_NACK 0x0004 /* Transfer not acknowledged */
<> 144:ef7eb2e8f9f7 87 #define I2C_IRQ_TO 0x0008 /* Transfer timed out */
<> 144:ef7eb2e8f9f7 88 #define I2C_IRQ_SLV_RDY 0x0010 /* Monitored slave ready */
<> 144:ef7eb2e8f9f7 89 #define I2C_IRQ_RX_OVF 0x0020 /* Receive overflow */
<> 144:ef7eb2e8f9f7 90 #define I2C_IRQ_TX_OVF 0x0040 /* Transmit overflow */
<> 144:ef7eb2e8f9f7 91 #define I2C_IRQ_RX_UNF 0x0080 /* Receive underflow */
<> 144:ef7eb2e8f9f7 92 #define I2C_IRQ_ARB_LOST 0x0200 /* Arbitration lost */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Transfer Size Register Masks */
<> 144:ef7eb2e8f9f7 95 #define I2C_TRANSFER_SIZE 0xFF
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Error codes */
<> 144:ef7eb2e8f9f7 98 #define E_SUCCESS 0x0
<> 144:ef7eb2e8f9f7 99 #define E_INCOMPLETE_DATA 0x1
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 #endif