mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_ARM_SSG/TARGET_BEETLE/gpio_irq_api.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 149:156823d33999
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2015 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 17 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 18 | #include "gpio_irq_api.h" |
<> | 144:ef7eb2e8f9f7 | 19 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | #define CHANNEL_NUM 32 |
<> | 144:ef7eb2e8f9f7 | 22 | #define CMSDK_GPIO_0 CMSDK_GPIO0 |
<> | 144:ef7eb2e8f9f7 | 23 | #define CMSDK_GPIO_1 CMSDK_GPIO1 |
<> | 144:ef7eb2e8f9f7 | 24 | #define PININT_IRQ 0 |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | static uint32_t channel_ids[CHANNEL_NUM] = {0}; |
<> | 144:ef7eb2e8f9f7 | 27 | static gpio_irq_handler irq_handler; |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | static inline void handle_interrupt_in(uint32_t channel) { |
<> | 144:ef7eb2e8f9f7 | 30 | uint32_t ch_bit = (1 << channel); |
<> | 144:ef7eb2e8f9f7 | 31 | // Return immediately if: |
<> | 144:ef7eb2e8f9f7 | 32 | // * The interrupt was already served |
<> | 144:ef7eb2e8f9f7 | 33 | // * There is no user handler |
<> | 144:ef7eb2e8f9f7 | 34 | // * It is a level interrupt, not an edge interrupt |
<> | 144:ef7eb2e8f9f7 | 35 | if (ch_bit <16){ |
<> | 144:ef7eb2e8f9f7 | 36 | if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) |
<> | 144:ef7eb2e8f9f7 | 37 | || ((CMSDK_GPIO_0->INTTYPESET) == 0)) |
<> | 144:ef7eb2e8f9f7 | 38 | return; |
<> | 144:ef7eb2e8f9f7 | 39 | |
<> | 144:ef7eb2e8f9f7 | 40 | if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) |
<> | 144:ef7eb2e8f9f7 | 41 | && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 42 | irq_handler(channel_ids[channel], IRQ_RISE); |
<> | 144:ef7eb2e8f9f7 | 43 | CMSDK_GPIO_0->INTPOLSET = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 44 | } |
<> | 144:ef7eb2e8f9f7 | 45 | if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) |
<> | 144:ef7eb2e8f9f7 | 46 | && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 47 | irq_handler(channel_ids[channel], IRQ_FALL); |
<> | 144:ef7eb2e8f9f7 | 48 | } |
<> | 144:ef7eb2e8f9f7 | 49 | CMSDK_GPIO_0->INTCLEAR = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 50 | } |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | if (ch_bit>=16) { |
<> | 144:ef7eb2e8f9f7 | 53 | if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) |
<> | 144:ef7eb2e8f9f7 | 54 | || ((CMSDK_GPIO_1->INTTYPESET) == 0)) |
<> | 144:ef7eb2e8f9f7 | 55 | return; |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) |
<> | 144:ef7eb2e8f9f7 | 58 | && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 59 | irq_handler(channel_ids[channel], IRQ_RISE); |
<> | 144:ef7eb2e8f9f7 | 60 | CMSDK_GPIO_1->INTPOLSET = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 61 | } |
<> | 144:ef7eb2e8f9f7 | 62 | if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) |
<> | 144:ef7eb2e8f9f7 | 63 | && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 64 | irq_handler(channel_ids[channel], IRQ_FALL); |
<> | 144:ef7eb2e8f9f7 | 65 | } |
<> | 144:ef7eb2e8f9f7 | 66 | CMSDK_GPIO_1->INTCLEAR = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 67 | } |
<> | 144:ef7eb2e8f9f7 | 68 | } |
<> | 144:ef7eb2e8f9f7 | 69 | |
<> | 144:ef7eb2e8f9f7 | 70 | void gpio0_irq0(void) { |
<> | 144:ef7eb2e8f9f7 | 71 | handle_interrupt_in(0); |
<> | 144:ef7eb2e8f9f7 | 72 | } |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | void gpio0_irq1(void) { |
<> | 144:ef7eb2e8f9f7 | 75 | handle_interrupt_in(1); |
<> | 144:ef7eb2e8f9f7 | 76 | } |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | void gpio0_irq2(void) { |
<> | 144:ef7eb2e8f9f7 | 79 | handle_interrupt_in(2); |
<> | 144:ef7eb2e8f9f7 | 80 | } |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | void gpio0_irq3(void) { |
<> | 144:ef7eb2e8f9f7 | 83 | handle_interrupt_in(3); |
<> | 144:ef7eb2e8f9f7 | 84 | } |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | void gpio0_irq4(void) { |
<> | 144:ef7eb2e8f9f7 | 87 | handle_interrupt_in(4); |
<> | 144:ef7eb2e8f9f7 | 88 | } |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | void gpio0_irq5(void) { |
<> | 144:ef7eb2e8f9f7 | 91 | handle_interrupt_in(5); |
<> | 144:ef7eb2e8f9f7 | 92 | } |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | void gpio0_irq6(void) { |
<> | 144:ef7eb2e8f9f7 | 95 | handle_interrupt_in(6); |
<> | 144:ef7eb2e8f9f7 | 96 | } |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | void gpio0_irq7(void) { |
<> | 144:ef7eb2e8f9f7 | 99 | handle_interrupt_in(7); |
<> | 144:ef7eb2e8f9f7 | 100 | } |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | void gpio0_irq8(void) { |
<> | 144:ef7eb2e8f9f7 | 103 | handle_interrupt_in(8); |
<> | 144:ef7eb2e8f9f7 | 104 | } |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | void gpio0_irq9(void) { |
<> | 144:ef7eb2e8f9f7 | 107 | handle_interrupt_in(9); |
<> | 144:ef7eb2e8f9f7 | 108 | } |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | void gpio0_irq10(void) { |
<> | 144:ef7eb2e8f9f7 | 111 | handle_interrupt_in(10); |
<> | 144:ef7eb2e8f9f7 | 112 | } |
<> | 144:ef7eb2e8f9f7 | 113 | |
<> | 144:ef7eb2e8f9f7 | 114 | void gpio0_irq11(void) { |
<> | 144:ef7eb2e8f9f7 | 115 | handle_interrupt_in(11); |
<> | 144:ef7eb2e8f9f7 | 116 | } |
<> | 144:ef7eb2e8f9f7 | 117 | |
<> | 144:ef7eb2e8f9f7 | 118 | void gpio0_irq12(void) { |
<> | 144:ef7eb2e8f9f7 | 119 | handle_interrupt_in(12); |
<> | 144:ef7eb2e8f9f7 | 120 | } |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | void gpio0_irq13(void) { |
<> | 144:ef7eb2e8f9f7 | 123 | handle_interrupt_in(13); |
<> | 144:ef7eb2e8f9f7 | 124 | } |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | void gpio0_irq14(void) { |
<> | 144:ef7eb2e8f9f7 | 127 | handle_interrupt_in(14); |
<> | 144:ef7eb2e8f9f7 | 128 | } |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | void gpio0_irq15(void) { |
<> | 144:ef7eb2e8f9f7 | 131 | handle_interrupt_in(15); |
<> | 144:ef7eb2e8f9f7 | 132 | } |
<> | 144:ef7eb2e8f9f7 | 133 | |
<> | 144:ef7eb2e8f9f7 | 134 | void gpio1_irq0(void) { |
<> | 144:ef7eb2e8f9f7 | 135 | handle_interrupt_in(16); |
<> | 144:ef7eb2e8f9f7 | 136 | } |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | void gpio1_irq1(void) { |
<> | 144:ef7eb2e8f9f7 | 139 | handle_interrupt_in(17); |
<> | 144:ef7eb2e8f9f7 | 140 | } |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | void gpio1_irq2(void) { |
<> | 144:ef7eb2e8f9f7 | 143 | handle_interrupt_in(18); |
<> | 144:ef7eb2e8f9f7 | 144 | } |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | void gpio1_irq3(void) { |
<> | 144:ef7eb2e8f9f7 | 147 | handle_interrupt_in(19); |
<> | 144:ef7eb2e8f9f7 | 148 | } |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | void gpio1_irq4(void) { |
<> | 144:ef7eb2e8f9f7 | 151 | handle_interrupt_in(20); |
<> | 144:ef7eb2e8f9f7 | 152 | } |
<> | 144:ef7eb2e8f9f7 | 153 | |
<> | 144:ef7eb2e8f9f7 | 154 | void gpio1_irq5(void) { |
<> | 144:ef7eb2e8f9f7 | 155 | handle_interrupt_in(21); |
<> | 144:ef7eb2e8f9f7 | 156 | } |
<> | 144:ef7eb2e8f9f7 | 157 | |
<> | 144:ef7eb2e8f9f7 | 158 | void gpio1_irq6(void) { |
<> | 144:ef7eb2e8f9f7 | 159 | handle_interrupt_in(22); |
<> | 144:ef7eb2e8f9f7 | 160 | } |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | void gpio1_irq7(void) { |
<> | 144:ef7eb2e8f9f7 | 163 | handle_interrupt_in(23); |
<> | 144:ef7eb2e8f9f7 | 164 | } |
<> | 144:ef7eb2e8f9f7 | 165 | |
<> | 144:ef7eb2e8f9f7 | 166 | void gpio1_irq8(void) { |
<> | 144:ef7eb2e8f9f7 | 167 | handle_interrupt_in(24); |
<> | 144:ef7eb2e8f9f7 | 168 | } |
<> | 144:ef7eb2e8f9f7 | 169 | |
<> | 144:ef7eb2e8f9f7 | 170 | void gpio1_irq9(void) { |
<> | 144:ef7eb2e8f9f7 | 171 | handle_interrupt_in(25); |
<> | 144:ef7eb2e8f9f7 | 172 | } |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | void gpio1_irq10(void) { |
<> | 144:ef7eb2e8f9f7 | 175 | handle_interrupt_in(26); |
<> | 144:ef7eb2e8f9f7 | 176 | } |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | void gpio1_irq11(void) { |
<> | 144:ef7eb2e8f9f7 | 179 | handle_interrupt_in(27); |
<> | 144:ef7eb2e8f9f7 | 180 | } |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | void gpio1_irq12(void) { |
<> | 144:ef7eb2e8f9f7 | 183 | handle_interrupt_in(28); |
<> | 144:ef7eb2e8f9f7 | 184 | } |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | void gpio1_irq13(void) { |
<> | 144:ef7eb2e8f9f7 | 187 | handle_interrupt_in(29); |
<> | 144:ef7eb2e8f9f7 | 188 | } |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | void gpio1_irq14(void) { |
<> | 144:ef7eb2e8f9f7 | 191 | handle_interrupt_in(30); |
<> | 144:ef7eb2e8f9f7 | 192 | } |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | void gpio1_irq15(void) { |
<> | 144:ef7eb2e8f9f7 | 195 | handle_interrupt_in(31); |
<> | 144:ef7eb2e8f9f7 | 196 | } |
<> | 144:ef7eb2e8f9f7 | 197 | |
<> | 144:ef7eb2e8f9f7 | 198 | int gpio_irq_init(gpio_irq_t *obj, PinName pin, |
<> | 144:ef7eb2e8f9f7 | 199 | gpio_irq_handler handler, uint32_t id) { |
<> | 144:ef7eb2e8f9f7 | 200 | if (pin == NC) {return -1;} |
<> | 144:ef7eb2e8f9f7 | 201 | else { |
<> | 144:ef7eb2e8f9f7 | 202 | |
<> | 144:ef7eb2e8f9f7 | 203 | irq_handler = handler; |
<> | 144:ef7eb2e8f9f7 | 204 | |
<> | 144:ef7eb2e8f9f7 | 205 | int found_free_channel = 0; |
<> | 144:ef7eb2e8f9f7 | 206 | int i = 0; |
<> | 144:ef7eb2e8f9f7 | 207 | for (i=0; i<CHANNEL_NUM; i++) { |
<> | 144:ef7eb2e8f9f7 | 208 | if (channel_ids[i] == 0) { |
<> | 144:ef7eb2e8f9f7 | 209 | channel_ids[i] = id; |
<> | 144:ef7eb2e8f9f7 | 210 | obj->ch = i; |
<> | 144:ef7eb2e8f9f7 | 211 | found_free_channel = 1; |
<> | 144:ef7eb2e8f9f7 | 212 | break; |
<> | 144:ef7eb2e8f9f7 | 213 | } |
<> | 144:ef7eb2e8f9f7 | 214 | } |
<> | 144:ef7eb2e8f9f7 | 215 | if (!found_free_channel) |
<> | 144:ef7eb2e8f9f7 | 216 | return -1; |
<> | 144:ef7eb2e8f9f7 | 217 | /* To select a pin for any of the eight pin interrupts, write the pin number |
<> | 144:ef7eb2e8f9f7 | 218 | * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55. |
<> | 144:ef7eb2e8f9f7 | 219 | * @see: mbed_capi/PinNames.h |
<> | 144:ef7eb2e8f9f7 | 220 | */ |
<> | 144:ef7eb2e8f9f7 | 221 | if (pin <16) { |
<> | 144:ef7eb2e8f9f7 | 222 | CMSDK_GPIO_0->INTENSET |= (0x1 << pin); |
<> | 144:ef7eb2e8f9f7 | 223 | } |
<> | 144:ef7eb2e8f9f7 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | if (pin >= 16) { |
<> | 144:ef7eb2e8f9f7 | 226 | CMSDK_GPIO_1->INTENSET |= (0x1 << pin); |
<> | 144:ef7eb2e8f9f7 | 227 | } |
<> | 144:ef7eb2e8f9f7 | 228 | |
<> | 144:ef7eb2e8f9f7 | 229 | void (*channels_irq)(void) = NULL; |
<> | 144:ef7eb2e8f9f7 | 230 | switch (obj->ch) { |
<> | 144:ef7eb2e8f9f7 | 231 | case 0: |
<> | 144:ef7eb2e8f9f7 | 232 | channels_irq = &gpio0_irq0; |
<> | 144:ef7eb2e8f9f7 | 233 | break; |
<> | 144:ef7eb2e8f9f7 | 234 | case 1: |
<> | 144:ef7eb2e8f9f7 | 235 | channels_irq = &gpio0_irq1; |
<> | 144:ef7eb2e8f9f7 | 236 | break; |
<> | 144:ef7eb2e8f9f7 | 237 | case 2: |
<> | 144:ef7eb2e8f9f7 | 238 | channels_irq = &gpio0_irq2; |
<> | 144:ef7eb2e8f9f7 | 239 | break; |
<> | 144:ef7eb2e8f9f7 | 240 | case 3: |
<> | 144:ef7eb2e8f9f7 | 241 | channels_irq = &gpio0_irq3; |
<> | 144:ef7eb2e8f9f7 | 242 | break; |
<> | 144:ef7eb2e8f9f7 | 243 | case 4: |
<> | 144:ef7eb2e8f9f7 | 244 | channels_irq = &gpio0_irq4; |
<> | 144:ef7eb2e8f9f7 | 245 | break; |
<> | 144:ef7eb2e8f9f7 | 246 | case 5: |
<> | 144:ef7eb2e8f9f7 | 247 | channels_irq = &gpio0_irq5; |
<> | 144:ef7eb2e8f9f7 | 248 | break; |
<> | 144:ef7eb2e8f9f7 | 249 | case 6: |
<> | 144:ef7eb2e8f9f7 | 250 | channels_irq = &gpio0_irq6; |
<> | 144:ef7eb2e8f9f7 | 251 | break; |
<> | 144:ef7eb2e8f9f7 | 252 | case 7: |
<> | 144:ef7eb2e8f9f7 | 253 | channels_irq = &gpio0_irq7; |
<> | 144:ef7eb2e8f9f7 | 254 | break; |
<> | 144:ef7eb2e8f9f7 | 255 | case 8: |
<> | 144:ef7eb2e8f9f7 | 256 | channels_irq = &gpio0_irq8; |
<> | 144:ef7eb2e8f9f7 | 257 | break; |
<> | 144:ef7eb2e8f9f7 | 258 | case 9: |
<> | 144:ef7eb2e8f9f7 | 259 | channels_irq = &gpio0_irq9; |
<> | 144:ef7eb2e8f9f7 | 260 | break; |
<> | 144:ef7eb2e8f9f7 | 261 | case 10: |
<> | 144:ef7eb2e8f9f7 | 262 | channels_irq = &gpio0_irq10; |
<> | 144:ef7eb2e8f9f7 | 263 | break; |
<> | 144:ef7eb2e8f9f7 | 264 | case 11: |
<> | 144:ef7eb2e8f9f7 | 265 | channels_irq = &gpio0_irq11; |
<> | 144:ef7eb2e8f9f7 | 266 | break; |
<> | 144:ef7eb2e8f9f7 | 267 | case 12: |
<> | 144:ef7eb2e8f9f7 | 268 | channels_irq = &gpio0_irq12; |
<> | 144:ef7eb2e8f9f7 | 269 | break; |
<> | 144:ef7eb2e8f9f7 | 270 | case 13: |
<> | 144:ef7eb2e8f9f7 | 271 | channels_irq = &gpio0_irq13; |
<> | 144:ef7eb2e8f9f7 | 272 | break; |
<> | 144:ef7eb2e8f9f7 | 273 | case 14: |
<> | 144:ef7eb2e8f9f7 | 274 | channels_irq = &gpio0_irq14; |
<> | 144:ef7eb2e8f9f7 | 275 | break; |
<> | 144:ef7eb2e8f9f7 | 276 | case 15: |
<> | 144:ef7eb2e8f9f7 | 277 | channels_irq = &gpio0_irq15; |
<> | 144:ef7eb2e8f9f7 | 278 | break; |
<> | 144:ef7eb2e8f9f7 | 279 | case 16: |
<> | 144:ef7eb2e8f9f7 | 280 | channels_irq = &gpio1_irq0; |
<> | 144:ef7eb2e8f9f7 | 281 | break; |
<> | 144:ef7eb2e8f9f7 | 282 | case 17: |
<> | 144:ef7eb2e8f9f7 | 283 | channels_irq = &gpio1_irq1; |
<> | 144:ef7eb2e8f9f7 | 284 | break; |
<> | 144:ef7eb2e8f9f7 | 285 | case 18: |
<> | 144:ef7eb2e8f9f7 | 286 | channels_irq = &gpio1_irq2; |
<> | 144:ef7eb2e8f9f7 | 287 | break; |
<> | 144:ef7eb2e8f9f7 | 288 | case 19: |
<> | 144:ef7eb2e8f9f7 | 289 | channels_irq = &gpio1_irq3; |
<> | 144:ef7eb2e8f9f7 | 290 | break; |
<> | 144:ef7eb2e8f9f7 | 291 | case 20: |
<> | 144:ef7eb2e8f9f7 | 292 | channels_irq = &gpio1_irq4; |
<> | 144:ef7eb2e8f9f7 | 293 | break; |
<> | 144:ef7eb2e8f9f7 | 294 | case 21: |
<> | 144:ef7eb2e8f9f7 | 295 | channels_irq = &gpio1_irq5; |
<> | 144:ef7eb2e8f9f7 | 296 | break; |
<> | 144:ef7eb2e8f9f7 | 297 | case 22: |
<> | 144:ef7eb2e8f9f7 | 298 | channels_irq = &gpio1_irq6; |
<> | 144:ef7eb2e8f9f7 | 299 | break; |
<> | 144:ef7eb2e8f9f7 | 300 | case 23: |
<> | 144:ef7eb2e8f9f7 | 301 | channels_irq = &gpio1_irq7; |
<> | 144:ef7eb2e8f9f7 | 302 | break; |
<> | 144:ef7eb2e8f9f7 | 303 | case 24: |
<> | 144:ef7eb2e8f9f7 | 304 | channels_irq = &gpio1_irq8; |
<> | 144:ef7eb2e8f9f7 | 305 | break; |
<> | 144:ef7eb2e8f9f7 | 306 | case 25: |
<> | 144:ef7eb2e8f9f7 | 307 | channels_irq = &gpio1_irq9; |
<> | 144:ef7eb2e8f9f7 | 308 | break; |
<> | 144:ef7eb2e8f9f7 | 309 | case 26: |
<> | 144:ef7eb2e8f9f7 | 310 | channels_irq = &gpio1_irq10; |
<> | 144:ef7eb2e8f9f7 | 311 | break; |
<> | 144:ef7eb2e8f9f7 | 312 | case 27: |
<> | 144:ef7eb2e8f9f7 | 313 | channels_irq = &gpio1_irq11; |
<> | 144:ef7eb2e8f9f7 | 314 | break; |
<> | 144:ef7eb2e8f9f7 | 315 | case 28: |
<> | 144:ef7eb2e8f9f7 | 316 | channels_irq = &gpio1_irq12; |
<> | 144:ef7eb2e8f9f7 | 317 | break; |
<> | 144:ef7eb2e8f9f7 | 318 | case 29: |
<> | 144:ef7eb2e8f9f7 | 319 | channels_irq = &gpio1_irq13; |
<> | 144:ef7eb2e8f9f7 | 320 | break; |
<> | 144:ef7eb2e8f9f7 | 321 | case 30: |
<> | 144:ef7eb2e8f9f7 | 322 | channels_irq = &gpio1_irq14; |
<> | 144:ef7eb2e8f9f7 | 323 | break; |
<> | 144:ef7eb2e8f9f7 | 324 | case 31: |
<> | 144:ef7eb2e8f9f7 | 325 | channels_irq = &gpio1_irq15; |
<> | 144:ef7eb2e8f9f7 | 326 | break; |
<> | 144:ef7eb2e8f9f7 | 327 | } |
<> | 144:ef7eb2e8f9f7 | 328 | NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), |
<> | 144:ef7eb2e8f9f7 | 329 | (uint32_t)channels_irq); |
<> | 144:ef7eb2e8f9f7 | 330 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
<> | 144:ef7eb2e8f9f7 | 331 | |
<> | 144:ef7eb2e8f9f7 | 332 | return 0; |
<> | 144:ef7eb2e8f9f7 | 333 | } |
<> | 144:ef7eb2e8f9f7 | 334 | } |
<> | 144:ef7eb2e8f9f7 | 335 | |
<> | 144:ef7eb2e8f9f7 | 336 | void gpio_irq_free(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 337 | } |
<> | 144:ef7eb2e8f9f7 | 338 | |
<> | 144:ef7eb2e8f9f7 | 339 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { |
<> | 144:ef7eb2e8f9f7 | 340 | unsigned int ch_bit = (1 << obj->ch); |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 144:ef7eb2e8f9f7 | 342 | // Clear interrupt |
<> | 144:ef7eb2e8f9f7 | 343 | if (obj->ch <16) { |
<> | 144:ef7eb2e8f9f7 | 344 | if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 345 | CMSDK_GPIO_0->INTCLEAR = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 346 | } |
<> | 144:ef7eb2e8f9f7 | 347 | } |
<> | 144:ef7eb2e8f9f7 | 348 | if (obj->ch >= 16) { |
<> | 144:ef7eb2e8f9f7 | 349 | if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) { |
<> | 144:ef7eb2e8f9f7 | 350 | CMSDK_GPIO_1->INTCLEAR = ch_bit; |
<> | 144:ef7eb2e8f9f7 | 351 | } |
<> | 144:ef7eb2e8f9f7 | 352 | } |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | // Edge trigger |
<> | 144:ef7eb2e8f9f7 | 355 | if (obj->ch <16) { |
<> | 144:ef7eb2e8f9f7 | 356 | CMSDK_GPIO_0->INTTYPESET &= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 357 | if (event == IRQ_RISE) { |
<> | 144:ef7eb2e8f9f7 | 358 | CMSDK_GPIO_0->INTPOLSET |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 359 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 360 | CMSDK_GPIO_0->INTENSET |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 361 | } else { |
<> | 144:ef7eb2e8f9f7 | 362 | CMSDK_GPIO_0->INTENCLR |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 363 | } |
<> | 144:ef7eb2e8f9f7 | 364 | } else { |
<> | 144:ef7eb2e8f9f7 | 365 | CMSDK_GPIO_0->INTPOLCLR |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 366 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 367 | CMSDK_GPIO_0->INTENSET |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 368 | } else { |
<> | 144:ef7eb2e8f9f7 | 369 | CMSDK_GPIO_0->INTENCLR |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 370 | } |
<> | 144:ef7eb2e8f9f7 | 371 | } |
<> | 144:ef7eb2e8f9f7 | 372 | } |
<> | 144:ef7eb2e8f9f7 | 373 | if (obj->ch >= 16) { |
<> | 144:ef7eb2e8f9f7 | 374 | CMSDK_GPIO_1->INTTYPESET &= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 375 | if (event == IRQ_RISE) { |
<> | 144:ef7eb2e8f9f7 | 376 | CMSDK_GPIO_1->INTPOLSET |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 377 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 378 | CMSDK_GPIO_1->INTENSET |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 379 | } else { |
<> | 144:ef7eb2e8f9f7 | 380 | CMSDK_GPIO_1->INTENCLR |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 381 | } |
<> | 144:ef7eb2e8f9f7 | 382 | } else { |
<> | 144:ef7eb2e8f9f7 | 383 | CMSDK_GPIO_1->INTPOLCLR |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 384 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 385 | CMSDK_GPIO_1->INTENSET |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 386 | } else { |
<> | 144:ef7eb2e8f9f7 | 387 | CMSDK_GPIO_1->INTENCLR |= ch_bit; |
<> | 144:ef7eb2e8f9f7 | 388 | } |
<> | 144:ef7eb2e8f9f7 | 389 | } |
<> | 144:ef7eb2e8f9f7 | 390 | } |
<> | 144:ef7eb2e8f9f7 | 391 | } |
<> | 144:ef7eb2e8f9f7 | 392 | |
<> | 144:ef7eb2e8f9f7 | 393 | void gpio_irq_enable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 394 | NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
<> | 144:ef7eb2e8f9f7 | 395 | } |
<> | 144:ef7eb2e8f9f7 | 396 | |
<> | 144:ef7eb2e8f9f7 | 397 | void gpio_irq_disable(gpio_irq_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 398 | NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); |
<> | 144:ef7eb2e8f9f7 | 399 | } |