mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ARM_FM/TARGET_FVP_MPS2/spi_def.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
186:707f6e361f3e 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 186:707f6e361f3e 1 /* mbed Microcontroller Library
Anna Bridge 186:707f6e361f3e 2 * Copyright (c) 2006-2018 ARM Limited
Anna Bridge 186:707f6e361f3e 3 *
Anna Bridge 186:707f6e361f3e 4 * Licensed under the Apache License, Version 2.0 (the "License");
Anna Bridge 186:707f6e361f3e 5 * you may not use this file except in compliance with the License.
Anna Bridge 186:707f6e361f3e 6 * You may obtain a copy of the License at
Anna Bridge 186:707f6e361f3e 7 *
Anna Bridge 186:707f6e361f3e 8 * http://www.apache.org/licenses/LICENSE-2.0
Anna Bridge 186:707f6e361f3e 9 *
Anna Bridge 186:707f6e361f3e 10 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 186:707f6e361f3e 11 * distributed under the License is distributed on an "AS IS" BASIS,
Anna Bridge 186:707f6e361f3e 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 186:707f6e361f3e 13 * See the License for the specific language governing permissions and
Anna Bridge 186:707f6e361f3e 14 * limitations under the License.
Anna Bridge 186:707f6e361f3e 15 * ----------------------------------------------------------------
Anna Bridge 186:707f6e361f3e 16 * File: apspi.h
Anna Bridge 186:707f6e361f3e 17 * Release: Version 2.0
Anna Bridge 186:707f6e361f3e 18 * ----------------------------------------------------------------
Anna Bridge 186:707f6e361f3e 19 *
Anna Bridge 186:707f6e361f3e 20 * SSP interface Support
Anna Bridge 186:707f6e361f3e 21 * =====================
Anna Bridge 186:707f6e361f3e 22 */
Anna Bridge 186:707f6e361f3e 23
Anna Bridge 186:707f6e361f3e 24 #define SSPCS_BASE (0x4002804C) // SSP chip select register
Anna Bridge 186:707f6e361f3e 25 #define SSP_BASE (0x40020000) // SSP Prime Cell
Anna Bridge 186:707f6e361f3e 26
Anna Bridge 186:707f6e361f3e 27 #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
Anna Bridge 186:707f6e361f3e 28 #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
Anna Bridge 186:707f6e361f3e 29 #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
Anna Bridge 186:707f6e361f3e 30 #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
Anna Bridge 186:707f6e361f3e 31 #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
Anna Bridge 186:707f6e361f3e 32 #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
Anna Bridge 186:707f6e361f3e 33 #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
Anna Bridge 186:707f6e361f3e 34 #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
Anna Bridge 186:707f6e361f3e 35 #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
Anna Bridge 186:707f6e361f3e 36 #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
Anna Bridge 186:707f6e361f3e 37 #define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
Anna Bridge 186:707f6e361f3e 38
Anna Bridge 186:707f6e361f3e 39 // SSPCR0 Control register 0
Anna Bridge 186:707f6e361f3e 40 #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
Anna Bridge 186:707f6e361f3e 41 #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
Anna Bridge 186:707f6e361f3e 42 #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
Anna Bridge 186:707f6e361f3e 43 #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
Anna Bridge 186:707f6e361f3e 44 #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
Anna Bridge 186:707f6e361f3e 45 #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
Anna Bridge 186:707f6e361f3e 46
Anna Bridge 186:707f6e361f3e 47 // SSPCR1 Control register 1
Anna Bridge 186:707f6e361f3e 48 #define SSPCR1_SOD 0x0008 // Slave Output mode Disable
Anna Bridge 186:707f6e361f3e 49 #define SSPCR1_MS 0x0004 // Master or Slave mode
Anna Bridge 186:707f6e361f3e 50 #define SSPCR1_SSE 0x0002 // Serial port enable
Anna Bridge 186:707f6e361f3e 51 #define SSPCR1_LBM 0x0001 // Loop Back Mode
Anna Bridge 186:707f6e361f3e 52
Anna Bridge 186:707f6e361f3e 53 // SSPSR Status register
Anna Bridge 186:707f6e361f3e 54 #define SSPSR_BSY 0x0010 // Busy
Anna Bridge 186:707f6e361f3e 55 #define SSPSR_RFF 0x0008 // Receive FIFO full
Anna Bridge 186:707f6e361f3e 56 #define SSPSR_RNE 0x0004 // Receive FIFO not empty
Anna Bridge 186:707f6e361f3e 57 #define SSPSR_TNF 0x0002 // Transmit FIFO not full
Anna Bridge 186:707f6e361f3e 58 #define SSPSR_TFE 0x0001 // Transmit FIFO empty
Anna Bridge 186:707f6e361f3e 59
Anna Bridge 186:707f6e361f3e 60 // SSPCPSR Clock prescale register
Anna Bridge 186:707f6e361f3e 61 #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
Anna Bridge 186:707f6e361f3e 62
Anna Bridge 186:707f6e361f3e 63 // SSPIMSC Interrupt mask set and clear register
Anna Bridge 186:707f6e361f3e 64 #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
Anna Bridge 186:707f6e361f3e 65 #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
Anna Bridge 186:707f6e361f3e 66 #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
Anna Bridge 186:707f6e361f3e 67 #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
Anna Bridge 186:707f6e361f3e 68
Anna Bridge 186:707f6e361f3e 69 // SSPRIS Raw interrupt status register
Anna Bridge 186:707f6e361f3e 70 #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
Anna Bridge 186:707f6e361f3e 71 #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
Anna Bridge 186:707f6e361f3e 72 #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
Anna Bridge 186:707f6e361f3e 73 #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
Anna Bridge 186:707f6e361f3e 74
Anna Bridge 186:707f6e361f3e 75 // SSPMIS Masked interrupt status register
Anna Bridge 186:707f6e361f3e 76 #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
Anna Bridge 186:707f6e361f3e 77 #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
Anna Bridge 186:707f6e361f3e 78 #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
Anna Bridge 186:707f6e361f3e 79 #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
Anna Bridge 186:707f6e361f3e 80
Anna Bridge 186:707f6e361f3e 81 // SSPICR Interrupt clear register
Anna Bridge 186:707f6e361f3e 82 #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
Anna Bridge 186:707f6e361f3e 83 #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
Anna Bridge 186:707f6e361f3e 84
Anna Bridge 186:707f6e361f3e 85 // SSPDMACR DMA control register
Anna Bridge 186:707f6e361f3e 86 #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
Anna Bridge 186:707f6e361f3e 87 #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
Anna Bridge 186:707f6e361f3e 88
Anna Bridge 186:707f6e361f3e 89 // SPICS register (0=Chip Select low)
Anna Bridge 186:707f6e361f3e 90 #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
Anna Bridge 186:707f6e361f3e 91
Anna Bridge 186:707f6e361f3e 92 // SPI defaults
Anna Bridge 186:707f6e361f3e 93 #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
Anna Bridge 186:707f6e361f3e 94
Anna Bridge 186:707f6e361f3e 95 // EEPROM instruction set
Anna Bridge 186:707f6e361f3e 96 #define EEWRSR 0x0001 // Write status
Anna Bridge 186:707f6e361f3e 97 #define EEWRITE 0x0002 // Write data
Anna Bridge 186:707f6e361f3e 98 #define EEREAD 0x0003 // Read data
Anna Bridge 186:707f6e361f3e 99 #define EEWDI 0x0004 // Write disable
Anna Bridge 186:707f6e361f3e 100 #define EEWREN 0x0006 // Write enable
Anna Bridge 186:707f6e361f3e 101 #define EERDSR 0x0005 // Read status
Anna Bridge 186:707f6e361f3e 102
Anna Bridge 186:707f6e361f3e 103 // EEPROM status register flags
Anna Bridge 186:707f6e361f3e 104 #define EERDSR_WIP 0x0001 // Write in process
Anna Bridge 186:707f6e361f3e 105 #define EERDSR_WEL 0x0002 // Write enable latch
Anna Bridge 186:707f6e361f3e 106 #define EERDSR_BP0 0x0004 // Block protect 0
Anna Bridge 186:707f6e361f3e 107 #define EERDSR_BP1 0x0008 // Block protect 1
Anna Bridge 186:707f6e361f3e 108 #define EERDSR_WPEN 0x0080 // Write protect enable
Anna Bridge 186:707f6e361f3e 109
Anna Bridge 186:707f6e361f3e 110 /* ----------------------------------------------------------------
Anna Bridge 186:707f6e361f3e 111 *
Anna Bridge 186:707f6e361f3e 112 * Color LCD Support
Anna Bridge 186:707f6e361f3e 113 * =================
Anna Bridge 186:707f6e361f3e 114 */
Anna Bridge 186:707f6e361f3e 115
Anna Bridge 186:707f6e361f3e 116 // Color LCD Controller Internal Register addresses
Anna Bridge 186:707f6e361f3e 117 #define LSSPCS_BASE (0x4002804C) // LSSP chip select register
Anna Bridge 186:707f6e361f3e 118 #define LSSP_BASE (0x40021000) // LSSP Prime Cell
Anna Bridge 186:707f6e361f3e 119
Anna Bridge 186:707f6e361f3e 120 #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
Anna Bridge 186:707f6e361f3e 121 #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
Anna Bridge 186:707f6e361f3e 122 #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
Anna Bridge 186:707f6e361f3e 123 #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
Anna Bridge 186:707f6e361f3e 124 #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
Anna Bridge 186:707f6e361f3e 125 #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
Anna Bridge 186:707f6e361f3e 126 #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
Anna Bridge 186:707f6e361f3e 127 #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
Anna Bridge 186:707f6e361f3e 128 #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
Anna Bridge 186:707f6e361f3e 129 #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
Anna Bridge 186:707f6e361f3e 130 #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
Anna Bridge 186:707f6e361f3e 131
Anna Bridge 186:707f6e361f3e 132 // LSSPCR0 Control register 0
Anna Bridge 186:707f6e361f3e 133 #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
Anna Bridge 186:707f6e361f3e 134 #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
Anna Bridge 186:707f6e361f3e 135 #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
Anna Bridge 186:707f6e361f3e 136 #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
Anna Bridge 186:707f6e361f3e 137 #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
Anna Bridge 186:707f6e361f3e 138 #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
Anna Bridge 186:707f6e361f3e 139
Anna Bridge 186:707f6e361f3e 140 // LSSPCR1 Control register 1
Anna Bridge 186:707f6e361f3e 141 #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
Anna Bridge 186:707f6e361f3e 142 #define LSSPCR1_MS 0x0004 // Master or Slave mode
Anna Bridge 186:707f6e361f3e 143 #define LSSPCR1_SSE 0x0002 // Serial port enable
Anna Bridge 186:707f6e361f3e 144 #define LSSPCR1_LBM 0x0001 // Loop Back Mode
Anna Bridge 186:707f6e361f3e 145
Anna Bridge 186:707f6e361f3e 146 // LSSPSR Status register
Anna Bridge 186:707f6e361f3e 147 #define LSSPSR_BSY 0x0010 // Busy
Anna Bridge 186:707f6e361f3e 148 #define LSSPSR_RFF 0x0008 // Receive FIFO full
Anna Bridge 186:707f6e361f3e 149 #define LSSPSR_RNE 0x0004 // Receive FIFO not empty
Anna Bridge 186:707f6e361f3e 150 #define LSSPSR_TNF 0x0002 // Transmit FIFO not full
Anna Bridge 186:707f6e361f3e 151 #define LSSPSR_TFE 0x0001 // Transmit FIFO empty
Anna Bridge 186:707f6e361f3e 152
Anna Bridge 186:707f6e361f3e 153 // LSSPCPSR Clock prescale register
Anna Bridge 186:707f6e361f3e 154 #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
Anna Bridge 186:707f6e361f3e 155
Anna Bridge 186:707f6e361f3e 156 // SPICS register
Anna Bridge 186:707f6e361f3e 157 #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
Anna Bridge 186:707f6e361f3e 158 #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
Anna Bridge 186:707f6e361f3e 159 #define LCD_RESET 0x0008 // RESET (CLCD_RESET)
Anna Bridge 186:707f6e361f3e 160 #define LCD_RS 0x0010 // RS (CLCD_RS)
Anna Bridge 186:707f6e361f3e 161 #define LCD_RD 0x0020 // RD (CLCD_RD)
Anna Bridge 186:707f6e361f3e 162 #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
Anna Bridge 186:707f6e361f3e 163
Anna Bridge 186:707f6e361f3e 164 // SPI defaults
Anna Bridge 186:707f6e361f3e 165 #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
Anna Bridge 186:707f6e361f3e 166 #define LSPI_START (0x70) // Start byte for SPI transfer
Anna Bridge 186:707f6e361f3e 167 #define LSPI_RD (0x01) // WR bit 1 within start
Anna Bridge 186:707f6e361f3e 168 #define LSPI_WR (0x00) // WR bit 0 within start
Anna Bridge 186:707f6e361f3e 169 #define LSPI_DATA (0x02) // RS bit 1 within start byte
Anna Bridge 186:707f6e361f3e 170 #define LSPI_INDEX (0x00) // RS bit 0 within start byte
Anna Bridge 186:707f6e361f3e 171
Anna Bridge 186:707f6e361f3e 172 // Screen size
Anna Bridge 186:707f6e361f3e 173 #define LCD_WIDTH 320 // Screen Width (in pixels)
Anna Bridge 186:707f6e361f3e 174 #define LCD_HEIGHT 240 // Screen Height (in pixels)