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targets/TARGET_ARM_FM/TARGET_FVP_MPS2/FVP_MPS2.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* MPS2 CMSIS Library
AnnaBridge 189:f392fc9709a3 2 *
AnnaBridge 189:f392fc9709a3 3 * Copyright (c) 2006-2018 ARM Limited
AnnaBridge 189:f392fc9709a3 4 * All rights reserved.
AnnaBridge 189:f392fc9709a3 5 *
AnnaBridge 189:f392fc9709a3 6 * Redistribution and use in source and binary forms, with or without
AnnaBridge 189:f392fc9709a3 7 * modification, are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 10 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 13 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 14 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 15 *
AnnaBridge 189:f392fc9709a3 16 * 3. Neither the name of the copyright holder nor the names of its contributors
AnnaBridge 189:f392fc9709a3 17 * may be used to endorse or promote products derived from this software without
AnnaBridge 189:f392fc9709a3 18 * specific prior written permission.
AnnaBridge 189:f392fc9709a3 19 *
AnnaBridge 189:f392fc9709a3 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
AnnaBridge 189:f392fc9709a3 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
AnnaBridge 189:f392fc9709a3 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
AnnaBridge 189:f392fc9709a3 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
AnnaBridge 189:f392fc9709a3 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
AnnaBridge 189:f392fc9709a3 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
AnnaBridge 189:f392fc9709a3 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
AnnaBridge 189:f392fc9709a3 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 189:f392fc9709a3 30 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 31 *******************************************************************************/
AnnaBridge 189:f392fc9709a3 32
AnnaBridge 189:f392fc9709a3 33 #ifndef __FVP_MPS2_H
AnnaBridge 189:f392fc9709a3 34 #define __FVP_MPS2_H
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 #include "peripherallink.h" /* device specific header file */
AnnaBridge 189:f392fc9709a3 37
AnnaBridge 189:f392fc9709a3 38 #if defined ( __CC_ARM )
AnnaBridge 189:f392fc9709a3 39 #pragma anon_unions
AnnaBridge 189:f392fc9709a3 40 #endif
AnnaBridge 189:f392fc9709a3 41
AnnaBridge 189:f392fc9709a3 42 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 43 /* FPGA System Register declaration */
AnnaBridge 189:f392fc9709a3 44 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 45
AnnaBridge 189:f392fc9709a3 46 typedef struct
AnnaBridge 189:f392fc9709a3 47 {
AnnaBridge 189:f392fc9709a3 48 __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
AnnaBridge 189:f392fc9709a3 49 // [31:2] : Reserved
AnnaBridge 189:f392fc9709a3 50 // [1:0] : LEDs
AnnaBridge 189:f392fc9709a3 51 uint32_t RESERVED1[1];
AnnaBridge 189:f392fc9709a3 52 __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
AnnaBridge 189:f392fc9709a3 53 // [31:2] : Reserved
AnnaBridge 189:f392fc9709a3 54 // [1:0] : Buttons
AnnaBridge 189:f392fc9709a3 55 uint32_t RESERVED2[1];
AnnaBridge 189:f392fc9709a3 56 __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
AnnaBridge 189:f392fc9709a3 57 __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
AnnaBridge 189:f392fc9709a3 58 __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
AnnaBridge 189:f392fc9709a3 59 // Increments when 32-bit prescale counter reach zero
AnnaBridge 189:f392fc9709a3 60 uint32_t RESERVED3[1];
AnnaBridge 189:f392fc9709a3 61 __IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
AnnaBridge 189:f392fc9709a3 62 // Bit[31:0] : reload value for prescale counter
AnnaBridge 189:f392fc9709a3 63 __IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
AnnaBridge 189:f392fc9709a3 64 // current value of the pre-scaler counter
AnnaBridge 189:f392fc9709a3 65 // The Cycle Up Counter increment when the prescale down counter reach 0
AnnaBridge 189:f392fc9709a3 66 // The pre-scaler counter is reloaded with PRESCALE after reaching 0.
AnnaBridge 189:f392fc9709a3 67 uint32_t RESERVED4[9];
AnnaBridge 189:f392fc9709a3 68 __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
AnnaBridge 189:f392fc9709a3 69 // [31:10] : Reserved
AnnaBridge 189:f392fc9709a3 70 // [9] : SHIELD_1_SPI_nCS
AnnaBridge 189:f392fc9709a3 71 // [8] : SHIELD_0_SPI_nCS
AnnaBridge 189:f392fc9709a3 72 // [7] : ADC_SPI_nCS
AnnaBridge 189:f392fc9709a3 73 // [6] : CLCD_BL_CTRL
AnnaBridge 189:f392fc9709a3 74 // [5] : CLCD_RD
AnnaBridge 189:f392fc9709a3 75 // [4] : CLCD_RS
AnnaBridge 189:f392fc9709a3 76 // [3] : CLCD_RESET
AnnaBridge 189:f392fc9709a3 77 // [2] : RESERVED
AnnaBridge 189:f392fc9709a3 78 // [1] : SPI_nSS
AnnaBridge 189:f392fc9709a3 79 // [0] : CLCD_CS
AnnaBridge 189:f392fc9709a3 80 } MPS2_FPGAIO_TypeDef;
AnnaBridge 189:f392fc9709a3 81
AnnaBridge 189:f392fc9709a3 82 // MISC register bit definitions
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 #define CLCD_CS_Pos 0
AnnaBridge 189:f392fc9709a3 85 #define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
AnnaBridge 189:f392fc9709a3 86 #define SPI_nSS_Pos 1
AnnaBridge 189:f392fc9709a3 87 #define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
AnnaBridge 189:f392fc9709a3 88 #define CLCD_RESET_Pos 3
AnnaBridge 189:f392fc9709a3 89 #define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
AnnaBridge 189:f392fc9709a3 90 #define CLCD_RS_Pos 4
AnnaBridge 189:f392fc9709a3 91 #define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
AnnaBridge 189:f392fc9709a3 92 #define CLCD_RD_Pos 5
AnnaBridge 189:f392fc9709a3 93 #define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
AnnaBridge 189:f392fc9709a3 94 #define CLCD_BL_Pos 6
AnnaBridge 189:f392fc9709a3 95 #define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
AnnaBridge 189:f392fc9709a3 96 #define ADC_nCS_Pos 7
AnnaBridge 189:f392fc9709a3 97 #define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
AnnaBridge 189:f392fc9709a3 98 #define SHIELD_0_nCS_Pos 8
AnnaBridge 189:f392fc9709a3 99 #define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
AnnaBridge 189:f392fc9709a3 100 #define SHIELD_1_nCS_Pos 9
AnnaBridge 189:f392fc9709a3 101 #define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
AnnaBridge 189:f392fc9709a3 102
AnnaBridge 189:f392fc9709a3 103 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 104 /* SCC Register declaration */
AnnaBridge 189:f392fc9709a3 105 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 106
AnnaBridge 189:f392fc9709a3 107 typedef struct //
AnnaBridge 189:f392fc9709a3 108 {
AnnaBridge 189:f392fc9709a3 109 __IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
AnnaBridge 189:f392fc9709a3 110 // [31:1] : Reserved
AnnaBridge 189:f392fc9709a3 111 // [0] 1 : REMAP BlockRam to ZBT
AnnaBridge 189:f392fc9709a3 112 __IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
AnnaBridge 189:f392fc9709a3 113 // [31:8] : Reserved
AnnaBridge 189:f392fc9709a3 114 // [7:0] : MCC LEDs
AnnaBridge 189:f392fc9709a3 115 uint32_t RESERVED0[1];
AnnaBridge 189:f392fc9709a3 116 __I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
AnnaBridge 189:f392fc9709a3 117 // [31:8] : Reserved
AnnaBridge 189:f392fc9709a3 118 // [7:0] : These bits indicate state of the MCC switches
AnnaBridge 189:f392fc9709a3 119 __I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
AnnaBridge 189:f392fc9709a3 120 // [31:4] : Reserved
AnnaBridge 189:f392fc9709a3 121 // [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
AnnaBridge 189:f392fc9709a3 122 uint32_t RESERVED1[35];
AnnaBridge 189:f392fc9709a3 123 __IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
AnnaBridge 189:f392fc9709a3 124 // [31:0] : Data
AnnaBridge 189:f392fc9709a3 125 __IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
AnnaBridge 189:f392fc9709a3 126 // [31:0] : Data
AnnaBridge 189:f392fc9709a3 127 __IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
AnnaBridge 189:f392fc9709a3 128 // [31] : Start (generates interrupt on write to this bit)
AnnaBridge 189:f392fc9709a3 129 // [30] : R/W access
AnnaBridge 189:f392fc9709a3 130 // [29:26] : Reserved
AnnaBridge 189:f392fc9709a3 131 // [25:20] : Function value
AnnaBridge 189:f392fc9709a3 132 // [19:12] : Reserved
AnnaBridge 189:f392fc9709a3 133 // [11:0] : Device (value of 0/1/2 for supported clocks)
AnnaBridge 189:f392fc9709a3 134 __IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
AnnaBridge 189:f392fc9709a3 135 // [31:2] : Reserved
AnnaBridge 189:f392fc9709a3 136 // [1] : Error
AnnaBridge 189:f392fc9709a3 137 // [0] : Complete
AnnaBridge 189:f392fc9709a3 138 __IO uint32_t RESERVED2[20];
AnnaBridge 189:f392fc9709a3 139 __IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
AnnaBridge 189:f392fc9709a3 140 // [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
AnnaBridge 189:f392fc9709a3 141 // [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
AnnaBridge 189:f392fc9709a3 142 // [15:1] : Reserved
AnnaBridge 189:f392fc9709a3 143 // [0] : This bit indicates if all enabled DLLs are locked
AnnaBridge 189:f392fc9709a3 144 uint32_t RESERVED3[957];
AnnaBridge 189:f392fc9709a3 145 __I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
AnnaBridge 189:f392fc9709a3 146 // [31:24] : FPGA build number
AnnaBridge 189:f392fc9709a3 147 // [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
AnnaBridge 189:f392fc9709a3 148 // [19:11] : Reserved
AnnaBridge 189:f392fc9709a3 149 // [10] : if “1” SCC_SW register has been implemented
AnnaBridge 189:f392fc9709a3 150 // [9] : if “1” SCC_LED register has been implemented
AnnaBridge 189:f392fc9709a3 151 // [8] : if “1” DLL lock register has been implemented
AnnaBridge 189:f392fc9709a3 152 // [7:0] : number of SCC configuration register
AnnaBridge 189:f392fc9709a3 153 __I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
AnnaBridge 189:f392fc9709a3 154 // [31:24] : Implementer ID: 0x41 = ARM
AnnaBridge 189:f392fc9709a3 155 // [23:20] : Application note IP variant number
AnnaBridge 189:f392fc9709a3 156 // [19:16] : IP Architecture: 0x4 =AHB
AnnaBridge 189:f392fc9709a3 157 // [15:4] : Primary part number: 386 = AN386
AnnaBridge 189:f392fc9709a3 158 // [3:0] : Application note IP revision number
AnnaBridge 189:f392fc9709a3 159 } MPS2_SCC_TypeDef;
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161
AnnaBridge 189:f392fc9709a3 162 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 163 /* SSP Peripheral declaration */
AnnaBridge 189:f392fc9709a3 164 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 165
AnnaBridge 189:f392fc9709a3 166 typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
AnnaBridge 189:f392fc9709a3 167 {
AnnaBridge 189:f392fc9709a3 168 __IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
AnnaBridge 189:f392fc9709a3 169 // [31:16] : Reserved
AnnaBridge 189:f392fc9709a3 170 // [15:8] : Serial clock rate
AnnaBridge 189:f392fc9709a3 171 // [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
AnnaBridge 189:f392fc9709a3 172 // [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
AnnaBridge 189:f392fc9709a3 173 // [5:4] : Frame format
AnnaBridge 189:f392fc9709a3 174 // [3:0] : Data Size Select
AnnaBridge 189:f392fc9709a3 175 __IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
AnnaBridge 189:f392fc9709a3 176 // [31:4] : Reserved
AnnaBridge 189:f392fc9709a3 177 // [3] : Slave-mode output disable
AnnaBridge 189:f392fc9709a3 178 // [2] : Master or slave mode select
AnnaBridge 189:f392fc9709a3 179 // [1] : Synchronous serial port enable
AnnaBridge 189:f392fc9709a3 180 // [0] : Loop back mode
AnnaBridge 189:f392fc9709a3 181 __IO uint32_t DR; // Offset: 0x008 (R/W) Data register
AnnaBridge 189:f392fc9709a3 182 // [31:16] : Reserved
AnnaBridge 189:f392fc9709a3 183 // [15:0] : Transmit/Receive FIFO
AnnaBridge 189:f392fc9709a3 184 __I uint32_t SR; // Offset: 0x00C (R/ ) Status register
AnnaBridge 189:f392fc9709a3 185 // [31:5] : Reserved
AnnaBridge 189:f392fc9709a3 186 // [4] : PrimeCell SSP busy flag
AnnaBridge 189:f392fc9709a3 187 // [3] : Receive FIFO full
AnnaBridge 189:f392fc9709a3 188 // [2] : Receive FIFO not empty
AnnaBridge 189:f392fc9709a3 189 // [1] : Transmit FIFO not full
AnnaBridge 189:f392fc9709a3 190 // [0] : Transmit FIFO empty
AnnaBridge 189:f392fc9709a3 191 __IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
AnnaBridge 189:f392fc9709a3 192 // [31:8] : Reserved
AnnaBridge 189:f392fc9709a3 193 // [8:0] : Clock prescale divisor
AnnaBridge 189:f392fc9709a3 194 __IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
AnnaBridge 189:f392fc9709a3 195 // [31:4] : Reserved
AnnaBridge 189:f392fc9709a3 196 // [3] : Transmit FIFO interrupt mask
AnnaBridge 189:f392fc9709a3 197 // [2] : Receive FIFO interrupt mask
AnnaBridge 189:f392fc9709a3 198 // [1] : Receive timeout interrupt mask
AnnaBridge 189:f392fc9709a3 199 // [0] : Receive overrun interrupt mask
AnnaBridge 189:f392fc9709a3 200 __I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
AnnaBridge 189:f392fc9709a3 201 // [31:4] : Reserved
AnnaBridge 189:f392fc9709a3 202 // [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
AnnaBridge 189:f392fc9709a3 203 // [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
AnnaBridge 189:f392fc9709a3 204 // [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
AnnaBridge 189:f392fc9709a3 205 // [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
AnnaBridge 189:f392fc9709a3 206 __I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
AnnaBridge 189:f392fc9709a3 207 // [31:4] : Reserved
AnnaBridge 189:f392fc9709a3 208 // [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
AnnaBridge 189:f392fc9709a3 209 // [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
AnnaBridge 189:f392fc9709a3 210 // [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
AnnaBridge 189:f392fc9709a3 211 // [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
AnnaBridge 189:f392fc9709a3 212 __O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
AnnaBridge 189:f392fc9709a3 213 // [31:2] : Reserved
AnnaBridge 189:f392fc9709a3 214 // [1] : Clears the SSPRTINTR interrupt
AnnaBridge 189:f392fc9709a3 215 // [0] : Clears the SSPRORINTR interrupt
AnnaBridge 189:f392fc9709a3 216 __IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
AnnaBridge 189:f392fc9709a3 217 // [31:2] : Reserved
AnnaBridge 189:f392fc9709a3 218 // [1] : Transmit DMA Enable
AnnaBridge 189:f392fc9709a3 219 // [0] : Receive DMA Enable
AnnaBridge 189:f392fc9709a3 220 } MPS2_SSP_TypeDef;
AnnaBridge 189:f392fc9709a3 221
AnnaBridge 189:f392fc9709a3 222
AnnaBridge 189:f392fc9709a3 223 // SSP_CR0 Control register 0
AnnaBridge 189:f392fc9709a3 224 #define SSP_CR0_DSS_Pos 0 // Data Size Select
AnnaBridge 189:f392fc9709a3 225 #define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
AnnaBridge 189:f392fc9709a3 226 #define SSP_CR0_FRF_Pos 4 // Frame Format Select
AnnaBridge 189:f392fc9709a3 227 #define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
AnnaBridge 189:f392fc9709a3 228 #define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
AnnaBridge 189:f392fc9709a3 229 #define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
AnnaBridge 189:f392fc9709a3 230 #define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
AnnaBridge 189:f392fc9709a3 231 #define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
AnnaBridge 189:f392fc9709a3 232 #define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
AnnaBridge 189:f392fc9709a3 233 #define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
AnnaBridge 189:f392fc9709a3 234
AnnaBridge 189:f392fc9709a3 235 #define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
AnnaBridge 189:f392fc9709a3 236 #define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
AnnaBridge 189:f392fc9709a3 237 #define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
AnnaBridge 189:f392fc9709a3 238 #define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
AnnaBridge 189:f392fc9709a3 239
AnnaBridge 189:f392fc9709a3 240 // SSP_CR1 Control register 1
AnnaBridge 189:f392fc9709a3 241 #define SSP_CR1_LBM_Pos 0 // Loop Back Mode
AnnaBridge 189:f392fc9709a3 242 #define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
AnnaBridge 189:f392fc9709a3 243 #define SSP_CR1_SSE_Pos 1 // Serial port enable
AnnaBridge 189:f392fc9709a3 244 #define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
AnnaBridge 189:f392fc9709a3 245 #define SSP_CR1_MS_Pos 2 // Master or Slave mode
AnnaBridge 189:f392fc9709a3 246 #define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
AnnaBridge 189:f392fc9709a3 247 #define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
AnnaBridge 189:f392fc9709a3 248 #define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
AnnaBridge 189:f392fc9709a3 249
AnnaBridge 189:f392fc9709a3 250 // SSP_SR Status register
AnnaBridge 189:f392fc9709a3 251 #define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
AnnaBridge 189:f392fc9709a3 252 #define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
AnnaBridge 189:f392fc9709a3 253 #define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
AnnaBridge 189:f392fc9709a3 254 #define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
AnnaBridge 189:f392fc9709a3 255 #define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
AnnaBridge 189:f392fc9709a3 256 #define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
AnnaBridge 189:f392fc9709a3 257 #define SSP_SR_RFF_Pos 3 // Receive FIFO full
AnnaBridge 189:f392fc9709a3 258 #define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
AnnaBridge 189:f392fc9709a3 259 #define SSP_SR_BSY_Pos 4 // Busy
AnnaBridge 189:f392fc9709a3 260 #define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
AnnaBridge 189:f392fc9709a3 261
AnnaBridge 189:f392fc9709a3 262 // SSP_CPSR Clock prescale register
AnnaBridge 189:f392fc9709a3 263 #define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
AnnaBridge 189:f392fc9709a3 264 #define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
AnnaBridge 189:f392fc9709a3 265
AnnaBridge 189:f392fc9709a3 266 #define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
AnnaBridge 189:f392fc9709a3 267
AnnaBridge 189:f392fc9709a3 268 // SSPIMSC Interrupt mask set and clear register
AnnaBridge 189:f392fc9709a3 269 #define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
AnnaBridge 189:f392fc9709a3 270 #define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
AnnaBridge 189:f392fc9709a3 271 #define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
AnnaBridge 189:f392fc9709a3 272 #define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
AnnaBridge 189:f392fc9709a3 273 #define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
AnnaBridge 189:f392fc9709a3 274 #define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
AnnaBridge 189:f392fc9709a3 275 #define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
AnnaBridge 189:f392fc9709a3 276 #define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
AnnaBridge 189:f392fc9709a3 277
AnnaBridge 189:f392fc9709a3 278 // SSPRIS Raw interrupt status register
AnnaBridge 189:f392fc9709a3 279 #define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
AnnaBridge 189:f392fc9709a3 280 #define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
AnnaBridge 189:f392fc9709a3 281 #define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
AnnaBridge 189:f392fc9709a3 282 #define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
AnnaBridge 189:f392fc9709a3 283 #define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
AnnaBridge 189:f392fc9709a3 284 #define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
AnnaBridge 189:f392fc9709a3 285 #define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
AnnaBridge 189:f392fc9709a3 286 #define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
AnnaBridge 189:f392fc9709a3 287
AnnaBridge 189:f392fc9709a3 288 // SSPMIS Masked interrupt status register
AnnaBridge 189:f392fc9709a3 289 #define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
AnnaBridge 189:f392fc9709a3 290 #define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
AnnaBridge 189:f392fc9709a3 291 #define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
AnnaBridge 189:f392fc9709a3 292 #define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
AnnaBridge 189:f392fc9709a3 293 #define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
AnnaBridge 189:f392fc9709a3 294 #define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
AnnaBridge 189:f392fc9709a3 295 #define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
AnnaBridge 189:f392fc9709a3 296 #define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
AnnaBridge 189:f392fc9709a3 297
AnnaBridge 189:f392fc9709a3 298 // SSPICR Interrupt clear register
AnnaBridge 189:f392fc9709a3 299 #define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
AnnaBridge 189:f392fc9709a3 300 #define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
AnnaBridge 189:f392fc9709a3 301 #define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
AnnaBridge 189:f392fc9709a3 302 #define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
AnnaBridge 189:f392fc9709a3 303
AnnaBridge 189:f392fc9709a3 304 // SSPDMACR DMA control register
AnnaBridge 189:f392fc9709a3 305 #define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
AnnaBridge 189:f392fc9709a3 306 #define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
AnnaBridge 189:f392fc9709a3 307 #define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
AnnaBridge 189:f392fc9709a3 308 #define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
AnnaBridge 189:f392fc9709a3 309
AnnaBridge 189:f392fc9709a3 310 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 311 /* Audio and Touch Screen (I2C) Peripheral declaration */
AnnaBridge 189:f392fc9709a3 312 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 313
AnnaBridge 189:f392fc9709a3 314 typedef struct
AnnaBridge 189:f392fc9709a3 315 {
AnnaBridge 189:f392fc9709a3 316 union {
AnnaBridge 189:f392fc9709a3 317 __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
AnnaBridge 189:f392fc9709a3 318 __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
AnnaBridge 189:f392fc9709a3 319 };
AnnaBridge 189:f392fc9709a3 320 __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
AnnaBridge 189:f392fc9709a3 321 } MPS2_I2C_TypeDef;
AnnaBridge 189:f392fc9709a3 322
AnnaBridge 189:f392fc9709a3 323 #define SDA 1 << 1
AnnaBridge 189:f392fc9709a3 324 #define SCL 1 << 0
AnnaBridge 189:f392fc9709a3 325
AnnaBridge 189:f392fc9709a3 326
AnnaBridge 189:f392fc9709a3 327 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 328 /* Audio I2S Peripheral declaration */
AnnaBridge 189:f392fc9709a3 329 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 330
AnnaBridge 189:f392fc9709a3 331 typedef struct
AnnaBridge 189:f392fc9709a3 332 {
AnnaBridge 189:f392fc9709a3 333 /*!< Offset: 0x000 CONTROL Register (R/W) */
AnnaBridge 189:f392fc9709a3 334 __IO uint32_t CONTROL; // <h> CONTROL </h>
AnnaBridge 189:f392fc9709a3 335 // <o.0> TX Enable
AnnaBridge 189:f392fc9709a3 336 // <0=> TX disabled
AnnaBridge 189:f392fc9709a3 337 // <1=> TX enabled
AnnaBridge 189:f392fc9709a3 338 // <o.1> TX IRQ Enable
AnnaBridge 189:f392fc9709a3 339 // <0=> TX IRQ disabled
AnnaBridge 189:f392fc9709a3 340 // <1=> TX IRQ enabled
AnnaBridge 189:f392fc9709a3 341 // <o.2> RX Enable
AnnaBridge 189:f392fc9709a3 342 // <0=> RX disabled
AnnaBridge 189:f392fc9709a3 343 // <1=> RX enabled
AnnaBridge 189:f392fc9709a3 344 // <o.3> RX IRQ Enable
AnnaBridge 189:f392fc9709a3 345 // <0=> RX IRQ disabled
AnnaBridge 189:f392fc9709a3 346 // <1=> RX IRQ enabled
AnnaBridge 189:f392fc9709a3 347 // <o.10..8> TX Buffer Water Level
AnnaBridge 189:f392fc9709a3 348 // <0=> / IRQ triggers when any space available
AnnaBridge 189:f392fc9709a3 349 // <1=> / IRQ triggers when more than 1 space available
AnnaBridge 189:f392fc9709a3 350 // <2=> / IRQ triggers when more than 2 space available
AnnaBridge 189:f392fc9709a3 351 // <3=> / IRQ triggers when more than 3 space available
AnnaBridge 189:f392fc9709a3 352 // <4=> Undefined!
AnnaBridge 189:f392fc9709a3 353 // <5=> Undefined!
AnnaBridge 189:f392fc9709a3 354 // <6=> Undefined!
AnnaBridge 189:f392fc9709a3 355 // <7=> Undefined!
AnnaBridge 189:f392fc9709a3 356 // <o.14..12> RX Buffer Water Level
AnnaBridge 189:f392fc9709a3 357 // <0=> Undefined!
AnnaBridge 189:f392fc9709a3 358 // <1=> / IRQ triggers when less than 1 space available
AnnaBridge 189:f392fc9709a3 359 // <2=> / IRQ triggers when less than 2 space available
AnnaBridge 189:f392fc9709a3 360 // <3=> / IRQ triggers when less than 3 space available
AnnaBridge 189:f392fc9709a3 361 // <4=> / IRQ triggers when less than 4 space available
AnnaBridge 189:f392fc9709a3 362 // <5=> Undefined!
AnnaBridge 189:f392fc9709a3 363 // <6=> Undefined!
AnnaBridge 189:f392fc9709a3 364 // <7=> Undefined!
AnnaBridge 189:f392fc9709a3 365 // <o.16> FIFO reset
AnnaBridge 189:f392fc9709a3 366 // <0=> Normal operation
AnnaBridge 189:f392fc9709a3 367 // <1=> FIFO reset
AnnaBridge 189:f392fc9709a3 368 // <o.17> Audio Codec reset
AnnaBridge 189:f392fc9709a3 369 // <0=> Normal operation
AnnaBridge 189:f392fc9709a3 370 // <1=> Assert audio Codec reset
AnnaBridge 189:f392fc9709a3 371 /*!< Offset: 0x004 STATUS Register (R/ ) */
AnnaBridge 189:f392fc9709a3 372 __I uint32_t STATUS; // <h> STATUS </h>
AnnaBridge 189:f392fc9709a3 373 // <o.0> TX Buffer alert
AnnaBridge 189:f392fc9709a3 374 // <0=> TX buffer don't need service yet
AnnaBridge 189:f392fc9709a3 375 // <1=> TX buffer need service
AnnaBridge 189:f392fc9709a3 376 // <o.1> RX Buffer alert
AnnaBridge 189:f392fc9709a3 377 // <0=> RX buffer don't need service yet
AnnaBridge 189:f392fc9709a3 378 // <1=> RX buffer need service
AnnaBridge 189:f392fc9709a3 379 // <o.2> TX Buffer Empty
AnnaBridge 189:f392fc9709a3 380 // <0=> TX buffer have data
AnnaBridge 189:f392fc9709a3 381 // <1=> TX buffer empty
AnnaBridge 189:f392fc9709a3 382 // <o.3> TX Buffer Full
AnnaBridge 189:f392fc9709a3 383 // <0=> TX buffer not full
AnnaBridge 189:f392fc9709a3 384 // <1=> TX buffer full
AnnaBridge 189:f392fc9709a3 385 // <o.4> RX Buffer Empty
AnnaBridge 189:f392fc9709a3 386 // <0=> RX buffer have data
AnnaBridge 189:f392fc9709a3 387 // <1=> RX buffer empty
AnnaBridge 189:f392fc9709a3 388 // <o.5> RX Buffer Full
AnnaBridge 189:f392fc9709a3 389 // <0=> RX buffer not full
AnnaBridge 189:f392fc9709a3 390 // <1=> RX buffer full
AnnaBridge 189:f392fc9709a3 391 union {
AnnaBridge 189:f392fc9709a3 392 /*!< Offset: 0x008 Error Status Register (R/ ) */
AnnaBridge 189:f392fc9709a3 393 __I uint32_t ERROR; // <h> ERROR </h>
AnnaBridge 189:f392fc9709a3 394 // <o.0> TX error
AnnaBridge 189:f392fc9709a3 395 // <0=> Okay
AnnaBridge 189:f392fc9709a3 396 // <1=> TX overrun/underrun
AnnaBridge 189:f392fc9709a3 397 // <o.1> RX error
AnnaBridge 189:f392fc9709a3 398 // <0=> Okay
AnnaBridge 189:f392fc9709a3 399 // <1=> RX overrun/underrun
AnnaBridge 189:f392fc9709a3 400 /*!< Offset: 0x008 Error Clear Register ( /W) */
AnnaBridge 189:f392fc9709a3 401 __O uint32_t ERRORCLR; // <h> ERRORCLR </h>
AnnaBridge 189:f392fc9709a3 402 // <o.0> TX error
AnnaBridge 189:f392fc9709a3 403 // <0=> Okay
AnnaBridge 189:f392fc9709a3 404 // <1=> Clear TX error
AnnaBridge 189:f392fc9709a3 405 // <o.1> RX error
AnnaBridge 189:f392fc9709a3 406 // <0=> Okay
AnnaBridge 189:f392fc9709a3 407 // <1=> Clear RX error
AnnaBridge 189:f392fc9709a3 408 };
AnnaBridge 189:f392fc9709a3 409 /*!< Offset: 0x00C Divide ratio Register (R/W) */
AnnaBridge 189:f392fc9709a3 410 __IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
AnnaBridge 189:f392fc9709a3 411 // <o.9..0> TX error (default 0x80)
AnnaBridge 189:f392fc9709a3 412 /*!< Offset: 0x010 Transmit Buffer ( /W) */
AnnaBridge 189:f392fc9709a3 413 __O uint32_t TXBUF; // <h> Transmit buffer </h>
AnnaBridge 189:f392fc9709a3 414 // <o.15..0> Right channel
AnnaBridge 189:f392fc9709a3 415 // <o.31..16> Left channel
AnnaBridge 189:f392fc9709a3 416 /*!< Offset: 0x014 Receive Buffer (R/ ) */
AnnaBridge 189:f392fc9709a3 417 __I uint32_t RXBUF; // <h> Receive buffer </h>
AnnaBridge 189:f392fc9709a3 418 // <o.15..0> Right channel
AnnaBridge 189:f392fc9709a3 419 // <o.31..16> Left channel
AnnaBridge 189:f392fc9709a3 420 uint32_t RESERVED1[186];
AnnaBridge 189:f392fc9709a3 421 __IO uint32_t ITCR; // <h> Integration Test Control Register </h>
AnnaBridge 189:f392fc9709a3 422 // <o.0> ITEN
AnnaBridge 189:f392fc9709a3 423 // <0=> Normal operation
AnnaBridge 189:f392fc9709a3 424 // <1=> Integration Test mode enable
AnnaBridge 189:f392fc9709a3 425 __O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
AnnaBridge 189:f392fc9709a3 426 // <o.0> SDIN
AnnaBridge 189:f392fc9709a3 427 __O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
AnnaBridge 189:f392fc9709a3 428 // <o.0> SDOUT
AnnaBridge 189:f392fc9709a3 429 // <o.1> SCLK
AnnaBridge 189:f392fc9709a3 430 // <o.2> LRCK
AnnaBridge 189:f392fc9709a3 431 // <o.3> IRQOUT
AnnaBridge 189:f392fc9709a3 432 } MPS2_I2S_TypeDef;
AnnaBridge 189:f392fc9709a3 433
AnnaBridge 189:f392fc9709a3 434 #define I2S_CONTROL_TXEN_Pos 0
AnnaBridge 189:f392fc9709a3 435 #define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
AnnaBridge 189:f392fc9709a3 436
AnnaBridge 189:f392fc9709a3 437 #define I2S_CONTROL_TXIRQEN_Pos 1
AnnaBridge 189:f392fc9709a3 438 #define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
AnnaBridge 189:f392fc9709a3 439
AnnaBridge 189:f392fc9709a3 440 #define I2S_CONTROL_RXEN_Pos 2
AnnaBridge 189:f392fc9709a3 441 #define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
AnnaBridge 189:f392fc9709a3 442
AnnaBridge 189:f392fc9709a3 443 #define I2S_CONTROL_RXIRQEN_Pos 3
AnnaBridge 189:f392fc9709a3 444 #define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
AnnaBridge 189:f392fc9709a3 445
AnnaBridge 189:f392fc9709a3 446 #define I2S_CONTROL_TXWLVL_Pos 8
AnnaBridge 189:f392fc9709a3 447 #define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
AnnaBridge 189:f392fc9709a3 448
AnnaBridge 189:f392fc9709a3 449 #define I2S_CONTROL_RXWLVL_Pos 12
AnnaBridge 189:f392fc9709a3 450 #define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
AnnaBridge 189:f392fc9709a3 451 /* FIFO reset*/
AnnaBridge 189:f392fc9709a3 452 #define I2S_CONTROL_FIFORST_Pos 16
AnnaBridge 189:f392fc9709a3 453 #define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
AnnaBridge 189:f392fc9709a3 454 /* Codec reset*/
AnnaBridge 189:f392fc9709a3 455 #define I2S_CONTROL_CODECRST_Pos 17
AnnaBridge 189:f392fc9709a3 456 #define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
AnnaBridge 189:f392fc9709a3 457
AnnaBridge 189:f392fc9709a3 458 #define I2S_STATUS_TXIRQ_Pos 0
AnnaBridge 189:f392fc9709a3 459 #define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
AnnaBridge 189:f392fc9709a3 460
AnnaBridge 189:f392fc9709a3 461 #define I2S_STATUS_RXIRQ_Pos 1
AnnaBridge 189:f392fc9709a3 462 #define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
AnnaBridge 189:f392fc9709a3 463
AnnaBridge 189:f392fc9709a3 464 #define I2S_STATUS_TXEmpty_Pos 2
AnnaBridge 189:f392fc9709a3 465 #define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
AnnaBridge 189:f392fc9709a3 466
AnnaBridge 189:f392fc9709a3 467 #define I2S_STATUS_TXFull_Pos 3
AnnaBridge 189:f392fc9709a3 468 #define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
AnnaBridge 189:f392fc9709a3 469
AnnaBridge 189:f392fc9709a3 470 #define I2S_STATUS_RXEmpty_Pos 4
AnnaBridge 189:f392fc9709a3 471 #define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
AnnaBridge 189:f392fc9709a3 472
AnnaBridge 189:f392fc9709a3 473 #define I2S_STATUS_RXFull_Pos 5
AnnaBridge 189:f392fc9709a3 474 #define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
AnnaBridge 189:f392fc9709a3 475
AnnaBridge 189:f392fc9709a3 476 #define I2S_ERROR_TXERR_Pos 0
AnnaBridge 189:f392fc9709a3 477 #define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
AnnaBridge 189:f392fc9709a3 478
AnnaBridge 189:f392fc9709a3 479 #define I2S_ERROR_RXERR_Pos 1
AnnaBridge 189:f392fc9709a3 480 #define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
AnnaBridge 189:f392fc9709a3 481
AnnaBridge 189:f392fc9709a3 482
AnnaBridge 189:f392fc9709a3 483 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 484 /* Peripheral memory map */
AnnaBridge 189:f392fc9709a3 485 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 486
AnnaBridge 189:f392fc9709a3 487 #define MPS2_SSP1_BASE (0x40020000ul) /* User SSP Base Address */
AnnaBridge 189:f392fc9709a3 488 #define MPS2_SSP0_BASE (0x40021000ul) /* CLCD SSP Base Address */
AnnaBridge 189:f392fc9709a3 489 #define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
AnnaBridge 189:f392fc9709a3 490 #define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
AnnaBridge 189:f392fc9709a3 491 #define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
AnnaBridge 189:f392fc9709a3 492 #define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
AnnaBridge 189:f392fc9709a3 493 #define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
AnnaBridge 189:f392fc9709a3 494 #define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
AnnaBridge 189:f392fc9709a3 495 #define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
AnnaBridge 189:f392fc9709a3 496 #define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Shield 0 I2C Base Address */
AnnaBridge 189:f392fc9709a3 497 #define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Shield 1 I2C Base Address */
AnnaBridge 189:f392fc9709a3 498 #define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
AnnaBridge 189:f392fc9709a3 499
AnnaBridge 189:f392fc9709a3 500 #define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
AnnaBridge 189:f392fc9709a3 501 #define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
AnnaBridge 189:f392fc9709a3 502
AnnaBridge 189:f392fc9709a3 503 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 504 /* Peripheral declaration */
AnnaBridge 189:f392fc9709a3 505 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 506
AnnaBridge 189:f392fc9709a3 507 #define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
AnnaBridge 189:f392fc9709a3 508 #define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
AnnaBridge 189:f392fc9709a3 509 #define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
AnnaBridge 189:f392fc9709a3 510 #define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
AnnaBridge 189:f392fc9709a3 511 #define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
AnnaBridge 189:f392fc9709a3 512 #define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
AnnaBridge 189:f392fc9709a3 513 #define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
AnnaBridge 189:f392fc9709a3 514 #define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
AnnaBridge 189:f392fc9709a3 515 #define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
AnnaBridge 189:f392fc9709a3 516 #define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
AnnaBridge 189:f392fc9709a3 517 #define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
AnnaBridge 189:f392fc9709a3 518 #define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
AnnaBridge 189:f392fc9709a3 519
AnnaBridge 189:f392fc9709a3 520 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 521 /* General Function Definitions */
AnnaBridge 189:f392fc9709a3 522 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 523
AnnaBridge 189:f392fc9709a3 524
AnnaBridge 189:f392fc9709a3 525 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 526 /* General MACRO Definitions */
AnnaBridge 189:f392fc9709a3 527 /******************************************************************************/
AnnaBridge 189:f392fc9709a3 528
AnnaBridge 189:f392fc9709a3 529
AnnaBridge 189:f392fc9709a3 530
AnnaBridge 189:f392fc9709a3 531 #endif /* __FVP_MPS2_H */