mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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hal/mpu/mbed_mpu_v8m.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2018 ARM Limited
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 5 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 6 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 13 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 14 * limitations under the License.
AnnaBridge 189:f392fc9709a3 15 */
AnnaBridge 189:f392fc9709a3 16 #include "hal/mpu_api.h"
AnnaBridge 189:f392fc9709a3 17 #include "platform/mbed_assert.h"
AnnaBridge 189:f392fc9709a3 18 #include "cmsis.h"
AnnaBridge 189:f392fc9709a3 19
AnnaBridge 189:f392fc9709a3 20 #if ((__ARM_ARCH_8M_BASE__ == 1U) || (__ARM_ARCH_8M_MAIN__ == 1U)) && \
AnnaBridge 189:f392fc9709a3 21 defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) && \
AnnaBridge 189:f392fc9709a3 22 !defined(MBED_MPU_CUSTOM)
AnnaBridge 189:f392fc9709a3 23
AnnaBridge 189:f392fc9709a3 24 #if !DEVICE_MPU
AnnaBridge 189:f392fc9709a3 25 #error "Device has v8m MPU but it is not enabled. Add 'MPU' to device_has in targets.json"
AnnaBridge 189:f392fc9709a3 26 #endif
AnnaBridge 189:f392fc9709a3 27
AnnaBridge 189:f392fc9709a3 28 #ifdef MBED_CONF_TARGET_MPU_ROM_END
AnnaBridge 189:f392fc9709a3 29 #define MBED_MPU_ROM_END MBED_CONF_TARGET_MPU_ROM_END
AnnaBridge 189:f392fc9709a3 30 #else
AnnaBridge 189:f392fc9709a3 31 #define MBED_MPU_ROM_END (0x10000000 - 1)
AnnaBridge 189:f392fc9709a3 32 #endif
AnnaBridge 189:f392fc9709a3 33 #define MBED_MPU_RAM_START (MBED_MPU_ROM_END + 1)
AnnaBridge 189:f392fc9709a3 34
AnnaBridge 189:f392fc9709a3 35 MBED_STATIC_ASSERT(MBED_MPU_ROM_END <= 0x20000000 - 1,
AnnaBridge 189:f392fc9709a3 36 "Unsupported value for MBED_MPU_ROM_END");
AnnaBridge 189:f392fc9709a3 37
AnnaBridge 189:f392fc9709a3 38 void mbed_mpu_init()
AnnaBridge 189:f392fc9709a3 39 {
AnnaBridge 189:f392fc9709a3 40 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 41 __DMB();
AnnaBridge 189:f392fc9709a3 42
AnnaBridge 189:f392fc9709a3 43 const uint32_t regions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos;
AnnaBridge 189:f392fc9709a3 44
AnnaBridge 189:f392fc9709a3 45 // Our MPU setup requires 4 or 5 regions - if this assert is hit, remove
AnnaBridge 189:f392fc9709a3 46 // a region by setting MPU_ROM_END to 0x1fffffff, or remove MPU from device_has
AnnaBridge 189:f392fc9709a3 47 #if MBED_MPU_RAM_START == 0x20000000
AnnaBridge 189:f392fc9709a3 48 MBED_ASSERT(regions >= 4);
AnnaBridge 189:f392fc9709a3 49 #else
AnnaBridge 189:f392fc9709a3 50 MBED_ASSERT(regions >= 5);
AnnaBridge 189:f392fc9709a3 51 #endif
AnnaBridge 189:f392fc9709a3 52
AnnaBridge 189:f392fc9709a3 53 // Disable the MCU
AnnaBridge 189:f392fc9709a3 54 MPU->CTRL = 0;
AnnaBridge 189:f392fc9709a3 55
AnnaBridge 189:f392fc9709a3 56 // Reset all mapping
AnnaBridge 189:f392fc9709a3 57 for (uint32_t i = 0; i < regions; i++) {
AnnaBridge 189:f392fc9709a3 58 ARM_MPU_ClrRegion(i);
AnnaBridge 189:f392fc9709a3 59 }
AnnaBridge 189:f392fc9709a3 60
AnnaBridge 189:f392fc9709a3 61 /*
AnnaBridge 189:f392fc9709a3 62 * ARMv8-M memory map:
AnnaBridge 189:f392fc9709a3 63 *
AnnaBridge 189:f392fc9709a3 64 * Start End Name Executable by default Default cache Mbed MPU protection
AnnaBridge 189:f392fc9709a3 65 * 0x00000000 - 0x1FFFFFFF Code Yes WT, WA Write disabled for first portion and execute disabled for the rest
AnnaBridge 189:f392fc9709a3 66 * 0x20000000 - 0x3FFFFFFF SRAM Yes WB, WA, RA Execute disabled
AnnaBridge 189:f392fc9709a3 67 * 0x40000000 - 0x5FFFFFFF Peripheral No
AnnaBridge 189:f392fc9709a3 68 * 0x60000000 - 0x7FFFFFFF RAM Yes WB, WA, RA Execute disabled
AnnaBridge 189:f392fc9709a3 69 * 0x80000000 - 0x9FFFFFFF RAM Yes WT, RA Execute disabled
AnnaBridge 189:f392fc9709a3 70 * 0xA0000000 - 0xBFFFFFFF Device No
AnnaBridge 189:f392fc9709a3 71 * 0xC0000000 - 0xDFFFFFFF Device No
AnnaBridge 189:f392fc9709a3 72 * 0xE0000000 - 0xFFFFFFFF System No
AnnaBridge 189:f392fc9709a3 73 */
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 const uint8_t WTRA = ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0); // Non-transient, Write-Through, Read-allocate, Not Write-allocate
AnnaBridge 189:f392fc9709a3 76 const uint8_t WBWARA = ARM_MPU_ATTR_MEMORY_(1, 1, 1, 1); // Non-transient, Write-Back, Read-allocate, Write-allocate
AnnaBridge 189:f392fc9709a3 77 enum {
AnnaBridge 189:f392fc9709a3 78 AttrIndex_WTRA,
AnnaBridge 189:f392fc9709a3 79 AttrIndex_WBWARA,
AnnaBridge 189:f392fc9709a3 80 };
AnnaBridge 189:f392fc9709a3 81
AnnaBridge 189:f392fc9709a3 82 ARM_MPU_SetMemAttr(AttrIndex_WTRA, ARM_MPU_ATTR(WTRA, WTRA));
AnnaBridge 189:f392fc9709a3 83 ARM_MPU_SetMemAttr(AttrIndex_WBWARA, ARM_MPU_ATTR(WBWARA, WBWARA));
AnnaBridge 189:f392fc9709a3 84
AnnaBridge 189:f392fc9709a3 85 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 86 0, // Region
AnnaBridge 189:f392fc9709a3 87 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 88 0x00000000, // Base
AnnaBridge 189:f392fc9709a3 89 ARM_MPU_SH_NON, // Non-shareable
AnnaBridge 189:f392fc9709a3 90 1, // Read-Only
AnnaBridge 189:f392fc9709a3 91 1, // Non-Privileged
AnnaBridge 189:f392fc9709a3 92 0), // Execute Never disabled
AnnaBridge 189:f392fc9709a3 93 ARM_MPU_RLAR(
AnnaBridge 189:f392fc9709a3 94 MBED_MPU_ROM_END, // Limit
AnnaBridge 189:f392fc9709a3 95 AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate
AnnaBridge 189:f392fc9709a3 96 );
AnnaBridge 189:f392fc9709a3 97
AnnaBridge 189:f392fc9709a3 98 #if MBED_MPU_RAM_START != 0x20000000
AnnaBridge 189:f392fc9709a3 99 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 100 4, // Region
AnnaBridge 189:f392fc9709a3 101 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 102 MBED_MPU_RAM_START, // Base
AnnaBridge 189:f392fc9709a3 103 ARM_MPU_SH_NON, // Non-shareable
AnnaBridge 189:f392fc9709a3 104 0, // Read-Write
AnnaBridge 189:f392fc9709a3 105 1, // Non-Privileged
AnnaBridge 189:f392fc9709a3 106 1), // Execute Never enabled
AnnaBridge 189:f392fc9709a3 107 ARM_MPU_RLAR(
AnnaBridge 189:f392fc9709a3 108 0x1FFFFFFF, // Limit
AnnaBridge 189:f392fc9709a3 109 AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate
AnnaBridge 189:f392fc9709a3 110 );
AnnaBridge 189:f392fc9709a3 111 #define LAST_RAM_REGION 4
AnnaBridge 189:f392fc9709a3 112 #else
AnnaBridge 189:f392fc9709a3 113 #define LAST_RAM_REGION 3
AnnaBridge 189:f392fc9709a3 114 #endif
AnnaBridge 189:f392fc9709a3 115
AnnaBridge 189:f392fc9709a3 116 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 117 1, // Region
AnnaBridge 189:f392fc9709a3 118 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 119 0x20000000, // Base
AnnaBridge 189:f392fc9709a3 120 ARM_MPU_SH_NON, // Non-shareable
AnnaBridge 189:f392fc9709a3 121 0, // Read-Write
AnnaBridge 189:f392fc9709a3 122 1, // Non-Privileged
AnnaBridge 189:f392fc9709a3 123 1), // Execute Never enabled
AnnaBridge 189:f392fc9709a3 124 ARM_MPU_RLAR(
AnnaBridge 189:f392fc9709a3 125 0x3FFFFFFF, // Limit
AnnaBridge 189:f392fc9709a3 126 AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate
AnnaBridge 189:f392fc9709a3 127 );
AnnaBridge 189:f392fc9709a3 128
AnnaBridge 189:f392fc9709a3 129 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 130 2, // Region
AnnaBridge 189:f392fc9709a3 131 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 132 0x60000000, // Base
AnnaBridge 189:f392fc9709a3 133 ARM_MPU_SH_NON, // Non-shareable
AnnaBridge 189:f392fc9709a3 134 0, // Read-Write
AnnaBridge 189:f392fc9709a3 135 1, // Non-Privileged
AnnaBridge 189:f392fc9709a3 136 1), // Execute Never enabled
AnnaBridge 189:f392fc9709a3 137 ARM_MPU_RLAR(
AnnaBridge 189:f392fc9709a3 138 0x7FFFFFFF, // Limit
AnnaBridge 189:f392fc9709a3 139 AttrIndex_WBWARA) // Attribute index - Write-Back, Write-allocate
AnnaBridge 189:f392fc9709a3 140 );
AnnaBridge 189:f392fc9709a3 141
AnnaBridge 189:f392fc9709a3 142 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 143 3, // Region
AnnaBridge 189:f392fc9709a3 144 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 145 0x80000000, // Base
AnnaBridge 189:f392fc9709a3 146 ARM_MPU_SH_NON, // Non-shareable
AnnaBridge 189:f392fc9709a3 147 0, // Read-Write
AnnaBridge 189:f392fc9709a3 148 1, // Non-Privileged
AnnaBridge 189:f392fc9709a3 149 1), // Execute Never enabled
AnnaBridge 189:f392fc9709a3 150 ARM_MPU_RLAR(
AnnaBridge 189:f392fc9709a3 151 0x9FFFFFFF, // Limit
AnnaBridge 189:f392fc9709a3 152 AttrIndex_WTRA) // Attribute index - Write-Through, Read-allocate
AnnaBridge 189:f392fc9709a3 153 );
AnnaBridge 189:f392fc9709a3 154
AnnaBridge 189:f392fc9709a3 155 // Enable the MPU
AnnaBridge 189:f392fc9709a3 156 MPU->CTRL =
AnnaBridge 189:f392fc9709a3 157 (1 << MPU_CTRL_PRIVDEFENA_Pos) | // Use the default memory map for unmapped addresses
AnnaBridge 189:f392fc9709a3 158 (1 << MPU_CTRL_HFNMIENA_Pos) | // Keep MPU turned on for faults
AnnaBridge 189:f392fc9709a3 159 (1 << MPU_CTRL_ENABLE_Pos); // Enable MPU
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 162 __DSB();
AnnaBridge 189:f392fc9709a3 163 __ISB();
AnnaBridge 189:f392fc9709a3 164 }
AnnaBridge 189:f392fc9709a3 165
AnnaBridge 189:f392fc9709a3 166 void mbed_mpu_free()
AnnaBridge 189:f392fc9709a3 167 {
AnnaBridge 189:f392fc9709a3 168 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 169 __DMB();
AnnaBridge 189:f392fc9709a3 170
AnnaBridge 189:f392fc9709a3 171 // Disable the MCU
AnnaBridge 189:f392fc9709a3 172 MPU->CTRL = 0;
AnnaBridge 189:f392fc9709a3 173
AnnaBridge 189:f392fc9709a3 174 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 175 __DSB();
AnnaBridge 189:f392fc9709a3 176 __ISB();
AnnaBridge 189:f392fc9709a3 177 }
AnnaBridge 189:f392fc9709a3 178
AnnaBridge 189:f392fc9709a3 179 static void enable_region(bool enable, uint32_t region)
AnnaBridge 189:f392fc9709a3 180 {
AnnaBridge 189:f392fc9709a3 181 MPU->RNR = region;
AnnaBridge 189:f392fc9709a3 182 MPU->RLAR = (MPU->RLAR & ~MPU_RLAR_EN_Msk) | (enable << MPU_RLAR_EN_Pos);
AnnaBridge 189:f392fc9709a3 183 }
AnnaBridge 189:f392fc9709a3 184
AnnaBridge 189:f392fc9709a3 185 void mbed_mpu_enable_rom_wn(bool enable)
AnnaBridge 189:f392fc9709a3 186 {
AnnaBridge 189:f392fc9709a3 187 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 188 __DMB();
AnnaBridge 189:f392fc9709a3 189
AnnaBridge 189:f392fc9709a3 190 enable_region(enable, 0);
AnnaBridge 189:f392fc9709a3 191
AnnaBridge 189:f392fc9709a3 192 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 193 __DSB();
AnnaBridge 189:f392fc9709a3 194 __ISB();
AnnaBridge 189:f392fc9709a3 195 }
AnnaBridge 189:f392fc9709a3 196
AnnaBridge 189:f392fc9709a3 197 void mbed_mpu_enable_ram_xn(bool enable)
AnnaBridge 189:f392fc9709a3 198 {
AnnaBridge 189:f392fc9709a3 199 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 200 __DMB();
AnnaBridge 189:f392fc9709a3 201
AnnaBridge 189:f392fc9709a3 202 for (uint32_t region = 1; region <= LAST_RAM_REGION; region++) {
AnnaBridge 189:f392fc9709a3 203 enable_region(enable, region);
AnnaBridge 189:f392fc9709a3 204 }
AnnaBridge 189:f392fc9709a3 205
AnnaBridge 189:f392fc9709a3 206 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 207 __DSB();
AnnaBridge 189:f392fc9709a3 208 __ISB();
AnnaBridge 189:f392fc9709a3 209 }
AnnaBridge 189:f392fc9709a3 210
AnnaBridge 189:f392fc9709a3 211 #endif