mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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hal/mpu/mbed_mpu_v7m.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /* mbed Microcontroller Library
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2018 ARM Limited
AnnaBridge 189:f392fc9709a3 3 *
AnnaBridge 189:f392fc9709a3 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 189:f392fc9709a3 5 * you may not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 6 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 189:f392fc9709a3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 13 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 14 * limitations under the License.
AnnaBridge 189:f392fc9709a3 15 */
AnnaBridge 189:f392fc9709a3 16 #include "hal/mpu_api.h"
AnnaBridge 189:f392fc9709a3 17 #include "platform/mbed_assert.h"
AnnaBridge 189:f392fc9709a3 18 #include "cmsis.h"
AnnaBridge 189:f392fc9709a3 19
AnnaBridge 189:f392fc9709a3 20 #if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_6M__ == 1U)) && \
AnnaBridge 189:f392fc9709a3 21 defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) && \
AnnaBridge 189:f392fc9709a3 22 !defined(MBED_MPU_CUSTOM)
AnnaBridge 189:f392fc9709a3 23
AnnaBridge 189:f392fc9709a3 24 #if !DEVICE_MPU
AnnaBridge 189:f392fc9709a3 25 #error "Device has v7m MPU but it is not enabled. Add 'MPU' to device_has in targets.json"
AnnaBridge 189:f392fc9709a3 26 #endif
AnnaBridge 189:f392fc9709a3 27
AnnaBridge 189:f392fc9709a3 28 #ifdef MBED_CONF_TARGET_MPU_ROM_END
AnnaBridge 189:f392fc9709a3 29 #define MBED_MPU_ROM_END MBED_CONF_TARGET_MPU_ROM_END
AnnaBridge 189:f392fc9709a3 30 #else
AnnaBridge 189:f392fc9709a3 31 #define MBED_MPU_ROM_END (0x10000000 - 1)
AnnaBridge 189:f392fc9709a3 32 #endif
AnnaBridge 189:f392fc9709a3 33 #define MBED_MPU_RAM_START (MBED_MPU_ROM_END + 1)
AnnaBridge 189:f392fc9709a3 34
AnnaBridge 189:f392fc9709a3 35 MBED_STATIC_ASSERT(
AnnaBridge 189:f392fc9709a3 36 MBED_MPU_ROM_END == 0x04000000 - 1 ||
AnnaBridge 189:f392fc9709a3 37 MBED_MPU_ROM_END == 0x08000000 - 1 ||
AnnaBridge 189:f392fc9709a3 38 MBED_MPU_ROM_END == 0x0C000000 - 1 ||
AnnaBridge 189:f392fc9709a3 39 MBED_MPU_ROM_END == 0x10000000 - 1 ||
AnnaBridge 189:f392fc9709a3 40 MBED_MPU_ROM_END == 0x14000000 - 1 ||
AnnaBridge 189:f392fc9709a3 41 MBED_MPU_ROM_END == 0x18000000 - 1 ||
AnnaBridge 189:f392fc9709a3 42 MBED_MPU_ROM_END == 0x1C000000 - 1 ||
AnnaBridge 189:f392fc9709a3 43 MBED_MPU_ROM_END == 0x20000000 - 1,
AnnaBridge 189:f392fc9709a3 44 "Unsupported value for MBED_MPU_ROM_END");
AnnaBridge 189:f392fc9709a3 45
AnnaBridge 189:f392fc9709a3 46 void mbed_mpu_init()
AnnaBridge 189:f392fc9709a3 47 {
AnnaBridge 189:f392fc9709a3 48 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 49 __DMB();
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 const uint32_t regions = (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos;
AnnaBridge 189:f392fc9709a3 52
AnnaBridge 189:f392fc9709a3 53 // Our MPU setup requires 3 or 4 regions - if this assert is hit, remove
AnnaBridge 189:f392fc9709a3 54 // a region by setting MPU_ROM_END to 0x1fffffff, or remove MPU from device_has
AnnaBridge 189:f392fc9709a3 55 #if MBED_MPU_RAM_START == 0x20000000
AnnaBridge 189:f392fc9709a3 56 MBED_ASSERT(regions >= 3);
AnnaBridge 189:f392fc9709a3 57 #else
AnnaBridge 189:f392fc9709a3 58 MBED_ASSERT(regions >= 4);
AnnaBridge 189:f392fc9709a3 59 #endif
AnnaBridge 189:f392fc9709a3 60
AnnaBridge 189:f392fc9709a3 61 // Disable the MCU
AnnaBridge 189:f392fc9709a3 62 MPU->CTRL = 0;
AnnaBridge 189:f392fc9709a3 63
AnnaBridge 189:f392fc9709a3 64 // Reset all mapping
AnnaBridge 189:f392fc9709a3 65 for (uint32_t i = 0; i < regions; i++) {
AnnaBridge 189:f392fc9709a3 66 ARM_MPU_ClrRegion(i);
AnnaBridge 189:f392fc9709a3 67 }
AnnaBridge 189:f392fc9709a3 68
AnnaBridge 189:f392fc9709a3 69 /*
AnnaBridge 189:f392fc9709a3 70 * ARMv6m and ARMv7-M memory map:
AnnaBridge 189:f392fc9709a3 71 *
AnnaBridge 189:f392fc9709a3 72 * Start End Name Executable by default Mbed MPU protection
AnnaBridge 189:f392fc9709a3 73 * 0x00000000 - 0x1FFFFFFF Code Yes Write disabled for first portion and execute disabled for the rest
AnnaBridge 189:f392fc9709a3 74 * 0x20000000 - 0x3FFFFFFF SRAM Yes Execute disabled
AnnaBridge 189:f392fc9709a3 75 * 0x40000000 - 0x5FFFFFFF Peripheral No
AnnaBridge 189:f392fc9709a3 76 * 0x60000000 - 0x7FFFFFFF RAM Yes Execute disabled
AnnaBridge 189:f392fc9709a3 77 * 0x80000000 - 0x9FFFFFFF RAM Yes Execute disabled
AnnaBridge 189:f392fc9709a3 78 * 0xA0000000 - 0xBFFFFFFF Device No
AnnaBridge 189:f392fc9709a3 79 * 0xC0000000 - 0xDFFFFFFF Device No
AnnaBridge 189:f392fc9709a3 80 * 0xE0000000 - 0xFFFFFFFF System No
AnnaBridge 189:f392fc9709a3 81 */
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 // Select region 0 and use it for the WT read-only rom region
AnnaBridge 189:f392fc9709a3 84 // - Code 0x00000000 to MBED_MPU_ROM_END
AnnaBridge 189:f392fc9709a3 85 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 86 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 87 0, // Region
AnnaBridge 189:f392fc9709a3 88 0x00000000), // Base
AnnaBridge 189:f392fc9709a3 89 ARM_MPU_RASR(
AnnaBridge 189:f392fc9709a3 90 0, // DisableExec
AnnaBridge 189:f392fc9709a3 91 ARM_MPU_AP_RO, // AccessPermission
AnnaBridge 189:f392fc9709a3 92 0, // TypeExtField
AnnaBridge 189:f392fc9709a3 93 0, // IsShareable
AnnaBridge 189:f392fc9709a3 94 1, // IsCacheable
AnnaBridge 189:f392fc9709a3 95 0, // IsBufferable
AnnaBridge 189:f392fc9709a3 96 // SubRegionDisable - based on where ROM ends
AnnaBridge 189:f392fc9709a3 97 ((MBED_MPU_ROM_END >= 0x00000000) ? 0 : (1 << 0)) | // 0 to enable, 1 << n to disable
AnnaBridge 189:f392fc9709a3 98 ((MBED_MPU_ROM_END >= 0x04000000) ? 0 : (1 << 1)) |
AnnaBridge 189:f392fc9709a3 99 ((MBED_MPU_ROM_END >= 0x08000000) ? 0 : (1 << 2)) |
AnnaBridge 189:f392fc9709a3 100 ((MBED_MPU_ROM_END >= 0x0C000000) ? 0 : (1 << 3)) |
AnnaBridge 189:f392fc9709a3 101 ((MBED_MPU_ROM_END >= 0x10000000) ? 0 : (1 << 4)) |
AnnaBridge 189:f392fc9709a3 102 ((MBED_MPU_ROM_END >= 0x14000000) ? 0 : (1 << 5)) |
AnnaBridge 189:f392fc9709a3 103 ((MBED_MPU_ROM_END >= 0x18000000) ? 0 : (1 << 6)) |
AnnaBridge 189:f392fc9709a3 104 ((MBED_MPU_ROM_END >= 0x1C000000) ? 0 : (1 << 7)),
AnnaBridge 189:f392fc9709a3 105 ARM_MPU_REGION_SIZE_512MB) // Size
AnnaBridge 189:f392fc9709a3 106 );
AnnaBridge 189:f392fc9709a3 107
AnnaBridge 189:f392fc9709a3 108 #if MBED_MPU_RAM_START < 0x20000000
AnnaBridge 189:f392fc9709a3 109 // Select region 3 and use it for a WT ram region in the Code area
AnnaBridge 189:f392fc9709a3 110 // - Code MBED_MPU_ROM_END + 1 to 0x1FFFFFFF
AnnaBridge 189:f392fc9709a3 111 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 112 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 113 3, // Region
AnnaBridge 189:f392fc9709a3 114 0x00000000), // Base
AnnaBridge 189:f392fc9709a3 115 ARM_MPU_RASR(
AnnaBridge 189:f392fc9709a3 116 1, // DisableExec
AnnaBridge 189:f392fc9709a3 117 ARM_MPU_AP_FULL, // AccessPermission
AnnaBridge 189:f392fc9709a3 118 0, // TypeExtField
AnnaBridge 189:f392fc9709a3 119 0, // IsShareable
AnnaBridge 189:f392fc9709a3 120 1, // IsCacheable
AnnaBridge 189:f392fc9709a3 121 0, // IsBufferable
AnnaBridge 189:f392fc9709a3 122 // SubRegionDisable - based on where RAM starts
AnnaBridge 189:f392fc9709a3 123 ((MBED_MPU_RAM_START <= 0x04000000) ? 0 : (1 << 0)) | // 0 to enable, 1 << n to disable
AnnaBridge 189:f392fc9709a3 124 ((MBED_MPU_RAM_START <= 0x08000000) ? 0 : (1 << 1)) |
AnnaBridge 189:f392fc9709a3 125 ((MBED_MPU_RAM_START <= 0x0C000000) ? 0 : (1 << 2)) |
AnnaBridge 189:f392fc9709a3 126 ((MBED_MPU_RAM_START <= 0x10000000) ? 0 : (1 << 3)) |
AnnaBridge 189:f392fc9709a3 127 ((MBED_MPU_RAM_START <= 0x14000000) ? 0 : (1 << 4)) |
AnnaBridge 189:f392fc9709a3 128 ((MBED_MPU_RAM_START <= 0x18000000) ? 0 : (1 << 5)) |
AnnaBridge 189:f392fc9709a3 129 ((MBED_MPU_RAM_START <= 0x1C000000) ? 0 : (1 << 6)) |
AnnaBridge 189:f392fc9709a3 130 ((MBED_MPU_RAM_START <= 0x20000000) ? 0 : (1 << 7)),
AnnaBridge 189:f392fc9709a3 131 ARM_MPU_REGION_SIZE_512MB) // Size
AnnaBridge 189:f392fc9709a3 132 );
AnnaBridge 189:f392fc9709a3 133 #define LAST_RAM_REGION 3
AnnaBridge 189:f392fc9709a3 134 #else
AnnaBridge 189:f392fc9709a3 135 #define LAST_RAM_REGION 2
AnnaBridge 189:f392fc9709a3 136 #endif
AnnaBridge 189:f392fc9709a3 137
AnnaBridge 189:f392fc9709a3 138 // Select region 1 and use it for WBWA ram regions
AnnaBridge 189:f392fc9709a3 139 // - SRAM 0x20000000 to 0x3FFFFFFF
AnnaBridge 189:f392fc9709a3 140 // - RAM 0x60000000 to 0x7FFFFFFF
AnnaBridge 189:f392fc9709a3 141 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 142 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 143 1, // Region
AnnaBridge 189:f392fc9709a3 144 0x00000000), // Base
AnnaBridge 189:f392fc9709a3 145 ARM_MPU_RASR(
AnnaBridge 189:f392fc9709a3 146 1, // DisableExec
AnnaBridge 189:f392fc9709a3 147 ARM_MPU_AP_FULL, // AccessPermission
AnnaBridge 189:f392fc9709a3 148 1, // TypeExtField
AnnaBridge 189:f392fc9709a3 149 0, // IsShareable
AnnaBridge 189:f392fc9709a3 150 1, // IsCacheable
AnnaBridge 189:f392fc9709a3 151 1, // IsBufferable
AnnaBridge 189:f392fc9709a3 152 // SubRegionDisable
AnnaBridge 189:f392fc9709a3 153 (1 << 0) | // Disable Sub-region
AnnaBridge 189:f392fc9709a3 154 (0 << 1) | // Enable Sub-region SRAM 0x20000000 - 0x3FFFFFFF
AnnaBridge 189:f392fc9709a3 155 (1 << 2) | // Disable Sub-region
AnnaBridge 189:f392fc9709a3 156 (0 << 3) | // Enable Sub-region RAM 0x60000000 - 0x7FFFFFFF
AnnaBridge 189:f392fc9709a3 157 (1 << 4) | // Disable Sub-region
AnnaBridge 189:f392fc9709a3 158 (1 << 5) | // Disable Sub-region
AnnaBridge 189:f392fc9709a3 159 (1 << 6) | // Disable Sub-region
AnnaBridge 189:f392fc9709a3 160 (1 << 7), // Disable Sub-region
AnnaBridge 189:f392fc9709a3 161 ARM_MPU_REGION_SIZE_4GB) // Size
AnnaBridge 189:f392fc9709a3 162 );
AnnaBridge 189:f392fc9709a3 163
AnnaBridge 189:f392fc9709a3 164 // Select region 2 and use it for the WT ram region
AnnaBridge 189:f392fc9709a3 165 // - RAM 0x80000000 to 0x9FFFFFFF
AnnaBridge 189:f392fc9709a3 166 ARM_MPU_SetRegion(
AnnaBridge 189:f392fc9709a3 167 ARM_MPU_RBAR(
AnnaBridge 189:f392fc9709a3 168 2, // Region
AnnaBridge 189:f392fc9709a3 169 0x80000000), // Base
AnnaBridge 189:f392fc9709a3 170 ARM_MPU_RASR(
AnnaBridge 189:f392fc9709a3 171 1, // DisableExec
AnnaBridge 189:f392fc9709a3 172 ARM_MPU_AP_FULL, // AccessPermission
AnnaBridge 189:f392fc9709a3 173 0, // TypeExtField
AnnaBridge 189:f392fc9709a3 174 0, // IsShareable
AnnaBridge 189:f392fc9709a3 175 1, // IsCacheable
AnnaBridge 189:f392fc9709a3 176 0, // IsBufferable
AnnaBridge 189:f392fc9709a3 177 0U, // SubRegionDisable
AnnaBridge 189:f392fc9709a3 178 ARM_MPU_REGION_SIZE_512MB) // Size
AnnaBridge 189:f392fc9709a3 179 );
AnnaBridge 189:f392fc9709a3 180
AnnaBridge 189:f392fc9709a3 181 // Enable the MPU
AnnaBridge 189:f392fc9709a3 182 MPU->CTRL =
AnnaBridge 189:f392fc9709a3 183 (1 << MPU_CTRL_PRIVDEFENA_Pos) | // Use the default memory map for unmapped addresses
AnnaBridge 189:f392fc9709a3 184 (1 << MPU_CTRL_HFNMIENA_Pos) | // Keep MPU turned on for faults
AnnaBridge 189:f392fc9709a3 185 (1 << MPU_CTRL_ENABLE_Pos); // Enable MPU
AnnaBridge 189:f392fc9709a3 186
AnnaBridge 189:f392fc9709a3 187 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 188 __DSB();
AnnaBridge 189:f392fc9709a3 189 __ISB();
AnnaBridge 189:f392fc9709a3 190 }
AnnaBridge 189:f392fc9709a3 191
AnnaBridge 189:f392fc9709a3 192 void mbed_mpu_free()
AnnaBridge 189:f392fc9709a3 193 {
AnnaBridge 189:f392fc9709a3 194 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 195 __DMB();
AnnaBridge 189:f392fc9709a3 196
AnnaBridge 189:f392fc9709a3 197 // Disable the MPU
AnnaBridge 189:f392fc9709a3 198 MPU->CTRL = 0;
AnnaBridge 189:f392fc9709a3 199
AnnaBridge 189:f392fc9709a3 200 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 201 __DSB();
AnnaBridge 189:f392fc9709a3 202 __ISB();
AnnaBridge 189:f392fc9709a3 203 }
AnnaBridge 189:f392fc9709a3 204
AnnaBridge 189:f392fc9709a3 205 static void enable_region(bool enable, uint32_t region)
AnnaBridge 189:f392fc9709a3 206 {
AnnaBridge 189:f392fc9709a3 207 MPU->RNR = region;
AnnaBridge 189:f392fc9709a3 208 MPU->RASR = (MPU->RASR & ~MPU_RASR_ENABLE_Msk) | (enable << MPU_RASR_ENABLE_Pos);
AnnaBridge 189:f392fc9709a3 209 }
AnnaBridge 189:f392fc9709a3 210
AnnaBridge 189:f392fc9709a3 211 void mbed_mpu_enable_rom_wn(bool enable)
AnnaBridge 189:f392fc9709a3 212 {
AnnaBridge 189:f392fc9709a3 213 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 214 __DMB();
AnnaBridge 189:f392fc9709a3 215
AnnaBridge 189:f392fc9709a3 216 enable_region(enable, 0);
AnnaBridge 189:f392fc9709a3 217
AnnaBridge 189:f392fc9709a3 218 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 219 __DSB();
AnnaBridge 189:f392fc9709a3 220 __ISB();
AnnaBridge 189:f392fc9709a3 221 }
AnnaBridge 189:f392fc9709a3 222
AnnaBridge 189:f392fc9709a3 223 void mbed_mpu_enable_ram_xn(bool enable)
AnnaBridge 189:f392fc9709a3 224 {
AnnaBridge 189:f392fc9709a3 225 // Flush memory writes before configuring the MPU.
AnnaBridge 189:f392fc9709a3 226 __DMB();
AnnaBridge 189:f392fc9709a3 227
AnnaBridge 189:f392fc9709a3 228 for (uint32_t region = 1; region <= LAST_RAM_REGION; region++) {
AnnaBridge 189:f392fc9709a3 229 enable_region(enable, region);
AnnaBridge 189:f392fc9709a3 230 }
AnnaBridge 189:f392fc9709a3 231
AnnaBridge 189:f392fc9709a3 232 // Ensure changes take effect
AnnaBridge 189:f392fc9709a3 233 __DSB();
AnnaBridge 189:f392fc9709a3 234 __ISB();
AnnaBridge 189:f392fc9709a3 235 }
AnnaBridge 189:f392fc9709a3 236
AnnaBridge 189:f392fc9709a3 237 #endif