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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_M/core_cm0plus.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 180:96ed750bd169 1 /**************************************************************************//**
Anna Bridge 180:96ed750bd169 2 * @file core_cm0plus.h
Anna Bridge 180:96ed750bd169 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
AnnaBridge 188:bcfe06ba3d64 4 * @version V5.0.6
AnnaBridge 188:bcfe06ba3d64 5 * @date 28. May 2018
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 186:707f6e361f3e 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 180:96ed750bd169 25 #if defined ( __ICCARM__ )
Anna Bridge 186:707f6e361f3e 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 186:707f6e361f3e 27 #elif defined (__clang__)
Anna Bridge 180:96ed750bd169 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 180:96ed750bd169 29 #endif
Anna Bridge 180:96ed750bd169 30
Anna Bridge 180:96ed750bd169 31 #ifndef __CORE_CM0PLUS_H_GENERIC
Anna Bridge 180:96ed750bd169 32 #define __CORE_CM0PLUS_H_GENERIC
Anna Bridge 180:96ed750bd169 33
Anna Bridge 180:96ed750bd169 34 #include <stdint.h>
Anna Bridge 180:96ed750bd169 35
Anna Bridge 180:96ed750bd169 36 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 37 extern "C" {
Anna Bridge 180:96ed750bd169 38 #endif
Anna Bridge 180:96ed750bd169 39
Anna Bridge 180:96ed750bd169 40 /**
Anna Bridge 180:96ed750bd169 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Anna Bridge 180:96ed750bd169 42 CMSIS violates the following MISRA-C:2004 rules:
Anna Bridge 180:96ed750bd169 43
Anna Bridge 180:96ed750bd169 44 \li Required Rule 8.5, object/function definition in header file.<br>
Anna Bridge 180:96ed750bd169 45 Function definitions in header files are used to allow 'inlining'.
Anna Bridge 180:96ed750bd169 46
Anna Bridge 180:96ed750bd169 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Anna Bridge 180:96ed750bd169 48 Unions are used for effective representation of core registers.
Anna Bridge 180:96ed750bd169 49
Anna Bridge 180:96ed750bd169 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Anna Bridge 180:96ed750bd169 51 Function-like macros are used to allow more efficient code.
Anna Bridge 180:96ed750bd169 52 */
Anna Bridge 180:96ed750bd169 53
Anna Bridge 180:96ed750bd169 54
Anna Bridge 180:96ed750bd169 55 /*******************************************************************************
Anna Bridge 180:96ed750bd169 56 * CMSIS definitions
Anna Bridge 180:96ed750bd169 57 ******************************************************************************/
Anna Bridge 180:96ed750bd169 58 /**
Anna Bridge 180:96ed750bd169 59 \ingroup Cortex-M0+
Anna Bridge 180:96ed750bd169 60 @{
Anna Bridge 180:96ed750bd169 61 */
Anna Bridge 180:96ed750bd169 62
Anna Bridge 180:96ed750bd169 63 #include "cmsis_version.h"
Anna Bridge 180:96ed750bd169 64
Anna Bridge 180:96ed750bd169 65 /* CMSIS CM0+ definitions */
Anna Bridge 180:96ed750bd169 66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
Anna Bridge 180:96ed750bd169 67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
Anna Bridge 180:96ed750bd169 68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 180:96ed750bd169 69 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
Anna Bridge 180:96ed750bd169 70
Anna Bridge 180:96ed750bd169 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
Anna Bridge 180:96ed750bd169 72
Anna Bridge 180:96ed750bd169 73 /** __FPU_USED indicates whether an FPU is used or not.
Anna Bridge 180:96ed750bd169 74 This core does not support an FPU at all
Anna Bridge 180:96ed750bd169 75 */
Anna Bridge 180:96ed750bd169 76 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 77
Anna Bridge 180:96ed750bd169 78 #if defined ( __CC_ARM )
Anna Bridge 180:96ed750bd169 79 #if defined __TARGET_FPU_VFP
Anna Bridge 180:96ed750bd169 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 81 #endif
Anna Bridge 180:96ed750bd169 82
Anna Bridge 180:96ed750bd169 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 189:f392fc9709a3 84 #if defined __ARM_FP
Anna Bridge 180:96ed750bd169 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 86 #endif
Anna Bridge 180:96ed750bd169 87
Anna Bridge 180:96ed750bd169 88 #elif defined ( __GNUC__ )
Anna Bridge 180:96ed750bd169 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 180:96ed750bd169 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 91 #endif
Anna Bridge 180:96ed750bd169 92
Anna Bridge 180:96ed750bd169 93 #elif defined ( __ICCARM__ )
Anna Bridge 180:96ed750bd169 94 #if defined __ARMVFP__
Anna Bridge 180:96ed750bd169 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 96 #endif
Anna Bridge 180:96ed750bd169 97
Anna Bridge 180:96ed750bd169 98 #elif defined ( __TI_ARM__ )
Anna Bridge 180:96ed750bd169 99 #if defined __TI_VFP_SUPPORT__
Anna Bridge 180:96ed750bd169 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 101 #endif
Anna Bridge 180:96ed750bd169 102
Anna Bridge 180:96ed750bd169 103 #elif defined ( __TASKING__ )
Anna Bridge 180:96ed750bd169 104 #if defined __FPU_VFP__
Anna Bridge 180:96ed750bd169 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 106 #endif
Anna Bridge 180:96ed750bd169 107
Anna Bridge 180:96ed750bd169 108 #elif defined ( __CSMC__ )
Anna Bridge 180:96ed750bd169 109 #if ( __CSMC__ & 0x400U)
Anna Bridge 180:96ed750bd169 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 111 #endif
Anna Bridge 180:96ed750bd169 112
Anna Bridge 180:96ed750bd169 113 #endif
Anna Bridge 180:96ed750bd169 114
Anna Bridge 180:96ed750bd169 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 180:96ed750bd169 116
Anna Bridge 180:96ed750bd169 117
Anna Bridge 180:96ed750bd169 118 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 119 }
Anna Bridge 180:96ed750bd169 120 #endif
Anna Bridge 180:96ed750bd169 121
Anna Bridge 180:96ed750bd169 122 #endif /* __CORE_CM0PLUS_H_GENERIC */
Anna Bridge 180:96ed750bd169 123
Anna Bridge 180:96ed750bd169 124 #ifndef __CMSIS_GENERIC
Anna Bridge 180:96ed750bd169 125
Anna Bridge 180:96ed750bd169 126 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 180:96ed750bd169 127 #define __CORE_CM0PLUS_H_DEPENDANT
Anna Bridge 180:96ed750bd169 128
Anna Bridge 180:96ed750bd169 129 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 130 extern "C" {
Anna Bridge 180:96ed750bd169 131 #endif
Anna Bridge 180:96ed750bd169 132
Anna Bridge 180:96ed750bd169 133 /* check device defines and use defaults */
Anna Bridge 180:96ed750bd169 134 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 180:96ed750bd169 135 #ifndef __CM0PLUS_REV
Anna Bridge 180:96ed750bd169 136 #define __CM0PLUS_REV 0x0000U
Anna Bridge 180:96ed750bd169 137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 138 #endif
Anna Bridge 180:96ed750bd169 139
Anna Bridge 180:96ed750bd169 140 #ifndef __MPU_PRESENT
Anna Bridge 180:96ed750bd169 141 #define __MPU_PRESENT 0U
Anna Bridge 180:96ed750bd169 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 143 #endif
Anna Bridge 180:96ed750bd169 144
Anna Bridge 180:96ed750bd169 145 #ifndef __VTOR_PRESENT
Anna Bridge 180:96ed750bd169 146 #define __VTOR_PRESENT 0U
Anna Bridge 180:96ed750bd169 147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 148 #endif
Anna Bridge 180:96ed750bd169 149
Anna Bridge 180:96ed750bd169 150 #ifndef __NVIC_PRIO_BITS
Anna Bridge 180:96ed750bd169 151 #define __NVIC_PRIO_BITS 2U
Anna Bridge 180:96ed750bd169 152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 153 #endif
Anna Bridge 180:96ed750bd169 154
Anna Bridge 180:96ed750bd169 155 #ifndef __Vendor_SysTickConfig
Anna Bridge 180:96ed750bd169 156 #define __Vendor_SysTickConfig 0U
Anna Bridge 180:96ed750bd169 157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 158 #endif
Anna Bridge 180:96ed750bd169 159 #endif
Anna Bridge 180:96ed750bd169 160
Anna Bridge 180:96ed750bd169 161 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 180:96ed750bd169 162 /**
Anna Bridge 180:96ed750bd169 163 \defgroup CMSIS_glob_defs CMSIS Global Defines
Anna Bridge 180:96ed750bd169 164
Anna Bridge 180:96ed750bd169 165 <strong>IO Type Qualifiers</strong> are used
Anna Bridge 180:96ed750bd169 166 \li to specify the access to peripheral variables.
Anna Bridge 180:96ed750bd169 167 \li for automatic generation of peripheral register debug information.
Anna Bridge 180:96ed750bd169 168 */
Anna Bridge 180:96ed750bd169 169 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 170 #define __I volatile /*!< Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 171 #else
Anna Bridge 180:96ed750bd169 172 #define __I volatile const /*!< Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 173 #endif
Anna Bridge 180:96ed750bd169 174 #define __O volatile /*!< Defines 'write only' permissions */
Anna Bridge 180:96ed750bd169 175 #define __IO volatile /*!< Defines 'read / write' permissions */
Anna Bridge 180:96ed750bd169 176
Anna Bridge 180:96ed750bd169 177 /* following defines should be used for structure members */
Anna Bridge 180:96ed750bd169 178 #define __IM volatile const /*! Defines 'read only' structure member permissions */
Anna Bridge 180:96ed750bd169 179 #define __OM volatile /*! Defines 'write only' structure member permissions */
Anna Bridge 180:96ed750bd169 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Anna Bridge 180:96ed750bd169 181
Anna Bridge 180:96ed750bd169 182 /*@} end of group Cortex-M0+ */
Anna Bridge 180:96ed750bd169 183
Anna Bridge 180:96ed750bd169 184
Anna Bridge 180:96ed750bd169 185
Anna Bridge 180:96ed750bd169 186 /*******************************************************************************
Anna Bridge 180:96ed750bd169 187 * Register Abstraction
Anna Bridge 180:96ed750bd169 188 Core Register contain:
Anna Bridge 180:96ed750bd169 189 - Core Register
Anna Bridge 180:96ed750bd169 190 - Core NVIC Register
Anna Bridge 180:96ed750bd169 191 - Core SCB Register
Anna Bridge 180:96ed750bd169 192 - Core SysTick Register
Anna Bridge 180:96ed750bd169 193 - Core MPU Register
Anna Bridge 180:96ed750bd169 194 ******************************************************************************/
Anna Bridge 180:96ed750bd169 195 /**
Anna Bridge 180:96ed750bd169 196 \defgroup CMSIS_core_register Defines and Type Definitions
Anna Bridge 180:96ed750bd169 197 \brief Type definitions and defines for Cortex-M processor based devices.
Anna Bridge 180:96ed750bd169 198 */
Anna Bridge 180:96ed750bd169 199
Anna Bridge 180:96ed750bd169 200 /**
Anna Bridge 180:96ed750bd169 201 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 202 \defgroup CMSIS_CORE Status and Control Registers
Anna Bridge 180:96ed750bd169 203 \brief Core Register type definitions.
Anna Bridge 180:96ed750bd169 204 @{
Anna Bridge 180:96ed750bd169 205 */
Anna Bridge 180:96ed750bd169 206
Anna Bridge 180:96ed750bd169 207 /**
Anna Bridge 180:96ed750bd169 208 \brief Union type to access the Application Program Status Register (APSR).
Anna Bridge 180:96ed750bd169 209 */
Anna Bridge 180:96ed750bd169 210 typedef union
Anna Bridge 180:96ed750bd169 211 {
Anna Bridge 180:96ed750bd169 212 struct
Anna Bridge 180:96ed750bd169 213 {
Anna Bridge 180:96ed750bd169 214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
Anna Bridge 180:96ed750bd169 215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 180:96ed750bd169 216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 180:96ed750bd169 217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 180:96ed750bd169 218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 180:96ed750bd169 219 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 220 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 221 } APSR_Type;
Anna Bridge 180:96ed750bd169 222
Anna Bridge 180:96ed750bd169 223 /* APSR Register Definitions */
Anna Bridge 180:96ed750bd169 224 #define APSR_N_Pos 31U /*!< APSR: N Position */
Anna Bridge 180:96ed750bd169 225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Anna Bridge 180:96ed750bd169 226
Anna Bridge 180:96ed750bd169 227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Anna Bridge 180:96ed750bd169 228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Anna Bridge 180:96ed750bd169 229
Anna Bridge 180:96ed750bd169 230 #define APSR_C_Pos 29U /*!< APSR: C Position */
Anna Bridge 180:96ed750bd169 231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Anna Bridge 180:96ed750bd169 232
Anna Bridge 180:96ed750bd169 233 #define APSR_V_Pos 28U /*!< APSR: V Position */
Anna Bridge 180:96ed750bd169 234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Anna Bridge 180:96ed750bd169 235
Anna Bridge 180:96ed750bd169 236
Anna Bridge 180:96ed750bd169 237 /**
Anna Bridge 180:96ed750bd169 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
Anna Bridge 180:96ed750bd169 239 */
Anna Bridge 180:96ed750bd169 240 typedef union
Anna Bridge 180:96ed750bd169 241 {
Anna Bridge 180:96ed750bd169 242 struct
Anna Bridge 180:96ed750bd169 243 {
Anna Bridge 180:96ed750bd169 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 180:96ed750bd169 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Anna Bridge 180:96ed750bd169 246 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 247 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 248 } IPSR_Type;
Anna Bridge 180:96ed750bd169 249
Anna Bridge 180:96ed750bd169 250 /* IPSR Register Definitions */
Anna Bridge 180:96ed750bd169 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Anna Bridge 180:96ed750bd169 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Anna Bridge 180:96ed750bd169 253
Anna Bridge 180:96ed750bd169 254
Anna Bridge 180:96ed750bd169 255 /**
Anna Bridge 180:96ed750bd169 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Anna Bridge 180:96ed750bd169 257 */
Anna Bridge 180:96ed750bd169 258 typedef union
Anna Bridge 180:96ed750bd169 259 {
Anna Bridge 180:96ed750bd169 260 struct
Anna Bridge 180:96ed750bd169 261 {
Anna Bridge 180:96ed750bd169 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Anna Bridge 180:96ed750bd169 263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Anna Bridge 180:96ed750bd169 264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Anna Bridge 180:96ed750bd169 265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
Anna Bridge 180:96ed750bd169 266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Anna Bridge 180:96ed750bd169 267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Anna Bridge 180:96ed750bd169 268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Anna Bridge 180:96ed750bd169 269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Anna Bridge 180:96ed750bd169 270 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 271 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 272 } xPSR_Type;
Anna Bridge 180:96ed750bd169 273
Anna Bridge 180:96ed750bd169 274 /* xPSR Register Definitions */
Anna Bridge 180:96ed750bd169 275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Anna Bridge 180:96ed750bd169 276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Anna Bridge 180:96ed750bd169 277
Anna Bridge 180:96ed750bd169 278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Anna Bridge 180:96ed750bd169 279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Anna Bridge 180:96ed750bd169 280
Anna Bridge 180:96ed750bd169 281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Anna Bridge 180:96ed750bd169 282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Anna Bridge 180:96ed750bd169 283
Anna Bridge 180:96ed750bd169 284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Anna Bridge 180:96ed750bd169 285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Anna Bridge 180:96ed750bd169 286
Anna Bridge 180:96ed750bd169 287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Anna Bridge 180:96ed750bd169 288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Anna Bridge 180:96ed750bd169 289
Anna Bridge 180:96ed750bd169 290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Anna Bridge 180:96ed750bd169 291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Anna Bridge 180:96ed750bd169 292
Anna Bridge 180:96ed750bd169 293
Anna Bridge 180:96ed750bd169 294 /**
Anna Bridge 180:96ed750bd169 295 \brief Union type to access the Control Registers (CONTROL).
Anna Bridge 180:96ed750bd169 296 */
Anna Bridge 180:96ed750bd169 297 typedef union
Anna Bridge 180:96ed750bd169 298 {
Anna Bridge 180:96ed750bd169 299 struct
Anna Bridge 180:96ed750bd169 300 {
Anna Bridge 180:96ed750bd169 301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Anna Bridge 180:96ed750bd169 302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Anna Bridge 180:96ed750bd169 303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
Anna Bridge 180:96ed750bd169 304 } b; /*!< Structure used for bit access */
Anna Bridge 180:96ed750bd169 305 uint32_t w; /*!< Type used for word access */
Anna Bridge 180:96ed750bd169 306 } CONTROL_Type;
Anna Bridge 180:96ed750bd169 307
Anna Bridge 180:96ed750bd169 308 /* CONTROL Register Definitions */
Anna Bridge 180:96ed750bd169 309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Anna Bridge 180:96ed750bd169 310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Anna Bridge 180:96ed750bd169 311
Anna Bridge 180:96ed750bd169 312 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
Anna Bridge 180:96ed750bd169 313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Anna Bridge 180:96ed750bd169 314
Anna Bridge 180:96ed750bd169 315 /*@} end of group CMSIS_CORE */
Anna Bridge 180:96ed750bd169 316
Anna Bridge 180:96ed750bd169 317
Anna Bridge 180:96ed750bd169 318 /**
Anna Bridge 180:96ed750bd169 319 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 320 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Anna Bridge 180:96ed750bd169 321 \brief Type definitions for the NVIC Registers
Anna Bridge 180:96ed750bd169 322 @{
Anna Bridge 180:96ed750bd169 323 */
Anna Bridge 180:96ed750bd169 324
Anna Bridge 180:96ed750bd169 325 /**
Anna Bridge 180:96ed750bd169 326 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Anna Bridge 180:96ed750bd169 327 */
Anna Bridge 180:96ed750bd169 328 typedef struct
Anna Bridge 180:96ed750bd169 329 {
Anna Bridge 180:96ed750bd169 330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Anna Bridge 180:96ed750bd169 331 uint32_t RESERVED0[31U];
Anna Bridge 180:96ed750bd169 332 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Anna Bridge 180:96ed750bd169 333 uint32_t RSERVED1[31U];
Anna Bridge 180:96ed750bd169 334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Anna Bridge 180:96ed750bd169 335 uint32_t RESERVED2[31U];
Anna Bridge 180:96ed750bd169 336 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Anna Bridge 180:96ed750bd169 337 uint32_t RESERVED3[31U];
Anna Bridge 180:96ed750bd169 338 uint32_t RESERVED4[64U];
Anna Bridge 180:96ed750bd169 339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Anna Bridge 180:96ed750bd169 340 } NVIC_Type;
Anna Bridge 180:96ed750bd169 341
Anna Bridge 180:96ed750bd169 342 /*@} end of group CMSIS_NVIC */
Anna Bridge 180:96ed750bd169 343
Anna Bridge 180:96ed750bd169 344
Anna Bridge 180:96ed750bd169 345 /**
Anna Bridge 180:96ed750bd169 346 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 347 \defgroup CMSIS_SCB System Control Block (SCB)
Anna Bridge 180:96ed750bd169 348 \brief Type definitions for the System Control Block Registers
Anna Bridge 180:96ed750bd169 349 @{
Anna Bridge 180:96ed750bd169 350 */
Anna Bridge 180:96ed750bd169 351
Anna Bridge 180:96ed750bd169 352 /**
Anna Bridge 180:96ed750bd169 353 \brief Structure type to access the System Control Block (SCB).
Anna Bridge 180:96ed750bd169 354 */
Anna Bridge 180:96ed750bd169 355 typedef struct
Anna Bridge 180:96ed750bd169 356 {
Anna Bridge 180:96ed750bd169 357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Anna Bridge 180:96ed750bd169 358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Anna Bridge 180:96ed750bd169 359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Anna Bridge 180:96ed750bd169 361 #else
Anna Bridge 180:96ed750bd169 362 uint32_t RESERVED0;
Anna Bridge 180:96ed750bd169 363 #endif
Anna Bridge 180:96ed750bd169 364 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Anna Bridge 180:96ed750bd169 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Anna Bridge 180:96ed750bd169 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Anna Bridge 180:96ed750bd169 367 uint32_t RESERVED1;
Anna Bridge 180:96ed750bd169 368 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Anna Bridge 180:96ed750bd169 369 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Anna Bridge 180:96ed750bd169 370 } SCB_Type;
Anna Bridge 180:96ed750bd169 371
Anna Bridge 180:96ed750bd169 372 /* SCB CPUID Register Definitions */
Anna Bridge 180:96ed750bd169 373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Anna Bridge 180:96ed750bd169 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Anna Bridge 180:96ed750bd169 375
Anna Bridge 180:96ed750bd169 376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Anna Bridge 180:96ed750bd169 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Anna Bridge 180:96ed750bd169 378
Anna Bridge 180:96ed750bd169 379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Anna Bridge 180:96ed750bd169 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Anna Bridge 180:96ed750bd169 381
Anna Bridge 180:96ed750bd169 382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Anna Bridge 180:96ed750bd169 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Anna Bridge 180:96ed750bd169 384
Anna Bridge 180:96ed750bd169 385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Anna Bridge 180:96ed750bd169 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Anna Bridge 180:96ed750bd169 387
Anna Bridge 180:96ed750bd169 388 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 180:96ed750bd169 389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Anna Bridge 180:96ed750bd169 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Anna Bridge 180:96ed750bd169 391
Anna Bridge 180:96ed750bd169 392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Anna Bridge 180:96ed750bd169 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Anna Bridge 180:96ed750bd169 394
Anna Bridge 180:96ed750bd169 395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Anna Bridge 180:96ed750bd169 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Anna Bridge 180:96ed750bd169 397
Anna Bridge 180:96ed750bd169 398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Anna Bridge 180:96ed750bd169 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Anna Bridge 180:96ed750bd169 400
Anna Bridge 180:96ed750bd169 401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Anna Bridge 180:96ed750bd169 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Anna Bridge 180:96ed750bd169 403
Anna Bridge 180:96ed750bd169 404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Anna Bridge 180:96ed750bd169 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Anna Bridge 180:96ed750bd169 406
Anna Bridge 180:96ed750bd169 407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Anna Bridge 180:96ed750bd169 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Anna Bridge 180:96ed750bd169 409
Anna Bridge 180:96ed750bd169 410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Anna Bridge 180:96ed750bd169 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Anna Bridge 180:96ed750bd169 412
Anna Bridge 180:96ed750bd169 413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Anna Bridge 180:96ed750bd169 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Anna Bridge 180:96ed750bd169 415
Anna Bridge 180:96ed750bd169 416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 417 /* SCB Interrupt Control State Register Definitions */
Anna Bridge 180:96ed750bd169 418 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
Anna Bridge 180:96ed750bd169 419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Anna Bridge 180:96ed750bd169 420 #endif
Anna Bridge 180:96ed750bd169 421
Anna Bridge 180:96ed750bd169 422 /* SCB Application Interrupt and Reset Control Register Definitions */
Anna Bridge 180:96ed750bd169 423 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Anna Bridge 180:96ed750bd169 424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Anna Bridge 180:96ed750bd169 425
Anna Bridge 180:96ed750bd169 426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Anna Bridge 180:96ed750bd169 427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Anna Bridge 180:96ed750bd169 428
Anna Bridge 180:96ed750bd169 429 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Anna Bridge 180:96ed750bd169 430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Anna Bridge 180:96ed750bd169 431
Anna Bridge 180:96ed750bd169 432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Anna Bridge 180:96ed750bd169 433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Anna Bridge 180:96ed750bd169 434
Anna Bridge 180:96ed750bd169 435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Anna Bridge 180:96ed750bd169 436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Anna Bridge 180:96ed750bd169 437
Anna Bridge 180:96ed750bd169 438 /* SCB System Control Register Definitions */
Anna Bridge 180:96ed750bd169 439 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Anna Bridge 180:96ed750bd169 440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Anna Bridge 180:96ed750bd169 441
Anna Bridge 180:96ed750bd169 442 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Anna Bridge 180:96ed750bd169 443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Anna Bridge 180:96ed750bd169 444
Anna Bridge 180:96ed750bd169 445 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Anna Bridge 180:96ed750bd169 446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Anna Bridge 180:96ed750bd169 447
Anna Bridge 180:96ed750bd169 448 /* SCB Configuration Control Register Definitions */
Anna Bridge 180:96ed750bd169 449 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Anna Bridge 180:96ed750bd169 450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Anna Bridge 180:96ed750bd169 451
Anna Bridge 180:96ed750bd169 452 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Anna Bridge 180:96ed750bd169 453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Anna Bridge 180:96ed750bd169 454
Anna Bridge 180:96ed750bd169 455 /* SCB System Handler Control and State Register Definitions */
Anna Bridge 180:96ed750bd169 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Anna Bridge 180:96ed750bd169 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Anna Bridge 180:96ed750bd169 458
Anna Bridge 180:96ed750bd169 459 /*@} end of group CMSIS_SCB */
Anna Bridge 180:96ed750bd169 460
Anna Bridge 180:96ed750bd169 461
Anna Bridge 180:96ed750bd169 462 /**
Anna Bridge 180:96ed750bd169 463 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 464 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Anna Bridge 180:96ed750bd169 465 \brief Type definitions for the System Timer Registers.
Anna Bridge 180:96ed750bd169 466 @{
Anna Bridge 180:96ed750bd169 467 */
Anna Bridge 180:96ed750bd169 468
Anna Bridge 180:96ed750bd169 469 /**
Anna Bridge 180:96ed750bd169 470 \brief Structure type to access the System Timer (SysTick).
Anna Bridge 180:96ed750bd169 471 */
Anna Bridge 180:96ed750bd169 472 typedef struct
Anna Bridge 180:96ed750bd169 473 {
Anna Bridge 180:96ed750bd169 474 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Anna Bridge 180:96ed750bd169 475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Anna Bridge 180:96ed750bd169 476 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Anna Bridge 180:96ed750bd169 477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Anna Bridge 180:96ed750bd169 478 } SysTick_Type;
Anna Bridge 180:96ed750bd169 479
Anna Bridge 180:96ed750bd169 480 /* SysTick Control / Status Register Definitions */
Anna Bridge 180:96ed750bd169 481 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Anna Bridge 180:96ed750bd169 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Anna Bridge 180:96ed750bd169 483
Anna Bridge 180:96ed750bd169 484 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Anna Bridge 180:96ed750bd169 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Anna Bridge 180:96ed750bd169 486
Anna Bridge 180:96ed750bd169 487 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Anna Bridge 180:96ed750bd169 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Anna Bridge 180:96ed750bd169 489
Anna Bridge 180:96ed750bd169 490 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Anna Bridge 180:96ed750bd169 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Anna Bridge 180:96ed750bd169 492
Anna Bridge 180:96ed750bd169 493 /* SysTick Reload Register Definitions */
Anna Bridge 180:96ed750bd169 494 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Anna Bridge 180:96ed750bd169 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Anna Bridge 180:96ed750bd169 496
Anna Bridge 180:96ed750bd169 497 /* SysTick Current Register Definitions */
Anna Bridge 180:96ed750bd169 498 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Anna Bridge 180:96ed750bd169 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Anna Bridge 180:96ed750bd169 500
Anna Bridge 180:96ed750bd169 501 /* SysTick Calibration Register Definitions */
Anna Bridge 180:96ed750bd169 502 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Anna Bridge 180:96ed750bd169 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Anna Bridge 180:96ed750bd169 504
Anna Bridge 180:96ed750bd169 505 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Anna Bridge 180:96ed750bd169 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Anna Bridge 180:96ed750bd169 507
Anna Bridge 180:96ed750bd169 508 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Anna Bridge 180:96ed750bd169 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Anna Bridge 180:96ed750bd169 510
Anna Bridge 180:96ed750bd169 511 /*@} end of group CMSIS_SysTick */
Anna Bridge 180:96ed750bd169 512
Anna Bridge 180:96ed750bd169 513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 514 /**
Anna Bridge 180:96ed750bd169 515 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 516 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Anna Bridge 180:96ed750bd169 517 \brief Type definitions for the Memory Protection Unit (MPU)
Anna Bridge 180:96ed750bd169 518 @{
Anna Bridge 180:96ed750bd169 519 */
Anna Bridge 180:96ed750bd169 520
Anna Bridge 180:96ed750bd169 521 /**
Anna Bridge 180:96ed750bd169 522 \brief Structure type to access the Memory Protection Unit (MPU).
Anna Bridge 180:96ed750bd169 523 */
Anna Bridge 180:96ed750bd169 524 typedef struct
Anna Bridge 180:96ed750bd169 525 {
Anna Bridge 180:96ed750bd169 526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Anna Bridge 180:96ed750bd169 527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Anna Bridge 180:96ed750bd169 528 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Anna Bridge 180:96ed750bd169 529 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Anna Bridge 180:96ed750bd169 530 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Anna Bridge 180:96ed750bd169 531 } MPU_Type;
Anna Bridge 180:96ed750bd169 532
Anna Bridge 180:96ed750bd169 533 #define MPU_TYPE_RALIASES 1U
Anna Bridge 180:96ed750bd169 534
Anna Bridge 180:96ed750bd169 535 /* MPU Type Register Definitions */
Anna Bridge 180:96ed750bd169 536 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Anna Bridge 180:96ed750bd169 537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Anna Bridge 180:96ed750bd169 538
Anna Bridge 180:96ed750bd169 539 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Anna Bridge 180:96ed750bd169 540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Anna Bridge 180:96ed750bd169 541
Anna Bridge 180:96ed750bd169 542 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Anna Bridge 180:96ed750bd169 543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Anna Bridge 180:96ed750bd169 544
Anna Bridge 180:96ed750bd169 545 /* MPU Control Register Definitions */
Anna Bridge 180:96ed750bd169 546 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Anna Bridge 180:96ed750bd169 547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Anna Bridge 180:96ed750bd169 548
Anna Bridge 180:96ed750bd169 549 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Anna Bridge 180:96ed750bd169 550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Anna Bridge 180:96ed750bd169 551
Anna Bridge 180:96ed750bd169 552 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Anna Bridge 180:96ed750bd169 553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Anna Bridge 180:96ed750bd169 554
Anna Bridge 180:96ed750bd169 555 /* MPU Region Number Register Definitions */
Anna Bridge 180:96ed750bd169 556 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Anna Bridge 180:96ed750bd169 557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Anna Bridge 180:96ed750bd169 558
Anna Bridge 180:96ed750bd169 559 /* MPU Region Base Address Register Definitions */
Anna Bridge 180:96ed750bd169 560 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
Anna Bridge 180:96ed750bd169 561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Anna Bridge 180:96ed750bd169 562
Anna Bridge 180:96ed750bd169 563 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Anna Bridge 180:96ed750bd169 564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Anna Bridge 180:96ed750bd169 565
Anna Bridge 180:96ed750bd169 566 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Anna Bridge 180:96ed750bd169 567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Anna Bridge 180:96ed750bd169 568
Anna Bridge 180:96ed750bd169 569 /* MPU Region Attribute and Size Register Definitions */
Anna Bridge 180:96ed750bd169 570 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Anna Bridge 180:96ed750bd169 571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Anna Bridge 180:96ed750bd169 572
Anna Bridge 180:96ed750bd169 573 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Anna Bridge 180:96ed750bd169 574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Anna Bridge 180:96ed750bd169 575
Anna Bridge 180:96ed750bd169 576 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Anna Bridge 180:96ed750bd169 577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Anna Bridge 180:96ed750bd169 578
Anna Bridge 180:96ed750bd169 579 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Anna Bridge 180:96ed750bd169 580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Anna Bridge 180:96ed750bd169 581
Anna Bridge 180:96ed750bd169 582 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Anna Bridge 180:96ed750bd169 583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Anna Bridge 180:96ed750bd169 584
Anna Bridge 180:96ed750bd169 585 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Anna Bridge 180:96ed750bd169 586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Anna Bridge 180:96ed750bd169 587
Anna Bridge 180:96ed750bd169 588 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Anna Bridge 180:96ed750bd169 589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Anna Bridge 180:96ed750bd169 590
Anna Bridge 180:96ed750bd169 591 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Anna Bridge 180:96ed750bd169 592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Anna Bridge 180:96ed750bd169 593
Anna Bridge 180:96ed750bd169 594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Anna Bridge 180:96ed750bd169 595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Anna Bridge 180:96ed750bd169 596
Anna Bridge 180:96ed750bd169 597 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Anna Bridge 180:96ed750bd169 598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Anna Bridge 180:96ed750bd169 599
Anna Bridge 180:96ed750bd169 600 /*@} end of group CMSIS_MPU */
Anna Bridge 180:96ed750bd169 601 #endif
Anna Bridge 180:96ed750bd169 602
Anna Bridge 180:96ed750bd169 603
Anna Bridge 180:96ed750bd169 604 /**
Anna Bridge 180:96ed750bd169 605 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 606 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Anna Bridge 180:96ed750bd169 607 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Anna Bridge 180:96ed750bd169 608 Therefore they are not covered by the Cortex-M0+ header file.
Anna Bridge 180:96ed750bd169 609 @{
Anna Bridge 180:96ed750bd169 610 */
Anna Bridge 180:96ed750bd169 611 /*@} end of group CMSIS_CoreDebug */
Anna Bridge 180:96ed750bd169 612
Anna Bridge 180:96ed750bd169 613
Anna Bridge 180:96ed750bd169 614 /**
Anna Bridge 180:96ed750bd169 615 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 616 \defgroup CMSIS_core_bitfield Core register bit field macros
Anna Bridge 180:96ed750bd169 617 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Anna Bridge 180:96ed750bd169 618 @{
Anna Bridge 180:96ed750bd169 619 */
Anna Bridge 180:96ed750bd169 620
Anna Bridge 180:96ed750bd169 621 /**
Anna Bridge 180:96ed750bd169 622 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 180:96ed750bd169 623 \param[in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 624 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 625 \return Masked and shifted value.
Anna Bridge 180:96ed750bd169 626 */
Anna Bridge 180:96ed750bd169 627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 180:96ed750bd169 628
Anna Bridge 180:96ed750bd169 629 /**
Anna Bridge 180:96ed750bd169 630 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 180:96ed750bd169 631 \param[in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 632 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 633 \return Masked and shifted bit field value.
Anna Bridge 180:96ed750bd169 634 */
Anna Bridge 180:96ed750bd169 635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 180:96ed750bd169 636
Anna Bridge 180:96ed750bd169 637 /*@} end of group CMSIS_core_bitfield */
Anna Bridge 180:96ed750bd169 638
Anna Bridge 180:96ed750bd169 639
Anna Bridge 180:96ed750bd169 640 /**
Anna Bridge 180:96ed750bd169 641 \ingroup CMSIS_core_register
Anna Bridge 180:96ed750bd169 642 \defgroup CMSIS_core_base Core Definitions
Anna Bridge 180:96ed750bd169 643 \brief Definitions for base addresses, unions, and structures.
Anna Bridge 180:96ed750bd169 644 @{
Anna Bridge 180:96ed750bd169 645 */
Anna Bridge 180:96ed750bd169 646
Anna Bridge 180:96ed750bd169 647 /* Memory mapping of Core Hardware */
Anna Bridge 180:96ed750bd169 648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Anna Bridge 180:96ed750bd169 649 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Anna Bridge 180:96ed750bd169 650 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Anna Bridge 180:96ed750bd169 651 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Anna Bridge 180:96ed750bd169 652
Anna Bridge 180:96ed750bd169 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Anna Bridge 180:96ed750bd169 654 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Anna Bridge 180:96ed750bd169 655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Anna Bridge 180:96ed750bd169 656
Anna Bridge 180:96ed750bd169 657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 658 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Anna Bridge 180:96ed750bd169 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Anna Bridge 180:96ed750bd169 660 #endif
Anna Bridge 180:96ed750bd169 661
Anna Bridge 180:96ed750bd169 662 /*@} */
Anna Bridge 180:96ed750bd169 663
Anna Bridge 180:96ed750bd169 664
Anna Bridge 180:96ed750bd169 665
Anna Bridge 180:96ed750bd169 666 /*******************************************************************************
Anna Bridge 180:96ed750bd169 667 * Hardware Abstraction Layer
Anna Bridge 180:96ed750bd169 668 Core Function Interface contains:
Anna Bridge 180:96ed750bd169 669 - Core NVIC Functions
Anna Bridge 180:96ed750bd169 670 - Core SysTick Functions
Anna Bridge 180:96ed750bd169 671 - Core Register Access Functions
Anna Bridge 180:96ed750bd169 672 ******************************************************************************/
Anna Bridge 180:96ed750bd169 673 /**
Anna Bridge 180:96ed750bd169 674 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Anna Bridge 180:96ed750bd169 675 */
Anna Bridge 180:96ed750bd169 676
Anna Bridge 180:96ed750bd169 677
Anna Bridge 180:96ed750bd169 678
Anna Bridge 180:96ed750bd169 679 /* ########################## NVIC functions #################################### */
Anna Bridge 180:96ed750bd169 680 /**
Anna Bridge 180:96ed750bd169 681 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 682 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Anna Bridge 180:96ed750bd169 683 \brief Functions that manage interrupts and exceptions via the NVIC.
Anna Bridge 180:96ed750bd169 684 @{
Anna Bridge 180:96ed750bd169 685 */
Anna Bridge 180:96ed750bd169 686
Anna Bridge 180:96ed750bd169 687 #ifdef CMSIS_NVIC_VIRTUAL
Anna Bridge 180:96ed750bd169 688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Anna Bridge 180:96ed750bd169 690 #endif
Anna Bridge 180:96ed750bd169 691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 692 #else
AnnaBridge 188:bcfe06ba3d64 693 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 188:bcfe06ba3d64 694 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Anna Bridge 180:96ed750bd169 695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Anna Bridge 180:96ed750bd169 696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
Anna Bridge 180:96ed750bd169 697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Anna Bridge 180:96ed750bd169 698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Anna Bridge 180:96ed750bd169 699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Anna Bridge 180:96ed750bd169 700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Anna Bridge 180:96ed750bd169 701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
Anna Bridge 180:96ed750bd169 702 #define NVIC_SetPriority __NVIC_SetPriority
Anna Bridge 180:96ed750bd169 703 #define NVIC_GetPriority __NVIC_GetPriority
Anna Bridge 180:96ed750bd169 704 #define NVIC_SystemReset __NVIC_SystemReset
Anna Bridge 180:96ed750bd169 705 #endif /* CMSIS_NVIC_VIRTUAL */
Anna Bridge 180:96ed750bd169 706
Anna Bridge 180:96ed750bd169 707 #ifdef CMSIS_VECTAB_VIRTUAL
Anna Bridge 180:96ed750bd169 708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Anna Bridge 180:96ed750bd169 710 #endif
Anna Bridge 180:96ed750bd169 711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Anna Bridge 180:96ed750bd169 712 #else
Anna Bridge 180:96ed750bd169 713 #define NVIC_SetVector __NVIC_SetVector
Anna Bridge 180:96ed750bd169 714 #define NVIC_GetVector __NVIC_GetVector
Anna Bridge 180:96ed750bd169 715 #endif /* (CMSIS_VECTAB_VIRTUAL) */
Anna Bridge 180:96ed750bd169 716
Anna Bridge 180:96ed750bd169 717 #define NVIC_USER_IRQ_OFFSET 16
Anna Bridge 180:96ed750bd169 718
Anna Bridge 180:96ed750bd169 719
AnnaBridge 188:bcfe06ba3d64 720 /* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge 188:bcfe06ba3d64 721 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge 188:bcfe06ba3d64 722 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge 188:bcfe06ba3d64 723 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge 188:bcfe06ba3d64 724
AnnaBridge 188:bcfe06ba3d64 725
Anna Bridge 186:707f6e361f3e 726 /* Interrupt Priorities are WORD accessible only under Armv6-M */
Anna Bridge 180:96ed750bd169 727 /* The following MACROS handle generation of the register offset and byte masks */
Anna Bridge 180:96ed750bd169 728 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Anna Bridge 180:96ed750bd169 729 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Anna Bridge 180:96ed750bd169 730 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Anna Bridge 180:96ed750bd169 731
AnnaBridge 188:bcfe06ba3d64 732 #define __NVIC_SetPriorityGrouping(X) (void)(X)
AnnaBridge 188:bcfe06ba3d64 733 #define __NVIC_GetPriorityGrouping() (0U)
Anna Bridge 180:96ed750bd169 734
Anna Bridge 180:96ed750bd169 735 /**
Anna Bridge 180:96ed750bd169 736 \brief Enable Interrupt
Anna Bridge 180:96ed750bd169 737 \details Enables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 738 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 739 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 740 */
Anna Bridge 180:96ed750bd169 741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 742 {
Anna Bridge 180:96ed750bd169 743 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 744 {
Anna Bridge 186:707f6e361f3e 745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 746 }
Anna Bridge 180:96ed750bd169 747 }
Anna Bridge 180:96ed750bd169 748
Anna Bridge 180:96ed750bd169 749
Anna Bridge 180:96ed750bd169 750 /**
Anna Bridge 180:96ed750bd169 751 \brief Get Interrupt Enable status
Anna Bridge 180:96ed750bd169 752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 753 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 754 \return 0 Interrupt is not enabled.
Anna Bridge 180:96ed750bd169 755 \return 1 Interrupt is enabled.
Anna Bridge 180:96ed750bd169 756 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 757 */
Anna Bridge 180:96ed750bd169 758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 759 {
Anna Bridge 180:96ed750bd169 760 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 761 {
Anna Bridge 186:707f6e361f3e 762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 763 }
Anna Bridge 180:96ed750bd169 764 else
Anna Bridge 180:96ed750bd169 765 {
Anna Bridge 180:96ed750bd169 766 return(0U);
Anna Bridge 180:96ed750bd169 767 }
Anna Bridge 180:96ed750bd169 768 }
Anna Bridge 180:96ed750bd169 769
Anna Bridge 180:96ed750bd169 770
Anna Bridge 180:96ed750bd169 771 /**
Anna Bridge 180:96ed750bd169 772 \brief Disable Interrupt
Anna Bridge 180:96ed750bd169 773 \details Disables a device specific interrupt in the NVIC interrupt controller.
Anna Bridge 180:96ed750bd169 774 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 775 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 776 */
Anna Bridge 180:96ed750bd169 777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 778 {
Anna Bridge 180:96ed750bd169 779 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 780 {
Anna Bridge 186:707f6e361f3e 781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 782 __DSB();
Anna Bridge 180:96ed750bd169 783 __ISB();
Anna Bridge 180:96ed750bd169 784 }
Anna Bridge 180:96ed750bd169 785 }
Anna Bridge 180:96ed750bd169 786
Anna Bridge 180:96ed750bd169 787
Anna Bridge 180:96ed750bd169 788 /**
Anna Bridge 180:96ed750bd169 789 \brief Get Pending Interrupt
Anna Bridge 180:96ed750bd169 790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
Anna Bridge 180:96ed750bd169 791 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 792 \return 0 Interrupt status is not pending.
Anna Bridge 180:96ed750bd169 793 \return 1 Interrupt status is pending.
Anna Bridge 180:96ed750bd169 794 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 795 */
Anna Bridge 180:96ed750bd169 796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 797 {
Anna Bridge 180:96ed750bd169 798 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 799 {
Anna Bridge 186:707f6e361f3e 800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
Anna Bridge 180:96ed750bd169 801 }
Anna Bridge 180:96ed750bd169 802 else
Anna Bridge 180:96ed750bd169 803 {
Anna Bridge 180:96ed750bd169 804 return(0U);
Anna Bridge 180:96ed750bd169 805 }
Anna Bridge 180:96ed750bd169 806 }
Anna Bridge 180:96ed750bd169 807
Anna Bridge 180:96ed750bd169 808
Anna Bridge 180:96ed750bd169 809 /**
Anna Bridge 180:96ed750bd169 810 \brief Set Pending Interrupt
Anna Bridge 180:96ed750bd169 811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 180:96ed750bd169 812 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 813 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 814 */
Anna Bridge 180:96ed750bd169 815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 816 {
Anna Bridge 180:96ed750bd169 817 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 818 {
Anna Bridge 186:707f6e361f3e 819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 820 }
Anna Bridge 180:96ed750bd169 821 }
Anna Bridge 180:96ed750bd169 822
Anna Bridge 180:96ed750bd169 823
Anna Bridge 180:96ed750bd169 824 /**
Anna Bridge 180:96ed750bd169 825 \brief Clear Pending Interrupt
Anna Bridge 180:96ed750bd169 826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
Anna Bridge 180:96ed750bd169 827 \param [in] IRQn Device specific interrupt number.
Anna Bridge 180:96ed750bd169 828 \note IRQn must not be negative.
Anna Bridge 180:96ed750bd169 829 */
Anna Bridge 180:96ed750bd169 830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 831 {
Anna Bridge 180:96ed750bd169 832 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 833 {
Anna Bridge 186:707f6e361f3e 834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
Anna Bridge 180:96ed750bd169 835 }
Anna Bridge 180:96ed750bd169 836 }
Anna Bridge 180:96ed750bd169 837
Anna Bridge 180:96ed750bd169 838
Anna Bridge 180:96ed750bd169 839 /**
Anna Bridge 180:96ed750bd169 840 \brief Set Interrupt Priority
Anna Bridge 180:96ed750bd169 841 \details Sets the priority of a device specific interrupt or a processor exception.
Anna Bridge 180:96ed750bd169 842 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 843 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 844 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 845 \param [in] priority Priority to set.
Anna Bridge 180:96ed750bd169 846 \note The priority cannot be set for every processor exception.
Anna Bridge 180:96ed750bd169 847 */
Anna Bridge 180:96ed750bd169 848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 180:96ed750bd169 849 {
Anna Bridge 180:96ed750bd169 850 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 851 {
Anna Bridge 180:96ed750bd169 852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 854 }
Anna Bridge 180:96ed750bd169 855 else
Anna Bridge 180:96ed750bd169 856 {
Anna Bridge 180:96ed750bd169 857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Anna Bridge 180:96ed750bd169 858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Anna Bridge 180:96ed750bd169 859 }
Anna Bridge 180:96ed750bd169 860 }
Anna Bridge 180:96ed750bd169 861
Anna Bridge 180:96ed750bd169 862
Anna Bridge 180:96ed750bd169 863 /**
Anna Bridge 180:96ed750bd169 864 \brief Get Interrupt Priority
Anna Bridge 180:96ed750bd169 865 \details Reads the priority of a device specific interrupt or a processor exception.
Anna Bridge 180:96ed750bd169 866 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 867 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 868 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 869 \return Interrupt Priority.
Anna Bridge 180:96ed750bd169 870 Value is aligned automatically to the implemented priority bits of the microcontroller.
Anna Bridge 180:96ed750bd169 871 */
Anna Bridge 180:96ed750bd169 872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 873 {
Anna Bridge 180:96ed750bd169 874
Anna Bridge 180:96ed750bd169 875 if ((int32_t)(IRQn) >= 0)
Anna Bridge 180:96ed750bd169 876 {
Anna Bridge 180:96ed750bd169 877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 878 }
Anna Bridge 180:96ed750bd169 879 else
Anna Bridge 180:96ed750bd169 880 {
Anna Bridge 180:96ed750bd169 881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
Anna Bridge 180:96ed750bd169 882 }
Anna Bridge 180:96ed750bd169 883 }
Anna Bridge 180:96ed750bd169 884
Anna Bridge 180:96ed750bd169 885
Anna Bridge 180:96ed750bd169 886 /**
AnnaBridge 188:bcfe06ba3d64 887 \brief Encode Priority
AnnaBridge 188:bcfe06ba3d64 888 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 188:bcfe06ba3d64 889 preemptive priority value, and subpriority value.
AnnaBridge 188:bcfe06ba3d64 890 In case of a conflict between priority grouping and available
AnnaBridge 188:bcfe06ba3d64 891 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 188:bcfe06ba3d64 892 \param [in] PriorityGroup Used priority group.
AnnaBridge 188:bcfe06ba3d64 893 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 894 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 895 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 188:bcfe06ba3d64 896 */
AnnaBridge 188:bcfe06ba3d64 897 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 188:bcfe06ba3d64 898 {
AnnaBridge 188:bcfe06ba3d64 899 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 188:bcfe06ba3d64 900 uint32_t PreemptPriorityBits;
AnnaBridge 188:bcfe06ba3d64 901 uint32_t SubPriorityBits;
AnnaBridge 188:bcfe06ba3d64 902
AnnaBridge 188:bcfe06ba3d64 903 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 188:bcfe06ba3d64 904 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 188:bcfe06ba3d64 905
AnnaBridge 188:bcfe06ba3d64 906 return (
AnnaBridge 188:bcfe06ba3d64 907 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 188:bcfe06ba3d64 908 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 188:bcfe06ba3d64 909 );
AnnaBridge 188:bcfe06ba3d64 910 }
AnnaBridge 188:bcfe06ba3d64 911
AnnaBridge 188:bcfe06ba3d64 912
AnnaBridge 188:bcfe06ba3d64 913 /**
AnnaBridge 188:bcfe06ba3d64 914 \brief Decode Priority
AnnaBridge 188:bcfe06ba3d64 915 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 188:bcfe06ba3d64 916 preemptive priority value and subpriority value.
AnnaBridge 188:bcfe06ba3d64 917 In case of a conflict between priority grouping and available
AnnaBridge 188:bcfe06ba3d64 918 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 188:bcfe06ba3d64 919 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 188:bcfe06ba3d64 920 \param [in] PriorityGroup Used priority group.
AnnaBridge 188:bcfe06ba3d64 921 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 922 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 188:bcfe06ba3d64 923 */
AnnaBridge 188:bcfe06ba3d64 924 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 188:bcfe06ba3d64 925 {
AnnaBridge 188:bcfe06ba3d64 926 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 188:bcfe06ba3d64 927 uint32_t PreemptPriorityBits;
AnnaBridge 188:bcfe06ba3d64 928 uint32_t SubPriorityBits;
AnnaBridge 188:bcfe06ba3d64 929
AnnaBridge 188:bcfe06ba3d64 930 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 188:bcfe06ba3d64 931 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 188:bcfe06ba3d64 932
AnnaBridge 188:bcfe06ba3d64 933 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 188:bcfe06ba3d64 934 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 188:bcfe06ba3d64 935 }
AnnaBridge 188:bcfe06ba3d64 936
AnnaBridge 188:bcfe06ba3d64 937
AnnaBridge 188:bcfe06ba3d64 938 /**
Anna Bridge 180:96ed750bd169 939 \brief Set Interrupt Vector
Anna Bridge 180:96ed750bd169 940 \details Sets an interrupt vector in SRAM based interrupt vector table.
Anna Bridge 180:96ed750bd169 941 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 942 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 943 VTOR must been relocated to SRAM before.
Anna Bridge 180:96ed750bd169 944 If VTOR is not present address 0 must be mapped to SRAM.
Anna Bridge 180:96ed750bd169 945 \param [in] IRQn Interrupt number
Anna Bridge 180:96ed750bd169 946 \param [in] vector Address of interrupt handler function
Anna Bridge 180:96ed750bd169 947 */
Anna Bridge 180:96ed750bd169 948 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Anna Bridge 180:96ed750bd169 949 {
Anna Bridge 180:96ed750bd169 950 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 951 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 180:96ed750bd169 952 #else
Anna Bridge 180:96ed750bd169 953 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 180:96ed750bd169 954 #endif
Anna Bridge 180:96ed750bd169 955 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
Anna Bridge 180:96ed750bd169 956 }
Anna Bridge 180:96ed750bd169 957
Anna Bridge 180:96ed750bd169 958
Anna Bridge 180:96ed750bd169 959 /**
Anna Bridge 180:96ed750bd169 960 \brief Get Interrupt Vector
Anna Bridge 180:96ed750bd169 961 \details Reads an interrupt vector from interrupt vector table.
Anna Bridge 180:96ed750bd169 962 The interrupt number can be positive to specify a device specific interrupt,
Anna Bridge 180:96ed750bd169 963 or negative to specify a processor exception.
Anna Bridge 180:96ed750bd169 964 \param [in] IRQn Interrupt number.
Anna Bridge 180:96ed750bd169 965 \return Address of interrupt handler function
Anna Bridge 180:96ed750bd169 966 */
Anna Bridge 180:96ed750bd169 967 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 968 {
Anna Bridge 180:96ed750bd169 969 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 970 uint32_t *vectors = (uint32_t *)SCB->VTOR;
Anna Bridge 180:96ed750bd169 971 #else
Anna Bridge 180:96ed750bd169 972 uint32_t *vectors = (uint32_t *)0x0U;
Anna Bridge 180:96ed750bd169 973 #endif
Anna Bridge 180:96ed750bd169 974 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
Anna Bridge 180:96ed750bd169 975
Anna Bridge 180:96ed750bd169 976 }
Anna Bridge 180:96ed750bd169 977
Anna Bridge 180:96ed750bd169 978
Anna Bridge 180:96ed750bd169 979 /**
Anna Bridge 180:96ed750bd169 980 \brief System Reset
Anna Bridge 180:96ed750bd169 981 \details Initiates a system reset request to reset the MCU.
Anna Bridge 180:96ed750bd169 982 */
AnnaBridge 188:bcfe06ba3d64 983 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
Anna Bridge 180:96ed750bd169 984 {
Anna Bridge 180:96ed750bd169 985 __DSB(); /* Ensure all outstanding memory accesses included
Anna Bridge 180:96ed750bd169 986 buffered write are completed before reset */
Anna Bridge 180:96ed750bd169 987 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Anna Bridge 180:96ed750bd169 988 SCB_AIRCR_SYSRESETREQ_Msk);
Anna Bridge 180:96ed750bd169 989 __DSB(); /* Ensure completion of memory access */
Anna Bridge 180:96ed750bd169 990
Anna Bridge 180:96ed750bd169 991 for(;;) /* wait until reset */
Anna Bridge 180:96ed750bd169 992 {
Anna Bridge 180:96ed750bd169 993 __NOP();
Anna Bridge 180:96ed750bd169 994 }
Anna Bridge 180:96ed750bd169 995 }
Anna Bridge 180:96ed750bd169 996
Anna Bridge 180:96ed750bd169 997 /*@} end of CMSIS_Core_NVICFunctions */
Anna Bridge 180:96ed750bd169 998
Anna Bridge 180:96ed750bd169 999 /* ########################## MPU functions #################################### */
Anna Bridge 180:96ed750bd169 1000
Anna Bridge 180:96ed750bd169 1001 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 1002
Anna Bridge 180:96ed750bd169 1003 #include "mpu_armv7.h"
Anna Bridge 180:96ed750bd169 1004
Anna Bridge 180:96ed750bd169 1005 #endif
Anna Bridge 180:96ed750bd169 1006
Anna Bridge 180:96ed750bd169 1007 /* ########################## FPU functions #################################### */
Anna Bridge 180:96ed750bd169 1008 /**
Anna Bridge 180:96ed750bd169 1009 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 1010 \defgroup CMSIS_Core_FpuFunctions FPU Functions
Anna Bridge 180:96ed750bd169 1011 \brief Function that provides FPU type.
Anna Bridge 180:96ed750bd169 1012 @{
Anna Bridge 180:96ed750bd169 1013 */
Anna Bridge 180:96ed750bd169 1014
Anna Bridge 180:96ed750bd169 1015 /**
Anna Bridge 180:96ed750bd169 1016 \brief get FPU type
Anna Bridge 180:96ed750bd169 1017 \details returns the FPU type
Anna Bridge 180:96ed750bd169 1018 \returns
Anna Bridge 180:96ed750bd169 1019 - \b 0: No FPU
Anna Bridge 180:96ed750bd169 1020 - \b 1: Single precision FPU
Anna Bridge 180:96ed750bd169 1021 - \b 2: Double + Single precision FPU
Anna Bridge 180:96ed750bd169 1022 */
Anna Bridge 180:96ed750bd169 1023 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
Anna Bridge 180:96ed750bd169 1024 {
Anna Bridge 180:96ed750bd169 1025 return 0U; /* No FPU */
Anna Bridge 180:96ed750bd169 1026 }
Anna Bridge 180:96ed750bd169 1027
Anna Bridge 180:96ed750bd169 1028
Anna Bridge 180:96ed750bd169 1029 /*@} end of CMSIS_Core_FpuFunctions */
Anna Bridge 180:96ed750bd169 1030
Anna Bridge 180:96ed750bd169 1031
Anna Bridge 180:96ed750bd169 1032
Anna Bridge 180:96ed750bd169 1033 /* ################################## SysTick function ############################################ */
Anna Bridge 180:96ed750bd169 1034 /**
Anna Bridge 180:96ed750bd169 1035 \ingroup CMSIS_Core_FunctionInterface
Anna Bridge 180:96ed750bd169 1036 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Anna Bridge 180:96ed750bd169 1037 \brief Functions that configure the System.
Anna Bridge 180:96ed750bd169 1038 @{
Anna Bridge 180:96ed750bd169 1039 */
Anna Bridge 180:96ed750bd169 1040
Anna Bridge 180:96ed750bd169 1041 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Anna Bridge 180:96ed750bd169 1042
Anna Bridge 180:96ed750bd169 1043 /**
Anna Bridge 180:96ed750bd169 1044 \brief System Tick Configuration
Anna Bridge 180:96ed750bd169 1045 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Anna Bridge 180:96ed750bd169 1046 Counter is in free running mode to generate periodic interrupts.
Anna Bridge 180:96ed750bd169 1047 \param [in] ticks Number of ticks between two interrupts.
Anna Bridge 180:96ed750bd169 1048 \return 0 Function succeeded.
Anna Bridge 180:96ed750bd169 1049 \return 1 Function failed.
Anna Bridge 180:96ed750bd169 1050 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Anna Bridge 180:96ed750bd169 1051 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Anna Bridge 180:96ed750bd169 1052 must contain a vendor-specific implementation of this function.
Anna Bridge 180:96ed750bd169 1053 */
Anna Bridge 180:96ed750bd169 1054 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Anna Bridge 180:96ed750bd169 1055 {
Anna Bridge 180:96ed750bd169 1056 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
Anna Bridge 180:96ed750bd169 1057 {
Anna Bridge 180:96ed750bd169 1058 return (1UL); /* Reload value impossible */
Anna Bridge 180:96ed750bd169 1059 }
Anna Bridge 180:96ed750bd169 1060
Anna Bridge 180:96ed750bd169 1061 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Anna Bridge 180:96ed750bd169 1062 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Anna Bridge 180:96ed750bd169 1063 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Anna Bridge 180:96ed750bd169 1064 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Anna Bridge 180:96ed750bd169 1065 SysTick_CTRL_TICKINT_Msk |
Anna Bridge 180:96ed750bd169 1066 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Anna Bridge 180:96ed750bd169 1067 return (0UL); /* Function successful */
Anna Bridge 180:96ed750bd169 1068 }
Anna Bridge 180:96ed750bd169 1069
Anna Bridge 180:96ed750bd169 1070 #endif
Anna Bridge 180:96ed750bd169 1071
Anna Bridge 180:96ed750bd169 1072 /*@} end of CMSIS_Core_SysTickFunctions */
Anna Bridge 180:96ed750bd169 1073
Anna Bridge 180:96ed750bd169 1074
Anna Bridge 180:96ed750bd169 1075
Anna Bridge 180:96ed750bd169 1076
Anna Bridge 180:96ed750bd169 1077 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 1078 }
Anna Bridge 180:96ed750bd169 1079 #endif
Anna Bridge 180:96ed750bd169 1080
Anna Bridge 180:96ed750bd169 1081 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Anna Bridge 180:96ed750bd169 1082
Anna Bridge 180:96ed750bd169 1083 #endif /* __CMSIS_GENERIC */