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mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_A/core_ca.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 180:96ed750bd169 1 /**************************************************************************//**
Anna Bridge 180:96ed750bd169 2 * @file core_ca.h
Anna Bridge 180:96ed750bd169 3 * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
AnnaBridge 188:bcfe06ba3d64 4 * @version V1.0.1
AnnaBridge 188:bcfe06ba3d64 5 * @date 07. May 2018
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 180:96ed750bd169 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 180:96ed750bd169 25 #if defined ( __ICCARM__ )
Anna Bridge 180:96ed750bd169 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 180:96ed750bd169 27 #elif defined (__clang__)
Anna Bridge 180:96ed750bd169 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 180:96ed750bd169 29 #endif
Anna Bridge 180:96ed750bd169 30
Anna Bridge 180:96ed750bd169 31 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 32 extern "C" {
Anna Bridge 180:96ed750bd169 33 #endif
Anna Bridge 180:96ed750bd169 34
Anna Bridge 180:96ed750bd169 35 #ifndef __CORE_CA_H_GENERIC
Anna Bridge 180:96ed750bd169 36 #define __CORE_CA_H_GENERIC
Anna Bridge 180:96ed750bd169 37
Anna Bridge 180:96ed750bd169 38
Anna Bridge 180:96ed750bd169 39 /*******************************************************************************
Anna Bridge 180:96ed750bd169 40 * CMSIS definitions
Anna Bridge 180:96ed750bd169 41 ******************************************************************************/
Anna Bridge 180:96ed750bd169 42
Anna Bridge 180:96ed750bd169 43 /* CMSIS CA definitions */
Anna Bridge 180:96ed750bd169 44 #define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */
Anna Bridge 180:96ed750bd169 45 #define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
Anna Bridge 180:96ed750bd169 46 #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
Anna Bridge 180:96ed750bd169 47 __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
Anna Bridge 180:96ed750bd169 48
Anna Bridge 180:96ed750bd169 49 #if defined ( __CC_ARM )
Anna Bridge 180:96ed750bd169 50 #if defined __TARGET_FPU_VFP
Anna Bridge 180:96ed750bd169 51 #if (__FPU_PRESENT == 1)
Anna Bridge 180:96ed750bd169 52 #define __FPU_USED 1U
Anna Bridge 180:96ed750bd169 53 #else
Anna Bridge 180:96ed750bd169 54 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 55 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 56 #endif
Anna Bridge 180:96ed750bd169 57 #else
Anna Bridge 180:96ed750bd169 58 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 59 #endif
Anna Bridge 180:96ed750bd169 60
Anna Bridge 180:96ed750bd169 61 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 189:f392fc9709a3 62 #if defined __ARM_FP
Anna Bridge 180:96ed750bd169 63 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 64 #define __FPU_USED 1U
Anna Bridge 180:96ed750bd169 65 #else
Anna Bridge 180:96ed750bd169 66 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 67 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 68 #endif
Anna Bridge 180:96ed750bd169 69 #else
Anna Bridge 180:96ed750bd169 70 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 71 #endif
Anna Bridge 180:96ed750bd169 72
Anna Bridge 180:96ed750bd169 73 #elif defined ( __ICCARM__ )
Anna Bridge 180:96ed750bd169 74 #if defined __ARMVFP__
Anna Bridge 180:96ed750bd169 75 #if (__FPU_PRESENT == 1)
Anna Bridge 180:96ed750bd169 76 #define __FPU_USED 1U
Anna Bridge 180:96ed750bd169 77 #else
Anna Bridge 180:96ed750bd169 78 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 79 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 80 #endif
Anna Bridge 180:96ed750bd169 81 #else
Anna Bridge 180:96ed750bd169 82 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 83 #endif
Anna Bridge 180:96ed750bd169 84
Anna Bridge 180:96ed750bd169 85 #elif defined ( __TMS470__ )
Anna Bridge 180:96ed750bd169 86 #if defined __TI_VFP_SUPPORT__
Anna Bridge 180:96ed750bd169 87 #if (__FPU_PRESENT == 1)
Anna Bridge 180:96ed750bd169 88 #define __FPU_USED 1U
Anna Bridge 180:96ed750bd169 89 #else
Anna Bridge 180:96ed750bd169 90 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 91 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 92 #endif
Anna Bridge 180:96ed750bd169 93 #else
Anna Bridge 180:96ed750bd169 94 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 95 #endif
Anna Bridge 180:96ed750bd169 96
Anna Bridge 180:96ed750bd169 97 #elif defined ( __GNUC__ )
Anna Bridge 180:96ed750bd169 98 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Anna Bridge 180:96ed750bd169 99 #if (__FPU_PRESENT == 1)
Anna Bridge 180:96ed750bd169 100 #define __FPU_USED 1U
Anna Bridge 180:96ed750bd169 101 #else
Anna Bridge 180:96ed750bd169 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 103 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 104 #endif
Anna Bridge 180:96ed750bd169 105 #else
Anna Bridge 180:96ed750bd169 106 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 107 #endif
Anna Bridge 180:96ed750bd169 108
Anna Bridge 180:96ed750bd169 109 #elif defined ( __TASKING__ )
Anna Bridge 180:96ed750bd169 110 #if defined __FPU_VFP__
Anna Bridge 180:96ed750bd169 111 #if (__FPU_PRESENT == 1)
Anna Bridge 180:96ed750bd169 112 #define __FPU_USED 1U
Anna Bridge 180:96ed750bd169 113 #else
Anna Bridge 180:96ed750bd169 114 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Anna Bridge 180:96ed750bd169 115 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 116 #endif
Anna Bridge 180:96ed750bd169 117 #else
Anna Bridge 180:96ed750bd169 118 #define __FPU_USED 0U
Anna Bridge 180:96ed750bd169 119 #endif
Anna Bridge 180:96ed750bd169 120 #endif
Anna Bridge 180:96ed750bd169 121
Anna Bridge 180:96ed750bd169 122 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
Anna Bridge 180:96ed750bd169 123
Anna Bridge 180:96ed750bd169 124 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 125 }
Anna Bridge 180:96ed750bd169 126 #endif
Anna Bridge 180:96ed750bd169 127
Anna Bridge 180:96ed750bd169 128 #endif /* __CORE_CA_H_GENERIC */
Anna Bridge 180:96ed750bd169 129
Anna Bridge 180:96ed750bd169 130 #ifndef __CMSIS_GENERIC
Anna Bridge 180:96ed750bd169 131
Anna Bridge 180:96ed750bd169 132 #ifndef __CORE_CA_H_DEPENDANT
Anna Bridge 180:96ed750bd169 133 #define __CORE_CA_H_DEPENDANT
Anna Bridge 180:96ed750bd169 134
Anna Bridge 180:96ed750bd169 135 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 136 extern "C" {
Anna Bridge 180:96ed750bd169 137 #endif
Anna Bridge 180:96ed750bd169 138
Anna Bridge 180:96ed750bd169 139 /* check device defines and use defaults */
Anna Bridge 180:96ed750bd169 140 #if defined __CHECK_DEVICE_DEFINES
Anna Bridge 180:96ed750bd169 141 #ifndef __CA_REV
Anna Bridge 180:96ed750bd169 142 #define __CA_REV 0x0000U
Anna Bridge 180:96ed750bd169 143 #warning "__CA_REV not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 144 #endif
Anna Bridge 180:96ed750bd169 145
Anna Bridge 180:96ed750bd169 146 #ifndef __FPU_PRESENT
Anna Bridge 180:96ed750bd169 147 #define __FPU_PRESENT 0U
Anna Bridge 180:96ed750bd169 148 #warning "__FPU_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 149 #endif
Anna Bridge 180:96ed750bd169 150
Anna Bridge 180:96ed750bd169 151 #ifndef __GIC_PRESENT
Anna Bridge 180:96ed750bd169 152 #define __GIC_PRESENT 1U
Anna Bridge 180:96ed750bd169 153 #warning "__GIC_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 154 #endif
Anna Bridge 180:96ed750bd169 155
Anna Bridge 180:96ed750bd169 156 #ifndef __TIM_PRESENT
Anna Bridge 180:96ed750bd169 157 #define __TIM_PRESENT 1U
Anna Bridge 180:96ed750bd169 158 #warning "__TIM_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 159 #endif
Anna Bridge 180:96ed750bd169 160
Anna Bridge 180:96ed750bd169 161 #ifndef __L2C_PRESENT
Anna Bridge 180:96ed750bd169 162 #define __L2C_PRESENT 0U
Anna Bridge 180:96ed750bd169 163 #warning "__L2C_PRESENT not defined in device header file; using default!"
Anna Bridge 180:96ed750bd169 164 #endif
Anna Bridge 180:96ed750bd169 165 #endif
Anna Bridge 180:96ed750bd169 166
Anna Bridge 180:96ed750bd169 167 /* IO definitions (access restrictions to peripheral registers) */
Anna Bridge 180:96ed750bd169 168 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 169 #define __I volatile /*!< \brief Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 170 #else
Anna Bridge 180:96ed750bd169 171 #define __I volatile const /*!< \brief Defines 'read only' permissions */
Anna Bridge 180:96ed750bd169 172 #endif
Anna Bridge 180:96ed750bd169 173 #define __O volatile /*!< \brief Defines 'write only' permissions */
Anna Bridge 180:96ed750bd169 174 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
Anna Bridge 180:96ed750bd169 175
Anna Bridge 180:96ed750bd169 176 /* following defines should be used for structure members */
Anna Bridge 180:96ed750bd169 177 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
Anna Bridge 180:96ed750bd169 178 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
Anna Bridge 180:96ed750bd169 179 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
Anna Bridge 180:96ed750bd169 180 #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
Anna Bridge 180:96ed750bd169 181
Anna Bridge 180:96ed750bd169 182 /*******************************************************************************
Anna Bridge 180:96ed750bd169 183 * Register Abstraction
Anna Bridge 180:96ed750bd169 184 Core Register contain:
Anna Bridge 180:96ed750bd169 185 - CPSR
Anna Bridge 180:96ed750bd169 186 - CP15 Registers
Anna Bridge 180:96ed750bd169 187 - L2C-310 Cache Controller
Anna Bridge 180:96ed750bd169 188 - Generic Interrupt Controller Distributor
Anna Bridge 180:96ed750bd169 189 - Generic Interrupt Controller Interface
Anna Bridge 180:96ed750bd169 190 ******************************************************************************/
Anna Bridge 180:96ed750bd169 191
Anna Bridge 180:96ed750bd169 192 /* Core Register CPSR */
Anna Bridge 180:96ed750bd169 193 typedef union
Anna Bridge 180:96ed750bd169 194 {
Anna Bridge 180:96ed750bd169 195 struct
Anna Bridge 180:96ed750bd169 196 {
Anna Bridge 180:96ed750bd169 197 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
Anna Bridge 180:96ed750bd169 198 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
Anna Bridge 180:96ed750bd169 199 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
Anna Bridge 180:96ed750bd169 200 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
Anna Bridge 180:96ed750bd169 201 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
Anna Bridge 180:96ed750bd169 202 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
Anna Bridge 180:96ed750bd169 203 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
Anna Bridge 180:96ed750bd169 204 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
Anna Bridge 180:96ed750bd169 205 RESERVED(0:4, uint32_t)
Anna Bridge 180:96ed750bd169 206 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
Anna Bridge 180:96ed750bd169 207 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
Anna Bridge 180:96ed750bd169 208 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
Anna Bridge 180:96ed750bd169 209 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
Anna Bridge 180:96ed750bd169 210 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
Anna Bridge 180:96ed750bd169 211 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
Anna Bridge 180:96ed750bd169 212 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
Anna Bridge 180:96ed750bd169 213 } b; /*!< \brief Structure used for bit access */
Anna Bridge 180:96ed750bd169 214 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 215 } CPSR_Type;
Anna Bridge 180:96ed750bd169 216
Anna Bridge 180:96ed750bd169 217
Anna Bridge 180:96ed750bd169 218
Anna Bridge 180:96ed750bd169 219 /* CPSR Register Definitions */
Anna Bridge 180:96ed750bd169 220 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
Anna Bridge 180:96ed750bd169 221 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
Anna Bridge 180:96ed750bd169 222
Anna Bridge 180:96ed750bd169 223 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
Anna Bridge 180:96ed750bd169 224 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
Anna Bridge 180:96ed750bd169 225
Anna Bridge 180:96ed750bd169 226 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
Anna Bridge 180:96ed750bd169 227 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
Anna Bridge 180:96ed750bd169 228
Anna Bridge 180:96ed750bd169 229 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
Anna Bridge 180:96ed750bd169 230 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
Anna Bridge 180:96ed750bd169 231
Anna Bridge 180:96ed750bd169 232 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
Anna Bridge 180:96ed750bd169 233 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
Anna Bridge 180:96ed750bd169 234
Anna Bridge 180:96ed750bd169 235 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
Anna Bridge 180:96ed750bd169 236 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
Anna Bridge 180:96ed750bd169 237
Anna Bridge 180:96ed750bd169 238 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
Anna Bridge 180:96ed750bd169 239 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
Anna Bridge 180:96ed750bd169 240
Anna Bridge 180:96ed750bd169 241 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
Anna Bridge 180:96ed750bd169 242 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
Anna Bridge 180:96ed750bd169 243
Anna Bridge 180:96ed750bd169 244 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
Anna Bridge 180:96ed750bd169 245 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
Anna Bridge 180:96ed750bd169 246
Anna Bridge 180:96ed750bd169 247 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
Anna Bridge 180:96ed750bd169 248 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
Anna Bridge 180:96ed750bd169 249
Anna Bridge 180:96ed750bd169 250 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
Anna Bridge 180:96ed750bd169 251 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
Anna Bridge 180:96ed750bd169 252
Anna Bridge 180:96ed750bd169 253 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
Anna Bridge 180:96ed750bd169 254 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
Anna Bridge 180:96ed750bd169 255
Anna Bridge 180:96ed750bd169 256 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
Anna Bridge 180:96ed750bd169 257 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
Anna Bridge 180:96ed750bd169 258
Anna Bridge 180:96ed750bd169 259 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
Anna Bridge 180:96ed750bd169 260 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
Anna Bridge 180:96ed750bd169 261
Anna Bridge 180:96ed750bd169 262 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
Anna Bridge 180:96ed750bd169 263 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
Anna Bridge 180:96ed750bd169 264
Anna Bridge 180:96ed750bd169 265 #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
Anna Bridge 180:96ed750bd169 266 #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
Anna Bridge 180:96ed750bd169 267 #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
Anna Bridge 180:96ed750bd169 268 #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
Anna Bridge 180:96ed750bd169 269 #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
Anna Bridge 180:96ed750bd169 270 #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
Anna Bridge 180:96ed750bd169 271 #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
Anna Bridge 180:96ed750bd169 272 #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
Anna Bridge 180:96ed750bd169 273 #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
Anna Bridge 180:96ed750bd169 274
Anna Bridge 180:96ed750bd169 275 /* CP15 Register SCTLR */
Anna Bridge 180:96ed750bd169 276 typedef union
Anna Bridge 180:96ed750bd169 277 {
Anna Bridge 180:96ed750bd169 278 struct
Anna Bridge 180:96ed750bd169 279 {
Anna Bridge 180:96ed750bd169 280 uint32_t M:1; /*!< \brief bit: 0 MMU enable */
Anna Bridge 180:96ed750bd169 281 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
Anna Bridge 180:96ed750bd169 282 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
Anna Bridge 180:96ed750bd169 283 RESERVED(0:2, uint32_t)
Anna Bridge 180:96ed750bd169 284 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
Anna Bridge 180:96ed750bd169 285 RESERVED(1:1, uint32_t)
Anna Bridge 180:96ed750bd169 286 uint32_t B:1; /*!< \brief bit: 7 Endianness model */
Anna Bridge 180:96ed750bd169 287 RESERVED(2:2, uint32_t)
Anna Bridge 180:96ed750bd169 288 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
Anna Bridge 180:96ed750bd169 289 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
Anna Bridge 180:96ed750bd169 290 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
Anna Bridge 180:96ed750bd169 291 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
Anna Bridge 180:96ed750bd169 292 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
Anna Bridge 180:96ed750bd169 293 RESERVED(3:2, uint32_t)
Anna Bridge 180:96ed750bd169 294 uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */
Anna Bridge 180:96ed750bd169 295 RESERVED(4:1, uint32_t)
Anna Bridge 180:96ed750bd169 296 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
Anna Bridge 180:96ed750bd169 297 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
Anna Bridge 180:96ed750bd169 298 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
Anna Bridge 180:96ed750bd169 299 uint32_t U:1; /*!< \brief bit: 22 Alignment model */
Anna Bridge 180:96ed750bd169 300 RESERVED(5:1, uint32_t)
Anna Bridge 180:96ed750bd169 301 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
Anna Bridge 180:96ed750bd169 302 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
Anna Bridge 180:96ed750bd169 303 RESERVED(6:1, uint32_t)
Anna Bridge 180:96ed750bd169 304 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
Anna Bridge 180:96ed750bd169 305 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
Anna Bridge 180:96ed750bd169 306 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
Anna Bridge 180:96ed750bd169 307 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
Anna Bridge 180:96ed750bd169 308 RESERVED(7:1, uint32_t)
Anna Bridge 180:96ed750bd169 309 } b; /*!< \brief Structure used for bit access */
Anna Bridge 180:96ed750bd169 310 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 311 } SCTLR_Type;
Anna Bridge 180:96ed750bd169 312
Anna Bridge 180:96ed750bd169 313 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
Anna Bridge 180:96ed750bd169 314 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
Anna Bridge 180:96ed750bd169 315
Anna Bridge 180:96ed750bd169 316 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
Anna Bridge 180:96ed750bd169 317 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
Anna Bridge 180:96ed750bd169 318
Anna Bridge 180:96ed750bd169 319 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
Anna Bridge 180:96ed750bd169 320 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
Anna Bridge 180:96ed750bd169 321
Anna Bridge 180:96ed750bd169 322 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
Anna Bridge 180:96ed750bd169 323 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
Anna Bridge 180:96ed750bd169 324
Anna Bridge 180:96ed750bd169 325 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
Anna Bridge 180:96ed750bd169 326 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
Anna Bridge 180:96ed750bd169 327
Anna Bridge 180:96ed750bd169 328 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
Anna Bridge 180:96ed750bd169 329 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
Anna Bridge 180:96ed750bd169 330
Anna Bridge 180:96ed750bd169 331 #define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */
Anna Bridge 180:96ed750bd169 332 #define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */
Anna Bridge 180:96ed750bd169 333
Anna Bridge 180:96ed750bd169 334 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
Anna Bridge 180:96ed750bd169 335 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
Anna Bridge 180:96ed750bd169 336
Anna Bridge 180:96ed750bd169 337 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
Anna Bridge 180:96ed750bd169 338 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
Anna Bridge 180:96ed750bd169 339
Anna Bridge 180:96ed750bd169 340 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
Anna Bridge 180:96ed750bd169 341 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
Anna Bridge 180:96ed750bd169 342
Anna Bridge 180:96ed750bd169 343 #define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */
Anna Bridge 180:96ed750bd169 344 #define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */
Anna Bridge 180:96ed750bd169 345
Anna Bridge 180:96ed750bd169 346 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
Anna Bridge 180:96ed750bd169 347 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
Anna Bridge 180:96ed750bd169 348
Anna Bridge 180:96ed750bd169 349 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
Anna Bridge 180:96ed750bd169 350 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
Anna Bridge 180:96ed750bd169 351
Anna Bridge 180:96ed750bd169 352 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
Anna Bridge 180:96ed750bd169 353 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
Anna Bridge 180:96ed750bd169 354
Anna Bridge 180:96ed750bd169 355 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
Anna Bridge 180:96ed750bd169 356 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
Anna Bridge 180:96ed750bd169 357
Anna Bridge 180:96ed750bd169 358 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
Anna Bridge 180:96ed750bd169 359 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
Anna Bridge 180:96ed750bd169 360
Anna Bridge 180:96ed750bd169 361 #define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */
Anna Bridge 180:96ed750bd169 362 #define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */
Anna Bridge 180:96ed750bd169 363
Anna Bridge 180:96ed750bd169 364 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
Anna Bridge 180:96ed750bd169 365 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
Anna Bridge 180:96ed750bd169 366
Anna Bridge 180:96ed750bd169 367 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
Anna Bridge 180:96ed750bd169 368 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
Anna Bridge 180:96ed750bd169 369
Anna Bridge 180:96ed750bd169 370 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
Anna Bridge 180:96ed750bd169 371 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
Anna Bridge 180:96ed750bd169 372
Anna Bridge 180:96ed750bd169 373 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
Anna Bridge 180:96ed750bd169 374 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
Anna Bridge 180:96ed750bd169 375
Anna Bridge 180:96ed750bd169 376 /* CP15 Register ACTLR */
Anna Bridge 180:96ed750bd169 377 typedef union
Anna Bridge 180:96ed750bd169 378 {
Anna Bridge 180:96ed750bd169 379 #if __CORTEX_A == 5 || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 380 /** \brief Structure used for bit access on Cortex-A5 */
Anna Bridge 180:96ed750bd169 381 struct
Anna Bridge 180:96ed750bd169 382 {
Anna Bridge 180:96ed750bd169 383 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
Anna Bridge 180:96ed750bd169 384 RESERVED(0:5, uint32_t)
Anna Bridge 180:96ed750bd169 385 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
Anna Bridge 180:96ed750bd169 386 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
Anna Bridge 180:96ed750bd169 387 RESERVED(1:2, uint32_t)
Anna Bridge 180:96ed750bd169 388 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
Anna Bridge 180:96ed750bd169 389 uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */
Anna Bridge 180:96ed750bd169 390 uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
Anna Bridge 180:96ed750bd169 391 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
Anna Bridge 180:96ed750bd169 392 uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */
Anna Bridge 180:96ed750bd169 393 uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */
Anna Bridge 180:96ed750bd169 394 uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */
Anna Bridge 180:96ed750bd169 395 RESERVED(3:9, uint32_t)
Anna Bridge 180:96ed750bd169 396 uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */
Anna Bridge 180:96ed750bd169 397 RESERVED(7:3, uint32_t)
Anna Bridge 180:96ed750bd169 398 } b;
Anna Bridge 180:96ed750bd169 399 #endif
Anna Bridge 180:96ed750bd169 400 #if __CORTEX_A == 7 || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 401 /** \brief Structure used for bit access on Cortex-A7 */
Anna Bridge 180:96ed750bd169 402 struct
Anna Bridge 180:96ed750bd169 403 {
Anna Bridge 180:96ed750bd169 404 RESERVED(0:6, uint32_t)
Anna Bridge 180:96ed750bd169 405 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
Anna Bridge 180:96ed750bd169 406 RESERVED(1:3, uint32_t)
Anna Bridge 180:96ed750bd169 407 uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */
Anna Bridge 180:96ed750bd169 408 uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */
Anna Bridge 180:96ed750bd169 409 uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */
Anna Bridge 180:96ed750bd169 410 uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */
Anna Bridge 180:96ed750bd169 411 uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */
Anna Bridge 180:96ed750bd169 412 RESERVED(3:12, uint32_t)
Anna Bridge 180:96ed750bd169 413 uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */
Anna Bridge 180:96ed750bd169 414 RESERVED(7:3, uint32_t)
Anna Bridge 180:96ed750bd169 415 } b;
Anna Bridge 180:96ed750bd169 416 #endif
Anna Bridge 180:96ed750bd169 417 #if __CORTEX_A == 9 || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 418 /** \brief Structure used for bit access on Cortex-A9 */
Anna Bridge 180:96ed750bd169 419 struct
Anna Bridge 180:96ed750bd169 420 {
Anna Bridge 180:96ed750bd169 421 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
Anna Bridge 180:96ed750bd169 422 RESERVED(0:1, uint32_t)
Anna Bridge 180:96ed750bd169 423 uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */
Anna Bridge 180:96ed750bd169 424 uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */
Anna Bridge 180:96ed750bd169 425 RESERVED(1:2, uint32_t)
Anna Bridge 180:96ed750bd169 426 uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */
Anna Bridge 180:96ed750bd169 427 uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */
Anna Bridge 180:96ed750bd169 428 uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */
Anna Bridge 180:96ed750bd169 429 uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */
Anna Bridge 180:96ed750bd169 430 RESERVED(7:22, uint32_t)
Anna Bridge 180:96ed750bd169 431 } b;
Anna Bridge 180:96ed750bd169 432 #endif
Anna Bridge 180:96ed750bd169 433 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 434 } ACTLR_Type;
Anna Bridge 180:96ed750bd169 435
Anna Bridge 180:96ed750bd169 436 #define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */
Anna Bridge 180:96ed750bd169 437 #define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */
Anna Bridge 180:96ed750bd169 438
Anna Bridge 180:96ed750bd169 439 #define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */
Anna Bridge 180:96ed750bd169 440 #define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */
Anna Bridge 180:96ed750bd169 441
Anna Bridge 180:96ed750bd169 442 #define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */
Anna Bridge 180:96ed750bd169 443 #define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */
Anna Bridge 180:96ed750bd169 444
Anna Bridge 180:96ed750bd169 445 #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
Anna Bridge 180:96ed750bd169 446 #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
Anna Bridge 180:96ed750bd169 447
Anna Bridge 180:96ed750bd169 448 #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
Anna Bridge 180:96ed750bd169 449 #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
Anna Bridge 180:96ed750bd169 450
Anna Bridge 180:96ed750bd169 451 #define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */
Anna Bridge 180:96ed750bd169 452 #define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */
Anna Bridge 180:96ed750bd169 453
Anna Bridge 180:96ed750bd169 454 #define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */
Anna Bridge 180:96ed750bd169 455 #define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */
Anna Bridge 180:96ed750bd169 456
Anna Bridge 180:96ed750bd169 457 #define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */
Anna Bridge 180:96ed750bd169 458 #define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */
Anna Bridge 180:96ed750bd169 459
Anna Bridge 180:96ed750bd169 460 #define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */
Anna Bridge 180:96ed750bd169 461 #define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */
Anna Bridge 180:96ed750bd169 462
Anna Bridge 180:96ed750bd169 463 #define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */
Anna Bridge 180:96ed750bd169 464 #define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */
Anna Bridge 180:96ed750bd169 465
Anna Bridge 180:96ed750bd169 466 #define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */
Anna Bridge 180:96ed750bd169 467 #define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */
Anna Bridge 180:96ed750bd169 468
Anna Bridge 180:96ed750bd169 469 #define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */
Anna Bridge 180:96ed750bd169 470 #define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */
Anna Bridge 180:96ed750bd169 471
Anna Bridge 180:96ed750bd169 472 #define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */
Anna Bridge 180:96ed750bd169 473 #define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */
Anna Bridge 180:96ed750bd169 474
Anna Bridge 180:96ed750bd169 475 #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
Anna Bridge 180:96ed750bd169 476 #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
Anna Bridge 180:96ed750bd169 477
Anna Bridge 180:96ed750bd169 478 #define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */
Anna Bridge 180:96ed750bd169 479 #define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */
Anna Bridge 180:96ed750bd169 480
Anna Bridge 180:96ed750bd169 481 #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
Anna Bridge 180:96ed750bd169 482 #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
Anna Bridge 180:96ed750bd169 483
Anna Bridge 180:96ed750bd169 484 #define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */
Anna Bridge 180:96ed750bd169 485 #define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */
Anna Bridge 180:96ed750bd169 486
Anna Bridge 180:96ed750bd169 487 #define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */
Anna Bridge 180:96ed750bd169 488 #define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */
Anna Bridge 180:96ed750bd169 489
Anna Bridge 180:96ed750bd169 490 #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
Anna Bridge 180:96ed750bd169 491 #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
Anna Bridge 180:96ed750bd169 492
Anna Bridge 180:96ed750bd169 493 /* CP15 Register CPACR */
Anna Bridge 180:96ed750bd169 494 typedef union
Anna Bridge 180:96ed750bd169 495 {
Anna Bridge 180:96ed750bd169 496 struct
Anna Bridge 180:96ed750bd169 497 {
Anna Bridge 180:96ed750bd169 498 uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
Anna Bridge 180:96ed750bd169 499 uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
Anna Bridge 180:96ed750bd169 500 uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
Anna Bridge 180:96ed750bd169 501 uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
Anna Bridge 180:96ed750bd169 502 uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
Anna Bridge 180:96ed750bd169 503 uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
Anna Bridge 180:96ed750bd169 504 uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
Anna Bridge 180:96ed750bd169 505 uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
Anna Bridge 180:96ed750bd169 506 uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
Anna Bridge 180:96ed750bd169 507 uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
Anna Bridge 180:96ed750bd169 508 uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
Anna Bridge 180:96ed750bd169 509 uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
Anna Bridge 180:96ed750bd169 510 uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
Anna Bridge 180:96ed750bd169 511 uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
Anna Bridge 180:96ed750bd169 512 uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
Anna Bridge 180:96ed750bd169 513 RESERVED(0:1, uint32_t)
Anna Bridge 180:96ed750bd169 514 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
Anna Bridge 180:96ed750bd169 515 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
Anna Bridge 180:96ed750bd169 516 } b; /*!< \brief Structure used for bit access */
Anna Bridge 180:96ed750bd169 517 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 518 } CPACR_Type;
Anna Bridge 180:96ed750bd169 519
Anna Bridge 180:96ed750bd169 520 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
Anna Bridge 180:96ed750bd169 521 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
Anna Bridge 180:96ed750bd169 522
Anna Bridge 180:96ed750bd169 523 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
Anna Bridge 180:96ed750bd169 524 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
Anna Bridge 180:96ed750bd169 525
Anna Bridge 180:96ed750bd169 526 #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
Anna Bridge 180:96ed750bd169 527 #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
Anna Bridge 180:96ed750bd169 528
Anna Bridge 180:96ed750bd169 529 #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
Anna Bridge 180:96ed750bd169 530 #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
Anna Bridge 180:96ed750bd169 531
Anna Bridge 180:96ed750bd169 532 #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
Anna Bridge 180:96ed750bd169 533 #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
Anna Bridge 180:96ed750bd169 534 #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
Anna Bridge 180:96ed750bd169 535
Anna Bridge 180:96ed750bd169 536 /* CP15 Register DFSR */
Anna Bridge 180:96ed750bd169 537 typedef union
Anna Bridge 180:96ed750bd169 538 {
Anna Bridge 180:96ed750bd169 539 struct
Anna Bridge 180:96ed750bd169 540 {
Anna Bridge 180:96ed750bd169 541 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
Anna Bridge 180:96ed750bd169 542 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
Anna Bridge 180:96ed750bd169 543 RESERVED(0:1, uint32_t)
Anna Bridge 180:96ed750bd169 544 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
Anna Bridge 180:96ed750bd169 545 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
Anna Bridge 180:96ed750bd169 546 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
Anna Bridge 180:96ed750bd169 547 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
Anna Bridge 180:96ed750bd169 548 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
Anna Bridge 180:96ed750bd169 549 RESERVED(1:18, uint32_t)
Anna Bridge 180:96ed750bd169 550 } s; /*!< \brief Structure used for bit access in short format */
Anna Bridge 180:96ed750bd169 551 struct
Anna Bridge 180:96ed750bd169 552 {
Anna Bridge 180:96ed750bd169 553 uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
Anna Bridge 180:96ed750bd169 554 RESERVED(0:3, uint32_t)
Anna Bridge 180:96ed750bd169 555 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
Anna Bridge 180:96ed750bd169 556 RESERVED(1:1, uint32_t)
Anna Bridge 180:96ed750bd169 557 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
Anna Bridge 180:96ed750bd169 558 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
Anna Bridge 180:96ed750bd169 559 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
Anna Bridge 180:96ed750bd169 560 RESERVED(2:18, uint32_t)
Anna Bridge 180:96ed750bd169 561 } l; /*!< \brief Structure used for bit access in long format */
Anna Bridge 180:96ed750bd169 562 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 563 } DFSR_Type;
Anna Bridge 180:96ed750bd169 564
Anna Bridge 180:96ed750bd169 565 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
Anna Bridge 180:96ed750bd169 566 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
Anna Bridge 180:96ed750bd169 567
Anna Bridge 180:96ed750bd169 568 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
Anna Bridge 180:96ed750bd169 569 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
Anna Bridge 180:96ed750bd169 570
Anna Bridge 180:96ed750bd169 571 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
Anna Bridge 180:96ed750bd169 572 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
Anna Bridge 180:96ed750bd169 573
Anna Bridge 180:96ed750bd169 574 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
Anna Bridge 180:96ed750bd169 575 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
Anna Bridge 180:96ed750bd169 576
Anna Bridge 180:96ed750bd169 577 #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
Anna Bridge 180:96ed750bd169 578 #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
Anna Bridge 180:96ed750bd169 579
Anna Bridge 180:96ed750bd169 580 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
Anna Bridge 180:96ed750bd169 581 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
Anna Bridge 180:96ed750bd169 582
Anna Bridge 180:96ed750bd169 583 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
Anna Bridge 180:96ed750bd169 584 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
Anna Bridge 180:96ed750bd169 585
Anna Bridge 180:96ed750bd169 586 #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
Anna Bridge 180:96ed750bd169 587 #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
Anna Bridge 180:96ed750bd169 588
Anna Bridge 180:96ed750bd169 589 /* CP15 Register IFSR */
Anna Bridge 180:96ed750bd169 590 typedef union
Anna Bridge 180:96ed750bd169 591 {
Anna Bridge 180:96ed750bd169 592 struct
Anna Bridge 180:96ed750bd169 593 {
Anna Bridge 180:96ed750bd169 594 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
Anna Bridge 180:96ed750bd169 595 RESERVED(0:5, uint32_t)
Anna Bridge 180:96ed750bd169 596 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
Anna Bridge 180:96ed750bd169 597 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
Anna Bridge 180:96ed750bd169 598 RESERVED(1:1, uint32_t)
Anna Bridge 180:96ed750bd169 599 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
Anna Bridge 180:96ed750bd169 600 RESERVED(2:19, uint32_t)
Anna Bridge 180:96ed750bd169 601 } s; /*!< \brief Structure used for bit access in short format */
Anna Bridge 180:96ed750bd169 602 struct
Anna Bridge 180:96ed750bd169 603 {
Anna Bridge 180:96ed750bd169 604 uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
Anna Bridge 180:96ed750bd169 605 RESERVED(0:3, uint32_t)
Anna Bridge 180:96ed750bd169 606 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
Anna Bridge 180:96ed750bd169 607 RESERVED(1:2, uint32_t)
Anna Bridge 180:96ed750bd169 608 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
Anna Bridge 180:96ed750bd169 609 RESERVED(2:19, uint32_t)
Anna Bridge 180:96ed750bd169 610 } l; /*!< \brief Structure used for bit access in long format */
Anna Bridge 180:96ed750bd169 611 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 612 } IFSR_Type;
Anna Bridge 180:96ed750bd169 613
Anna Bridge 180:96ed750bd169 614 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
Anna Bridge 180:96ed750bd169 615 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
Anna Bridge 180:96ed750bd169 616
Anna Bridge 180:96ed750bd169 617 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
Anna Bridge 180:96ed750bd169 618 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
Anna Bridge 180:96ed750bd169 619
Anna Bridge 180:96ed750bd169 620 #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
Anna Bridge 180:96ed750bd169 621 #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
Anna Bridge 180:96ed750bd169 622
Anna Bridge 180:96ed750bd169 623 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
Anna Bridge 180:96ed750bd169 624 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
Anna Bridge 180:96ed750bd169 625
Anna Bridge 180:96ed750bd169 626 #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
Anna Bridge 180:96ed750bd169 627 #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
Anna Bridge 180:96ed750bd169 628
Anna Bridge 180:96ed750bd169 629 /* CP15 Register ISR */
Anna Bridge 180:96ed750bd169 630 typedef union
Anna Bridge 180:96ed750bd169 631 {
Anna Bridge 180:96ed750bd169 632 struct
Anna Bridge 180:96ed750bd169 633 {
Anna Bridge 180:96ed750bd169 634 RESERVED(0:6, uint32_t)
Anna Bridge 180:96ed750bd169 635 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
Anna Bridge 180:96ed750bd169 636 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
Anna Bridge 180:96ed750bd169 637 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
Anna Bridge 180:96ed750bd169 638 RESERVED(1:23, uint32_t)
Anna Bridge 180:96ed750bd169 639 } b; /*!< \brief Structure used for bit access */
Anna Bridge 180:96ed750bd169 640 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 641 } ISR_Type;
Anna Bridge 180:96ed750bd169 642
Anna Bridge 180:96ed750bd169 643 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
Anna Bridge 180:96ed750bd169 644 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
Anna Bridge 180:96ed750bd169 645
Anna Bridge 180:96ed750bd169 646 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
Anna Bridge 180:96ed750bd169 647 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
Anna Bridge 180:96ed750bd169 648
Anna Bridge 180:96ed750bd169 649 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
Anna Bridge 180:96ed750bd169 650 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
Anna Bridge 180:96ed750bd169 651
Anna Bridge 180:96ed750bd169 652 /* DACR Register */
Anna Bridge 180:96ed750bd169 653 #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
Anna Bridge 180:96ed750bd169 654 #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
Anna Bridge 180:96ed750bd169 655 #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
Anna Bridge 180:96ed750bd169 656 #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
Anna Bridge 180:96ed750bd169 657 #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
Anna Bridge 180:96ed750bd169 658
Anna Bridge 180:96ed750bd169 659 /**
Anna Bridge 180:96ed750bd169 660 \brief Mask and shift a bit field value for use in a register bit range.
Anna Bridge 180:96ed750bd169 661 \param [in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 662 \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 663 \return Masked and shifted value.
Anna Bridge 180:96ed750bd169 664 */
Anna Bridge 180:96ed750bd169 665 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Anna Bridge 180:96ed750bd169 666
Anna Bridge 180:96ed750bd169 667 /**
Anna Bridge 180:96ed750bd169 668 \brief Mask and shift a register value to extract a bit filed value.
Anna Bridge 180:96ed750bd169 669 \param [in] field Name of the register bit field.
Anna Bridge 180:96ed750bd169 670 \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
Anna Bridge 180:96ed750bd169 671 \return Masked and shifted bit field value.
Anna Bridge 180:96ed750bd169 672 */
Anna Bridge 180:96ed750bd169 673 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Anna Bridge 180:96ed750bd169 674
Anna Bridge 180:96ed750bd169 675
Anna Bridge 180:96ed750bd169 676 /**
Anna Bridge 180:96ed750bd169 677 \brief Union type to access the L2C_310 Cache Controller.
Anna Bridge 180:96ed750bd169 678 */
Anna Bridge 180:96ed750bd169 679 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 680 typedef struct
Anna Bridge 180:96ed750bd169 681 {
Anna Bridge 180:96ed750bd169 682 __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */
Anna Bridge 180:96ed750bd169 683 __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */
Anna Bridge 180:96ed750bd169 684 RESERVED(0[0x3e], uint32_t)
Anna Bridge 180:96ed750bd169 685 __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */
Anna Bridge 180:96ed750bd169 686 __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */
Anna Bridge 180:96ed750bd169 687 RESERVED(1[0x3e], uint32_t)
Anna Bridge 180:96ed750bd169 688 __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */
Anna Bridge 180:96ed750bd169 689 __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */
Anna Bridge 180:96ed750bd169 690 __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */
Anna Bridge 180:96ed750bd169 691 RESERVED(2[0x2], uint32_t)
Anna Bridge 180:96ed750bd169 692 __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */
Anna Bridge 180:96ed750bd169 693 __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */
Anna Bridge 180:96ed750bd169 694 __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */
Anna Bridge 180:96ed750bd169 695 __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */
Anna Bridge 180:96ed750bd169 696 RESERVED(3[0x143], uint32_t)
Anna Bridge 180:96ed750bd169 697 __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */
Anna Bridge 180:96ed750bd169 698 RESERVED(4[0xf], uint32_t)
Anna Bridge 180:96ed750bd169 699 __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */
Anna Bridge 180:96ed750bd169 700 RESERVED(6[2], uint32_t)
Anna Bridge 180:96ed750bd169 701 __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */
Anna Bridge 180:96ed750bd169 702 RESERVED(5[0xc], uint32_t)
Anna Bridge 180:96ed750bd169 703 __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */
Anna Bridge 180:96ed750bd169 704 RESERVED(7[1], uint32_t)
Anna Bridge 180:96ed750bd169 705 __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */
Anna Bridge 180:96ed750bd169 706 __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */
Anna Bridge 180:96ed750bd169 707 RESERVED(8[0xc], uint32_t)
Anna Bridge 180:96ed750bd169 708 __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */
Anna Bridge 180:96ed750bd169 709 RESERVED(9[1], uint32_t)
Anna Bridge 180:96ed750bd169 710 __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */
Anna Bridge 180:96ed750bd169 711 __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */
Anna Bridge 180:96ed750bd169 712 RESERVED(10[0x40], uint32_t)
Anna Bridge 180:96ed750bd169 713 __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */
Anna Bridge 180:96ed750bd169 714 __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */
Anna Bridge 180:96ed750bd169 715 __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */
Anna Bridge 180:96ed750bd169 716 __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */
Anna Bridge 180:96ed750bd169 717 __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */
Anna Bridge 180:96ed750bd169 718 __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */
Anna Bridge 180:96ed750bd169 719 __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */
Anna Bridge 180:96ed750bd169 720 __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */
Anna Bridge 180:96ed750bd169 721 __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */
Anna Bridge 180:96ed750bd169 722 __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */
Anna Bridge 180:96ed750bd169 723 __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */
Anna Bridge 180:96ed750bd169 724 __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */
Anna Bridge 180:96ed750bd169 725 __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */
Anna Bridge 180:96ed750bd169 726 __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */
Anna Bridge 180:96ed750bd169 727 __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */
Anna Bridge 180:96ed750bd169 728 __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */
Anna Bridge 180:96ed750bd169 729 RESERVED(11[0x4], uint32_t)
Anna Bridge 180:96ed750bd169 730 __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */
Anna Bridge 180:96ed750bd169 731 __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */
Anna Bridge 180:96ed750bd169 732 RESERVED(12[0xaa], uint32_t)
Anna Bridge 180:96ed750bd169 733 __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */
Anna Bridge 180:96ed750bd169 734 __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */
Anna Bridge 180:96ed750bd169 735 RESERVED(13[0xce], uint32_t)
Anna Bridge 180:96ed750bd169 736 __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */
Anna Bridge 180:96ed750bd169 737 } L2C_310_TypeDef;
Anna Bridge 180:96ed750bd169 738
Anna Bridge 180:96ed750bd169 739 #define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */
Anna Bridge 180:96ed750bd169 740 #endif
Anna Bridge 180:96ed750bd169 741
Anna Bridge 180:96ed750bd169 742 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 743
Anna Bridge 180:96ed750bd169 744 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
Anna Bridge 180:96ed750bd169 745 */
Anna Bridge 180:96ed750bd169 746 typedef struct
Anna Bridge 180:96ed750bd169 747 {
Anna Bridge 180:96ed750bd169 748 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
Anna Bridge 180:96ed750bd169 749 __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
Anna Bridge 180:96ed750bd169 750 __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
Anna Bridge 180:96ed750bd169 751 RESERVED(0, uint32_t)
Anna Bridge 180:96ed750bd169 752 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
Anna Bridge 180:96ed750bd169 753 RESERVED(1[11], uint32_t)
Anna Bridge 180:96ed750bd169 754 __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
Anna Bridge 180:96ed750bd169 755 RESERVED(2, uint32_t)
Anna Bridge 180:96ed750bd169 756 __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
Anna Bridge 180:96ed750bd169 757 RESERVED(3, uint32_t)
Anna Bridge 180:96ed750bd169 758 __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
Anna Bridge 180:96ed750bd169 759 RESERVED(4, uint32_t)
Anna Bridge 180:96ed750bd169 760 __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
Anna Bridge 180:96ed750bd169 761 RESERVED(5[9], uint32_t)
Anna Bridge 180:96ed750bd169 762 __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
Anna Bridge 180:96ed750bd169 763 __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
Anna Bridge 180:96ed750bd169 764 __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
Anna Bridge 180:96ed750bd169 765 __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
Anna Bridge 180:96ed750bd169 766 __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
Anna Bridge 180:96ed750bd169 767 __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
Anna Bridge 180:96ed750bd169 768 __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
Anna Bridge 180:96ed750bd169 769 __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
Anna Bridge 180:96ed750bd169 770 RESERVED(6, uint32_t)
Anna Bridge 180:96ed750bd169 771 __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
Anna Bridge 180:96ed750bd169 772 RESERVED(7, uint32_t)
Anna Bridge 180:96ed750bd169 773 __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
Anna Bridge 180:96ed750bd169 774 __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
Anna Bridge 180:96ed750bd169 775 RESERVED(8[32], uint32_t)
Anna Bridge 180:96ed750bd169 776 __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
Anna Bridge 180:96ed750bd169 777 __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
Anna Bridge 180:96ed750bd169 778 RESERVED(9[3], uint32_t)
Anna Bridge 180:96ed750bd169 779 __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
Anna Bridge 180:96ed750bd169 780 __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
Anna Bridge 180:96ed750bd169 781 RESERVED(10[5236], uint32_t)
Anna Bridge 180:96ed750bd169 782 __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
Anna Bridge 180:96ed750bd169 783 } GICDistributor_Type;
Anna Bridge 180:96ed750bd169 784
Anna Bridge 180:96ed750bd169 785 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
Anna Bridge 180:96ed750bd169 786
Anna Bridge 180:96ed750bd169 787 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
Anna Bridge 180:96ed750bd169 788 */
Anna Bridge 180:96ed750bd169 789 typedef struct
Anna Bridge 180:96ed750bd169 790 {
Anna Bridge 180:96ed750bd169 791 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
Anna Bridge 180:96ed750bd169 792 __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
Anna Bridge 180:96ed750bd169 793 __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
Anna Bridge 180:96ed750bd169 794 __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
Anna Bridge 180:96ed750bd169 795 __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
Anna Bridge 180:96ed750bd169 796 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
Anna Bridge 180:96ed750bd169 797 __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
Anna Bridge 180:96ed750bd169 798 __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
Anna Bridge 180:96ed750bd169 799 __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
Anna Bridge 180:96ed750bd169 800 __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
Anna Bridge 180:96ed750bd169 801 __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
Anna Bridge 180:96ed750bd169 802 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
Anna Bridge 180:96ed750bd169 803 RESERVED(1[40], uint32_t)
Anna Bridge 180:96ed750bd169 804 __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
Anna Bridge 180:96ed750bd169 805 __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
Anna Bridge 180:96ed750bd169 806 RESERVED(2[3], uint32_t)
Anna Bridge 180:96ed750bd169 807 __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
Anna Bridge 180:96ed750bd169 808 RESERVED(3[960], uint32_t)
Anna Bridge 180:96ed750bd169 809 __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
Anna Bridge 180:96ed750bd169 810 } GICInterface_Type;
Anna Bridge 180:96ed750bd169 811
Anna Bridge 180:96ed750bd169 812 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
Anna Bridge 180:96ed750bd169 813 #endif
Anna Bridge 180:96ed750bd169 814
Anna Bridge 180:96ed750bd169 815 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 816 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 817 /** \brief Structure type to access the Private Timer
Anna Bridge 180:96ed750bd169 818 */
Anna Bridge 180:96ed750bd169 819 typedef struct
Anna Bridge 180:96ed750bd169 820 {
Anna Bridge 180:96ed750bd169 821 __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
Anna Bridge 180:96ed750bd169 822 __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
Anna Bridge 180:96ed750bd169 823 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
Anna Bridge 180:96ed750bd169 824 __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
Anna Bridge 180:96ed750bd169 825 RESERVED(0[4], uint32_t)
Anna Bridge 180:96ed750bd169 826 __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
Anna Bridge 180:96ed750bd169 827 __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
Anna Bridge 180:96ed750bd169 828 __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
Anna Bridge 180:96ed750bd169 829 __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
Anna Bridge 180:96ed750bd169 830 __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
Anna Bridge 180:96ed750bd169 831 __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
Anna Bridge 180:96ed750bd169 832 } Timer_Type;
Anna Bridge 180:96ed750bd169 833 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
Anna Bridge 180:96ed750bd169 834 #endif
Anna Bridge 180:96ed750bd169 835 #endif
Anna Bridge 180:96ed750bd169 836
Anna Bridge 180:96ed750bd169 837 /*******************************************************************************
Anna Bridge 180:96ed750bd169 838 * Hardware Abstraction Layer
Anna Bridge 180:96ed750bd169 839 Core Function Interface contains:
Anna Bridge 180:96ed750bd169 840 - L1 Cache Functions
Anna Bridge 180:96ed750bd169 841 - L2C-310 Cache Controller Functions
Anna Bridge 180:96ed750bd169 842 - PL1 Timer Functions
Anna Bridge 180:96ed750bd169 843 - GIC Functions
Anna Bridge 180:96ed750bd169 844 - MMU Functions
Anna Bridge 180:96ed750bd169 845 ******************************************************************************/
Anna Bridge 180:96ed750bd169 846
Anna Bridge 180:96ed750bd169 847 /* ########################## L1 Cache functions ################################# */
Anna Bridge 180:96ed750bd169 848
Anna Bridge 180:96ed750bd169 849 /** \brief Enable Caches by setting I and C bits in SCTLR register.
Anna Bridge 180:96ed750bd169 850 */
Anna Bridge 180:96ed750bd169 851 __STATIC_FORCEINLINE void L1C_EnableCaches(void) {
Anna Bridge 180:96ed750bd169 852 __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
Anna Bridge 180:96ed750bd169 853 __ISB();
Anna Bridge 180:96ed750bd169 854 }
Anna Bridge 180:96ed750bd169 855
Anna Bridge 180:96ed750bd169 856 /** \brief Disable Caches by clearing I and C bits in SCTLR register.
Anna Bridge 180:96ed750bd169 857 */
Anna Bridge 180:96ed750bd169 858 __STATIC_FORCEINLINE void L1C_DisableCaches(void) {
Anna Bridge 180:96ed750bd169 859 __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
Anna Bridge 180:96ed750bd169 860 __ISB();
Anna Bridge 180:96ed750bd169 861 }
Anna Bridge 180:96ed750bd169 862
Anna Bridge 180:96ed750bd169 863 /** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
Anna Bridge 180:96ed750bd169 864 */
Anna Bridge 180:96ed750bd169 865 __STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
Anna Bridge 180:96ed750bd169 866 __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
Anna Bridge 180:96ed750bd169 867 __ISB();
Anna Bridge 180:96ed750bd169 868 }
Anna Bridge 180:96ed750bd169 869
Anna Bridge 180:96ed750bd169 870 /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
Anna Bridge 180:96ed750bd169 871 */
Anna Bridge 180:96ed750bd169 872 __STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
Anna Bridge 180:96ed750bd169 873 __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
Anna Bridge 180:96ed750bd169 874 __ISB();
Anna Bridge 180:96ed750bd169 875 }
Anna Bridge 180:96ed750bd169 876
Anna Bridge 180:96ed750bd169 877 /** \brief Invalidate entire branch predictor array
Anna Bridge 180:96ed750bd169 878 */
Anna Bridge 180:96ed750bd169 879 __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
Anna Bridge 180:96ed750bd169 880 __set_BPIALL(0);
Anna Bridge 180:96ed750bd169 881 __DSB(); //ensure completion of the invalidation
Anna Bridge 180:96ed750bd169 882 __ISB(); //ensure instruction fetch path sees new state
Anna Bridge 180:96ed750bd169 883 }
Anna Bridge 180:96ed750bd169 884
Anna Bridge 180:96ed750bd169 885 /** \brief Invalidate the whole instruction cache
Anna Bridge 180:96ed750bd169 886 */
Anna Bridge 180:96ed750bd169 887 __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
Anna Bridge 180:96ed750bd169 888 __set_ICIALLU(0);
Anna Bridge 180:96ed750bd169 889 __DSB(); //ensure completion of the invalidation
Anna Bridge 180:96ed750bd169 890 __ISB(); //ensure instruction fetch path sees new I cache state
Anna Bridge 180:96ed750bd169 891 }
Anna Bridge 180:96ed750bd169 892
Anna Bridge 180:96ed750bd169 893 /** \brief Clean data cache line by address.
Anna Bridge 180:96ed750bd169 894 * \param [in] va Pointer to data to clear the cache for.
Anna Bridge 180:96ed750bd169 895 */
Anna Bridge 180:96ed750bd169 896 __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
Anna Bridge 180:96ed750bd169 897 __set_DCCMVAC((uint32_t)va);
Anna Bridge 180:96ed750bd169 898 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 180:96ed750bd169 899 }
Anna Bridge 180:96ed750bd169 900
Anna Bridge 180:96ed750bd169 901 /** \brief Invalidate data cache line by address.
Anna Bridge 180:96ed750bd169 902 * \param [in] va Pointer to data to invalidate the cache for.
Anna Bridge 180:96ed750bd169 903 */
Anna Bridge 180:96ed750bd169 904 __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
Anna Bridge 180:96ed750bd169 905 __set_DCIMVAC((uint32_t)va);
Anna Bridge 180:96ed750bd169 906 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 180:96ed750bd169 907 }
Anna Bridge 180:96ed750bd169 908
Anna Bridge 180:96ed750bd169 909 /** \brief Clean and Invalidate data cache by address.
Anna Bridge 180:96ed750bd169 910 * \param [in] va Pointer to data to invalidate the cache for.
Anna Bridge 180:96ed750bd169 911 */
Anna Bridge 180:96ed750bd169 912 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
Anna Bridge 180:96ed750bd169 913 __set_DCCIMVAC((uint32_t)va);
Anna Bridge 180:96ed750bd169 914 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Anna Bridge 180:96ed750bd169 915 }
Anna Bridge 180:96ed750bd169 916
Anna Bridge 180:96ed750bd169 917 /** \brief Calculate log2 rounded up
Anna Bridge 180:96ed750bd169 918 * - log(0) => 0
Anna Bridge 180:96ed750bd169 919 * - log(1) => 0
Anna Bridge 180:96ed750bd169 920 * - log(2) => 1
Anna Bridge 180:96ed750bd169 921 * - log(3) => 2
Anna Bridge 180:96ed750bd169 922 * - log(4) => 2
Anna Bridge 180:96ed750bd169 923 * - log(5) => 3
Anna Bridge 180:96ed750bd169 924 * : :
Anna Bridge 180:96ed750bd169 925 * - log(16) => 4
Anna Bridge 180:96ed750bd169 926 * - log(32) => 5
Anna Bridge 180:96ed750bd169 927 * : :
Anna Bridge 180:96ed750bd169 928 * \param [in] n input value parameter
Anna Bridge 180:96ed750bd169 929 * \return log2(n)
Anna Bridge 180:96ed750bd169 930 */
Anna Bridge 180:96ed750bd169 931 __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
Anna Bridge 180:96ed750bd169 932 {
Anna Bridge 180:96ed750bd169 933 if (n < 2U) {
Anna Bridge 180:96ed750bd169 934 return 0U;
Anna Bridge 180:96ed750bd169 935 }
Anna Bridge 180:96ed750bd169 936 uint8_t log = 0U;
Anna Bridge 180:96ed750bd169 937 uint32_t t = n;
Anna Bridge 180:96ed750bd169 938 while(t > 1U)
Anna Bridge 180:96ed750bd169 939 {
Anna Bridge 180:96ed750bd169 940 log++;
Anna Bridge 180:96ed750bd169 941 t >>= 1U;
Anna Bridge 180:96ed750bd169 942 }
Anna Bridge 180:96ed750bd169 943 if (n & 1U) { log++; }
Anna Bridge 180:96ed750bd169 944 return log;
Anna Bridge 180:96ed750bd169 945 }
Anna Bridge 180:96ed750bd169 946
Anna Bridge 180:96ed750bd169 947 /** \brief Apply cache maintenance to given cache level.
Anna Bridge 180:96ed750bd169 948 * \param [in] level cache level to be maintained
Anna Bridge 180:96ed750bd169 949 * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
Anna Bridge 180:96ed750bd169 950 */
Anna Bridge 180:96ed750bd169 951 __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
Anna Bridge 180:96ed750bd169 952 {
Anna Bridge 186:707f6e361f3e 953 uint32_t Dummy;
Anna Bridge 186:707f6e361f3e 954 uint32_t ccsidr;
Anna Bridge 180:96ed750bd169 955 uint32_t num_sets;
Anna Bridge 180:96ed750bd169 956 uint32_t num_ways;
Anna Bridge 180:96ed750bd169 957 uint32_t shift_way;
Anna Bridge 180:96ed750bd169 958 uint32_t log2_linesize;
Anna Bridge 180:96ed750bd169 959 int32_t log2_num_ways;
Anna Bridge 180:96ed750bd169 960
Anna Bridge 180:96ed750bd169 961 Dummy = level << 1U;
Anna Bridge 180:96ed750bd169 962 /* set csselr, select ccsidr register */
Anna Bridge 186:707f6e361f3e 963 __set_CSSELR(Dummy);
Anna Bridge 180:96ed750bd169 964 /* get current ccsidr register */
Anna Bridge 180:96ed750bd169 965 ccsidr = __get_CCSIDR();
Anna Bridge 180:96ed750bd169 966 num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
Anna Bridge 180:96ed750bd169 967 num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
Anna Bridge 180:96ed750bd169 968 log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
Anna Bridge 180:96ed750bd169 969 log2_num_ways = __log2_up(num_ways);
Anna Bridge 180:96ed750bd169 970 if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
Anna Bridge 180:96ed750bd169 971 return; // FATAL ERROR
Anna Bridge 180:96ed750bd169 972 }
Anna Bridge 180:96ed750bd169 973 shift_way = 32U - (uint32_t)log2_num_ways;
Anna Bridge 180:96ed750bd169 974 for(int32_t way = num_ways-1; way >= 0; way--)
Anna Bridge 180:96ed750bd169 975 {
Anna Bridge 180:96ed750bd169 976 for(int32_t set = num_sets-1; set >= 0; set--)
Anna Bridge 180:96ed750bd169 977 {
Anna Bridge 180:96ed750bd169 978 Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
Anna Bridge 180:96ed750bd169 979 switch (maint)
Anna Bridge 180:96ed750bd169 980 {
Anna Bridge 180:96ed750bd169 981 case 0U: __set_DCISW(Dummy); break;
Anna Bridge 180:96ed750bd169 982 case 1U: __set_DCCSW(Dummy); break;
Anna Bridge 180:96ed750bd169 983 default: __set_DCCISW(Dummy); break;
Anna Bridge 180:96ed750bd169 984 }
Anna Bridge 180:96ed750bd169 985 }
Anna Bridge 180:96ed750bd169 986 }
Anna Bridge 180:96ed750bd169 987 __DMB();
Anna Bridge 180:96ed750bd169 988 }
Anna Bridge 180:96ed750bd169 989
Anna Bridge 180:96ed750bd169 990 /** \brief Clean and Invalidate the entire data or unified cache
Anna Bridge 180:96ed750bd169 991 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
Anna Bridge 180:96ed750bd169 992 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
Anna Bridge 180:96ed750bd169 993 */
Anna Bridge 180:96ed750bd169 994 __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
Anna Bridge 186:707f6e361f3e 995 uint32_t clidr;
Anna Bridge 180:96ed750bd169 996 uint32_t cache_type;
Anna Bridge 180:96ed750bd169 997 clidr = __get_CLIDR();
Anna Bridge 180:96ed750bd169 998 for(uint32_t i = 0U; i<7U; i++)
Anna Bridge 180:96ed750bd169 999 {
Anna Bridge 180:96ed750bd169 1000 cache_type = (clidr >> i*3U) & 0x7UL;
Anna Bridge 180:96ed750bd169 1001 if ((cache_type >= 2U) && (cache_type <= 4U))
Anna Bridge 180:96ed750bd169 1002 {
Anna Bridge 180:96ed750bd169 1003 __L1C_MaintainDCacheSetWay(i, op);
Anna Bridge 180:96ed750bd169 1004 }
Anna Bridge 180:96ed750bd169 1005 }
Anna Bridge 180:96ed750bd169 1006 }
Anna Bridge 180:96ed750bd169 1007
Anna Bridge 180:96ed750bd169 1008 /** \brief Clean and Invalidate the entire data or unified cache
Anna Bridge 180:96ed750bd169 1009 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
Anna Bridge 180:96ed750bd169 1010 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
Anna Bridge 180:96ed750bd169 1011 * \deprecated Use generic L1C_CleanInvalidateCache instead.
Anna Bridge 180:96ed750bd169 1012 */
Anna Bridge 180:96ed750bd169 1013 CMSIS_DEPRECATED
Anna Bridge 180:96ed750bd169 1014 __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
Anna Bridge 180:96ed750bd169 1015 L1C_CleanInvalidateCache(op);
Anna Bridge 180:96ed750bd169 1016 }
Anna Bridge 180:96ed750bd169 1017
Anna Bridge 180:96ed750bd169 1018 /** \brief Invalidate the whole data cache.
Anna Bridge 180:96ed750bd169 1019 */
Anna Bridge 180:96ed750bd169 1020 __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
Anna Bridge 180:96ed750bd169 1021 L1C_CleanInvalidateCache(0);
Anna Bridge 180:96ed750bd169 1022 }
Anna Bridge 180:96ed750bd169 1023
Anna Bridge 180:96ed750bd169 1024 /** \brief Clean the whole data cache.
Anna Bridge 180:96ed750bd169 1025 */
Anna Bridge 180:96ed750bd169 1026 __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
Anna Bridge 180:96ed750bd169 1027 L1C_CleanInvalidateCache(1);
Anna Bridge 180:96ed750bd169 1028 }
Anna Bridge 180:96ed750bd169 1029
Anna Bridge 180:96ed750bd169 1030 /** \brief Clean and invalidate the whole data cache.
Anna Bridge 180:96ed750bd169 1031 */
Anna Bridge 180:96ed750bd169 1032 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
Anna Bridge 180:96ed750bd169 1033 L1C_CleanInvalidateCache(2);
Anna Bridge 180:96ed750bd169 1034 }
Anna Bridge 180:96ed750bd169 1035
Anna Bridge 180:96ed750bd169 1036 /* ########################## L2 Cache functions ################################# */
Anna Bridge 180:96ed750bd169 1037 #if (__L2C_PRESENT == 1U) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 1038 /** \brief Cache Sync operation by writing CACHE_SYNC register.
Anna Bridge 180:96ed750bd169 1039 */
Anna Bridge 180:96ed750bd169 1040 __STATIC_INLINE void L2C_Sync(void)
Anna Bridge 180:96ed750bd169 1041 {
Anna Bridge 180:96ed750bd169 1042 L2C_310->CACHE_SYNC = 0x0;
Anna Bridge 180:96ed750bd169 1043 }
Anna Bridge 180:96ed750bd169 1044
Anna Bridge 180:96ed750bd169 1045 /** \brief Read cache controller cache ID from CACHE_ID register.
Anna Bridge 180:96ed750bd169 1046 * \return L2C_310_TypeDef::CACHE_ID
Anna Bridge 180:96ed750bd169 1047 */
Anna Bridge 180:96ed750bd169 1048 __STATIC_INLINE int L2C_GetID (void)
Anna Bridge 180:96ed750bd169 1049 {
Anna Bridge 180:96ed750bd169 1050 return L2C_310->CACHE_ID;
Anna Bridge 180:96ed750bd169 1051 }
Anna Bridge 180:96ed750bd169 1052
Anna Bridge 180:96ed750bd169 1053 /** \brief Read cache controller cache type from CACHE_TYPE register.
Anna Bridge 180:96ed750bd169 1054 * \return L2C_310_TypeDef::CACHE_TYPE
Anna Bridge 180:96ed750bd169 1055 */
Anna Bridge 180:96ed750bd169 1056 __STATIC_INLINE int L2C_GetType (void)
Anna Bridge 180:96ed750bd169 1057 {
Anna Bridge 180:96ed750bd169 1058 return L2C_310->CACHE_TYPE;
Anna Bridge 180:96ed750bd169 1059 }
Anna Bridge 180:96ed750bd169 1060
Anna Bridge 180:96ed750bd169 1061 /** \brief Invalidate all cache by way
Anna Bridge 180:96ed750bd169 1062 */
Anna Bridge 180:96ed750bd169 1063 __STATIC_INLINE void L2C_InvAllByWay (void)
Anna Bridge 180:96ed750bd169 1064 {
Anna Bridge 180:96ed750bd169 1065 unsigned int assoc;
Anna Bridge 180:96ed750bd169 1066
Anna Bridge 180:96ed750bd169 1067 if (L2C_310->AUX_CNT & (1U << 16U)) {
Anna Bridge 180:96ed750bd169 1068 assoc = 16U;
Anna Bridge 180:96ed750bd169 1069 } else {
Anna Bridge 180:96ed750bd169 1070 assoc = 8U;
Anna Bridge 180:96ed750bd169 1071 }
Anna Bridge 180:96ed750bd169 1072
Anna Bridge 180:96ed750bd169 1073 L2C_310->INV_WAY = (1U << assoc) - 1U;
Anna Bridge 180:96ed750bd169 1074 while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
Anna Bridge 180:96ed750bd169 1075
Anna Bridge 180:96ed750bd169 1076 L2C_Sync();
Anna Bridge 180:96ed750bd169 1077 }
Anna Bridge 180:96ed750bd169 1078
Anna Bridge 180:96ed750bd169 1079 /** \brief Clean and Invalidate all cache by way
Anna Bridge 180:96ed750bd169 1080 */
Anna Bridge 180:96ed750bd169 1081 __STATIC_INLINE void L2C_CleanInvAllByWay (void)
Anna Bridge 180:96ed750bd169 1082 {
Anna Bridge 180:96ed750bd169 1083 unsigned int assoc;
Anna Bridge 180:96ed750bd169 1084
Anna Bridge 180:96ed750bd169 1085 if (L2C_310->AUX_CNT & (1U << 16U)) {
Anna Bridge 180:96ed750bd169 1086 assoc = 16U;
Anna Bridge 180:96ed750bd169 1087 } else {
Anna Bridge 180:96ed750bd169 1088 assoc = 8U;
Anna Bridge 180:96ed750bd169 1089 }
Anna Bridge 180:96ed750bd169 1090
Anna Bridge 180:96ed750bd169 1091 L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
Anna Bridge 180:96ed750bd169 1092 while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
Anna Bridge 180:96ed750bd169 1093
Anna Bridge 180:96ed750bd169 1094 L2C_Sync();
Anna Bridge 180:96ed750bd169 1095 }
Anna Bridge 180:96ed750bd169 1096
Anna Bridge 180:96ed750bd169 1097 /** \brief Enable Level 2 Cache
Anna Bridge 180:96ed750bd169 1098 */
Anna Bridge 180:96ed750bd169 1099 __STATIC_INLINE void L2C_Enable(void)
Anna Bridge 180:96ed750bd169 1100 {
Anna Bridge 180:96ed750bd169 1101 L2C_310->CONTROL = 0;
Anna Bridge 180:96ed750bd169 1102 L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
Anna Bridge 180:96ed750bd169 1103 L2C_310->DEBUG_CONTROL = 0;
Anna Bridge 180:96ed750bd169 1104 L2C_310->DATA_LOCK_0_WAY = 0;
Anna Bridge 180:96ed750bd169 1105 L2C_310->CACHE_SYNC = 0;
Anna Bridge 180:96ed750bd169 1106 L2C_310->CONTROL = 0x01;
Anna Bridge 180:96ed750bd169 1107 L2C_Sync();
Anna Bridge 180:96ed750bd169 1108 }
Anna Bridge 180:96ed750bd169 1109
Anna Bridge 180:96ed750bd169 1110 /** \brief Disable Level 2 Cache
Anna Bridge 180:96ed750bd169 1111 */
Anna Bridge 180:96ed750bd169 1112 __STATIC_INLINE void L2C_Disable(void)
Anna Bridge 180:96ed750bd169 1113 {
Anna Bridge 180:96ed750bd169 1114 L2C_310->CONTROL = 0x00;
Anna Bridge 180:96ed750bd169 1115 L2C_Sync();
Anna Bridge 180:96ed750bd169 1116 }
Anna Bridge 180:96ed750bd169 1117
Anna Bridge 180:96ed750bd169 1118 /** \brief Invalidate cache by physical address
Anna Bridge 180:96ed750bd169 1119 * \param [in] pa Pointer to data to invalidate cache for.
Anna Bridge 180:96ed750bd169 1120 */
Anna Bridge 180:96ed750bd169 1121 __STATIC_INLINE void L2C_InvPa (void *pa)
Anna Bridge 180:96ed750bd169 1122 {
Anna Bridge 180:96ed750bd169 1123 L2C_310->INV_LINE_PA = (unsigned int)pa;
Anna Bridge 180:96ed750bd169 1124 L2C_Sync();
Anna Bridge 180:96ed750bd169 1125 }
Anna Bridge 180:96ed750bd169 1126
Anna Bridge 180:96ed750bd169 1127 /** \brief Clean cache by physical address
Anna Bridge 180:96ed750bd169 1128 * \param [in] pa Pointer to data to invalidate cache for.
Anna Bridge 180:96ed750bd169 1129 */
Anna Bridge 180:96ed750bd169 1130 __STATIC_INLINE void L2C_CleanPa (void *pa)
Anna Bridge 180:96ed750bd169 1131 {
Anna Bridge 180:96ed750bd169 1132 L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
Anna Bridge 180:96ed750bd169 1133 L2C_Sync();
Anna Bridge 180:96ed750bd169 1134 }
Anna Bridge 180:96ed750bd169 1135
Anna Bridge 180:96ed750bd169 1136 /** \brief Clean and invalidate cache by physical address
Anna Bridge 180:96ed750bd169 1137 * \param [in] pa Pointer to data to invalidate cache for.
Anna Bridge 180:96ed750bd169 1138 */
Anna Bridge 180:96ed750bd169 1139 __STATIC_INLINE void L2C_CleanInvPa (void *pa)
Anna Bridge 180:96ed750bd169 1140 {
Anna Bridge 180:96ed750bd169 1141 L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
Anna Bridge 180:96ed750bd169 1142 L2C_Sync();
Anna Bridge 180:96ed750bd169 1143 }
Anna Bridge 180:96ed750bd169 1144 #endif
Anna Bridge 180:96ed750bd169 1145
Anna Bridge 180:96ed750bd169 1146 /* ########################## GIC functions ###################################### */
Anna Bridge 180:96ed750bd169 1147 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 1148
Anna Bridge 180:96ed750bd169 1149 /** \brief Enable the interrupt distributor using the GIC's CTLR register.
Anna Bridge 180:96ed750bd169 1150 */
Anna Bridge 180:96ed750bd169 1151 __STATIC_INLINE void GIC_EnableDistributor(void)
Anna Bridge 180:96ed750bd169 1152 {
Anna Bridge 180:96ed750bd169 1153 GICDistributor->CTLR |= 1U;
Anna Bridge 180:96ed750bd169 1154 }
Anna Bridge 180:96ed750bd169 1155
Anna Bridge 180:96ed750bd169 1156 /** \brief Disable the interrupt distributor using the GIC's CTLR register.
Anna Bridge 180:96ed750bd169 1157 */
Anna Bridge 180:96ed750bd169 1158 __STATIC_INLINE void GIC_DisableDistributor(void)
Anna Bridge 180:96ed750bd169 1159 {
Anna Bridge 180:96ed750bd169 1160 GICDistributor->CTLR &=~1U;
Anna Bridge 180:96ed750bd169 1161 }
Anna Bridge 180:96ed750bd169 1162
Anna Bridge 180:96ed750bd169 1163 /** \brief Read the GIC's TYPER register.
Anna Bridge 180:96ed750bd169 1164 * \return GICDistributor_Type::TYPER
Anna Bridge 180:96ed750bd169 1165 */
Anna Bridge 180:96ed750bd169 1166 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
Anna Bridge 180:96ed750bd169 1167 {
Anna Bridge 180:96ed750bd169 1168 return (GICDistributor->TYPER);
Anna Bridge 180:96ed750bd169 1169 }
Anna Bridge 180:96ed750bd169 1170
Anna Bridge 180:96ed750bd169 1171 /** \brief Reads the GIC's IIDR register.
Anna Bridge 180:96ed750bd169 1172 * \return GICDistributor_Type::IIDR
Anna Bridge 180:96ed750bd169 1173 */
Anna Bridge 180:96ed750bd169 1174 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
Anna Bridge 180:96ed750bd169 1175 {
Anna Bridge 180:96ed750bd169 1176 return (GICDistributor->IIDR);
Anna Bridge 180:96ed750bd169 1177 }
Anna Bridge 180:96ed750bd169 1178
Anna Bridge 180:96ed750bd169 1179 /** \brief Sets the GIC's ITARGETSR register for the given interrupt.
Anna Bridge 180:96ed750bd169 1180 * \param [in] IRQn Interrupt to be configured.
Anna Bridge 180:96ed750bd169 1181 * \param [in] cpu_target CPU interfaces to assign this interrupt to.
Anna Bridge 180:96ed750bd169 1182 */
Anna Bridge 180:96ed750bd169 1183 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
Anna Bridge 180:96ed750bd169 1184 {
Anna Bridge 180:96ed750bd169 1185 uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
Anna Bridge 180:96ed750bd169 1186 GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
Anna Bridge 180:96ed750bd169 1187 }
Anna Bridge 180:96ed750bd169 1188
Anna Bridge 180:96ed750bd169 1189 /** \brief Read the GIC's ITARGETSR register.
Anna Bridge 180:96ed750bd169 1190 * \param [in] IRQn Interrupt to acquire the configuration for.
Anna Bridge 180:96ed750bd169 1191 * \return GICDistributor_Type::ITARGETSR
Anna Bridge 180:96ed750bd169 1192 */
Anna Bridge 180:96ed750bd169 1193 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1194 {
Anna Bridge 180:96ed750bd169 1195 return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
Anna Bridge 180:96ed750bd169 1196 }
Anna Bridge 180:96ed750bd169 1197
Anna Bridge 180:96ed750bd169 1198 /** \brief Enable the CPU's interrupt interface.
Anna Bridge 180:96ed750bd169 1199 */
Anna Bridge 180:96ed750bd169 1200 __STATIC_INLINE void GIC_EnableInterface(void)
Anna Bridge 180:96ed750bd169 1201 {
Anna Bridge 180:96ed750bd169 1202 GICInterface->CTLR |= 1U; //enable interface
Anna Bridge 180:96ed750bd169 1203 }
Anna Bridge 180:96ed750bd169 1204
Anna Bridge 180:96ed750bd169 1205 /** \brief Disable the CPU's interrupt interface.
Anna Bridge 180:96ed750bd169 1206 */
Anna Bridge 180:96ed750bd169 1207 __STATIC_INLINE void GIC_DisableInterface(void)
Anna Bridge 180:96ed750bd169 1208 {
Anna Bridge 180:96ed750bd169 1209 GICInterface->CTLR &=~1U; //disable distributor
Anna Bridge 180:96ed750bd169 1210 }
Anna Bridge 180:96ed750bd169 1211
Anna Bridge 180:96ed750bd169 1212 /** \brief Read the CPU's IAR register.
Anna Bridge 180:96ed750bd169 1213 * \return GICInterface_Type::IAR
Anna Bridge 180:96ed750bd169 1214 */
Anna Bridge 180:96ed750bd169 1215 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
Anna Bridge 180:96ed750bd169 1216 {
Anna Bridge 180:96ed750bd169 1217 return (IRQn_Type)(GICInterface->IAR);
Anna Bridge 180:96ed750bd169 1218 }
Anna Bridge 180:96ed750bd169 1219
Anna Bridge 180:96ed750bd169 1220 /** \brief Writes the given interrupt number to the CPU's EOIR register.
Anna Bridge 180:96ed750bd169 1221 * \param [in] IRQn The interrupt to be signaled as finished.
Anna Bridge 180:96ed750bd169 1222 */
Anna Bridge 180:96ed750bd169 1223 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1224 {
Anna Bridge 180:96ed750bd169 1225 GICInterface->EOIR = IRQn;
Anna Bridge 180:96ed750bd169 1226 }
Anna Bridge 180:96ed750bd169 1227
Anna Bridge 180:96ed750bd169 1228 /** \brief Enables the given interrupt using GIC's ISENABLER register.
Anna Bridge 180:96ed750bd169 1229 * \param [in] IRQn The interrupt to be enabled.
Anna Bridge 180:96ed750bd169 1230 */
Anna Bridge 180:96ed750bd169 1231 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1232 {
Anna Bridge 180:96ed750bd169 1233 GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
Anna Bridge 180:96ed750bd169 1234 }
Anna Bridge 180:96ed750bd169 1235
Anna Bridge 180:96ed750bd169 1236 /** \brief Get interrupt enable status using GIC's ISENABLER register.
Anna Bridge 180:96ed750bd169 1237 * \param [in] IRQn The interrupt to be queried.
Anna Bridge 180:96ed750bd169 1238 * \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
Anna Bridge 180:96ed750bd169 1239 */
Anna Bridge 180:96ed750bd169 1240 __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1241 {
Anna Bridge 180:96ed750bd169 1242 return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
Anna Bridge 180:96ed750bd169 1243 }
Anna Bridge 180:96ed750bd169 1244
Anna Bridge 180:96ed750bd169 1245 /** \brief Disables the given interrupt using GIC's ICENABLER register.
Anna Bridge 180:96ed750bd169 1246 * \param [in] IRQn The interrupt to be disabled.
Anna Bridge 180:96ed750bd169 1247 */
Anna Bridge 180:96ed750bd169 1248 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1249 {
Anna Bridge 180:96ed750bd169 1250 GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
Anna Bridge 180:96ed750bd169 1251 }
Anna Bridge 180:96ed750bd169 1252
Anna Bridge 180:96ed750bd169 1253 /** \brief Get interrupt pending status from GIC's ISPENDR register.
Anna Bridge 180:96ed750bd169 1254 * \param [in] IRQn The interrupt to be queried.
Anna Bridge 180:96ed750bd169 1255 * \return 0 - interrupt is not pending, 1 - interrupt is pendig.
Anna Bridge 180:96ed750bd169 1256 */
Anna Bridge 180:96ed750bd169 1257 __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1258 {
Anna Bridge 180:96ed750bd169 1259 uint32_t pend;
Anna Bridge 180:96ed750bd169 1260
Anna Bridge 180:96ed750bd169 1261 if (IRQn >= 16U) {
Anna Bridge 180:96ed750bd169 1262 pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
Anna Bridge 180:96ed750bd169 1263 } else {
Anna Bridge 180:96ed750bd169 1264 // INTID 0-15 Software Generated Interrupt
Anna Bridge 180:96ed750bd169 1265 pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
Anna Bridge 180:96ed750bd169 1266 // No CPU identification offered
Anna Bridge 180:96ed750bd169 1267 if (pend != 0U) {
Anna Bridge 180:96ed750bd169 1268 pend = 1U;
Anna Bridge 180:96ed750bd169 1269 } else {
Anna Bridge 180:96ed750bd169 1270 pend = 0U;
Anna Bridge 180:96ed750bd169 1271 }
Anna Bridge 180:96ed750bd169 1272 }
Anna Bridge 180:96ed750bd169 1273
Anna Bridge 180:96ed750bd169 1274 return (pend);
Anna Bridge 180:96ed750bd169 1275 }
Anna Bridge 180:96ed750bd169 1276
Anna Bridge 180:96ed750bd169 1277 /** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
Anna Bridge 180:96ed750bd169 1278 * \param [in] IRQn The interrupt to be enabled.
Anna Bridge 180:96ed750bd169 1279 */
Anna Bridge 180:96ed750bd169 1280 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1281 {
Anna Bridge 180:96ed750bd169 1282 if (IRQn >= 16U) {
Anna Bridge 180:96ed750bd169 1283 GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
Anna Bridge 180:96ed750bd169 1284 } else {
Anna Bridge 180:96ed750bd169 1285 // INTID 0-15 Software Generated Interrupt
Anna Bridge 180:96ed750bd169 1286 GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
Anna Bridge 180:96ed750bd169 1287 }
Anna Bridge 180:96ed750bd169 1288 }
Anna Bridge 180:96ed750bd169 1289
Anna Bridge 180:96ed750bd169 1290 /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
Anna Bridge 180:96ed750bd169 1291 * \param [in] IRQn The interrupt to be enabled.
Anna Bridge 180:96ed750bd169 1292 */
Anna Bridge 180:96ed750bd169 1293 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1294 {
Anna Bridge 180:96ed750bd169 1295 if (IRQn >= 16U) {
Anna Bridge 180:96ed750bd169 1296 GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
Anna Bridge 180:96ed750bd169 1297 } else {
Anna Bridge 180:96ed750bd169 1298 // INTID 0-15 Software Generated Interrupt
Anna Bridge 180:96ed750bd169 1299 GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
Anna Bridge 180:96ed750bd169 1300 }
Anna Bridge 180:96ed750bd169 1301 }
Anna Bridge 180:96ed750bd169 1302
Anna Bridge 180:96ed750bd169 1303 /** \brief Sets the interrupt configuration using GIC's ICFGR register.
Anna Bridge 180:96ed750bd169 1304 * \param [in] IRQn The interrupt to be configured.
Anna Bridge 180:96ed750bd169 1305 * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
Anna Bridge 180:96ed750bd169 1306 * Bit 1: 0 - level sensitive, 1 - edge triggered
Anna Bridge 180:96ed750bd169 1307 */
Anna Bridge 180:96ed750bd169 1308 __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
Anna Bridge 180:96ed750bd169 1309 {
Anna Bridge 180:96ed750bd169 1310 uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
Anna Bridge 180:96ed750bd169 1311 uint32_t shift = (IRQn % 16U) << 1U;
Anna Bridge 180:96ed750bd169 1312
Anna Bridge 180:96ed750bd169 1313 icfgr &= (~(3U << shift));
Anna Bridge 180:96ed750bd169 1314 icfgr |= ( int_config << shift);
Anna Bridge 180:96ed750bd169 1315
Anna Bridge 180:96ed750bd169 1316 GICDistributor->ICFGR[IRQn / 16U] = icfgr;
Anna Bridge 180:96ed750bd169 1317 }
Anna Bridge 180:96ed750bd169 1318
Anna Bridge 180:96ed750bd169 1319 /** \brief Get the interrupt configuration from the GIC's ICFGR register.
Anna Bridge 180:96ed750bd169 1320 * \param [in] IRQn Interrupt to acquire the configuration for.
Anna Bridge 180:96ed750bd169 1321 * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
Anna Bridge 180:96ed750bd169 1322 * Bit 1: 0 - level sensitive, 1 - edge triggered
Anna Bridge 180:96ed750bd169 1323 */
Anna Bridge 180:96ed750bd169 1324 __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1325 {
Anna Bridge 180:96ed750bd169 1326 return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
Anna Bridge 180:96ed750bd169 1327 }
Anna Bridge 180:96ed750bd169 1328
Anna Bridge 180:96ed750bd169 1329 /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
Anna Bridge 180:96ed750bd169 1330 * \param [in] IRQn The interrupt to be configured.
Anna Bridge 180:96ed750bd169 1331 * \param [in] priority The priority for the interrupt, lower values denote higher priorities.
Anna Bridge 180:96ed750bd169 1332 */
Anna Bridge 180:96ed750bd169 1333 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Anna Bridge 180:96ed750bd169 1334 {
Anna Bridge 180:96ed750bd169 1335 uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
Anna Bridge 180:96ed750bd169 1336 GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
Anna Bridge 180:96ed750bd169 1337 }
Anna Bridge 180:96ed750bd169 1338
Anna Bridge 180:96ed750bd169 1339 /** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
Anna Bridge 180:96ed750bd169 1340 * \param [in] IRQn The interrupt to be queried.
Anna Bridge 180:96ed750bd169 1341 */
Anna Bridge 180:96ed750bd169 1342 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1343 {
Anna Bridge 180:96ed750bd169 1344 return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
Anna Bridge 180:96ed750bd169 1345 }
Anna Bridge 180:96ed750bd169 1346
Anna Bridge 180:96ed750bd169 1347 /** \brief Set the interrupt priority mask using CPU's PMR register.
Anna Bridge 180:96ed750bd169 1348 * \param [in] priority Priority mask to be set.
Anna Bridge 180:96ed750bd169 1349 */
Anna Bridge 180:96ed750bd169 1350 __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
Anna Bridge 180:96ed750bd169 1351 {
Anna Bridge 180:96ed750bd169 1352 GICInterface->PMR = priority & 0xFFUL; //set priority mask
Anna Bridge 180:96ed750bd169 1353 }
Anna Bridge 180:96ed750bd169 1354
Anna Bridge 180:96ed750bd169 1355 /** \brief Read the current interrupt priority mask from CPU's PMR register.
Anna Bridge 180:96ed750bd169 1356 * \result GICInterface_Type::PMR
Anna Bridge 180:96ed750bd169 1357 */
Anna Bridge 180:96ed750bd169 1358 __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
Anna Bridge 180:96ed750bd169 1359 {
Anna Bridge 180:96ed750bd169 1360 return GICInterface->PMR;
Anna Bridge 180:96ed750bd169 1361 }
Anna Bridge 180:96ed750bd169 1362
Anna Bridge 180:96ed750bd169 1363 /** \brief Configures the group priority and subpriority split point using CPU's BPR register.
Anna Bridge 180:96ed750bd169 1364 * \param [in] binary_point Amount of bits used as subpriority.
Anna Bridge 180:96ed750bd169 1365 */
Anna Bridge 180:96ed750bd169 1366 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
Anna Bridge 180:96ed750bd169 1367 {
Anna Bridge 180:96ed750bd169 1368 GICInterface->BPR = binary_point & 7U; //set binary point
Anna Bridge 180:96ed750bd169 1369 }
Anna Bridge 180:96ed750bd169 1370
Anna Bridge 180:96ed750bd169 1371 /** \brief Read the current group priority and subpriority split point from CPU's BPR register.
Anna Bridge 180:96ed750bd169 1372 * \return GICInterface_Type::BPR
Anna Bridge 180:96ed750bd169 1373 */
Anna Bridge 180:96ed750bd169 1374 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
Anna Bridge 180:96ed750bd169 1375 {
Anna Bridge 180:96ed750bd169 1376 return GICInterface->BPR;
Anna Bridge 180:96ed750bd169 1377 }
Anna Bridge 180:96ed750bd169 1378
Anna Bridge 180:96ed750bd169 1379 /** \brief Get the status for a given interrupt.
Anna Bridge 180:96ed750bd169 1380 * \param [in] IRQn The interrupt to get status for.
Anna Bridge 180:96ed750bd169 1381 * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
Anna Bridge 180:96ed750bd169 1382 */
Anna Bridge 180:96ed750bd169 1383 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1384 {
Anna Bridge 180:96ed750bd169 1385 uint32_t pending, active;
Anna Bridge 180:96ed750bd169 1386
Anna Bridge 180:96ed750bd169 1387 active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
Anna Bridge 180:96ed750bd169 1388 pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
Anna Bridge 180:96ed750bd169 1389
Anna Bridge 180:96ed750bd169 1390 return ((active<<1U) | pending);
Anna Bridge 180:96ed750bd169 1391 }
Anna Bridge 180:96ed750bd169 1392
Anna Bridge 180:96ed750bd169 1393 /** \brief Generate a software interrupt using GIC's SGIR register.
Anna Bridge 180:96ed750bd169 1394 * \param [in] IRQn Software interrupt to be generated.
Anna Bridge 180:96ed750bd169 1395 * \param [in] target_list List of CPUs the software interrupt should be forwarded to.
Anna Bridge 180:96ed750bd169 1396 * \param [in] filter_list Filter to be applied to determine interrupt receivers.
Anna Bridge 180:96ed750bd169 1397 */
Anna Bridge 180:96ed750bd169 1398 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
Anna Bridge 180:96ed750bd169 1399 {
Anna Bridge 180:96ed750bd169 1400 GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
Anna Bridge 180:96ed750bd169 1401 }
Anna Bridge 180:96ed750bd169 1402
Anna Bridge 180:96ed750bd169 1403 /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
Anna Bridge 180:96ed750bd169 1404 * \return GICInterface_Type::HPPIR
Anna Bridge 180:96ed750bd169 1405 */
Anna Bridge 180:96ed750bd169 1406 __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
Anna Bridge 180:96ed750bd169 1407 {
Anna Bridge 180:96ed750bd169 1408 return GICInterface->HPPIR;
Anna Bridge 180:96ed750bd169 1409 }
Anna Bridge 180:96ed750bd169 1410
Anna Bridge 180:96ed750bd169 1411 /** \brief Provides information about the implementer and revision of the CPU interface.
Anna Bridge 180:96ed750bd169 1412 * \return GICInterface_Type::IIDR
Anna Bridge 180:96ed750bd169 1413 */
Anna Bridge 180:96ed750bd169 1414 __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
Anna Bridge 180:96ed750bd169 1415 {
Anna Bridge 180:96ed750bd169 1416 return GICInterface->IIDR;
Anna Bridge 180:96ed750bd169 1417 }
Anna Bridge 180:96ed750bd169 1418
Anna Bridge 180:96ed750bd169 1419 /** \brief Set the interrupt group from the GIC's IGROUPR register.
Anna Bridge 180:96ed750bd169 1420 * \param [in] IRQn The interrupt to be queried.
Anna Bridge 180:96ed750bd169 1421 * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
Anna Bridge 180:96ed750bd169 1422 */
Anna Bridge 180:96ed750bd169 1423 __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
Anna Bridge 180:96ed750bd169 1424 {
Anna Bridge 180:96ed750bd169 1425 uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
Anna Bridge 180:96ed750bd169 1426 uint32_t shift = (IRQn % 32U);
Anna Bridge 180:96ed750bd169 1427
Anna Bridge 180:96ed750bd169 1428 igroupr &= (~(1U << shift));
Anna Bridge 180:96ed750bd169 1429 igroupr |= ( (group & 1U) << shift);
Anna Bridge 180:96ed750bd169 1430
Anna Bridge 180:96ed750bd169 1431 GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
Anna Bridge 180:96ed750bd169 1432 }
Anna Bridge 180:96ed750bd169 1433 #define GIC_SetSecurity GIC_SetGroup
Anna Bridge 180:96ed750bd169 1434
Anna Bridge 180:96ed750bd169 1435 /** \brief Get the interrupt group from the GIC's IGROUPR register.
Anna Bridge 180:96ed750bd169 1436 * \param [in] IRQn The interrupt to be queried.
Anna Bridge 180:96ed750bd169 1437 * \return 0 - Group 0, 1 - Group 1
Anna Bridge 180:96ed750bd169 1438 */
Anna Bridge 180:96ed750bd169 1439 __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
Anna Bridge 180:96ed750bd169 1440 {
Anna Bridge 180:96ed750bd169 1441 return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
Anna Bridge 180:96ed750bd169 1442 }
Anna Bridge 180:96ed750bd169 1443 #define GIC_GetSecurity GIC_GetGroup
Anna Bridge 180:96ed750bd169 1444
Anna Bridge 180:96ed750bd169 1445 /** \brief Initialize the interrupt distributor.
Anna Bridge 180:96ed750bd169 1446 */
Anna Bridge 180:96ed750bd169 1447 __STATIC_INLINE void GIC_DistInit(void)
Anna Bridge 180:96ed750bd169 1448 {
Anna Bridge 180:96ed750bd169 1449 uint32_t i;
Anna Bridge 180:96ed750bd169 1450 uint32_t num_irq = 0U;
Anna Bridge 180:96ed750bd169 1451 uint32_t priority_field;
Anna Bridge 180:96ed750bd169 1452
Anna Bridge 180:96ed750bd169 1453 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
Anna Bridge 180:96ed750bd169 1454 //configuring all of the interrupts as Secure.
Anna Bridge 180:96ed750bd169 1455
Anna Bridge 180:96ed750bd169 1456 //Disable interrupt forwarding
Anna Bridge 180:96ed750bd169 1457 GIC_DisableDistributor();
Anna Bridge 180:96ed750bd169 1458 //Get the maximum number of interrupts that the GIC supports
Anna Bridge 180:96ed750bd169 1459 num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
Anna Bridge 180:96ed750bd169 1460
Anna Bridge 180:96ed750bd169 1461 /* Priority level is implementation defined.
Anna Bridge 180:96ed750bd169 1462 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
Anna Bridge 180:96ed750bd169 1463 priority field and read back the value stored.*/
Anna Bridge 180:96ed750bd169 1464 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
Anna Bridge 180:96ed750bd169 1465 priority_field = GIC_GetPriority((IRQn_Type)0U);
Anna Bridge 180:96ed750bd169 1466
Anna Bridge 180:96ed750bd169 1467 for (i = 32U; i < num_irq; i++)
Anna Bridge 180:96ed750bd169 1468 {
Anna Bridge 180:96ed750bd169 1469 //Disable the SPI interrupt
Anna Bridge 180:96ed750bd169 1470 GIC_DisableIRQ((IRQn_Type)i);
Anna Bridge 180:96ed750bd169 1471 //Set level-sensitive (and N-N model)
Anna Bridge 180:96ed750bd169 1472 GIC_SetConfiguration((IRQn_Type)i, 0U);
Anna Bridge 180:96ed750bd169 1473 //Set priority
Anna Bridge 180:96ed750bd169 1474 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
Anna Bridge 180:96ed750bd169 1475 //Set target list to CPU0
Anna Bridge 180:96ed750bd169 1476 GIC_SetTarget((IRQn_Type)i, 1U);
Anna Bridge 180:96ed750bd169 1477 }
Anna Bridge 180:96ed750bd169 1478 //Enable distributor
Anna Bridge 180:96ed750bd169 1479 GIC_EnableDistributor();
Anna Bridge 180:96ed750bd169 1480 }
Anna Bridge 180:96ed750bd169 1481
Anna Bridge 180:96ed750bd169 1482 /** \brief Initialize the CPU's interrupt interface
Anna Bridge 180:96ed750bd169 1483 */
Anna Bridge 180:96ed750bd169 1484 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
Anna Bridge 180:96ed750bd169 1485 {
Anna Bridge 180:96ed750bd169 1486 uint32_t i;
Anna Bridge 180:96ed750bd169 1487 uint32_t priority_field;
Anna Bridge 180:96ed750bd169 1488
Anna Bridge 180:96ed750bd169 1489 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
Anna Bridge 180:96ed750bd169 1490 //configuring all of the interrupts as Secure.
Anna Bridge 180:96ed750bd169 1491
Anna Bridge 180:96ed750bd169 1492 //Disable interrupt forwarding
Anna Bridge 180:96ed750bd169 1493 GIC_DisableInterface();
Anna Bridge 180:96ed750bd169 1494
Anna Bridge 180:96ed750bd169 1495 /* Priority level is implementation defined.
Anna Bridge 180:96ed750bd169 1496 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
Anna Bridge 180:96ed750bd169 1497 priority field and read back the value stored.*/
Anna Bridge 180:96ed750bd169 1498 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
Anna Bridge 180:96ed750bd169 1499 priority_field = GIC_GetPriority((IRQn_Type)0U);
Anna Bridge 180:96ed750bd169 1500
Anna Bridge 180:96ed750bd169 1501 //SGI and PPI
Anna Bridge 180:96ed750bd169 1502 for (i = 0U; i < 32U; i++)
Anna Bridge 180:96ed750bd169 1503 {
Anna Bridge 180:96ed750bd169 1504 if(i > 15U) {
Anna Bridge 180:96ed750bd169 1505 //Set level-sensitive (and N-N model) for PPI
Anna Bridge 180:96ed750bd169 1506 GIC_SetConfiguration((IRQn_Type)i, 0U);
Anna Bridge 180:96ed750bd169 1507 }
Anna Bridge 180:96ed750bd169 1508 //Disable SGI and PPI interrupts
Anna Bridge 180:96ed750bd169 1509 GIC_DisableIRQ((IRQn_Type)i);
Anna Bridge 180:96ed750bd169 1510 //Set priority
Anna Bridge 180:96ed750bd169 1511 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
Anna Bridge 180:96ed750bd169 1512 }
Anna Bridge 180:96ed750bd169 1513 //Enable interface
Anna Bridge 180:96ed750bd169 1514 GIC_EnableInterface();
Anna Bridge 180:96ed750bd169 1515 //Set binary point to 0
Anna Bridge 180:96ed750bd169 1516 GIC_SetBinaryPoint(0U);
Anna Bridge 180:96ed750bd169 1517 //Set priority mask
Anna Bridge 180:96ed750bd169 1518 GIC_SetInterfacePriorityMask(0xFFU);
Anna Bridge 180:96ed750bd169 1519 }
Anna Bridge 180:96ed750bd169 1520
Anna Bridge 180:96ed750bd169 1521 /** \brief Initialize and enable the GIC
Anna Bridge 180:96ed750bd169 1522 */
Anna Bridge 180:96ed750bd169 1523 __STATIC_INLINE void GIC_Enable(void)
Anna Bridge 180:96ed750bd169 1524 {
Anna Bridge 180:96ed750bd169 1525 GIC_DistInit();
Anna Bridge 180:96ed750bd169 1526 GIC_CPUInterfaceInit(); //per CPU
Anna Bridge 180:96ed750bd169 1527 }
Anna Bridge 180:96ed750bd169 1528 #endif
Anna Bridge 180:96ed750bd169 1529
Anna Bridge 180:96ed750bd169 1530 /* ########################## Generic Timer functions ############################ */
Anna Bridge 180:96ed750bd169 1531 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 1532
Anna Bridge 180:96ed750bd169 1533 /* PL1 Physical Timer */
Anna Bridge 180:96ed750bd169 1534 #if (__CORTEX_A == 7U) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 1535
Anna Bridge 180:96ed750bd169 1536 /** \brief Physical Timer Control register */
Anna Bridge 180:96ed750bd169 1537 typedef union
Anna Bridge 180:96ed750bd169 1538 {
Anna Bridge 180:96ed750bd169 1539 struct
Anna Bridge 180:96ed750bd169 1540 {
Anna Bridge 180:96ed750bd169 1541 uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
Anna Bridge 180:96ed750bd169 1542 uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
Anna Bridge 180:96ed750bd169 1543 uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
Anna Bridge 180:96ed750bd169 1544 RESERVED(0:29, uint32_t)
Anna Bridge 180:96ed750bd169 1545 } b; /*!< \brief Structure used for bit access */
Anna Bridge 180:96ed750bd169 1546 uint32_t w; /*!< \brief Type used for word access */
Anna Bridge 180:96ed750bd169 1547 } CNTP_CTL_Type;
Anna Bridge 180:96ed750bd169 1548
Anna Bridge 180:96ed750bd169 1549 /** \brief Configures the frequency the timer shall run at.
Anna Bridge 180:96ed750bd169 1550 * \param [in] value The timer frequency in Hz.
Anna Bridge 180:96ed750bd169 1551 */
Anna Bridge 180:96ed750bd169 1552 __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
Anna Bridge 180:96ed750bd169 1553 {
Anna Bridge 180:96ed750bd169 1554 __set_CNTFRQ(value);
Anna Bridge 180:96ed750bd169 1555 __ISB();
Anna Bridge 180:96ed750bd169 1556 }
Anna Bridge 180:96ed750bd169 1557
Anna Bridge 180:96ed750bd169 1558 /** \brief Sets the reset value of the timer.
Anna Bridge 180:96ed750bd169 1559 * \param [in] value The value the timer is loaded with.
Anna Bridge 180:96ed750bd169 1560 */
Anna Bridge 180:96ed750bd169 1561 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
Anna Bridge 180:96ed750bd169 1562 {
Anna Bridge 180:96ed750bd169 1563 __set_CNTP_TVAL(value);
Anna Bridge 180:96ed750bd169 1564 __ISB();
Anna Bridge 180:96ed750bd169 1565 }
Anna Bridge 180:96ed750bd169 1566
Anna Bridge 180:96ed750bd169 1567 /** \brief Get the current counter value.
Anna Bridge 180:96ed750bd169 1568 * \return Current counter value.
Anna Bridge 180:96ed750bd169 1569 */
Anna Bridge 180:96ed750bd169 1570 __STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
Anna Bridge 180:96ed750bd169 1571 {
Anna Bridge 180:96ed750bd169 1572 return(__get_CNTP_TVAL());
Anna Bridge 180:96ed750bd169 1573 }
Anna Bridge 180:96ed750bd169 1574
Anna Bridge 180:96ed750bd169 1575 /** \brief Get the current physical counter value.
Anna Bridge 180:96ed750bd169 1576 * \return Current physical counter value.
Anna Bridge 180:96ed750bd169 1577 */
Anna Bridge 180:96ed750bd169 1578 __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
Anna Bridge 180:96ed750bd169 1579 {
Anna Bridge 180:96ed750bd169 1580 return(__get_CNTPCT());
Anna Bridge 180:96ed750bd169 1581 }
Anna Bridge 180:96ed750bd169 1582
Anna Bridge 180:96ed750bd169 1583 /** \brief Set the physical compare value.
Anna Bridge 180:96ed750bd169 1584 * \param [in] value New physical timer compare value.
Anna Bridge 180:96ed750bd169 1585 */
Anna Bridge 180:96ed750bd169 1586 __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
Anna Bridge 180:96ed750bd169 1587 {
Anna Bridge 180:96ed750bd169 1588 __set_CNTP_CVAL(value);
Anna Bridge 180:96ed750bd169 1589 __ISB();
Anna Bridge 180:96ed750bd169 1590 }
Anna Bridge 180:96ed750bd169 1591
Anna Bridge 180:96ed750bd169 1592 /** \brief Get the physical compare value.
Anna Bridge 180:96ed750bd169 1593 * \return Physical compare value.
Anna Bridge 180:96ed750bd169 1594 */
Anna Bridge 180:96ed750bd169 1595 __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
Anna Bridge 180:96ed750bd169 1596 {
Anna Bridge 180:96ed750bd169 1597 return(__get_CNTP_CVAL());
Anna Bridge 180:96ed750bd169 1598 }
Anna Bridge 180:96ed750bd169 1599
Anna Bridge 180:96ed750bd169 1600 /** \brief Configure the timer by setting the control value.
Anna Bridge 180:96ed750bd169 1601 * \param [in] value New timer control value.
Anna Bridge 180:96ed750bd169 1602 */
Anna Bridge 180:96ed750bd169 1603 __STATIC_INLINE void PL1_SetControl(uint32_t value)
Anna Bridge 180:96ed750bd169 1604 {
Anna Bridge 180:96ed750bd169 1605 __set_CNTP_CTL(value);
Anna Bridge 180:96ed750bd169 1606 __ISB();
Anna Bridge 180:96ed750bd169 1607 }
Anna Bridge 180:96ed750bd169 1608
Anna Bridge 180:96ed750bd169 1609 /** \brief Get the control value.
Anna Bridge 180:96ed750bd169 1610 * \return Control value.
Anna Bridge 180:96ed750bd169 1611 */
Anna Bridge 180:96ed750bd169 1612 __STATIC_INLINE uint32_t PL1_GetControl(void)
Anna Bridge 180:96ed750bd169 1613 {
Anna Bridge 180:96ed750bd169 1614 return(__get_CNTP_CTL());
Anna Bridge 180:96ed750bd169 1615 }
Anna Bridge 180:96ed750bd169 1616 #endif
Anna Bridge 180:96ed750bd169 1617
Anna Bridge 180:96ed750bd169 1618 /* Private Timer */
Anna Bridge 180:96ed750bd169 1619 #if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)
Anna Bridge 180:96ed750bd169 1620 /** \brief Set the load value to timers LOAD register.
Anna Bridge 180:96ed750bd169 1621 * \param [in] value The load value to be set.
Anna Bridge 180:96ed750bd169 1622 */
Anna Bridge 180:96ed750bd169 1623 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
Anna Bridge 180:96ed750bd169 1624 {
Anna Bridge 180:96ed750bd169 1625 PTIM->LOAD = value;
Anna Bridge 180:96ed750bd169 1626 }
Anna Bridge 180:96ed750bd169 1627
Anna Bridge 180:96ed750bd169 1628 /** \brief Get the load value from timers LOAD register.
Anna Bridge 180:96ed750bd169 1629 * \return Timer_Type::LOAD
Anna Bridge 180:96ed750bd169 1630 */
Anna Bridge 180:96ed750bd169 1631 __STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
Anna Bridge 180:96ed750bd169 1632 {
Anna Bridge 180:96ed750bd169 1633 return(PTIM->LOAD);
Anna Bridge 180:96ed750bd169 1634 }
Anna Bridge 180:96ed750bd169 1635
Anna Bridge 180:96ed750bd169 1636 /** \brief Set current counter value from its COUNTER register.
Anna Bridge 180:96ed750bd169 1637 */
Anna Bridge 180:96ed750bd169 1638 __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
Anna Bridge 180:96ed750bd169 1639 {
Anna Bridge 180:96ed750bd169 1640 PTIM->COUNTER = value;
Anna Bridge 180:96ed750bd169 1641 }
Anna Bridge 180:96ed750bd169 1642
Anna Bridge 180:96ed750bd169 1643 /** \brief Get current counter value from timers COUNTER register.
Anna Bridge 180:96ed750bd169 1644 * \result Timer_Type::COUNTER
Anna Bridge 180:96ed750bd169 1645 */
Anna Bridge 180:96ed750bd169 1646 __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
Anna Bridge 180:96ed750bd169 1647 {
Anna Bridge 180:96ed750bd169 1648 return(PTIM->COUNTER);
Anna Bridge 180:96ed750bd169 1649 }
Anna Bridge 180:96ed750bd169 1650
Anna Bridge 180:96ed750bd169 1651 /** \brief Configure the timer using its CONTROL register.
Anna Bridge 180:96ed750bd169 1652 * \param [in] value The new configuration value to be set.
Anna Bridge 180:96ed750bd169 1653 */
Anna Bridge 180:96ed750bd169 1654 __STATIC_INLINE void PTIM_SetControl(uint32_t value)
Anna Bridge 180:96ed750bd169 1655 {
Anna Bridge 180:96ed750bd169 1656 PTIM->CONTROL = value;
Anna Bridge 180:96ed750bd169 1657 }
Anna Bridge 180:96ed750bd169 1658
Anna Bridge 180:96ed750bd169 1659 /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
Anna Bridge 180:96ed750bd169 1660 * \return Timer_Type::CONTROL
Anna Bridge 180:96ed750bd169 1661 */
Anna Bridge 180:96ed750bd169 1662 __STATIC_INLINE uint32_t PTIM_GetControl(void)
Anna Bridge 180:96ed750bd169 1663 {
Anna Bridge 180:96ed750bd169 1664 return(PTIM->CONTROL);
Anna Bridge 180:96ed750bd169 1665 }
Anna Bridge 180:96ed750bd169 1666
Anna Bridge 180:96ed750bd169 1667 /** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
Anna Bridge 180:96ed750bd169 1668 * \return 0 - flag is not set, 1- flag is set
Anna Bridge 180:96ed750bd169 1669 */
Anna Bridge 180:96ed750bd169 1670 __STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
Anna Bridge 180:96ed750bd169 1671 {
Anna Bridge 180:96ed750bd169 1672 return (PTIM->ISR & 1UL);
Anna Bridge 180:96ed750bd169 1673 }
Anna Bridge 180:96ed750bd169 1674
Anna Bridge 180:96ed750bd169 1675 /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
Anna Bridge 180:96ed750bd169 1676 */
Anna Bridge 180:96ed750bd169 1677 __STATIC_INLINE void PTIM_ClearEventFlag(void)
Anna Bridge 180:96ed750bd169 1678 {
Anna Bridge 180:96ed750bd169 1679 PTIM->ISR = 1;
Anna Bridge 180:96ed750bd169 1680 }
Anna Bridge 180:96ed750bd169 1681 #endif
Anna Bridge 180:96ed750bd169 1682 #endif
Anna Bridge 180:96ed750bd169 1683
Anna Bridge 180:96ed750bd169 1684 /* ########################## MMU functions ###################################### */
Anna Bridge 180:96ed750bd169 1685
Anna Bridge 180:96ed750bd169 1686 #define SECTION_DESCRIPTOR (0x2)
Anna Bridge 180:96ed750bd169 1687 #define SECTION_MASK (0xFFFFFFFC)
Anna Bridge 180:96ed750bd169 1688
Anna Bridge 180:96ed750bd169 1689 #define SECTION_TEXCB_MASK (0xFFFF8FF3)
Anna Bridge 180:96ed750bd169 1690 #define SECTION_B_SHIFT (2)
Anna Bridge 180:96ed750bd169 1691 #define SECTION_C_SHIFT (3)
Anna Bridge 180:96ed750bd169 1692 #define SECTION_TEX0_SHIFT (12)
Anna Bridge 180:96ed750bd169 1693 #define SECTION_TEX1_SHIFT (13)
Anna Bridge 180:96ed750bd169 1694 #define SECTION_TEX2_SHIFT (14)
Anna Bridge 180:96ed750bd169 1695
Anna Bridge 180:96ed750bd169 1696 #define SECTION_XN_MASK (0xFFFFFFEF)
Anna Bridge 180:96ed750bd169 1697 #define SECTION_XN_SHIFT (4)
Anna Bridge 180:96ed750bd169 1698
Anna Bridge 180:96ed750bd169 1699 #define SECTION_DOMAIN_MASK (0xFFFFFE1F)
Anna Bridge 180:96ed750bd169 1700 #define SECTION_DOMAIN_SHIFT (5)
Anna Bridge 180:96ed750bd169 1701
Anna Bridge 180:96ed750bd169 1702 #define SECTION_P_MASK (0xFFFFFDFF)
Anna Bridge 180:96ed750bd169 1703 #define SECTION_P_SHIFT (9)
Anna Bridge 180:96ed750bd169 1704
Anna Bridge 180:96ed750bd169 1705 #define SECTION_AP_MASK (0xFFFF73FF)
Anna Bridge 180:96ed750bd169 1706 #define SECTION_AP_SHIFT (10)
Anna Bridge 180:96ed750bd169 1707 #define SECTION_AP2_SHIFT (15)
Anna Bridge 180:96ed750bd169 1708
Anna Bridge 180:96ed750bd169 1709 #define SECTION_S_MASK (0xFFFEFFFF)
Anna Bridge 180:96ed750bd169 1710 #define SECTION_S_SHIFT (16)
Anna Bridge 180:96ed750bd169 1711
Anna Bridge 180:96ed750bd169 1712 #define SECTION_NG_MASK (0xFFFDFFFF)
Anna Bridge 180:96ed750bd169 1713 #define SECTION_NG_SHIFT (17)
Anna Bridge 180:96ed750bd169 1714
Anna Bridge 180:96ed750bd169 1715 #define SECTION_NS_MASK (0xFFF7FFFF)
Anna Bridge 180:96ed750bd169 1716 #define SECTION_NS_SHIFT (19)
Anna Bridge 180:96ed750bd169 1717
Anna Bridge 180:96ed750bd169 1718 #define PAGE_L1_DESCRIPTOR (0x1)
Anna Bridge 180:96ed750bd169 1719 #define PAGE_L1_MASK (0xFFFFFFFC)
Anna Bridge 180:96ed750bd169 1720
Anna Bridge 180:96ed750bd169 1721 #define PAGE_L2_4K_DESC (0x2)
Anna Bridge 180:96ed750bd169 1722 #define PAGE_L2_4K_MASK (0xFFFFFFFD)
Anna Bridge 180:96ed750bd169 1723
Anna Bridge 180:96ed750bd169 1724 #define PAGE_L2_64K_DESC (0x1)
Anna Bridge 180:96ed750bd169 1725 #define PAGE_L2_64K_MASK (0xFFFFFFFC)
Anna Bridge 180:96ed750bd169 1726
Anna Bridge 180:96ed750bd169 1727 #define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
Anna Bridge 180:96ed750bd169 1728 #define PAGE_4K_B_SHIFT (2)
Anna Bridge 180:96ed750bd169 1729 #define PAGE_4K_C_SHIFT (3)
Anna Bridge 180:96ed750bd169 1730 #define PAGE_4K_TEX0_SHIFT (6)
Anna Bridge 180:96ed750bd169 1731 #define PAGE_4K_TEX1_SHIFT (7)
Anna Bridge 180:96ed750bd169 1732 #define PAGE_4K_TEX2_SHIFT (8)
Anna Bridge 180:96ed750bd169 1733
Anna Bridge 180:96ed750bd169 1734 #define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
Anna Bridge 180:96ed750bd169 1735 #define PAGE_64K_B_SHIFT (2)
Anna Bridge 180:96ed750bd169 1736 #define PAGE_64K_C_SHIFT (3)
Anna Bridge 180:96ed750bd169 1737 #define PAGE_64K_TEX0_SHIFT (12)
Anna Bridge 180:96ed750bd169 1738 #define PAGE_64K_TEX1_SHIFT (13)
Anna Bridge 180:96ed750bd169 1739 #define PAGE_64K_TEX2_SHIFT (14)
Anna Bridge 180:96ed750bd169 1740
Anna Bridge 180:96ed750bd169 1741 #define PAGE_TEXCB_MASK (0xFFFF8FF3)
Anna Bridge 180:96ed750bd169 1742 #define PAGE_B_SHIFT (2)
Anna Bridge 180:96ed750bd169 1743 #define PAGE_C_SHIFT (3)
Anna Bridge 180:96ed750bd169 1744 #define PAGE_TEX_SHIFT (12)
Anna Bridge 180:96ed750bd169 1745
Anna Bridge 180:96ed750bd169 1746 #define PAGE_XN_4K_MASK (0xFFFFFFFE)
Anna Bridge 180:96ed750bd169 1747 #define PAGE_XN_4K_SHIFT (0)
Anna Bridge 180:96ed750bd169 1748 #define PAGE_XN_64K_MASK (0xFFFF7FFF)
Anna Bridge 180:96ed750bd169 1749 #define PAGE_XN_64K_SHIFT (15)
Anna Bridge 180:96ed750bd169 1750
Anna Bridge 180:96ed750bd169 1751 #define PAGE_DOMAIN_MASK (0xFFFFFE1F)
Anna Bridge 180:96ed750bd169 1752 #define PAGE_DOMAIN_SHIFT (5)
Anna Bridge 180:96ed750bd169 1753
Anna Bridge 180:96ed750bd169 1754 #define PAGE_P_MASK (0xFFFFFDFF)
Anna Bridge 180:96ed750bd169 1755 #define PAGE_P_SHIFT (9)
Anna Bridge 180:96ed750bd169 1756
Anna Bridge 180:96ed750bd169 1757 #define PAGE_AP_MASK (0xFFFFFDCF)
Anna Bridge 180:96ed750bd169 1758 #define PAGE_AP_SHIFT (4)
Anna Bridge 180:96ed750bd169 1759 #define PAGE_AP2_SHIFT (9)
Anna Bridge 180:96ed750bd169 1760
Anna Bridge 180:96ed750bd169 1761 #define PAGE_S_MASK (0xFFFFFBFF)
Anna Bridge 180:96ed750bd169 1762 #define PAGE_S_SHIFT (10)
Anna Bridge 180:96ed750bd169 1763
Anna Bridge 180:96ed750bd169 1764 #define PAGE_NG_MASK (0xFFFFF7FF)
Anna Bridge 180:96ed750bd169 1765 #define PAGE_NG_SHIFT (11)
Anna Bridge 180:96ed750bd169 1766
Anna Bridge 180:96ed750bd169 1767 #define PAGE_NS_MASK (0xFFFFFFF7)
Anna Bridge 180:96ed750bd169 1768 #define PAGE_NS_SHIFT (3)
Anna Bridge 180:96ed750bd169 1769
Anna Bridge 180:96ed750bd169 1770 #define OFFSET_1M (0x00100000)
Anna Bridge 180:96ed750bd169 1771 #define OFFSET_64K (0x00010000)
Anna Bridge 180:96ed750bd169 1772 #define OFFSET_4K (0x00001000)
Anna Bridge 180:96ed750bd169 1773
Anna Bridge 180:96ed750bd169 1774 #define DESCRIPTOR_FAULT (0x00000000)
Anna Bridge 180:96ed750bd169 1775
Anna Bridge 180:96ed750bd169 1776 /* Attributes enumerations */
Anna Bridge 180:96ed750bd169 1777
Anna Bridge 180:96ed750bd169 1778 /* Region size attributes */
Anna Bridge 180:96ed750bd169 1779 typedef enum
Anna Bridge 180:96ed750bd169 1780 {
Anna Bridge 180:96ed750bd169 1781 SECTION,
Anna Bridge 180:96ed750bd169 1782 PAGE_4k,
Anna Bridge 180:96ed750bd169 1783 PAGE_64k,
Anna Bridge 180:96ed750bd169 1784 } mmu_region_size_Type;
Anna Bridge 180:96ed750bd169 1785
Anna Bridge 180:96ed750bd169 1786 /* Region type attributes */
Anna Bridge 180:96ed750bd169 1787 typedef enum
Anna Bridge 180:96ed750bd169 1788 {
Anna Bridge 180:96ed750bd169 1789 NORMAL,
Anna Bridge 180:96ed750bd169 1790 DEVICE,
Anna Bridge 180:96ed750bd169 1791 SHARED_DEVICE,
Anna Bridge 180:96ed750bd169 1792 NON_SHARED_DEVICE,
Anna Bridge 180:96ed750bd169 1793 STRONGLY_ORDERED
Anna Bridge 180:96ed750bd169 1794 } mmu_memory_Type;
Anna Bridge 180:96ed750bd169 1795
Anna Bridge 180:96ed750bd169 1796 /* Region cacheability attributes */
Anna Bridge 180:96ed750bd169 1797 typedef enum
Anna Bridge 180:96ed750bd169 1798 {
Anna Bridge 180:96ed750bd169 1799 NON_CACHEABLE,
Anna Bridge 180:96ed750bd169 1800 WB_WA,
Anna Bridge 180:96ed750bd169 1801 WT,
Anna Bridge 180:96ed750bd169 1802 WB_NO_WA,
Anna Bridge 180:96ed750bd169 1803 } mmu_cacheability_Type;
Anna Bridge 180:96ed750bd169 1804
Anna Bridge 180:96ed750bd169 1805 /* Region parity check attributes */
Anna Bridge 180:96ed750bd169 1806 typedef enum
Anna Bridge 180:96ed750bd169 1807 {
Anna Bridge 180:96ed750bd169 1808 ECC_DISABLED,
Anna Bridge 180:96ed750bd169 1809 ECC_ENABLED,
Anna Bridge 180:96ed750bd169 1810 } mmu_ecc_check_Type;
Anna Bridge 180:96ed750bd169 1811
Anna Bridge 180:96ed750bd169 1812 /* Region execution attributes */
Anna Bridge 180:96ed750bd169 1813 typedef enum
Anna Bridge 180:96ed750bd169 1814 {
Anna Bridge 180:96ed750bd169 1815 EXECUTE,
Anna Bridge 180:96ed750bd169 1816 NON_EXECUTE,
Anna Bridge 180:96ed750bd169 1817 } mmu_execute_Type;
Anna Bridge 180:96ed750bd169 1818
Anna Bridge 180:96ed750bd169 1819 /* Region global attributes */
Anna Bridge 180:96ed750bd169 1820 typedef enum
Anna Bridge 180:96ed750bd169 1821 {
Anna Bridge 180:96ed750bd169 1822 GLOBAL,
Anna Bridge 180:96ed750bd169 1823 NON_GLOBAL,
Anna Bridge 180:96ed750bd169 1824 } mmu_global_Type;
Anna Bridge 180:96ed750bd169 1825
Anna Bridge 180:96ed750bd169 1826 /* Region shareability attributes */
Anna Bridge 180:96ed750bd169 1827 typedef enum
Anna Bridge 180:96ed750bd169 1828 {
Anna Bridge 180:96ed750bd169 1829 NON_SHARED,
Anna Bridge 180:96ed750bd169 1830 SHARED,
Anna Bridge 180:96ed750bd169 1831 } mmu_shared_Type;
Anna Bridge 180:96ed750bd169 1832
Anna Bridge 180:96ed750bd169 1833 /* Region security attributes */
Anna Bridge 180:96ed750bd169 1834 typedef enum
Anna Bridge 180:96ed750bd169 1835 {
Anna Bridge 180:96ed750bd169 1836 SECURE,
Anna Bridge 180:96ed750bd169 1837 NON_SECURE,
Anna Bridge 180:96ed750bd169 1838 } mmu_secure_Type;
Anna Bridge 180:96ed750bd169 1839
Anna Bridge 180:96ed750bd169 1840 /* Region access attributes */
Anna Bridge 180:96ed750bd169 1841 typedef enum
Anna Bridge 180:96ed750bd169 1842 {
Anna Bridge 180:96ed750bd169 1843 NO_ACCESS,
Anna Bridge 180:96ed750bd169 1844 RW,
Anna Bridge 180:96ed750bd169 1845 READ,
Anna Bridge 180:96ed750bd169 1846 } mmu_access_Type;
Anna Bridge 180:96ed750bd169 1847
Anna Bridge 180:96ed750bd169 1848 /* Memory Region definition */
Anna Bridge 180:96ed750bd169 1849 typedef struct RegionStruct {
Anna Bridge 180:96ed750bd169 1850 mmu_region_size_Type rg_t;
Anna Bridge 180:96ed750bd169 1851 mmu_memory_Type mem_t;
Anna Bridge 180:96ed750bd169 1852 uint8_t domain;
Anna Bridge 180:96ed750bd169 1853 mmu_cacheability_Type inner_norm_t;
Anna Bridge 180:96ed750bd169 1854 mmu_cacheability_Type outer_norm_t;
Anna Bridge 180:96ed750bd169 1855 mmu_ecc_check_Type e_t;
Anna Bridge 180:96ed750bd169 1856 mmu_execute_Type xn_t;
Anna Bridge 180:96ed750bd169 1857 mmu_global_Type g_t;
Anna Bridge 180:96ed750bd169 1858 mmu_secure_Type sec_t;
Anna Bridge 180:96ed750bd169 1859 mmu_access_Type priv_t;
Anna Bridge 180:96ed750bd169 1860 mmu_access_Type user_t;
Anna Bridge 180:96ed750bd169 1861 mmu_shared_Type sh_t;
Anna Bridge 180:96ed750bd169 1862
Anna Bridge 180:96ed750bd169 1863 } mmu_region_attributes_Type;
Anna Bridge 180:96ed750bd169 1864
Anna Bridge 180:96ed750bd169 1865 //Following macros define the descriptors and attributes
Anna Bridge 180:96ed750bd169 1866 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
Anna Bridge 180:96ed750bd169 1867 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1868 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1869 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1870 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1871 region.inner_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1872 region.outer_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1873 region.mem_t = NORMAL; \
Anna Bridge 180:96ed750bd169 1874 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1875 region.xn_t = EXECUTE; \
Anna Bridge 180:96ed750bd169 1876 region.priv_t = RW; \
Anna Bridge 180:96ed750bd169 1877 region.user_t = RW; \
Anna Bridge 180:96ed750bd169 1878 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1879 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1880
Anna Bridge 180:96ed750bd169 1881 //Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
Anna Bridge 180:96ed750bd169 1882 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1883 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1884 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1885 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1886 region.inner_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1887 region.outer_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1888 region.mem_t = NORMAL; \
Anna Bridge 180:96ed750bd169 1889 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1890 region.xn_t = EXECUTE; \
Anna Bridge 180:96ed750bd169 1891 region.priv_t = RW; \
Anna Bridge 180:96ed750bd169 1892 region.user_t = RW; \
Anna Bridge 180:96ed750bd169 1893 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1894 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1895
Anna Bridge 180:96ed750bd169 1896 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
Anna Bridge 180:96ed750bd169 1897 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1898 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1899 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1900 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1901 region.inner_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1902 region.outer_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1903 region.mem_t = NORMAL; \
Anna Bridge 180:96ed750bd169 1904 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1905 region.xn_t = EXECUTE; \
Anna Bridge 180:96ed750bd169 1906 region.priv_t = READ; \
Anna Bridge 180:96ed750bd169 1907 region.user_t = READ; \
Anna Bridge 180:96ed750bd169 1908 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1909 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1910
Anna Bridge 180:96ed750bd169 1911 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
Anna Bridge 180:96ed750bd169 1912 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1913 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1914 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1915 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1916 region.inner_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1917 region.outer_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1918 region.mem_t = NORMAL; \
Anna Bridge 180:96ed750bd169 1919 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1920 region.xn_t = NON_EXECUTE; \
Anna Bridge 180:96ed750bd169 1921 region.priv_t = READ; \
Anna Bridge 180:96ed750bd169 1922 region.user_t = READ; \
Anna Bridge 180:96ed750bd169 1923 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1924 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1925
Anna Bridge 180:96ed750bd169 1926 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
Anna Bridge 180:96ed750bd169 1927 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1928 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1929 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1930 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1931 region.inner_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1932 region.outer_norm_t = WB_WA; \
Anna Bridge 180:96ed750bd169 1933 region.mem_t = NORMAL; \
Anna Bridge 180:96ed750bd169 1934 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1935 region.xn_t = NON_EXECUTE; \
Anna Bridge 180:96ed750bd169 1936 region.priv_t = RW; \
Anna Bridge 180:96ed750bd169 1937 region.user_t = RW; \
Anna Bridge 180:96ed750bd169 1938 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1939 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1940 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
Anna Bridge 180:96ed750bd169 1941 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1942 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1943 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1944 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1945 region.inner_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1946 region.outer_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1947 region.mem_t = STRONGLY_ORDERED; \
Anna Bridge 180:96ed750bd169 1948 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1949 region.xn_t = NON_EXECUTE; \
Anna Bridge 180:96ed750bd169 1950 region.priv_t = RW; \
Anna Bridge 180:96ed750bd169 1951 region.user_t = RW; \
Anna Bridge 180:96ed750bd169 1952 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1953 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1954
Anna Bridge 180:96ed750bd169 1955 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
Anna Bridge 180:96ed750bd169 1956 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1957 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1958 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1959 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1960 region.inner_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1961 region.outer_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1962 region.mem_t = STRONGLY_ORDERED; \
Anna Bridge 180:96ed750bd169 1963 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1964 region.xn_t = NON_EXECUTE; \
Anna Bridge 180:96ed750bd169 1965 region.priv_t = READ; \
Anna Bridge 180:96ed750bd169 1966 region.user_t = READ; \
Anna Bridge 180:96ed750bd169 1967 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1968 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1969
Anna Bridge 180:96ed750bd169 1970 //Sect_Device_RW. Sect_Device_RO, but writeable
Anna Bridge 180:96ed750bd169 1971 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
Anna Bridge 180:96ed750bd169 1972 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1973 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1974 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1975 region.inner_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1976 region.outer_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1977 region.mem_t = STRONGLY_ORDERED; \
Anna Bridge 180:96ed750bd169 1978 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1979 region.xn_t = NON_EXECUTE; \
Anna Bridge 180:96ed750bd169 1980 region.priv_t = RW; \
Anna Bridge 180:96ed750bd169 1981 region.user_t = RW; \
Anna Bridge 180:96ed750bd169 1982 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1983 MMU_GetSectionDescriptor(&descriptor_l1, region);
Anna Bridge 180:96ed750bd169 1984 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
Anna Bridge 180:96ed750bd169 1985 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
Anna Bridge 180:96ed750bd169 1986 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 1987 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 1988 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 1989 region.inner_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1990 region.outer_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 1991 region.mem_t = SHARED_DEVICE; \
Anna Bridge 180:96ed750bd169 1992 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 1993 region.xn_t = NON_EXECUTE; \
Anna Bridge 180:96ed750bd169 1994 region.priv_t = RW; \
Anna Bridge 180:96ed750bd169 1995 region.user_t = RW; \
Anna Bridge 180:96ed750bd169 1996 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 1997 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
Anna Bridge 180:96ed750bd169 1998
Anna Bridge 180:96ed750bd169 1999 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
Anna Bridge 180:96ed750bd169 2000 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
Anna Bridge 180:96ed750bd169 2001 region.domain = 0x0; \
Anna Bridge 180:96ed750bd169 2002 region.e_t = ECC_DISABLED; \
Anna Bridge 180:96ed750bd169 2003 region.g_t = GLOBAL; \
Anna Bridge 180:96ed750bd169 2004 region.inner_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 2005 region.outer_norm_t = NON_CACHEABLE; \
Anna Bridge 180:96ed750bd169 2006 region.mem_t = SHARED_DEVICE; \
Anna Bridge 180:96ed750bd169 2007 region.sec_t = SECURE; \
Anna Bridge 180:96ed750bd169 2008 region.xn_t = NON_EXECUTE; \
Anna Bridge 180:96ed750bd169 2009 region.priv_t = RW; \
Anna Bridge 180:96ed750bd169 2010 region.user_t = RW; \
Anna Bridge 180:96ed750bd169 2011 region.sh_t = NON_SHARED; \
Anna Bridge 180:96ed750bd169 2012 MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
Anna Bridge 180:96ed750bd169 2013
Anna Bridge 180:96ed750bd169 2014 /** \brief Set section execution-never attribute
Anna Bridge 180:96ed750bd169 2015
Anna Bridge 180:96ed750bd169 2016 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2017 \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
Anna Bridge 180:96ed750bd169 2018
Anna Bridge 180:96ed750bd169 2019 \return 0
Anna Bridge 180:96ed750bd169 2020 */
Anna Bridge 180:96ed750bd169 2021 __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
Anna Bridge 180:96ed750bd169 2022 {
Anna Bridge 180:96ed750bd169 2023 *descriptor_l1 &= SECTION_XN_MASK;
Anna Bridge 180:96ed750bd169 2024 *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
Anna Bridge 180:96ed750bd169 2025 return 0;
Anna Bridge 180:96ed750bd169 2026 }
Anna Bridge 180:96ed750bd169 2027
Anna Bridge 180:96ed750bd169 2028 /** \brief Set section domain
Anna Bridge 180:96ed750bd169 2029
Anna Bridge 180:96ed750bd169 2030 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2031 \param [in] domain Section domain
Anna Bridge 180:96ed750bd169 2032
Anna Bridge 180:96ed750bd169 2033 \return 0
Anna Bridge 180:96ed750bd169 2034 */
Anna Bridge 180:96ed750bd169 2035 __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
Anna Bridge 180:96ed750bd169 2036 {
Anna Bridge 180:96ed750bd169 2037 *descriptor_l1 &= SECTION_DOMAIN_MASK;
Anna Bridge 180:96ed750bd169 2038 *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
Anna Bridge 180:96ed750bd169 2039 return 0;
Anna Bridge 180:96ed750bd169 2040 }
Anna Bridge 180:96ed750bd169 2041
Anna Bridge 180:96ed750bd169 2042 /** \brief Set section parity check
Anna Bridge 180:96ed750bd169 2043
Anna Bridge 180:96ed750bd169 2044 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2045 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
Anna Bridge 180:96ed750bd169 2046
Anna Bridge 180:96ed750bd169 2047 \return 0
Anna Bridge 180:96ed750bd169 2048 */
Anna Bridge 180:96ed750bd169 2049 __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
Anna Bridge 180:96ed750bd169 2050 {
Anna Bridge 180:96ed750bd169 2051 *descriptor_l1 &= SECTION_P_MASK;
Anna Bridge 180:96ed750bd169 2052 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
Anna Bridge 180:96ed750bd169 2053 return 0;
Anna Bridge 180:96ed750bd169 2054 }
Anna Bridge 180:96ed750bd169 2055
Anna Bridge 180:96ed750bd169 2056 /** \brief Set section access privileges
Anna Bridge 180:96ed750bd169 2057
Anna Bridge 180:96ed750bd169 2058 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2059 \param [in] user User Level Access: NO_ACCESS, RW, READ
Anna Bridge 180:96ed750bd169 2060 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
Anna Bridge 180:96ed750bd169 2061 \param [in] afe Access flag enable
Anna Bridge 180:96ed750bd169 2062
Anna Bridge 180:96ed750bd169 2063 \return 0
Anna Bridge 180:96ed750bd169 2064 */
Anna Bridge 180:96ed750bd169 2065 __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
Anna Bridge 180:96ed750bd169 2066 {
Anna Bridge 180:96ed750bd169 2067 uint32_t ap = 0;
Anna Bridge 180:96ed750bd169 2068
Anna Bridge 180:96ed750bd169 2069 if (afe == 0) { //full access
Anna Bridge 180:96ed750bd169 2070 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
Anna Bridge 180:96ed750bd169 2071 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
Anna Bridge 180:96ed750bd169 2072 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
Anna Bridge 180:96ed750bd169 2073 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
Anna Bridge 180:96ed750bd169 2074 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
Anna Bridge 180:96ed750bd169 2075 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
Anna Bridge 180:96ed750bd169 2076 }
Anna Bridge 180:96ed750bd169 2077
Anna Bridge 180:96ed750bd169 2078 else { //Simplified access
Anna Bridge 180:96ed750bd169 2079 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
Anna Bridge 180:96ed750bd169 2080 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
Anna Bridge 180:96ed750bd169 2081 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
Anna Bridge 180:96ed750bd169 2082 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
Anna Bridge 180:96ed750bd169 2083 }
Anna Bridge 180:96ed750bd169 2084
Anna Bridge 180:96ed750bd169 2085 *descriptor_l1 &= SECTION_AP_MASK;
Anna Bridge 180:96ed750bd169 2086 *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
Anna Bridge 180:96ed750bd169 2087 *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
Anna Bridge 180:96ed750bd169 2088
Anna Bridge 180:96ed750bd169 2089 return 0;
Anna Bridge 180:96ed750bd169 2090 }
Anna Bridge 180:96ed750bd169 2091
Anna Bridge 180:96ed750bd169 2092 /** \brief Set section shareability
Anna Bridge 180:96ed750bd169 2093
Anna Bridge 180:96ed750bd169 2094 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2095 \param [in] s_bit Section shareability: NON_SHARED, SHARED
Anna Bridge 180:96ed750bd169 2096
Anna Bridge 180:96ed750bd169 2097 \return 0
Anna Bridge 180:96ed750bd169 2098 */
Anna Bridge 180:96ed750bd169 2099 __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
Anna Bridge 180:96ed750bd169 2100 {
Anna Bridge 180:96ed750bd169 2101 *descriptor_l1 &= SECTION_S_MASK;
Anna Bridge 180:96ed750bd169 2102 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
Anna Bridge 180:96ed750bd169 2103 return 0;
Anna Bridge 180:96ed750bd169 2104 }
Anna Bridge 180:96ed750bd169 2105
Anna Bridge 180:96ed750bd169 2106 /** \brief Set section Global attribute
Anna Bridge 180:96ed750bd169 2107
Anna Bridge 180:96ed750bd169 2108 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2109 \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
Anna Bridge 180:96ed750bd169 2110
Anna Bridge 180:96ed750bd169 2111 \return 0
Anna Bridge 180:96ed750bd169 2112 */
Anna Bridge 180:96ed750bd169 2113 __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
Anna Bridge 180:96ed750bd169 2114 {
Anna Bridge 180:96ed750bd169 2115 *descriptor_l1 &= SECTION_NG_MASK;
Anna Bridge 180:96ed750bd169 2116 *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
Anna Bridge 180:96ed750bd169 2117 return 0;
Anna Bridge 180:96ed750bd169 2118 }
Anna Bridge 180:96ed750bd169 2119
Anna Bridge 180:96ed750bd169 2120 /** \brief Set section Security attribute
Anna Bridge 180:96ed750bd169 2121
Anna Bridge 180:96ed750bd169 2122 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2123 \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
Anna Bridge 180:96ed750bd169 2124
Anna Bridge 180:96ed750bd169 2125 \return 0
Anna Bridge 180:96ed750bd169 2126 */
Anna Bridge 180:96ed750bd169 2127 __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
Anna Bridge 180:96ed750bd169 2128 {
Anna Bridge 180:96ed750bd169 2129 *descriptor_l1 &= SECTION_NS_MASK;
Anna Bridge 180:96ed750bd169 2130 *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
Anna Bridge 180:96ed750bd169 2131 return 0;
Anna Bridge 180:96ed750bd169 2132 }
Anna Bridge 180:96ed750bd169 2133
Anna Bridge 180:96ed750bd169 2134 /* Page 4k or 64k */
Anna Bridge 180:96ed750bd169 2135 /** \brief Set 4k/64k page execution-never attribute
Anna Bridge 180:96ed750bd169 2136
Anna Bridge 180:96ed750bd169 2137 \param [out] descriptor_l2 L2 descriptor.
Anna Bridge 180:96ed750bd169 2138 \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
Anna Bridge 180:96ed750bd169 2139 \param [in] page Page size: PAGE_4k, PAGE_64k,
Anna Bridge 180:96ed750bd169 2140
Anna Bridge 180:96ed750bd169 2141 \return 0
Anna Bridge 180:96ed750bd169 2142 */
Anna Bridge 180:96ed750bd169 2143 __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
Anna Bridge 180:96ed750bd169 2144 {
Anna Bridge 180:96ed750bd169 2145 if (page == PAGE_4k)
Anna Bridge 180:96ed750bd169 2146 {
Anna Bridge 180:96ed750bd169 2147 *descriptor_l2 &= PAGE_XN_4K_MASK;
Anna Bridge 180:96ed750bd169 2148 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
Anna Bridge 180:96ed750bd169 2149 }
Anna Bridge 180:96ed750bd169 2150 else
Anna Bridge 180:96ed750bd169 2151 {
Anna Bridge 180:96ed750bd169 2152 *descriptor_l2 &= PAGE_XN_64K_MASK;
Anna Bridge 180:96ed750bd169 2153 *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
Anna Bridge 180:96ed750bd169 2154 }
Anna Bridge 180:96ed750bd169 2155 return 0;
Anna Bridge 180:96ed750bd169 2156 }
Anna Bridge 180:96ed750bd169 2157
Anna Bridge 180:96ed750bd169 2158 /** \brief Set 4k/64k page domain
Anna Bridge 180:96ed750bd169 2159
Anna Bridge 180:96ed750bd169 2160 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2161 \param [in] domain Page domain
Anna Bridge 180:96ed750bd169 2162
Anna Bridge 180:96ed750bd169 2163 \return 0
Anna Bridge 180:96ed750bd169 2164 */
Anna Bridge 180:96ed750bd169 2165 __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
Anna Bridge 180:96ed750bd169 2166 {
Anna Bridge 180:96ed750bd169 2167 *descriptor_l1 &= PAGE_DOMAIN_MASK;
Anna Bridge 180:96ed750bd169 2168 *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
Anna Bridge 180:96ed750bd169 2169 return 0;
Anna Bridge 180:96ed750bd169 2170 }
Anna Bridge 180:96ed750bd169 2171
Anna Bridge 180:96ed750bd169 2172 /** \brief Set 4k/64k page parity check
Anna Bridge 180:96ed750bd169 2173
Anna Bridge 180:96ed750bd169 2174 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2175 \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
Anna Bridge 180:96ed750bd169 2176
Anna Bridge 180:96ed750bd169 2177 \return 0
Anna Bridge 180:96ed750bd169 2178 */
Anna Bridge 180:96ed750bd169 2179 __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
Anna Bridge 180:96ed750bd169 2180 {
Anna Bridge 180:96ed750bd169 2181 *descriptor_l1 &= SECTION_P_MASK;
Anna Bridge 180:96ed750bd169 2182 *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
Anna Bridge 180:96ed750bd169 2183 return 0;
Anna Bridge 180:96ed750bd169 2184 }
Anna Bridge 180:96ed750bd169 2185
Anna Bridge 180:96ed750bd169 2186 /** \brief Set 4k/64k page access privileges
Anna Bridge 180:96ed750bd169 2187
Anna Bridge 180:96ed750bd169 2188 \param [out] descriptor_l2 L2 descriptor.
Anna Bridge 180:96ed750bd169 2189 \param [in] user User Level Access: NO_ACCESS, RW, READ
Anna Bridge 180:96ed750bd169 2190 \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
Anna Bridge 180:96ed750bd169 2191 \param [in] afe Access flag enable
Anna Bridge 180:96ed750bd169 2192
Anna Bridge 180:96ed750bd169 2193 \return 0
Anna Bridge 180:96ed750bd169 2194 */
Anna Bridge 180:96ed750bd169 2195 __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
Anna Bridge 180:96ed750bd169 2196 {
Anna Bridge 180:96ed750bd169 2197 uint32_t ap = 0;
Anna Bridge 180:96ed750bd169 2198
Anna Bridge 180:96ed750bd169 2199 if (afe == 0) { //full access
Anna Bridge 180:96ed750bd169 2200 if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
Anna Bridge 180:96ed750bd169 2201 else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
Anna Bridge 180:96ed750bd169 2202 else if ((priv == RW) && (user == READ)) { ap = 0x2; }
Anna Bridge 180:96ed750bd169 2203 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
Anna Bridge 180:96ed750bd169 2204 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
Anna Bridge 180:96ed750bd169 2205 else if ((priv == READ) && (user == READ)) { ap = 0x6; }
Anna Bridge 180:96ed750bd169 2206 }
Anna Bridge 180:96ed750bd169 2207
Anna Bridge 180:96ed750bd169 2208 else { //Simplified access
Anna Bridge 180:96ed750bd169 2209 if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
Anna Bridge 180:96ed750bd169 2210 else if ((priv == RW) && (user == RW)) { ap = 0x3; }
Anna Bridge 180:96ed750bd169 2211 else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
Anna Bridge 180:96ed750bd169 2212 else if ((priv == READ) && (user == READ)) { ap = 0x7; }
Anna Bridge 180:96ed750bd169 2213 }
Anna Bridge 180:96ed750bd169 2214
Anna Bridge 180:96ed750bd169 2215 *descriptor_l2 &= PAGE_AP_MASK;
Anna Bridge 180:96ed750bd169 2216 *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
Anna Bridge 180:96ed750bd169 2217 *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
Anna Bridge 180:96ed750bd169 2218
Anna Bridge 180:96ed750bd169 2219 return 0;
Anna Bridge 180:96ed750bd169 2220 }
Anna Bridge 180:96ed750bd169 2221
Anna Bridge 180:96ed750bd169 2222 /** \brief Set 4k/64k page shareability
Anna Bridge 180:96ed750bd169 2223
Anna Bridge 180:96ed750bd169 2224 \param [out] descriptor_l2 L2 descriptor.
Anna Bridge 180:96ed750bd169 2225 \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
Anna Bridge 180:96ed750bd169 2226
Anna Bridge 180:96ed750bd169 2227 \return 0
Anna Bridge 180:96ed750bd169 2228 */
Anna Bridge 180:96ed750bd169 2229 __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
Anna Bridge 180:96ed750bd169 2230 {
Anna Bridge 180:96ed750bd169 2231 *descriptor_l2 &= PAGE_S_MASK;
Anna Bridge 180:96ed750bd169 2232 *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
Anna Bridge 180:96ed750bd169 2233 return 0;
Anna Bridge 180:96ed750bd169 2234 }
Anna Bridge 180:96ed750bd169 2235
Anna Bridge 180:96ed750bd169 2236 /** \brief Set 4k/64k page Global attribute
Anna Bridge 180:96ed750bd169 2237
Anna Bridge 180:96ed750bd169 2238 \param [out] descriptor_l2 L2 descriptor.
Anna Bridge 180:96ed750bd169 2239 \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
Anna Bridge 180:96ed750bd169 2240
Anna Bridge 180:96ed750bd169 2241 \return 0
Anna Bridge 180:96ed750bd169 2242 */
Anna Bridge 180:96ed750bd169 2243 __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
Anna Bridge 180:96ed750bd169 2244 {
Anna Bridge 180:96ed750bd169 2245 *descriptor_l2 &= PAGE_NG_MASK;
Anna Bridge 180:96ed750bd169 2246 *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
Anna Bridge 180:96ed750bd169 2247 return 0;
Anna Bridge 180:96ed750bd169 2248 }
Anna Bridge 180:96ed750bd169 2249
Anna Bridge 180:96ed750bd169 2250 /** \brief Set 4k/64k page Security attribute
Anna Bridge 180:96ed750bd169 2251
Anna Bridge 180:96ed750bd169 2252 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2253 \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
Anna Bridge 180:96ed750bd169 2254
Anna Bridge 180:96ed750bd169 2255 \return 0
Anna Bridge 180:96ed750bd169 2256 */
Anna Bridge 180:96ed750bd169 2257 __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
Anna Bridge 180:96ed750bd169 2258 {
Anna Bridge 180:96ed750bd169 2259 *descriptor_l1 &= PAGE_NS_MASK;
Anna Bridge 180:96ed750bd169 2260 *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
Anna Bridge 180:96ed750bd169 2261 return 0;
Anna Bridge 180:96ed750bd169 2262 }
Anna Bridge 180:96ed750bd169 2263
Anna Bridge 180:96ed750bd169 2264 /** \brief Set Section memory attributes
Anna Bridge 180:96ed750bd169 2265
Anna Bridge 180:96ed750bd169 2266 \param [out] descriptor_l1 L1 descriptor.
Anna Bridge 180:96ed750bd169 2267 \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
Anna Bridge 180:96ed750bd169 2268 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
Anna Bridge 180:96ed750bd169 2269 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
Anna Bridge 180:96ed750bd169 2270
Anna Bridge 180:96ed750bd169 2271 \return 0
Anna Bridge 180:96ed750bd169 2272 */
Anna Bridge 180:96ed750bd169 2273 __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
Anna Bridge 180:96ed750bd169 2274 {
Anna Bridge 180:96ed750bd169 2275 *descriptor_l1 &= SECTION_TEXCB_MASK;
Anna Bridge 180:96ed750bd169 2276
Anna Bridge 180:96ed750bd169 2277 if (STRONGLY_ORDERED == mem)
Anna Bridge 180:96ed750bd169 2278 {
Anna Bridge 180:96ed750bd169 2279 return 0;
Anna Bridge 180:96ed750bd169 2280 }
Anna Bridge 180:96ed750bd169 2281 else if (SHARED_DEVICE == mem)
Anna Bridge 180:96ed750bd169 2282 {
Anna Bridge 180:96ed750bd169 2283 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
Anna Bridge 180:96ed750bd169 2284 }
Anna Bridge 180:96ed750bd169 2285 else if (NON_SHARED_DEVICE == mem)
Anna Bridge 180:96ed750bd169 2286 {
Anna Bridge 180:96ed750bd169 2287 *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
Anna Bridge 180:96ed750bd169 2288 }
Anna Bridge 180:96ed750bd169 2289 else if (NORMAL == mem)
Anna Bridge 180:96ed750bd169 2290 {
Anna Bridge 180:96ed750bd169 2291 *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
Anna Bridge 180:96ed750bd169 2292 switch(inner)
Anna Bridge 180:96ed750bd169 2293 {
Anna Bridge 180:96ed750bd169 2294 case NON_CACHEABLE:
Anna Bridge 180:96ed750bd169 2295 break;
Anna Bridge 180:96ed750bd169 2296 case WB_WA:
Anna Bridge 180:96ed750bd169 2297 *descriptor_l1 |= (1 << SECTION_B_SHIFT);
Anna Bridge 180:96ed750bd169 2298 break;
Anna Bridge 180:96ed750bd169 2299 case WT:
Anna Bridge 180:96ed750bd169 2300 *descriptor_l1 |= 1 << SECTION_C_SHIFT;
Anna Bridge 180:96ed750bd169 2301 break;
Anna Bridge 180:96ed750bd169 2302 case WB_NO_WA:
Anna Bridge 180:96ed750bd169 2303 *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
Anna Bridge 180:96ed750bd169 2304 break;
Anna Bridge 180:96ed750bd169 2305 }
Anna Bridge 180:96ed750bd169 2306 switch(outer)
Anna Bridge 180:96ed750bd169 2307 {
Anna Bridge 180:96ed750bd169 2308 case NON_CACHEABLE:
Anna Bridge 180:96ed750bd169 2309 break;
Anna Bridge 180:96ed750bd169 2310 case WB_WA:
Anna Bridge 180:96ed750bd169 2311 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
Anna Bridge 180:96ed750bd169 2312 break;
Anna Bridge 180:96ed750bd169 2313 case WT:
Anna Bridge 180:96ed750bd169 2314 *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
Anna Bridge 180:96ed750bd169 2315 break;
Anna Bridge 180:96ed750bd169 2316 case WB_NO_WA:
Anna Bridge 180:96ed750bd169 2317 *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
Anna Bridge 180:96ed750bd169 2318 break;
Anna Bridge 180:96ed750bd169 2319 }
Anna Bridge 180:96ed750bd169 2320 }
Anna Bridge 180:96ed750bd169 2321 return 0;
Anna Bridge 180:96ed750bd169 2322 }
Anna Bridge 180:96ed750bd169 2323
Anna Bridge 180:96ed750bd169 2324 /** \brief Set 4k/64k page memory attributes
Anna Bridge 180:96ed750bd169 2325
Anna Bridge 180:96ed750bd169 2326 \param [out] descriptor_l2 L2 descriptor.
Anna Bridge 180:96ed750bd169 2327 \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
Anna Bridge 180:96ed750bd169 2328 \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
Anna Bridge 180:96ed750bd169 2329 \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
Anna Bridge 180:96ed750bd169 2330 \param [in] page Page size
Anna Bridge 180:96ed750bd169 2331
Anna Bridge 180:96ed750bd169 2332 \return 0
Anna Bridge 180:96ed750bd169 2333 */
Anna Bridge 180:96ed750bd169 2334 __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
Anna Bridge 180:96ed750bd169 2335 {
Anna Bridge 180:96ed750bd169 2336 *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
Anna Bridge 180:96ed750bd169 2337
Anna Bridge 180:96ed750bd169 2338 if (page == PAGE_64k)
Anna Bridge 180:96ed750bd169 2339 {
Anna Bridge 180:96ed750bd169 2340 //same as section
Anna Bridge 180:96ed750bd169 2341 MMU_MemorySection(descriptor_l2, mem, outer, inner);
Anna Bridge 180:96ed750bd169 2342 }
Anna Bridge 180:96ed750bd169 2343 else
Anna Bridge 180:96ed750bd169 2344 {
Anna Bridge 180:96ed750bd169 2345 if (STRONGLY_ORDERED == mem)
Anna Bridge 180:96ed750bd169 2346 {
Anna Bridge 180:96ed750bd169 2347 return 0;
Anna Bridge 180:96ed750bd169 2348 }
Anna Bridge 180:96ed750bd169 2349 else if (SHARED_DEVICE == mem)
Anna Bridge 180:96ed750bd169 2350 {
Anna Bridge 180:96ed750bd169 2351 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
Anna Bridge 180:96ed750bd169 2352 }
Anna Bridge 180:96ed750bd169 2353 else if (NON_SHARED_DEVICE == mem)
Anna Bridge 180:96ed750bd169 2354 {
Anna Bridge 180:96ed750bd169 2355 *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
Anna Bridge 180:96ed750bd169 2356 }
Anna Bridge 180:96ed750bd169 2357 else if (NORMAL == mem)
Anna Bridge 180:96ed750bd169 2358 {
Anna Bridge 180:96ed750bd169 2359 *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
Anna Bridge 180:96ed750bd169 2360 switch(inner)
Anna Bridge 180:96ed750bd169 2361 {
Anna Bridge 180:96ed750bd169 2362 case NON_CACHEABLE:
Anna Bridge 180:96ed750bd169 2363 break;
Anna Bridge 180:96ed750bd169 2364 case WB_WA:
Anna Bridge 180:96ed750bd169 2365 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
Anna Bridge 180:96ed750bd169 2366 break;
Anna Bridge 180:96ed750bd169 2367 case WT:
Anna Bridge 180:96ed750bd169 2368 *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
Anna Bridge 180:96ed750bd169 2369 break;
Anna Bridge 180:96ed750bd169 2370 case WB_NO_WA:
Anna Bridge 180:96ed750bd169 2371 *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
Anna Bridge 180:96ed750bd169 2372 break;
Anna Bridge 180:96ed750bd169 2373 }
Anna Bridge 180:96ed750bd169 2374 switch(outer)
Anna Bridge 180:96ed750bd169 2375 {
Anna Bridge 180:96ed750bd169 2376 case NON_CACHEABLE:
Anna Bridge 180:96ed750bd169 2377 break;
Anna Bridge 180:96ed750bd169 2378 case WB_WA:
Anna Bridge 180:96ed750bd169 2379 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
Anna Bridge 180:96ed750bd169 2380 break;
Anna Bridge 180:96ed750bd169 2381 case WT:
Anna Bridge 180:96ed750bd169 2382 *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
Anna Bridge 180:96ed750bd169 2383 break;
Anna Bridge 180:96ed750bd169 2384 case WB_NO_WA:
Anna Bridge 180:96ed750bd169 2385 *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
Anna Bridge 180:96ed750bd169 2386 break;
Anna Bridge 180:96ed750bd169 2387 }
Anna Bridge 180:96ed750bd169 2388 }
Anna Bridge 180:96ed750bd169 2389 }
Anna Bridge 180:96ed750bd169 2390
Anna Bridge 180:96ed750bd169 2391 return 0;
Anna Bridge 180:96ed750bd169 2392 }
Anna Bridge 180:96ed750bd169 2393
Anna Bridge 180:96ed750bd169 2394 /** \brief Create a L1 section descriptor
Anna Bridge 180:96ed750bd169 2395
Anna Bridge 180:96ed750bd169 2396 \param [out] descriptor L1 descriptor
Anna Bridge 180:96ed750bd169 2397 \param [in] reg Section attributes
Anna Bridge 180:96ed750bd169 2398
Anna Bridge 180:96ed750bd169 2399 \return 0
Anna Bridge 180:96ed750bd169 2400 */
Anna Bridge 180:96ed750bd169 2401 __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
Anna Bridge 180:96ed750bd169 2402 {
Anna Bridge 180:96ed750bd169 2403 *descriptor = 0;
Anna Bridge 180:96ed750bd169 2404
Anna Bridge 180:96ed750bd169 2405 MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
Anna Bridge 180:96ed750bd169 2406 MMU_XNSection(descriptor,reg.xn_t);
Anna Bridge 180:96ed750bd169 2407 MMU_DomainSection(descriptor, reg.domain);
Anna Bridge 180:96ed750bd169 2408 MMU_PSection(descriptor, reg.e_t);
Anna Bridge 180:96ed750bd169 2409 MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
Anna Bridge 180:96ed750bd169 2410 MMU_SharedSection(descriptor,reg.sh_t);
Anna Bridge 180:96ed750bd169 2411 MMU_GlobalSection(descriptor,reg.g_t);
Anna Bridge 180:96ed750bd169 2412 MMU_SecureSection(descriptor,reg.sec_t);
Anna Bridge 180:96ed750bd169 2413 *descriptor &= SECTION_MASK;
Anna Bridge 180:96ed750bd169 2414 *descriptor |= SECTION_DESCRIPTOR;
Anna Bridge 180:96ed750bd169 2415
Anna Bridge 180:96ed750bd169 2416 return 0;
Anna Bridge 180:96ed750bd169 2417 }
Anna Bridge 180:96ed750bd169 2418
Anna Bridge 180:96ed750bd169 2419
Anna Bridge 180:96ed750bd169 2420 /** \brief Create a L1 and L2 4k/64k page descriptor
Anna Bridge 180:96ed750bd169 2421
Anna Bridge 180:96ed750bd169 2422 \param [out] descriptor L1 descriptor
Anna Bridge 180:96ed750bd169 2423 \param [out] descriptor2 L2 descriptor
Anna Bridge 180:96ed750bd169 2424 \param [in] reg 4k/64k page attributes
Anna Bridge 180:96ed750bd169 2425
Anna Bridge 180:96ed750bd169 2426 \return 0
Anna Bridge 180:96ed750bd169 2427 */
Anna Bridge 180:96ed750bd169 2428 __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
Anna Bridge 180:96ed750bd169 2429 {
Anna Bridge 180:96ed750bd169 2430 *descriptor = 0;
Anna Bridge 180:96ed750bd169 2431 *descriptor2 = 0;
Anna Bridge 180:96ed750bd169 2432
Anna Bridge 180:96ed750bd169 2433 switch (reg.rg_t)
Anna Bridge 180:96ed750bd169 2434 {
Anna Bridge 180:96ed750bd169 2435 case PAGE_4k:
Anna Bridge 180:96ed750bd169 2436 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
Anna Bridge 180:96ed750bd169 2437 MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
Anna Bridge 180:96ed750bd169 2438 MMU_DomainPage(descriptor, reg.domain);
Anna Bridge 180:96ed750bd169 2439 MMU_PPage(descriptor, reg.e_t);
Anna Bridge 180:96ed750bd169 2440 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
Anna Bridge 180:96ed750bd169 2441 MMU_SharedPage(descriptor2,reg.sh_t);
Anna Bridge 180:96ed750bd169 2442 MMU_GlobalPage(descriptor2,reg.g_t);
Anna Bridge 180:96ed750bd169 2443 MMU_SecurePage(descriptor,reg.sec_t);
Anna Bridge 180:96ed750bd169 2444 *descriptor &= PAGE_L1_MASK;
Anna Bridge 180:96ed750bd169 2445 *descriptor |= PAGE_L1_DESCRIPTOR;
Anna Bridge 180:96ed750bd169 2446 *descriptor2 &= PAGE_L2_4K_MASK;
Anna Bridge 180:96ed750bd169 2447 *descriptor2 |= PAGE_L2_4K_DESC;
Anna Bridge 180:96ed750bd169 2448 break;
Anna Bridge 180:96ed750bd169 2449
Anna Bridge 180:96ed750bd169 2450 case PAGE_64k:
Anna Bridge 180:96ed750bd169 2451 MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
Anna Bridge 180:96ed750bd169 2452 MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
Anna Bridge 180:96ed750bd169 2453 MMU_DomainPage(descriptor, reg.domain);
Anna Bridge 180:96ed750bd169 2454 MMU_PPage(descriptor, reg.e_t);
Anna Bridge 180:96ed750bd169 2455 MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
Anna Bridge 180:96ed750bd169 2456 MMU_SharedPage(descriptor2,reg.sh_t);
Anna Bridge 180:96ed750bd169 2457 MMU_GlobalPage(descriptor2,reg.g_t);
Anna Bridge 180:96ed750bd169 2458 MMU_SecurePage(descriptor,reg.sec_t);
Anna Bridge 180:96ed750bd169 2459 *descriptor &= PAGE_L1_MASK;
Anna Bridge 180:96ed750bd169 2460 *descriptor |= PAGE_L1_DESCRIPTOR;
Anna Bridge 180:96ed750bd169 2461 *descriptor2 &= PAGE_L2_64K_MASK;
Anna Bridge 180:96ed750bd169 2462 *descriptor2 |= PAGE_L2_64K_DESC;
Anna Bridge 180:96ed750bd169 2463 break;
Anna Bridge 180:96ed750bd169 2464
Anna Bridge 180:96ed750bd169 2465 case SECTION:
Anna Bridge 180:96ed750bd169 2466 //error
Anna Bridge 180:96ed750bd169 2467 break;
Anna Bridge 180:96ed750bd169 2468 }
Anna Bridge 180:96ed750bd169 2469
Anna Bridge 180:96ed750bd169 2470 return 0;
Anna Bridge 180:96ed750bd169 2471 }
Anna Bridge 180:96ed750bd169 2472
Anna Bridge 180:96ed750bd169 2473 /** \brief Create a 1MB Section
Anna Bridge 180:96ed750bd169 2474
Anna Bridge 180:96ed750bd169 2475 \param [in] ttb Translation table base address
Anna Bridge 180:96ed750bd169 2476 \param [in] base_address Section base address
Anna Bridge 180:96ed750bd169 2477 \param [in] count Number of sections to create
Anna Bridge 180:96ed750bd169 2478 \param [in] descriptor_l1 L1 descriptor (region attributes)
Anna Bridge 180:96ed750bd169 2479
Anna Bridge 180:96ed750bd169 2480 */
Anna Bridge 180:96ed750bd169 2481 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
Anna Bridge 180:96ed750bd169 2482 {
Anna Bridge 180:96ed750bd169 2483 uint32_t offset;
Anna Bridge 180:96ed750bd169 2484 uint32_t entry;
Anna Bridge 180:96ed750bd169 2485 uint32_t i;
Anna Bridge 180:96ed750bd169 2486
Anna Bridge 180:96ed750bd169 2487 offset = base_address >> 20;
Anna Bridge 180:96ed750bd169 2488 entry = (base_address & 0xFFF00000) | descriptor_l1;
Anna Bridge 180:96ed750bd169 2489
Anna Bridge 180:96ed750bd169 2490 //4 bytes aligned
Anna Bridge 180:96ed750bd169 2491 ttb = ttb + offset;
Anna Bridge 180:96ed750bd169 2492
Anna Bridge 180:96ed750bd169 2493 for (i = 0; i < count; i++ )
Anna Bridge 180:96ed750bd169 2494 {
Anna Bridge 180:96ed750bd169 2495 //4 bytes aligned
Anna Bridge 180:96ed750bd169 2496 *ttb++ = entry;
Anna Bridge 180:96ed750bd169 2497 entry += OFFSET_1M;
Anna Bridge 180:96ed750bd169 2498 }
Anna Bridge 180:96ed750bd169 2499 }
Anna Bridge 180:96ed750bd169 2500
Anna Bridge 180:96ed750bd169 2501 /** \brief Create a 4k page entry
Anna Bridge 180:96ed750bd169 2502
Anna Bridge 180:96ed750bd169 2503 \param [in] ttb L1 table base address
Anna Bridge 180:96ed750bd169 2504 \param [in] base_address 4k base address
Anna Bridge 180:96ed750bd169 2505 \param [in] count Number of 4k pages to create
Anna Bridge 180:96ed750bd169 2506 \param [in] descriptor_l1 L1 descriptor (region attributes)
Anna Bridge 180:96ed750bd169 2507 \param [in] ttb_l2 L2 table base address
Anna Bridge 180:96ed750bd169 2508 \param [in] descriptor_l2 L2 descriptor (region attributes)
Anna Bridge 180:96ed750bd169 2509
Anna Bridge 180:96ed750bd169 2510 */
Anna Bridge 180:96ed750bd169 2511 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
Anna Bridge 180:96ed750bd169 2512 {
Anna Bridge 180:96ed750bd169 2513
Anna Bridge 180:96ed750bd169 2514 uint32_t offset, offset2;
Anna Bridge 180:96ed750bd169 2515 uint32_t entry, entry2;
Anna Bridge 180:96ed750bd169 2516 uint32_t i;
Anna Bridge 180:96ed750bd169 2517
Anna Bridge 180:96ed750bd169 2518 offset = base_address >> 20;
Anna Bridge 180:96ed750bd169 2519 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
Anna Bridge 180:96ed750bd169 2520
Anna Bridge 180:96ed750bd169 2521 //4 bytes aligned
Anna Bridge 180:96ed750bd169 2522 ttb += offset;
Anna Bridge 180:96ed750bd169 2523 //create l1_entry
Anna Bridge 180:96ed750bd169 2524 *ttb = entry;
Anna Bridge 180:96ed750bd169 2525
Anna Bridge 180:96ed750bd169 2526 offset2 = (base_address & 0xff000) >> 12;
Anna Bridge 180:96ed750bd169 2527 ttb_l2 += offset2;
Anna Bridge 180:96ed750bd169 2528 entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
Anna Bridge 180:96ed750bd169 2529 for (i = 0; i < count; i++ )
Anna Bridge 180:96ed750bd169 2530 {
Anna Bridge 180:96ed750bd169 2531 //4 bytes aligned
Anna Bridge 180:96ed750bd169 2532 *ttb_l2++ = entry2;
Anna Bridge 180:96ed750bd169 2533 entry2 += OFFSET_4K;
Anna Bridge 180:96ed750bd169 2534 }
Anna Bridge 180:96ed750bd169 2535 }
Anna Bridge 180:96ed750bd169 2536
Anna Bridge 180:96ed750bd169 2537 /** \brief Create a 64k page entry
Anna Bridge 180:96ed750bd169 2538
Anna Bridge 180:96ed750bd169 2539 \param [in] ttb L1 table base address
Anna Bridge 180:96ed750bd169 2540 \param [in] base_address 64k base address
Anna Bridge 180:96ed750bd169 2541 \param [in] count Number of 64k pages to create
Anna Bridge 180:96ed750bd169 2542 \param [in] descriptor_l1 L1 descriptor (region attributes)
Anna Bridge 180:96ed750bd169 2543 \param [in] ttb_l2 L2 table base address
Anna Bridge 180:96ed750bd169 2544 \param [in] descriptor_l2 L2 descriptor (region attributes)
Anna Bridge 180:96ed750bd169 2545
Anna Bridge 180:96ed750bd169 2546 */
Anna Bridge 180:96ed750bd169 2547 __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
Anna Bridge 180:96ed750bd169 2548 {
Anna Bridge 180:96ed750bd169 2549 uint32_t offset, offset2;
Anna Bridge 180:96ed750bd169 2550 uint32_t entry, entry2;
Anna Bridge 180:96ed750bd169 2551 uint32_t i,j;
Anna Bridge 180:96ed750bd169 2552
Anna Bridge 180:96ed750bd169 2553
Anna Bridge 180:96ed750bd169 2554 offset = base_address >> 20;
Anna Bridge 180:96ed750bd169 2555 entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
Anna Bridge 180:96ed750bd169 2556
Anna Bridge 180:96ed750bd169 2557 //4 bytes aligned
Anna Bridge 180:96ed750bd169 2558 ttb += offset;
Anna Bridge 180:96ed750bd169 2559 //create l1_entry
Anna Bridge 180:96ed750bd169 2560 *ttb = entry;
Anna Bridge 180:96ed750bd169 2561
Anna Bridge 180:96ed750bd169 2562 offset2 = (base_address & 0xff000) >> 12;
Anna Bridge 180:96ed750bd169 2563 ttb_l2 += offset2;
Anna Bridge 180:96ed750bd169 2564 entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
Anna Bridge 180:96ed750bd169 2565 for (i = 0; i < count; i++ )
Anna Bridge 180:96ed750bd169 2566 {
Anna Bridge 180:96ed750bd169 2567 //create 16 entries
Anna Bridge 180:96ed750bd169 2568 for (j = 0; j < 16; j++)
Anna Bridge 180:96ed750bd169 2569 {
Anna Bridge 180:96ed750bd169 2570 //4 bytes aligned
Anna Bridge 180:96ed750bd169 2571 *ttb_l2++ = entry2;
Anna Bridge 180:96ed750bd169 2572 }
Anna Bridge 180:96ed750bd169 2573 entry2 += OFFSET_64K;
Anna Bridge 180:96ed750bd169 2574 }
Anna Bridge 180:96ed750bd169 2575 }
Anna Bridge 180:96ed750bd169 2576
Anna Bridge 180:96ed750bd169 2577 /** \brief Enable MMU
Anna Bridge 180:96ed750bd169 2578 */
Anna Bridge 180:96ed750bd169 2579 __STATIC_INLINE void MMU_Enable(void)
Anna Bridge 180:96ed750bd169 2580 {
Anna Bridge 180:96ed750bd169 2581 // Set M bit 0 to enable the MMU
Anna Bridge 180:96ed750bd169 2582 // Set AFE bit to enable simplified access permissions model
Anna Bridge 180:96ed750bd169 2583 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Anna Bridge 180:96ed750bd169 2584 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Anna Bridge 180:96ed750bd169 2585 __ISB();
Anna Bridge 180:96ed750bd169 2586 }
Anna Bridge 180:96ed750bd169 2587
Anna Bridge 180:96ed750bd169 2588 /** \brief Disable MMU
Anna Bridge 180:96ed750bd169 2589 */
Anna Bridge 180:96ed750bd169 2590 __STATIC_INLINE void MMU_Disable(void)
Anna Bridge 180:96ed750bd169 2591 {
Anna Bridge 180:96ed750bd169 2592 // Clear M bit 0 to disable the MMU
Anna Bridge 180:96ed750bd169 2593 __set_SCTLR( __get_SCTLR() & ~1);
Anna Bridge 180:96ed750bd169 2594 __ISB();
Anna Bridge 180:96ed750bd169 2595 }
Anna Bridge 180:96ed750bd169 2596
Anna Bridge 180:96ed750bd169 2597 /** \brief Invalidate entire unified TLB
Anna Bridge 180:96ed750bd169 2598 */
Anna Bridge 180:96ed750bd169 2599
Anna Bridge 180:96ed750bd169 2600 __STATIC_INLINE void MMU_InvalidateTLB(void)
Anna Bridge 180:96ed750bd169 2601 {
Anna Bridge 180:96ed750bd169 2602 __set_TLBIALL(0);
Anna Bridge 180:96ed750bd169 2603 __DSB(); //ensure completion of the invalidation
Anna Bridge 180:96ed750bd169 2604 __ISB(); //ensure instruction fetch path sees new state
Anna Bridge 180:96ed750bd169 2605 }
Anna Bridge 180:96ed750bd169 2606
Anna Bridge 180:96ed750bd169 2607
Anna Bridge 180:96ed750bd169 2608 #ifdef __cplusplus
Anna Bridge 180:96ed750bd169 2609 }
Anna Bridge 180:96ed750bd169 2610 #endif
Anna Bridge 180:96ed750bd169 2611
Anna Bridge 180:96ed750bd169 2612 #endif /* __CORE_CA_H_DEPENDANT */
Anna Bridge 180:96ed750bd169 2613
Anna Bridge 180:96ed750bd169 2614 #endif /* __CMSIS_GENERIC */