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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/fsl_sdhc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 189:f392fc9709a3 1 /*
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 189:f392fc9709a3 3 * All rights reserved.
AnnaBridge 189:f392fc9709a3 4 *
AnnaBridge 189:f392fc9709a3 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 6 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 189:f392fc9709a3 9 * of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 189:f392fc9709a3 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 189:f392fc9709a3 13 * other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 14 *
AnnaBridge 189:f392fc9709a3 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 189:f392fc9709a3 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 189:f392fc9709a3 17 * software without specific prior written permission.
AnnaBridge 189:f392fc9709a3 18 *
AnnaBridge 189:f392fc9709a3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 189:f392fc9709a3 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 189:f392fc9709a3 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 22 * DISCLAIMED. IN NO EVENT SL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 189:f392fc9709a3 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 189:f392fc9709a3 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 189:f392fc9709a3 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 189:f392fc9709a3 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 189:f392fc9709a3 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 189:f392fc9709a3 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 29 */
AnnaBridge 189:f392fc9709a3 30 #ifndef _FSL_SDHC_H_
AnnaBridge 189:f392fc9709a3 31 #define _FSL_SDHC_H_
AnnaBridge 189:f392fc9709a3 32
AnnaBridge 189:f392fc9709a3 33 #include "fsl_common.h"
AnnaBridge 189:f392fc9709a3 34
AnnaBridge 189:f392fc9709a3 35 /*!
AnnaBridge 189:f392fc9709a3 36 * @addtogroup sdhc
AnnaBridge 189:f392fc9709a3 37 * @{
AnnaBridge 189:f392fc9709a3 38 */
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 /******************************************************************************
AnnaBridge 189:f392fc9709a3 41 * Definitions.
AnnaBridge 189:f392fc9709a3 42 *****************************************************************************/
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 /*! @name Driver version */
AnnaBridge 189:f392fc9709a3 45 /*@{*/
AnnaBridge 189:f392fc9709a3 46 /*! @brief Driver version 2.1.2. */
AnnaBridge 189:f392fc9709a3 47 #define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 2U))
AnnaBridge 189:f392fc9709a3 48 /*@}*/
AnnaBridge 189:f392fc9709a3 49
AnnaBridge 189:f392fc9709a3 50 /*! @brief Maximum block count can be set one time */
AnnaBridge 189:f392fc9709a3 51 #define SDHC_MAX_BLOCK_COUNT (SDHC_BLKATTR_BLKCNT_MASK >> SDHC_BLKATTR_BLKCNT_SHIFT)
AnnaBridge 189:f392fc9709a3 52
AnnaBridge 189:f392fc9709a3 53 /*! @brief SDHC status */
AnnaBridge 189:f392fc9709a3 54 enum _sdhc_status
AnnaBridge 189:f392fc9709a3 55 {
AnnaBridge 189:f392fc9709a3 56 kStatus_SDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_SDHC, 0U), /*!< Transfer is on-going */
AnnaBridge 189:f392fc9709a3 57 kStatus_SDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_SDHC, 1U), /*!< Set DMA descriptor failed */
AnnaBridge 189:f392fc9709a3 58 kStatus_SDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDHC, 2U), /*!< Send command failed */
AnnaBridge 189:f392fc9709a3 59 kStatus_SDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_SDHC, 3U), /*!< Transfer data failed */
AnnaBridge 189:f392fc9709a3 60 };
AnnaBridge 189:f392fc9709a3 61
AnnaBridge 189:f392fc9709a3 62 /*! @brief Host controller capabilities flag mask */
AnnaBridge 189:f392fc9709a3 63 enum _sdhc_capability_flag
AnnaBridge 189:f392fc9709a3 64 {
AnnaBridge 189:f392fc9709a3 65 kSDHC_SupportAdmaFlag = SDHC_HTCAPBLT_ADMAS_MASK, /*!< Support ADMA */
AnnaBridge 189:f392fc9709a3 66 kSDHC_SupportHighSpeedFlag = SDHC_HTCAPBLT_HSS_MASK, /*!< Support high-speed */
AnnaBridge 189:f392fc9709a3 67 kSDHC_SupportDmaFlag = SDHC_HTCAPBLT_DMAS_MASK, /*!< Support DMA */
AnnaBridge 189:f392fc9709a3 68 kSDHC_SupportSuspendResumeFlag = SDHC_HTCAPBLT_SRS_MASK, /*!< Support suspend/resume */
AnnaBridge 189:f392fc9709a3 69 kSDHC_SupportV330Flag = SDHC_HTCAPBLT_VS33_MASK, /*!< Support voltage 3.3V */
AnnaBridge 189:f392fc9709a3 70 #if defined FSL_FEATURE_SDHC_HAS_V300_SUPPORT && FSL_FEATURE_SDHC_HAS_V300_SUPPORT
AnnaBridge 189:f392fc9709a3 71 kSDHC_SupportV300Flag = SDHC_HTCAPBLT_VS30_MASK, /*!< Support voltage 3.0V */
AnnaBridge 189:f392fc9709a3 72 #endif
AnnaBridge 189:f392fc9709a3 73 #if defined FSL_FEATURE_SDHC_HAS_V180_SUPPORT && FSL_FEATURE_SDHC_HAS_V180_SUPPORT
AnnaBridge 189:f392fc9709a3 74 kSDHC_SupportV180Flag = SDHC_HTCAPBLT_VS18_MASK, /*!< Support voltage 1.8V */
AnnaBridge 189:f392fc9709a3 75 #endif
AnnaBridge 189:f392fc9709a3 76 /* Put additional two flags in HTCAPBLT_MBL's position. */
AnnaBridge 189:f392fc9709a3 77 kSDHC_Support4BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 0U), /*!< Support 4 bit mode */
AnnaBridge 189:f392fc9709a3 78 kSDHC_Support8BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 1U), /*!< Support 8 bit mode */
AnnaBridge 189:f392fc9709a3 79 };
AnnaBridge 189:f392fc9709a3 80
AnnaBridge 189:f392fc9709a3 81 /*! @brief Wakeup event mask */
AnnaBridge 189:f392fc9709a3 82 enum _sdhc_wakeup_event
AnnaBridge 189:f392fc9709a3 83 {
AnnaBridge 189:f392fc9709a3 84 kSDHC_WakeupEventOnCardInt = SDHC_PROCTL_WECINT_MASK, /*!< Wakeup on card interrupt */
AnnaBridge 189:f392fc9709a3 85 kSDHC_WakeupEventOnCardInsert = SDHC_PROCTL_WECINS_MASK, /*!< Wakeup on card insertion */
AnnaBridge 189:f392fc9709a3 86 kSDHC_WakeupEventOnCardRemove = SDHC_PROCTL_WECRM_MASK, /*!< Wakeup on card removal */
AnnaBridge 189:f392fc9709a3 87
AnnaBridge 189:f392fc9709a3 88 kSDHC_WakeupEventsAll = (kSDHC_WakeupEventOnCardInt | kSDHC_WakeupEventOnCardInsert |
AnnaBridge 189:f392fc9709a3 89 kSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */
AnnaBridge 189:f392fc9709a3 90 };
AnnaBridge 189:f392fc9709a3 91
AnnaBridge 189:f392fc9709a3 92 /*! @brief Reset type mask */
AnnaBridge 189:f392fc9709a3 93 enum _sdhc_reset
AnnaBridge 189:f392fc9709a3 94 {
AnnaBridge 189:f392fc9709a3 95 kSDHC_ResetAll = SDHC_SYSCTL_RSTA_MASK, /*!< Reset all except card detection */
AnnaBridge 189:f392fc9709a3 96 kSDHC_ResetCommand = SDHC_SYSCTL_RSTC_MASK, /*!< Reset command line */
AnnaBridge 189:f392fc9709a3 97 kSDHC_ResetData = SDHC_SYSCTL_RSTD_MASK, /*!< Reset data line */
AnnaBridge 189:f392fc9709a3 98
AnnaBridge 189:f392fc9709a3 99 kSDHC_ResetsAll = (kSDHC_ResetAll | kSDHC_ResetCommand | kSDHC_ResetData), /*!< All reset types */
AnnaBridge 189:f392fc9709a3 100 };
AnnaBridge 189:f392fc9709a3 101
AnnaBridge 189:f392fc9709a3 102 /*! @brief Transfer flag mask */
AnnaBridge 189:f392fc9709a3 103 enum _sdhc_transfer_flag
AnnaBridge 189:f392fc9709a3 104 {
AnnaBridge 189:f392fc9709a3 105 kSDHC_EnableDmaFlag = SDHC_XFERTYP_DMAEN_MASK, /*!< Enable DMA */
AnnaBridge 189:f392fc9709a3 106
AnnaBridge 189:f392fc9709a3 107 kSDHC_CommandTypeSuspendFlag = (SDHC_XFERTYP_CMDTYP(1U)), /*!< Suspend command */
AnnaBridge 189:f392fc9709a3 108 kSDHC_CommandTypeResumeFlag = (SDHC_XFERTYP_CMDTYP(2U)), /*!< Resume command */
AnnaBridge 189:f392fc9709a3 109 kSDHC_CommandTypeAbortFlag = (SDHC_XFERTYP_CMDTYP(3U)), /*!< Abort command */
AnnaBridge 189:f392fc9709a3 110
AnnaBridge 189:f392fc9709a3 111 kSDHC_EnableBlockCountFlag = SDHC_XFERTYP_BCEN_MASK, /*!< Enable block count */
AnnaBridge 189:f392fc9709a3 112 kSDHC_EnableAutoCommand12Flag = SDHC_XFERTYP_AC12EN_MASK, /*!< Enable auto CMD12 */
AnnaBridge 189:f392fc9709a3 113 kSDHC_DataReadFlag = SDHC_XFERTYP_DTDSEL_MASK, /*!< Enable data read */
AnnaBridge 189:f392fc9709a3 114 kSDHC_MultipleBlockFlag = SDHC_XFERTYP_MSBSEL_MASK, /*!< Multiple block data read/write */
AnnaBridge 189:f392fc9709a3 115
AnnaBridge 189:f392fc9709a3 116 kSDHC_ResponseLength136Flag = SDHC_XFERTYP_RSPTYP(1U), /*!< 136 bit response length */
AnnaBridge 189:f392fc9709a3 117 kSDHC_ResponseLength48Flag = SDHC_XFERTYP_RSPTYP(2U), /*!< 48 bit response length */
AnnaBridge 189:f392fc9709a3 118 kSDHC_ResponseLength48BusyFlag = SDHC_XFERTYP_RSPTYP(3U), /*!< 48 bit response length with busy status */
AnnaBridge 189:f392fc9709a3 119
AnnaBridge 189:f392fc9709a3 120 kSDHC_EnableCrcCheckFlag = SDHC_XFERTYP_CCCEN_MASK, /*!< Enable CRC check */
AnnaBridge 189:f392fc9709a3 121 kSDHC_EnableIndexCheckFlag = SDHC_XFERTYP_CICEN_MASK, /*!< Enable index check */
AnnaBridge 189:f392fc9709a3 122 kSDHC_DataPresentFlag = SDHC_XFERTYP_DPSEL_MASK, /*!< Data present flag */
AnnaBridge 189:f392fc9709a3 123 };
AnnaBridge 189:f392fc9709a3 124
AnnaBridge 189:f392fc9709a3 125 /*! @brief Present status flag mask */
AnnaBridge 189:f392fc9709a3 126 enum _sdhc_present_status_flag
AnnaBridge 189:f392fc9709a3 127 {
AnnaBridge 189:f392fc9709a3 128 kSDHC_CommandInhibitFlag = SDHC_PRSSTAT_CIHB_MASK, /*!< Command inhibit */
AnnaBridge 189:f392fc9709a3 129 kSDHC_DataInhibitFlag = SDHC_PRSSTAT_CDIHB_MASK, /*!< Data inhibit */
AnnaBridge 189:f392fc9709a3 130 kSDHC_DataLineActiveFlag = SDHC_PRSSTAT_DLA_MASK, /*!< Data line active */
AnnaBridge 189:f392fc9709a3 131 kSDHC_SdClockStableFlag = SDHC_PRSSTAT_SDSTB_MASK, /*!< SD bus clock stable */
AnnaBridge 189:f392fc9709a3 132 kSDHC_WriteTransferActiveFlag = SDHC_PRSSTAT_WTA_MASK, /*!< Write transfer active */
AnnaBridge 189:f392fc9709a3 133 kSDHC_ReadTransferActiveFlag = SDHC_PRSSTAT_RTA_MASK, /*!< Read transfer active */
AnnaBridge 189:f392fc9709a3 134 kSDHC_BufferWriteEnableFlag = SDHC_PRSSTAT_BWEN_MASK, /*!< Buffer write enable */
AnnaBridge 189:f392fc9709a3 135 kSDHC_BufferReadEnableFlag = SDHC_PRSSTAT_BREN_MASK, /*!< Buffer read enable */
AnnaBridge 189:f392fc9709a3 136 kSDHC_CardInsertedFlag = SDHC_PRSSTAT_CINS_MASK, /*!< Card inserted */
AnnaBridge 189:f392fc9709a3 137 kSDHC_CommandLineLevelFlag = SDHC_PRSSTAT_CLSL_MASK, /*!< Command line signal level */
AnnaBridge 189:f392fc9709a3 138 kSDHC_Data0LineLevelFlag = (1U << 24U), /*!< Data0 line signal level */
AnnaBridge 189:f392fc9709a3 139 kSDHC_Data1LineLevelFlag = (1U << 25U), /*!< Data1 line signal level */
AnnaBridge 189:f392fc9709a3 140 kSDHC_Data2LineLevelFlag = (1U << 26U), /*!< Data2 line signal level */
AnnaBridge 189:f392fc9709a3 141 kSDHC_Data3LineLevelFlag = (1U << 27U), /*!< Data3 line signal level */
AnnaBridge 189:f392fc9709a3 142 kSDHC_Data4LineLevelFlag = (1U << 28U), /*!< Data4 line signal level */
AnnaBridge 189:f392fc9709a3 143 kSDHC_Data5LineLevelFlag = (1U << 29U), /*!< Data5 line signal level */
AnnaBridge 189:f392fc9709a3 144 kSDHC_Data6LineLevelFlag = (1U << 30U), /*!< Data6 line signal level */
AnnaBridge 189:f392fc9709a3 145 kSDHC_Data7LineLevelFlag = (1U << 31U), /*!< Data7 line signal level */
AnnaBridge 189:f392fc9709a3 146 };
AnnaBridge 189:f392fc9709a3 147
AnnaBridge 189:f392fc9709a3 148 /*! @brief Interrupt status flag mask */
AnnaBridge 189:f392fc9709a3 149 enum _sdhc_interrupt_status_flag
AnnaBridge 189:f392fc9709a3 150 {
AnnaBridge 189:f392fc9709a3 151 kSDHC_CommandCompleteFlag = SDHC_IRQSTAT_CC_MASK, /*!< Command complete */
AnnaBridge 189:f392fc9709a3 152 kSDHC_DataCompleteFlag = SDHC_IRQSTAT_TC_MASK, /*!< Data complete */
AnnaBridge 189:f392fc9709a3 153 kSDHC_BlockGapEventFlag = SDHC_IRQSTAT_BGE_MASK, /*!< Block gap event */
AnnaBridge 189:f392fc9709a3 154 kSDHC_DmaCompleteFlag = SDHC_IRQSTAT_DINT_MASK, /*!< DMA interrupt */
AnnaBridge 189:f392fc9709a3 155 kSDHC_BufferWriteReadyFlag = SDHC_IRQSTAT_BWR_MASK, /*!< Buffer write ready */
AnnaBridge 189:f392fc9709a3 156 kSDHC_BufferReadReadyFlag = SDHC_IRQSTAT_BRR_MASK, /*!< Buffer read ready */
AnnaBridge 189:f392fc9709a3 157 kSDHC_CardInsertionFlag = SDHC_IRQSTAT_CINS_MASK, /*!< Card inserted */
AnnaBridge 189:f392fc9709a3 158 kSDHC_CardRemovalFlag = SDHC_IRQSTAT_CRM_MASK, /*!< Card removed */
AnnaBridge 189:f392fc9709a3 159 kSDHC_CardInterruptFlag = SDHC_IRQSTAT_CINT_MASK, /*!< Card interrupt */
AnnaBridge 189:f392fc9709a3 160 kSDHC_CommandTimeoutFlag = SDHC_IRQSTAT_CTOE_MASK, /*!< Command timeout error */
AnnaBridge 189:f392fc9709a3 161 kSDHC_CommandCrcErrorFlag = SDHC_IRQSTAT_CCE_MASK, /*!< Command CRC error */
AnnaBridge 189:f392fc9709a3 162 kSDHC_CommandEndBitErrorFlag = SDHC_IRQSTAT_CEBE_MASK, /*!< Command end bit error */
AnnaBridge 189:f392fc9709a3 163 kSDHC_CommandIndexErrorFlag = SDHC_IRQSTAT_CIE_MASK, /*!< Command index error */
AnnaBridge 189:f392fc9709a3 164 kSDHC_DataTimeoutFlag = SDHC_IRQSTAT_DTOE_MASK, /*!< Data timeout error */
AnnaBridge 189:f392fc9709a3 165 kSDHC_DataCrcErrorFlag = SDHC_IRQSTAT_DCE_MASK, /*!< Data CRC error */
AnnaBridge 189:f392fc9709a3 166 kSDHC_DataEndBitErrorFlag = SDHC_IRQSTAT_DEBE_MASK, /*!< Data end bit error */
AnnaBridge 189:f392fc9709a3 167 kSDHC_AutoCommand12ErrorFlag = SDHC_IRQSTAT_AC12E_MASK, /*!< Auto CMD12 error */
AnnaBridge 189:f392fc9709a3 168 kSDHC_DmaErrorFlag = SDHC_IRQSTAT_DMAE_MASK, /*!< DMA error */
AnnaBridge 189:f392fc9709a3 169
AnnaBridge 189:f392fc9709a3 170 kSDHC_CommandErrorFlag = (kSDHC_CommandTimeoutFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag |
AnnaBridge 189:f392fc9709a3 171 kSDHC_CommandIndexErrorFlag), /*!< Command error */
AnnaBridge 189:f392fc9709a3 172 kSDHC_DataErrorFlag = (kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag | kSDHC_DataEndBitErrorFlag |
AnnaBridge 189:f392fc9709a3 173 kSDHC_AutoCommand12ErrorFlag), /*!< Data error */
AnnaBridge 189:f392fc9709a3 174 kSDHC_ErrorFlag = (kSDHC_CommandErrorFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< All error */
AnnaBridge 189:f392fc9709a3 175 kSDHC_DataFlag = (kSDHC_DataCompleteFlag | kSDHC_DmaCompleteFlag | kSDHC_BufferWriteReadyFlag |
AnnaBridge 189:f392fc9709a3 176 kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< Data interrupts */
AnnaBridge 189:f392fc9709a3 177 kSDHC_CommandFlag = (kSDHC_CommandErrorFlag | kSDHC_CommandCompleteFlag), /*!< Command interrupts */
AnnaBridge 189:f392fc9709a3 178 kSDHC_CardDetectFlag = (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag), /*!< Card detection interrupts */
AnnaBridge 189:f392fc9709a3 179
AnnaBridge 189:f392fc9709a3 180 kSDHC_AllInterruptFlags = (kSDHC_BlockGapEventFlag | kSDHC_CardInterruptFlag | kSDHC_CommandFlag | kSDHC_DataFlag |
AnnaBridge 189:f392fc9709a3 181 kSDHC_ErrorFlag), /*!< All flags mask */
AnnaBridge 189:f392fc9709a3 182 };
AnnaBridge 189:f392fc9709a3 183
AnnaBridge 189:f392fc9709a3 184 /*! @brief Auto CMD12 error status flag mask */
AnnaBridge 189:f392fc9709a3 185 enum _sdhc_auto_command12_error_status_flag
AnnaBridge 189:f392fc9709a3 186 {
AnnaBridge 189:f392fc9709a3 187 kSDHC_AutoCommand12NotExecutedFlag = SDHC_AC12ERR_AC12NE_MASK, /*!< Not executed error */
AnnaBridge 189:f392fc9709a3 188 kSDHC_AutoCommand12TimeoutFlag = SDHC_AC12ERR_AC12TOE_MASK, /*!< Timeout error */
AnnaBridge 189:f392fc9709a3 189 kSDHC_AutoCommand12EndBitErrorFlag = SDHC_AC12ERR_AC12EBE_MASK, /*!< End bit error */
AnnaBridge 189:f392fc9709a3 190 kSDHC_AutoCommand12CrcErrorFlag = SDHC_AC12ERR_AC12CE_MASK, /*!< CRC error */
AnnaBridge 189:f392fc9709a3 191 kSDHC_AutoCommand12IndexErrorFlag = SDHC_AC12ERR_AC12IE_MASK, /*!< Index error */
AnnaBridge 189:f392fc9709a3 192 kSDHC_AutoCommand12NotIssuedFlag = SDHC_AC12ERR_CNIBAC12E_MASK, /*!< Not issued error */
AnnaBridge 189:f392fc9709a3 193 };
AnnaBridge 189:f392fc9709a3 194
AnnaBridge 189:f392fc9709a3 195 /*! @brief ADMA error status flag mask */
AnnaBridge 189:f392fc9709a3 196 enum _sdhc_adma_error_status_flag
AnnaBridge 189:f392fc9709a3 197 {
AnnaBridge 189:f392fc9709a3 198 kSDHC_AdmaLenghMismatchFlag = SDHC_ADMAES_ADMALME_MASK, /*!< Length mismatch error */
AnnaBridge 189:f392fc9709a3 199 kSDHC_AdmaDescriptorErrorFlag = SDHC_ADMAES_ADMADCE_MASK, /*!< Descriptor error */
AnnaBridge 189:f392fc9709a3 200 };
AnnaBridge 189:f392fc9709a3 201
AnnaBridge 189:f392fc9709a3 202 /*!
AnnaBridge 189:f392fc9709a3 203 * @brief ADMA error state
AnnaBridge 189:f392fc9709a3 204 *
AnnaBridge 189:f392fc9709a3 205 * This state is the detail state when ADMA error has occurred.
AnnaBridge 189:f392fc9709a3 206 */
AnnaBridge 189:f392fc9709a3 207 typedef enum _sdhc_adma_error_state
AnnaBridge 189:f392fc9709a3 208 {
AnnaBridge 189:f392fc9709a3 209 kSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */
AnnaBridge 189:f392fc9709a3 210 kSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */
AnnaBridge 189:f392fc9709a3 211 kSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */
AnnaBridge 189:f392fc9709a3 212 kSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */
AnnaBridge 189:f392fc9709a3 213 } sdhc_adma_error_state_t;
AnnaBridge 189:f392fc9709a3 214
AnnaBridge 189:f392fc9709a3 215 /*! @brief Force event mask */
AnnaBridge 189:f392fc9709a3 216 enum _sdhc_force_event
AnnaBridge 189:f392fc9709a3 217 {
AnnaBridge 189:f392fc9709a3 218 kSDHC_ForceEventAutoCommand12NotExecuted = SDHC_FEVT_AC12NE_MASK, /*!< Auto CMD12 not executed error */
AnnaBridge 189:f392fc9709a3 219 kSDHC_ForceEventAutoCommand12Timeout = SDHC_FEVT_AC12TOE_MASK, /*!< Auto CMD12 timeout error */
AnnaBridge 189:f392fc9709a3 220 kSDHC_ForceEventAutoCommand12CrcError = SDHC_FEVT_AC12CE_MASK, /*!< Auto CMD12 CRC error */
AnnaBridge 189:f392fc9709a3 221 kSDHC_ForceEventEndBitError = SDHC_FEVT_AC12EBE_MASK, /*!< Auto CMD12 end bit error */
AnnaBridge 189:f392fc9709a3 222 kSDHC_ForceEventAutoCommand12IndexError = SDHC_FEVT_AC12IE_MASK, /*!< Auto CMD12 index error */
AnnaBridge 189:f392fc9709a3 223 kSDHC_ForceEventAutoCommand12NotIssued = SDHC_FEVT_CNIBAC12E_MASK, /*!< Auto CMD12 not issued error */
AnnaBridge 189:f392fc9709a3 224 kSDHC_ForceEventCommandTimeout = SDHC_FEVT_CTOE_MASK, /*!< Command timeout error */
AnnaBridge 189:f392fc9709a3 225 kSDHC_ForceEventCommandCrcError = SDHC_FEVT_CCE_MASK, /*!< Command CRC error */
AnnaBridge 189:f392fc9709a3 226 kSDHC_ForceEventCommandEndBitError = SDHC_FEVT_CEBE_MASK, /*!< Command end bit error */
AnnaBridge 189:f392fc9709a3 227 kSDHC_ForceEventCommandIndexError = SDHC_FEVT_CIE_MASK, /*!< Command index error */
AnnaBridge 189:f392fc9709a3 228 kSDHC_ForceEventDataTimeout = SDHC_FEVT_DTOE_MASK, /*!< Data timeout error */
AnnaBridge 189:f392fc9709a3 229 kSDHC_ForceEventDataCrcError = SDHC_FEVT_DCE_MASK, /*!< Data CRC error */
AnnaBridge 189:f392fc9709a3 230 kSDHC_ForceEventDataEndBitError = SDHC_FEVT_DEBE_MASK, /*!< Data end bit error */
AnnaBridge 189:f392fc9709a3 231 kSDHC_ForceEventAutoCommand12Error = SDHC_FEVT_AC12E_MASK, /*!< Auto CMD12 error */
AnnaBridge 189:f392fc9709a3 232 kSDHC_ForceEventCardInt = SDHC_FEVT_CINT_MASK, /*!< Card interrupt */
AnnaBridge 189:f392fc9709a3 233 kSDHC_ForceEventDmaError = SDHC_FEVT_DMAE_MASK, /*!< Dma error */
AnnaBridge 189:f392fc9709a3 234
AnnaBridge 189:f392fc9709a3 235 kSDHC_ForceEventsAll =
AnnaBridge 189:f392fc9709a3 236 (kSDHC_ForceEventAutoCommand12NotExecuted | kSDHC_ForceEventAutoCommand12Timeout |
AnnaBridge 189:f392fc9709a3 237 kSDHC_ForceEventAutoCommand12CrcError | kSDHC_ForceEventEndBitError | kSDHC_ForceEventAutoCommand12IndexError |
AnnaBridge 189:f392fc9709a3 238 kSDHC_ForceEventAutoCommand12NotIssued | kSDHC_ForceEventCommandTimeout | kSDHC_ForceEventCommandCrcError |
AnnaBridge 189:f392fc9709a3 239 kSDHC_ForceEventCommandEndBitError | kSDHC_ForceEventCommandIndexError | kSDHC_ForceEventDataTimeout |
AnnaBridge 189:f392fc9709a3 240 kSDHC_ForceEventDataCrcError | kSDHC_ForceEventDataEndBitError | kSDHC_ForceEventAutoCommand12Error |
AnnaBridge 189:f392fc9709a3 241 kSDHC_ForceEventCardInt | kSDHC_ForceEventDmaError), /*!< All force event flags mask */
AnnaBridge 189:f392fc9709a3 242 };
AnnaBridge 189:f392fc9709a3 243
AnnaBridge 189:f392fc9709a3 244 /*! @brief Data transfer width */
AnnaBridge 189:f392fc9709a3 245 typedef enum _sdhc_data_bus_width
AnnaBridge 189:f392fc9709a3 246 {
AnnaBridge 189:f392fc9709a3 247 kSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */
AnnaBridge 189:f392fc9709a3 248 kSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */
AnnaBridge 189:f392fc9709a3 249 kSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */
AnnaBridge 189:f392fc9709a3 250 } sdhc_data_bus_width_t;
AnnaBridge 189:f392fc9709a3 251
AnnaBridge 189:f392fc9709a3 252 /*! @brief Endian mode */
AnnaBridge 189:f392fc9709a3 253 typedef enum _sdhc_endian_mode
AnnaBridge 189:f392fc9709a3 254 {
AnnaBridge 189:f392fc9709a3 255 kSDHC_EndianModeBig = 0U, /*!< Big endian mode */
AnnaBridge 189:f392fc9709a3 256 kSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */
AnnaBridge 189:f392fc9709a3 257 kSDHC_EndianModeLittle = 2U, /*!< Little endian mode */
AnnaBridge 189:f392fc9709a3 258 } sdhc_endian_mode_t;
AnnaBridge 189:f392fc9709a3 259
AnnaBridge 189:f392fc9709a3 260 /*! @brief DMA mode */
AnnaBridge 189:f392fc9709a3 261 typedef enum _sdhc_dma_mode
AnnaBridge 189:f392fc9709a3 262 {
AnnaBridge 189:f392fc9709a3 263 kSDHC_DmaModeNo = 0U, /*!< No DMA */
AnnaBridge 189:f392fc9709a3 264 kSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */
AnnaBridge 189:f392fc9709a3 265 kSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */
AnnaBridge 189:f392fc9709a3 266 } sdhc_dma_mode_t;
AnnaBridge 189:f392fc9709a3 267
AnnaBridge 189:f392fc9709a3 268 /*! @brief SDIO control flag mask */
AnnaBridge 189:f392fc9709a3 269 enum _sdhc_sdio_control_flag
AnnaBridge 189:f392fc9709a3 270 {
AnnaBridge 189:f392fc9709a3 271 kSDHC_StopAtBlockGapFlag = 0x01, /*!< Stop at block gap */
AnnaBridge 189:f392fc9709a3 272 kSDHC_ReadWaitControlFlag = 0x02, /*!< Read wait control */
AnnaBridge 189:f392fc9709a3 273 kSDHC_InterruptAtBlockGapFlag = 0x04, /*!< Interrupt at block gap */
AnnaBridge 189:f392fc9709a3 274 kSDHC_ExactBlockNumberReadFlag = 0x08, /*!< Exact block number read */
AnnaBridge 189:f392fc9709a3 275 };
AnnaBridge 189:f392fc9709a3 276
AnnaBridge 189:f392fc9709a3 277 /*! @brief MMC card boot mode */
AnnaBridge 189:f392fc9709a3 278 typedef enum _sdhc_boot_mode
AnnaBridge 189:f392fc9709a3 279 {
AnnaBridge 189:f392fc9709a3 280 kSDHC_BootModeNormal = 0U, /*!< Normal boot */
AnnaBridge 189:f392fc9709a3 281 kSDHC_BootModeAlternative = 1U, /*!< Alternative boot */
AnnaBridge 189:f392fc9709a3 282 } sdhc_boot_mode_t;
AnnaBridge 189:f392fc9709a3 283
AnnaBridge 189:f392fc9709a3 284 /*! @brief The command type */
AnnaBridge 189:f392fc9709a3 285 typedef enum _sdhc_command_type
AnnaBridge 189:f392fc9709a3 286 {
AnnaBridge 189:f392fc9709a3 287 kSDHC_CommandTypeNormal = 0U, /*!< Normal command */
AnnaBridge 189:f392fc9709a3 288 kSDHC_CommandTypeSuspend = 1U, /*!< Suspend command */
AnnaBridge 189:f392fc9709a3 289 kSDHC_CommandTypeResume = 2U, /*!< Resume command */
AnnaBridge 189:f392fc9709a3 290 kSDHC_CommandTypeAbort = 3U, /*!< Abort command */
AnnaBridge 189:f392fc9709a3 291 } sdhc_command_type_t;
AnnaBridge 189:f392fc9709a3 292
AnnaBridge 189:f392fc9709a3 293 /*!
AnnaBridge 189:f392fc9709a3 294 * @brief The command response type.
AnnaBridge 189:f392fc9709a3 295 *
AnnaBridge 189:f392fc9709a3 296 * Define the command response type from card to host controller.
AnnaBridge 189:f392fc9709a3 297 */
AnnaBridge 189:f392fc9709a3 298 typedef enum _sdhc_response_type
AnnaBridge 189:f392fc9709a3 299 {
AnnaBridge 189:f392fc9709a3 300 kSDHC_ResponseTypeNone = 0U, /*!< Response type: none */
AnnaBridge 189:f392fc9709a3 301 kSDHC_ResponseTypeR1 = 1U, /*!< Response type: R1 */
AnnaBridge 189:f392fc9709a3 302 kSDHC_ResponseTypeR1b = 2U, /*!< Response type: R1b */
AnnaBridge 189:f392fc9709a3 303 kSDHC_ResponseTypeR2 = 3U, /*!< Response type: R2 */
AnnaBridge 189:f392fc9709a3 304 kSDHC_ResponseTypeR3 = 4U, /*!< Response type: R3 */
AnnaBridge 189:f392fc9709a3 305 kSDHC_ResponseTypeR4 = 5U, /*!< Response type: R4 */
AnnaBridge 189:f392fc9709a3 306 kSDHC_ResponseTypeR5 = 6U, /*!< Response type: R5 */
AnnaBridge 189:f392fc9709a3 307 kSDHC_ResponseTypeR5b = 7U, /*!< Response type: R5b */
AnnaBridge 189:f392fc9709a3 308 kSDHC_ResponseTypeR6 = 8U, /*!< Response type: R6 */
AnnaBridge 189:f392fc9709a3 309 kSDHC_ResponseTypeR7 = 9U, /*!< Response type: R7 */
AnnaBridge 189:f392fc9709a3 310 } sdhc_response_type_t;
AnnaBridge 189:f392fc9709a3 311
AnnaBridge 189:f392fc9709a3 312 /*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */
AnnaBridge 189:f392fc9709a3 313 #define SDHC_ADMA1_ADDRESS_ALIGN (4096U)
AnnaBridge 189:f392fc9709a3 314 /*! @brief The alignment size for LENGTH field in ADMA1's descriptor */
AnnaBridge 189:f392fc9709a3 315 #define SDHC_ADMA1_LENGTH_ALIGN (4096U)
AnnaBridge 189:f392fc9709a3 316 /*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */
AnnaBridge 189:f392fc9709a3 317 #define SDHC_ADMA2_ADDRESS_ALIGN (4U)
AnnaBridge 189:f392fc9709a3 318 /*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */
AnnaBridge 189:f392fc9709a3 319 #define SDHC_ADMA2_LENGTH_ALIGN (4U)
AnnaBridge 189:f392fc9709a3 320
AnnaBridge 189:f392fc9709a3 321 /* ADMA1 descriptor table
AnnaBridge 189:f392fc9709a3 322 * |------------------------|---------|--------------------------|
AnnaBridge 189:f392fc9709a3 323 * | Address/page field |Reserved | Attribute |
AnnaBridge 189:f392fc9709a3 324 * |------------------------|---------|--------------------------|
AnnaBridge 189:f392fc9709a3 325 * |31 12|11 6|05 |04 |03|02 |01 |00 |
AnnaBridge 189:f392fc9709a3 326 * |------------------------|---------|----|----|--|---|---|-----|
AnnaBridge 189:f392fc9709a3 327 * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|
AnnaBridge 189:f392fc9709a3 328 * |------------------------|---------|----|----|--|---|---|-----|
AnnaBridge 189:f392fc9709a3 329 *
AnnaBridge 189:f392fc9709a3 330 *
AnnaBridge 189:f392fc9709a3 331 * |------|------|-----------------|-------|-------------|
AnnaBridge 189:f392fc9709a3 332 * | Act2 | Act1 | Comment | 31-28 | 27 - 12 |
AnnaBridge 189:f392fc9709a3 333 * |------|------|-----------------|---------------------|
AnnaBridge 189:f392fc9709a3 334 * | 0 | 0 | No op | Don't care |
AnnaBridge 189:f392fc9709a3 335 * |------|------|-----------------|-------|-------------|
AnnaBridge 189:f392fc9709a3 336 * | 0 | 1 | Set data length | 0000 | Data Length |
AnnaBridge 189:f392fc9709a3 337 * |------|------|-----------------|-------|-------------|
AnnaBridge 189:f392fc9709a3 338 * | 1 | 0 | Transfer data | Data address |
AnnaBridge 189:f392fc9709a3 339 * |------|------|-----------------|---------------------|
AnnaBridge 189:f392fc9709a3 340 * | 1 | 1 | Link descriptor | Descriptor address |
AnnaBridge 189:f392fc9709a3 341 * |------|------|-----------------|---------------------|
AnnaBridge 189:f392fc9709a3 342 */
AnnaBridge 189:f392fc9709a3 343 /*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */
AnnaBridge 189:f392fc9709a3 344 #define SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 345 /*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */
AnnaBridge 189:f392fc9709a3 346 #define SDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)
AnnaBridge 189:f392fc9709a3 347 /*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */
AnnaBridge 189:f392fc9709a3 348 #define SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 349 /*! @brief The mask for LENGTH field in ADMA1's descriptor */
AnnaBridge 189:f392fc9709a3 350 #define SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 351 /*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */
AnnaBridge 189:f392fc9709a3 352 #define SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U)
AnnaBridge 189:f392fc9709a3 353
AnnaBridge 189:f392fc9709a3 354 /*! @brief The mask for the control/status field in ADMA1 descriptor */
AnnaBridge 189:f392fc9709a3 355 enum _sdhc_adma1_descriptor_flag
AnnaBridge 189:f392fc9709a3 356 {
AnnaBridge 189:f392fc9709a3 357 kSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
AnnaBridge 189:f392fc9709a3 358 kSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */
AnnaBridge 189:f392fc9709a3 359 kSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */
AnnaBridge 189:f392fc9709a3 360 kSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */
AnnaBridge 189:f392fc9709a3 361 kSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */
AnnaBridge 189:f392fc9709a3 362 kSDHC_Adma1DescriptorTypeNop = (kSDHC_Adma1DescriptorValidFlag), /*!< No operation */
AnnaBridge 189:f392fc9709a3 363 kSDHC_Adma1DescriptorTypeTransfer =
AnnaBridge 189:f392fc9709a3 364 (kSDHC_Adma1DescriptorActivity2Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */
AnnaBridge 189:f392fc9709a3 365 kSDHC_Adma1DescriptorTypeLink = (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorActivity2Flag |
AnnaBridge 189:f392fc9709a3 366 kSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */
AnnaBridge 189:f392fc9709a3 367 kSDHC_Adma1DescriptorTypeSetLength =
AnnaBridge 189:f392fc9709a3 368 (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Set data length */
AnnaBridge 189:f392fc9709a3 369 };
AnnaBridge 189:f392fc9709a3 370
AnnaBridge 189:f392fc9709a3 371 /* ADMA2 descriptor table
AnnaBridge 189:f392fc9709a3 372 * |----------------|---------------|-------------|--------------------------|
AnnaBridge 189:f392fc9709a3 373 * | Address field | Length | Reserved | Attribute |
AnnaBridge 189:f392fc9709a3 374 * |----------------|---------------|-------------|--------------------------|
AnnaBridge 189:f392fc9709a3 375 * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |
AnnaBridge 189:f392fc9709a3 376 * |----------------|---------------|-------------|----|----|--|---|---|-----|
AnnaBridge 189:f392fc9709a3 377 * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|
AnnaBridge 189:f392fc9709a3 378 * |----------------|---------------|-------------|----|----|--|---|---|-----|
AnnaBridge 189:f392fc9709a3 379 *
AnnaBridge 189:f392fc9709a3 380 *
AnnaBridge 189:f392fc9709a3 381 * | Act2 | Act1 | Comment | Operation |
AnnaBridge 189:f392fc9709a3 382 * |------|------|-----------------|-------------------------------------------------------------------|
AnnaBridge 189:f392fc9709a3 383 * | 0 | 0 | No op | Don't care |
AnnaBridge 189:f392fc9709a3 384 * |------|------|-----------------|-------------------------------------------------------------------|
AnnaBridge 189:f392fc9709a3 385 * | 0 | 1 | Reserved | Read this line and go to next one |
AnnaBridge 189:f392fc9709a3 386 * |------|------|-----------------|-------------------------------------------------------------------|
AnnaBridge 189:f392fc9709a3 387 * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |
AnnaBridge 189:f392fc9709a3 388 * |------|------|-----------------|-------------------------------------------------------------------|
AnnaBridge 189:f392fc9709a3 389 * | 1 | 1 | Link descriptor | Link to another descriptor |
AnnaBridge 189:f392fc9709a3 390 * |------|------|-----------------|-------------------------------------------------------------------|
AnnaBridge 189:f392fc9709a3 391 */
AnnaBridge 189:f392fc9709a3 392 /*! @brief The bit shift for LENGTH field in ADMA2's descriptor */
AnnaBridge 189:f392fc9709a3 393 #define SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 394 /*! @brief The bit mask for LENGTH field in ADMA2's descriptor */
AnnaBridge 189:f392fc9709a3 395 #define SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 396 /*! @brief The maximum value of LENGTH field in ADMA2's descriptor */
AnnaBridge 189:f392fc9709a3 397 #define SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK)
AnnaBridge 189:f392fc9709a3 398
AnnaBridge 189:f392fc9709a3 399 /*! @brief ADMA1 descriptor control and status mask */
AnnaBridge 189:f392fc9709a3 400 enum _sdhc_adma2_descriptor_flag
AnnaBridge 189:f392fc9709a3 401 {
AnnaBridge 189:f392fc9709a3 402 kSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */
AnnaBridge 189:f392fc9709a3 403 kSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */
AnnaBridge 189:f392fc9709a3 404 kSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */
AnnaBridge 189:f392fc9709a3 405 kSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */
AnnaBridge 189:f392fc9709a3 406 kSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 kSDHC_Adma2DescriptorTypeNop = (kSDHC_Adma2DescriptorValidFlag), /*!< No operation */
AnnaBridge 189:f392fc9709a3 409 kSDHC_Adma2DescriptorTypeReserved =
AnnaBridge 189:f392fc9709a3 410 (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Reserved */
AnnaBridge 189:f392fc9709a3 411 kSDHC_Adma2DescriptorTypeTransfer =
AnnaBridge 189:f392fc9709a3 412 (kSDHC_Adma2DescriptorActivity2Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */
AnnaBridge 189:f392fc9709a3 413 kSDHC_Adma2DescriptorTypeLink = (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorActivity2Flag |
AnnaBridge 189:f392fc9709a3 414 kSDHC_Adma2DescriptorValidFlag), /*!< Link type */
AnnaBridge 189:f392fc9709a3 415 };
AnnaBridge 189:f392fc9709a3 416
AnnaBridge 189:f392fc9709a3 417 /*! @brief Defines the adma1 descriptor structure. */
AnnaBridge 189:f392fc9709a3 418 typedef uint32_t sdhc_adma1_descriptor_t;
AnnaBridge 189:f392fc9709a3 419
AnnaBridge 189:f392fc9709a3 420 /*! @brief Defines the ADMA2 descriptor structure. */
AnnaBridge 189:f392fc9709a3 421 typedef struct _sdhc_adma2_descriptor
AnnaBridge 189:f392fc9709a3 422 {
AnnaBridge 189:f392fc9709a3 423 uint32_t attribute; /*!< The control and status field */
AnnaBridge 189:f392fc9709a3 424 const uint32_t *address; /*!< The address field */
AnnaBridge 189:f392fc9709a3 425 } sdhc_adma2_descriptor_t;
AnnaBridge 189:f392fc9709a3 426
AnnaBridge 189:f392fc9709a3 427 /*!
AnnaBridge 189:f392fc9709a3 428 * @brief SDHC capability information.
AnnaBridge 189:f392fc9709a3 429 *
AnnaBridge 189:f392fc9709a3 430 * Defines a structure to save the capability information of SDHC.
AnnaBridge 189:f392fc9709a3 431 */
AnnaBridge 189:f392fc9709a3 432 typedef struct _sdhc_capability
AnnaBridge 189:f392fc9709a3 433 {
AnnaBridge 189:f392fc9709a3 434 uint32_t specVersion; /*!< Specification version */
AnnaBridge 189:f392fc9709a3 435 uint32_t vendorVersion; /*!< Vendor version */
AnnaBridge 189:f392fc9709a3 436 uint32_t maxBlockLength; /*!< Maximum block length united as byte */
AnnaBridge 189:f392fc9709a3 437 uint32_t maxBlockCount; /*!< Maximum block count can be set one time */
AnnaBridge 189:f392fc9709a3 438 uint32_t flags; /*!< Capability flags to indicate the support information(_sdhc_capability_flag) */
AnnaBridge 189:f392fc9709a3 439 } sdhc_capability_t;
AnnaBridge 189:f392fc9709a3 440
AnnaBridge 189:f392fc9709a3 441 /*! @brief Card transfer configuration.
AnnaBridge 189:f392fc9709a3 442 *
AnnaBridge 189:f392fc9709a3 443 * Define structure to configure the transfer-related command index/argument/flags and data block
AnnaBridge 189:f392fc9709a3 444 * size/data block numbers. This structure needs to be filled each time a command is sent to the card.
AnnaBridge 189:f392fc9709a3 445 */
AnnaBridge 189:f392fc9709a3 446 typedef struct _sdhc_transfer_config
AnnaBridge 189:f392fc9709a3 447 {
AnnaBridge 189:f392fc9709a3 448 size_t dataBlockSize; /*!< Data block size */
AnnaBridge 189:f392fc9709a3 449 uint32_t dataBlockCount; /*!< Data block count */
AnnaBridge 189:f392fc9709a3 450 uint32_t commandArgument; /*!< Command argument */
AnnaBridge 189:f392fc9709a3 451 uint32_t commandIndex; /*!< Command index */
AnnaBridge 189:f392fc9709a3 452 uint32_t flags; /*!< Transfer flags(_sdhc_transfer_flag) */
AnnaBridge 189:f392fc9709a3 453 } sdhc_transfer_config_t;
AnnaBridge 189:f392fc9709a3 454
AnnaBridge 189:f392fc9709a3 455 /*! @brief Data structure to configure the MMC boot feature */
AnnaBridge 189:f392fc9709a3 456 typedef struct _sdhc_boot_config
AnnaBridge 189:f392fc9709a3 457 {
AnnaBridge 189:f392fc9709a3 458 uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */
AnnaBridge 189:f392fc9709a3 459 sdhc_boot_mode_t bootMode; /*!< Boot mode selection. */
AnnaBridge 189:f392fc9709a3 460 uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */
AnnaBridge 189:f392fc9709a3 461 bool enableBootAck; /*!< Enable or disable boot ACK */
AnnaBridge 189:f392fc9709a3 462 bool enableBoot; /*!< Enable or disable fast boot */
AnnaBridge 189:f392fc9709a3 463 bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */
AnnaBridge 189:f392fc9709a3 464 } sdhc_boot_config_t;
AnnaBridge 189:f392fc9709a3 465
AnnaBridge 189:f392fc9709a3 466 /*! @brief Data structure to initialize the SDHC */
AnnaBridge 189:f392fc9709a3 467 typedef struct _sdhc_config
AnnaBridge 189:f392fc9709a3 468 {
AnnaBridge 189:f392fc9709a3 469 bool cardDetectDat3; /*!< Enable DAT3 as card detection pin */
AnnaBridge 189:f392fc9709a3 470 sdhc_endian_mode_t endianMode; /*!< Endian mode */
AnnaBridge 189:f392fc9709a3 471 sdhc_dma_mode_t dmaMode; /*!< DMA mode */
AnnaBridge 189:f392fc9709a3 472 uint32_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */
AnnaBridge 189:f392fc9709a3 473 uint32_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */
AnnaBridge 189:f392fc9709a3 474 } sdhc_config_t;
AnnaBridge 189:f392fc9709a3 475
AnnaBridge 189:f392fc9709a3 476 /*!
AnnaBridge 189:f392fc9709a3 477 * @brief Card data descriptor
AnnaBridge 189:f392fc9709a3 478 *
AnnaBridge 189:f392fc9709a3 479 * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card
AnnaBridge 189:f392fc9709a3 480 * driver
AnnaBridge 189:f392fc9709a3 481 * want to ignore the error event to read/write all the data not to stop read/write immediately when error event
AnnaBridge 189:f392fc9709a3 482 * happen for example bus testing procedure for MMC card.
AnnaBridge 189:f392fc9709a3 483 */
AnnaBridge 189:f392fc9709a3 484 typedef struct _sdhc_data
AnnaBridge 189:f392fc9709a3 485 {
AnnaBridge 189:f392fc9709a3 486 bool enableAutoCommand12; /*!< Enable auto CMD12 */
AnnaBridge 189:f392fc9709a3 487 bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */
AnnaBridge 189:f392fc9709a3 488 size_t blockSize; /*!< Block size */
AnnaBridge 189:f392fc9709a3 489 uint32_t blockCount; /*!< Block count */
AnnaBridge 189:f392fc9709a3 490 uint32_t *rxData; /*!< Buffer to save data read */
AnnaBridge 189:f392fc9709a3 491 const uint32_t *txData; /*!< Data buffer to write */
AnnaBridge 189:f392fc9709a3 492 } sdhc_data_t;
AnnaBridge 189:f392fc9709a3 493
AnnaBridge 189:f392fc9709a3 494 /*!
AnnaBridge 189:f392fc9709a3 495 * @brief Card command descriptor
AnnaBridge 189:f392fc9709a3 496 *
AnnaBridge 189:f392fc9709a3 497 * Define card command-related attribute.
AnnaBridge 189:f392fc9709a3 498 */
AnnaBridge 189:f392fc9709a3 499 typedef struct _sdhc_command
AnnaBridge 189:f392fc9709a3 500 {
AnnaBridge 189:f392fc9709a3 501 uint32_t index; /*!< Command index */
AnnaBridge 189:f392fc9709a3 502 uint32_t argument; /*!< Command argument */
AnnaBridge 189:f392fc9709a3 503 sdhc_command_type_t type; /*!< Command type */
AnnaBridge 189:f392fc9709a3 504 sdhc_response_type_t responseType; /*!< Command response type */
AnnaBridge 189:f392fc9709a3 505 uint32_t response[4U]; /*!< Response for this command */
AnnaBridge 189:f392fc9709a3 506 } sdhc_command_t;
AnnaBridge 189:f392fc9709a3 507
AnnaBridge 189:f392fc9709a3 508 /*! @brief Transfer state */
AnnaBridge 189:f392fc9709a3 509 typedef struct _sdhc_transfer
AnnaBridge 189:f392fc9709a3 510 {
AnnaBridge 189:f392fc9709a3 511 sdhc_data_t *data; /*!< Data to transfer */
AnnaBridge 189:f392fc9709a3 512 sdhc_command_t *command; /*!< Command to send */
AnnaBridge 189:f392fc9709a3 513 } sdhc_transfer_t;
AnnaBridge 189:f392fc9709a3 514
AnnaBridge 189:f392fc9709a3 515 /*! @brief SDHC handle typedef */
AnnaBridge 189:f392fc9709a3 516 typedef struct _sdhc_handle sdhc_handle_t;
AnnaBridge 189:f392fc9709a3 517
AnnaBridge 189:f392fc9709a3 518 /*! @brief SDHC callback functions. */
AnnaBridge 189:f392fc9709a3 519 typedef struct _sdhc_transfer_callback
AnnaBridge 189:f392fc9709a3 520 {
AnnaBridge 189:f392fc9709a3 521 void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */
AnnaBridge 189:f392fc9709a3 522 void (*CardRemoved)(void); /*!< Card removed occurs */
AnnaBridge 189:f392fc9709a3 523 void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */
AnnaBridge 189:f392fc9709a3 524 void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */
AnnaBridge 189:f392fc9709a3 525 void (*TransferComplete)(SDHC_Type *base,
AnnaBridge 189:f392fc9709a3 526 sdhc_handle_t *handle,
AnnaBridge 189:f392fc9709a3 527 status_t status,
AnnaBridge 189:f392fc9709a3 528 void *userData); /*!< Transfer complete callback */
AnnaBridge 189:f392fc9709a3 529 } sdhc_transfer_callback_t;
AnnaBridge 189:f392fc9709a3 530
AnnaBridge 189:f392fc9709a3 531 /*!
AnnaBridge 189:f392fc9709a3 532 * @brief SDHC handle
AnnaBridge 189:f392fc9709a3 533 *
AnnaBridge 189:f392fc9709a3 534 * Defines the structure to save the SDHC state information and callback function. The detailed interrupt status when
AnnaBridge 189:f392fc9709a3 535 * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in
AnnaBridge 189:f392fc9709a3 536 * sdhc_interrupt_flag_t.
AnnaBridge 189:f392fc9709a3 537 *
AnnaBridge 189:f392fc9709a3 538 * @note All the fields except interruptFlags and transferredWords must be allocated by the user.
AnnaBridge 189:f392fc9709a3 539 */
AnnaBridge 189:f392fc9709a3 540 struct _sdhc_handle
AnnaBridge 189:f392fc9709a3 541 {
AnnaBridge 189:f392fc9709a3 542 /* Transfer parameter */
AnnaBridge 189:f392fc9709a3 543 sdhc_data_t *volatile data; /*!< Data to transfer */
AnnaBridge 189:f392fc9709a3 544 sdhc_command_t *volatile command; /*!< Command to send */
AnnaBridge 189:f392fc9709a3 545
AnnaBridge 189:f392fc9709a3 546 /* Transfer status */
AnnaBridge 189:f392fc9709a3 547 volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */
AnnaBridge 189:f392fc9709a3 548 volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */
AnnaBridge 189:f392fc9709a3 549
AnnaBridge 189:f392fc9709a3 550 /* Callback functions */
AnnaBridge 189:f392fc9709a3 551 sdhc_transfer_callback_t callback; /*!< Callback function */
AnnaBridge 189:f392fc9709a3 552 void *userData; /*!< Parameter for transfer complete callback */
AnnaBridge 189:f392fc9709a3 553 };
AnnaBridge 189:f392fc9709a3 554
AnnaBridge 189:f392fc9709a3 555 /*! @brief SDHC transfer function. */
AnnaBridge 189:f392fc9709a3 556 typedef status_t (*sdhc_transfer_function_t)(SDHC_Type *base, sdhc_transfer_t *content);
AnnaBridge 189:f392fc9709a3 557
AnnaBridge 189:f392fc9709a3 558 /*! @brief SDHC host descriptor */
AnnaBridge 189:f392fc9709a3 559 typedef struct _sdhc_host
AnnaBridge 189:f392fc9709a3 560 {
AnnaBridge 189:f392fc9709a3 561 SDHC_Type *base; /*!< SDHC peripheral base address */
AnnaBridge 189:f392fc9709a3 562 uint32_t sourceClock_Hz; /*!< SDHC source clock frequency united in Hz */
AnnaBridge 189:f392fc9709a3 563 sdhc_config_t config; /*!< SDHC configuration */
AnnaBridge 189:f392fc9709a3 564 sdhc_capability_t capability; /*!< SDHC capability information */
AnnaBridge 189:f392fc9709a3 565 sdhc_transfer_function_t transfer; /*!< SDHC transfer function */
AnnaBridge 189:f392fc9709a3 566 } sdhc_host_t;
AnnaBridge 189:f392fc9709a3 567
AnnaBridge 189:f392fc9709a3 568 /*************************************************************************************************
AnnaBridge 189:f392fc9709a3 569 * API
AnnaBridge 189:f392fc9709a3 570 ************************************************************************************************/
AnnaBridge 189:f392fc9709a3 571 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 572 extern "C" {
AnnaBridge 189:f392fc9709a3 573 #endif
AnnaBridge 189:f392fc9709a3 574
AnnaBridge 189:f392fc9709a3 575 /*!
AnnaBridge 189:f392fc9709a3 576 * @name Initialization and deinitialization
AnnaBridge 189:f392fc9709a3 577 * @{
AnnaBridge 189:f392fc9709a3 578 */
AnnaBridge 189:f392fc9709a3 579
AnnaBridge 189:f392fc9709a3 580 /*!
AnnaBridge 189:f392fc9709a3 581 * @brief SDHC module initialization function.
AnnaBridge 189:f392fc9709a3 582 *
AnnaBridge 189:f392fc9709a3 583 * Configures the SDHC according to the user configuration.
AnnaBridge 189:f392fc9709a3 584 *
AnnaBridge 189:f392fc9709a3 585 * Example:
AnnaBridge 189:f392fc9709a3 586 @code
AnnaBridge 189:f392fc9709a3 587 sdhc_config_t config;
AnnaBridge 189:f392fc9709a3 588 config.cardDetectDat3 = false;
AnnaBridge 189:f392fc9709a3 589 config.endianMode = kSDHC_EndianModeLittle;
AnnaBridge 189:f392fc9709a3 590 config.dmaMode = kSDHC_DmaModeAdma2;
AnnaBridge 189:f392fc9709a3 591 config.readWatermarkLevel = 128U;
AnnaBridge 189:f392fc9709a3 592 config.writeWatermarkLevel = 128U;
AnnaBridge 189:f392fc9709a3 593 SDHC_Init(SDHC, &config);
AnnaBridge 189:f392fc9709a3 594 @endcode
AnnaBridge 189:f392fc9709a3 595 *
AnnaBridge 189:f392fc9709a3 596 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 597 * @param config SDHC configuration information.
AnnaBridge 189:f392fc9709a3 598 * @retval kStatus_Success Operate successfully.
AnnaBridge 189:f392fc9709a3 599 */
AnnaBridge 189:f392fc9709a3 600 void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config);
AnnaBridge 189:f392fc9709a3 601
AnnaBridge 189:f392fc9709a3 602 /*!
AnnaBridge 189:f392fc9709a3 603 * @brief Deinitializes the SDHC.
AnnaBridge 189:f392fc9709a3 604 *
AnnaBridge 189:f392fc9709a3 605 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 606 */
AnnaBridge 189:f392fc9709a3 607 void SDHC_Deinit(SDHC_Type *base);
AnnaBridge 189:f392fc9709a3 608
AnnaBridge 189:f392fc9709a3 609 /*!
AnnaBridge 189:f392fc9709a3 610 * @brief Resets the SDHC.
AnnaBridge 189:f392fc9709a3 611 *
AnnaBridge 189:f392fc9709a3 612 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 613 * @param mask The reset type mask(_sdhc_reset).
AnnaBridge 189:f392fc9709a3 614 * @param timeout Timeout for reset.
AnnaBridge 189:f392fc9709a3 615 * @retval true Reset successfully.
AnnaBridge 189:f392fc9709a3 616 * @retval false Reset failed.
AnnaBridge 189:f392fc9709a3 617 */
AnnaBridge 189:f392fc9709a3 618 bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout);
AnnaBridge 189:f392fc9709a3 619
AnnaBridge 189:f392fc9709a3 620 /* @} */
AnnaBridge 189:f392fc9709a3 621
AnnaBridge 189:f392fc9709a3 622 /*!
AnnaBridge 189:f392fc9709a3 623 * @name DMA Control
AnnaBridge 189:f392fc9709a3 624 * @{
AnnaBridge 189:f392fc9709a3 625 */
AnnaBridge 189:f392fc9709a3 626
AnnaBridge 189:f392fc9709a3 627 /*!
AnnaBridge 189:f392fc9709a3 628 * @brief Sets the ADMA descriptor table configuration.
AnnaBridge 189:f392fc9709a3 629 *
AnnaBridge 189:f392fc9709a3 630 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 631 * @param dmaMode DMA mode.
AnnaBridge 189:f392fc9709a3 632 * @param table ADMA table address.
AnnaBridge 189:f392fc9709a3 633 * @param tableWords ADMA table buffer length united as Words.
AnnaBridge 189:f392fc9709a3 634 * @param data Data buffer address.
AnnaBridge 189:f392fc9709a3 635 * @param dataBytes Data length united as bytes.
AnnaBridge 189:f392fc9709a3 636 * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data.
AnnaBridge 189:f392fc9709a3 637 * @retval kStatus_Success Operate successfully.
AnnaBridge 189:f392fc9709a3 638 */
AnnaBridge 189:f392fc9709a3 639 status_t SDHC_SetAdmaTableConfig(SDHC_Type *base,
AnnaBridge 189:f392fc9709a3 640 sdhc_dma_mode_t dmaMode,
AnnaBridge 189:f392fc9709a3 641 uint32_t *table,
AnnaBridge 189:f392fc9709a3 642 uint32_t tableWords,
AnnaBridge 189:f392fc9709a3 643 const uint32_t *data,
AnnaBridge 189:f392fc9709a3 644 uint32_t dataBytes);
AnnaBridge 189:f392fc9709a3 645
AnnaBridge 189:f392fc9709a3 646 /* @} */
AnnaBridge 189:f392fc9709a3 647
AnnaBridge 189:f392fc9709a3 648 /*!
AnnaBridge 189:f392fc9709a3 649 * @name Interrupts
AnnaBridge 189:f392fc9709a3 650 * @{
AnnaBridge 189:f392fc9709a3 651 */
AnnaBridge 189:f392fc9709a3 652
AnnaBridge 189:f392fc9709a3 653 /*!
AnnaBridge 189:f392fc9709a3 654 * @brief Enables the interrupt status.
AnnaBridge 189:f392fc9709a3 655 *
AnnaBridge 189:f392fc9709a3 656 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 657 * @param mask Interrupt status flags mask(_sdhc_interrupt_status_flag).
AnnaBridge 189:f392fc9709a3 658 */
AnnaBridge 189:f392fc9709a3 659 static inline void SDHC_EnableInterruptStatus(SDHC_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 660 {
AnnaBridge 189:f392fc9709a3 661 base->IRQSTATEN |= mask;
AnnaBridge 189:f392fc9709a3 662 }
AnnaBridge 189:f392fc9709a3 663
AnnaBridge 189:f392fc9709a3 664 /*!
AnnaBridge 189:f392fc9709a3 665 * @brief Disables the interrupt status.
AnnaBridge 189:f392fc9709a3 666 *
AnnaBridge 189:f392fc9709a3 667 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 668 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
AnnaBridge 189:f392fc9709a3 669 */
AnnaBridge 189:f392fc9709a3 670 static inline void SDHC_DisableInterruptStatus(SDHC_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 671 {
AnnaBridge 189:f392fc9709a3 672 base->IRQSTATEN &= ~mask;
AnnaBridge 189:f392fc9709a3 673 }
AnnaBridge 189:f392fc9709a3 674
AnnaBridge 189:f392fc9709a3 675 /*!
AnnaBridge 189:f392fc9709a3 676 * @brief Enables the interrupt signal corresponding to the interrupt status flag.
AnnaBridge 189:f392fc9709a3 677 *
AnnaBridge 189:f392fc9709a3 678 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 679 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
AnnaBridge 189:f392fc9709a3 680 */
AnnaBridge 189:f392fc9709a3 681 static inline void SDHC_EnableInterruptSignal(SDHC_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 682 {
AnnaBridge 189:f392fc9709a3 683 base->IRQSIGEN |= mask;
AnnaBridge 189:f392fc9709a3 684 }
AnnaBridge 189:f392fc9709a3 685
AnnaBridge 189:f392fc9709a3 686 /*!
AnnaBridge 189:f392fc9709a3 687 * @brief Disables the interrupt signal corresponding to the interrupt status flag.
AnnaBridge 189:f392fc9709a3 688 *
AnnaBridge 189:f392fc9709a3 689 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 690 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
AnnaBridge 189:f392fc9709a3 691 */
AnnaBridge 189:f392fc9709a3 692 static inline void SDHC_DisableInterruptSignal(SDHC_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 693 {
AnnaBridge 189:f392fc9709a3 694 base->IRQSIGEN &= ~mask;
AnnaBridge 189:f392fc9709a3 695 }
AnnaBridge 189:f392fc9709a3 696
AnnaBridge 189:f392fc9709a3 697 /* @} */
AnnaBridge 189:f392fc9709a3 698
AnnaBridge 189:f392fc9709a3 699 /*!
AnnaBridge 189:f392fc9709a3 700 * @name Status
AnnaBridge 189:f392fc9709a3 701 * @{
AnnaBridge 189:f392fc9709a3 702 */
AnnaBridge 189:f392fc9709a3 703
AnnaBridge 189:f392fc9709a3 704 /*!
AnnaBridge 189:f392fc9709a3 705 * @brief Gets the current interrupt status.
AnnaBridge 189:f392fc9709a3 706 *
AnnaBridge 189:f392fc9709a3 707 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 708 * @return Current interrupt status flags mask(_sdhc_interrupt_status_flag).
AnnaBridge 189:f392fc9709a3 709 */
AnnaBridge 189:f392fc9709a3 710 static inline uint32_t SDHC_GetInterruptStatusFlags(SDHC_Type *base)
AnnaBridge 189:f392fc9709a3 711 {
AnnaBridge 189:f392fc9709a3 712 return base->IRQSTAT;
AnnaBridge 189:f392fc9709a3 713 }
AnnaBridge 189:f392fc9709a3 714
AnnaBridge 189:f392fc9709a3 715 /*!
AnnaBridge 189:f392fc9709a3 716 * @brief Clears a specified interrupt status.
AnnaBridge 189:f392fc9709a3 717 *
AnnaBridge 189:f392fc9709a3 718 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 719 * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag).
AnnaBridge 189:f392fc9709a3 720 */
AnnaBridge 189:f392fc9709a3 721 static inline void SDHC_ClearInterruptStatusFlags(SDHC_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 722 {
AnnaBridge 189:f392fc9709a3 723 base->IRQSTAT = mask;
AnnaBridge 189:f392fc9709a3 724 }
AnnaBridge 189:f392fc9709a3 725
AnnaBridge 189:f392fc9709a3 726 /*!
AnnaBridge 189:f392fc9709a3 727 * @brief Gets the status of auto command 12 error.
AnnaBridge 189:f392fc9709a3 728 *
AnnaBridge 189:f392fc9709a3 729 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 730 * @return Auto command 12 error status flags mask(_sdhc_auto_command12_error_status_flag).
AnnaBridge 189:f392fc9709a3 731 */
AnnaBridge 189:f392fc9709a3 732 static inline uint32_t SDHC_GetAutoCommand12ErrorStatusFlags(SDHC_Type *base)
AnnaBridge 189:f392fc9709a3 733 {
AnnaBridge 189:f392fc9709a3 734 return base->AC12ERR;
AnnaBridge 189:f392fc9709a3 735 }
AnnaBridge 189:f392fc9709a3 736
AnnaBridge 189:f392fc9709a3 737 /*!
AnnaBridge 189:f392fc9709a3 738 * @brief Gets the status of the ADMA error.
AnnaBridge 189:f392fc9709a3 739 *
AnnaBridge 189:f392fc9709a3 740 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 741 * @return ADMA error status flags mask(_sdhc_adma_error_status_flag).
AnnaBridge 189:f392fc9709a3 742 */
AnnaBridge 189:f392fc9709a3 743 static inline uint32_t SDHC_GetAdmaErrorStatusFlags(SDHC_Type *base)
AnnaBridge 189:f392fc9709a3 744 {
AnnaBridge 189:f392fc9709a3 745 return base->ADMAES;
AnnaBridge 189:f392fc9709a3 746 }
AnnaBridge 189:f392fc9709a3 747
AnnaBridge 189:f392fc9709a3 748 /*!
AnnaBridge 189:f392fc9709a3 749 * @brief Gets a present status.
AnnaBridge 189:f392fc9709a3 750 *
AnnaBridge 189:f392fc9709a3 751 * This function gets the present SDHC's status except for an interrupt status and an error status.
AnnaBridge 189:f392fc9709a3 752 *
AnnaBridge 189:f392fc9709a3 753 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 754 * @return Present SDHC's status flags mask(_sdhc_present_status_flag).
AnnaBridge 189:f392fc9709a3 755 */
AnnaBridge 189:f392fc9709a3 756 static inline uint32_t SDHC_GetPresentStatusFlags(SDHC_Type *base)
AnnaBridge 189:f392fc9709a3 757 {
AnnaBridge 189:f392fc9709a3 758 return base->PRSSTAT;
AnnaBridge 189:f392fc9709a3 759 }
AnnaBridge 189:f392fc9709a3 760
AnnaBridge 189:f392fc9709a3 761 /* @} */
AnnaBridge 189:f392fc9709a3 762
AnnaBridge 189:f392fc9709a3 763 /*!
AnnaBridge 189:f392fc9709a3 764 * @name Bus Operations
AnnaBridge 189:f392fc9709a3 765 * @{
AnnaBridge 189:f392fc9709a3 766 */
AnnaBridge 189:f392fc9709a3 767
AnnaBridge 189:f392fc9709a3 768 /*!
AnnaBridge 189:f392fc9709a3 769 * @brief Gets the capability information.
AnnaBridge 189:f392fc9709a3 770 *
AnnaBridge 189:f392fc9709a3 771 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 772 * @param capability Structure to save capability information.
AnnaBridge 189:f392fc9709a3 773 */
AnnaBridge 189:f392fc9709a3 774 void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability);
AnnaBridge 189:f392fc9709a3 775
AnnaBridge 189:f392fc9709a3 776 /*!
AnnaBridge 189:f392fc9709a3 777 * @brief Enables or disables the SD bus clock.
AnnaBridge 189:f392fc9709a3 778 *
AnnaBridge 189:f392fc9709a3 779 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 780 * @param enable True to enable, false to disable.
AnnaBridge 189:f392fc9709a3 781 */
AnnaBridge 189:f392fc9709a3 782 static inline void SDHC_EnableSdClock(SDHC_Type *base, bool enable)
AnnaBridge 189:f392fc9709a3 783 {
AnnaBridge 189:f392fc9709a3 784 if (enable)
AnnaBridge 189:f392fc9709a3 785 {
AnnaBridge 189:f392fc9709a3 786 base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK;
AnnaBridge 189:f392fc9709a3 787 }
AnnaBridge 189:f392fc9709a3 788 else
AnnaBridge 189:f392fc9709a3 789 {
AnnaBridge 189:f392fc9709a3 790 base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK;
AnnaBridge 189:f392fc9709a3 791 }
AnnaBridge 189:f392fc9709a3 792 }
AnnaBridge 189:f392fc9709a3 793
AnnaBridge 189:f392fc9709a3 794 /*!
AnnaBridge 189:f392fc9709a3 795 * @brief Sets the SD bus clock frequency.
AnnaBridge 189:f392fc9709a3 796 *
AnnaBridge 189:f392fc9709a3 797 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 798 * @param srcClock_Hz SDHC source clock frequency united in Hz.
AnnaBridge 189:f392fc9709a3 799 * @param busClock_Hz SD bus clock frequency united in Hz.
AnnaBridge 189:f392fc9709a3 800 *
AnnaBridge 189:f392fc9709a3 801 * @return The nearest frequency of busClock_Hz configured to SD bus.
AnnaBridge 189:f392fc9709a3 802 */
AnnaBridge 189:f392fc9709a3 803 uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz);
AnnaBridge 189:f392fc9709a3 804
AnnaBridge 189:f392fc9709a3 805 /*!
AnnaBridge 189:f392fc9709a3 806 * @brief Sends 80 clocks to the card to set it to the active state.
AnnaBridge 189:f392fc9709a3 807 *
AnnaBridge 189:f392fc9709a3 808 * This function must be called each time the card is inserted to ensure that the card can receive the command
AnnaBridge 189:f392fc9709a3 809 * correctly.
AnnaBridge 189:f392fc9709a3 810 *
AnnaBridge 189:f392fc9709a3 811 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 812 * @param timeout Timeout to initialize card.
AnnaBridge 189:f392fc9709a3 813 * @retval true Set card active successfully.
AnnaBridge 189:f392fc9709a3 814 * @retval false Set card active failed.
AnnaBridge 189:f392fc9709a3 815 */
AnnaBridge 189:f392fc9709a3 816 bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout);
AnnaBridge 189:f392fc9709a3 817
AnnaBridge 189:f392fc9709a3 818 /*!
AnnaBridge 189:f392fc9709a3 819 * @brief Sets the data transfer width.
AnnaBridge 189:f392fc9709a3 820 *
AnnaBridge 189:f392fc9709a3 821 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 822 * @param width Data transfer width.
AnnaBridge 189:f392fc9709a3 823 */
AnnaBridge 189:f392fc9709a3 824 static inline void SDHC_SetDataBusWidth(SDHC_Type *base, sdhc_data_bus_width_t width)
AnnaBridge 189:f392fc9709a3 825 {
AnnaBridge 189:f392fc9709a3 826 base->PROCTL = ((base->PROCTL & ~SDHC_PROCTL_DTW_MASK) | SDHC_PROCTL_DTW(width));
AnnaBridge 189:f392fc9709a3 827 }
AnnaBridge 189:f392fc9709a3 828
AnnaBridge 189:f392fc9709a3 829 /*!
AnnaBridge 189:f392fc9709a3 830 * @brief Sets the card transfer-related configuration.
AnnaBridge 189:f392fc9709a3 831 *
AnnaBridge 189:f392fc9709a3 832 * This function fills the card transfer-related command argument/transfer flag/data size. The command and data are sent
AnnaBridge 189:f392fc9709a3 833 by
AnnaBridge 189:f392fc9709a3 834 * SDHC after calling this function.
AnnaBridge 189:f392fc9709a3 835 *
AnnaBridge 189:f392fc9709a3 836 * Example:
AnnaBridge 189:f392fc9709a3 837 @code
AnnaBridge 189:f392fc9709a3 838 sdhc_transfer_config_t transferConfig;
AnnaBridge 189:f392fc9709a3 839 transferConfig.dataBlockSize = 512U;
AnnaBridge 189:f392fc9709a3 840 transferConfig.dataBlockCount = 2U;
AnnaBridge 189:f392fc9709a3 841 transferConfig.commandArgument = 0x01AAU;
AnnaBridge 189:f392fc9709a3 842 transferConfig.commandIndex = 8U;
AnnaBridge 189:f392fc9709a3 843 transferConfig.flags |= (kSDHC_EnableDmaFlag | kSDHC_EnableAutoCommand12Flag | kSDHC_MultipleBlockFlag);
AnnaBridge 189:f392fc9709a3 844 SDHC_SetTransferConfig(SDHC, &transferConfig);
AnnaBridge 189:f392fc9709a3 845 @endcode
AnnaBridge 189:f392fc9709a3 846 *
AnnaBridge 189:f392fc9709a3 847 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 848 * @param config Command configuration structure.
AnnaBridge 189:f392fc9709a3 849 */
AnnaBridge 189:f392fc9709a3 850 void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config);
AnnaBridge 189:f392fc9709a3 851
AnnaBridge 189:f392fc9709a3 852 /*!
AnnaBridge 189:f392fc9709a3 853 * @brief Gets the command response.
AnnaBridge 189:f392fc9709a3 854 *
AnnaBridge 189:f392fc9709a3 855 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 856 * @param index The index of response register, range from 0 to 3.
AnnaBridge 189:f392fc9709a3 857 * @return Response register transfer.
AnnaBridge 189:f392fc9709a3 858 */
AnnaBridge 189:f392fc9709a3 859 static inline uint32_t SDHC_GetCommandResponse(SDHC_Type *base, uint32_t index)
AnnaBridge 189:f392fc9709a3 860 {
AnnaBridge 189:f392fc9709a3 861 assert(index < 4U);
AnnaBridge 189:f392fc9709a3 862
AnnaBridge 189:f392fc9709a3 863 return base->CMDRSP[index];
AnnaBridge 189:f392fc9709a3 864 }
AnnaBridge 189:f392fc9709a3 865
AnnaBridge 189:f392fc9709a3 866 /*!
AnnaBridge 189:f392fc9709a3 867 * @brief Fills the the data port.
AnnaBridge 189:f392fc9709a3 868 *
AnnaBridge 189:f392fc9709a3 869 * This function is used to implement the data transfer by Data Port instead of DMA.
AnnaBridge 189:f392fc9709a3 870 *
AnnaBridge 189:f392fc9709a3 871 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 872 * @param data The data about to be sent.
AnnaBridge 189:f392fc9709a3 873 */
AnnaBridge 189:f392fc9709a3 874 static inline void SDHC_WriteData(SDHC_Type *base, uint32_t data)
AnnaBridge 189:f392fc9709a3 875 {
AnnaBridge 189:f392fc9709a3 876 base->DATPORT = data;
AnnaBridge 189:f392fc9709a3 877 }
AnnaBridge 189:f392fc9709a3 878
AnnaBridge 189:f392fc9709a3 879 /*!
AnnaBridge 189:f392fc9709a3 880 * @brief Retrieves the data from the data port.
AnnaBridge 189:f392fc9709a3 881 *
AnnaBridge 189:f392fc9709a3 882 * This function is used to implement the data transfer by Data Port instead of DMA.
AnnaBridge 189:f392fc9709a3 883 *
AnnaBridge 189:f392fc9709a3 884 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 885 * @return The data has been read.
AnnaBridge 189:f392fc9709a3 886 */
AnnaBridge 189:f392fc9709a3 887 static inline uint32_t SDHC_ReadData(SDHC_Type *base)
AnnaBridge 189:f392fc9709a3 888 {
AnnaBridge 189:f392fc9709a3 889 return base->DATPORT;
AnnaBridge 189:f392fc9709a3 890 }
AnnaBridge 189:f392fc9709a3 891
AnnaBridge 189:f392fc9709a3 892 /*!
AnnaBridge 189:f392fc9709a3 893 * @brief Enables or disables a wakeup event in low-power mode.
AnnaBridge 189:f392fc9709a3 894 *
AnnaBridge 189:f392fc9709a3 895 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 896 * @param mask Wakeup events mask(_sdhc_wakeup_event).
AnnaBridge 189:f392fc9709a3 897 * @param enable True to enable, false to disable.
AnnaBridge 189:f392fc9709a3 898 */
AnnaBridge 189:f392fc9709a3 899 static inline void SDHC_EnableWakeupEvent(SDHC_Type *base, uint32_t mask, bool enable)
AnnaBridge 189:f392fc9709a3 900 {
AnnaBridge 189:f392fc9709a3 901 if (enable)
AnnaBridge 189:f392fc9709a3 902 {
AnnaBridge 189:f392fc9709a3 903 base->PROCTL |= mask;
AnnaBridge 189:f392fc9709a3 904 }
AnnaBridge 189:f392fc9709a3 905 else
AnnaBridge 189:f392fc9709a3 906 {
AnnaBridge 189:f392fc9709a3 907 base->PROCTL &= ~mask;
AnnaBridge 189:f392fc9709a3 908 }
AnnaBridge 189:f392fc9709a3 909 }
AnnaBridge 189:f392fc9709a3 910
AnnaBridge 189:f392fc9709a3 911 /*!
AnnaBridge 189:f392fc9709a3 912 * @brief Enables or disables the card detection level for testing.
AnnaBridge 189:f392fc9709a3 913 *
AnnaBridge 189:f392fc9709a3 914 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 915 * @param enable True to enable, false to disable.
AnnaBridge 189:f392fc9709a3 916 */
AnnaBridge 189:f392fc9709a3 917 static inline void SDHC_EnableCardDetectTest(SDHC_Type *base, bool enable)
AnnaBridge 189:f392fc9709a3 918 {
AnnaBridge 189:f392fc9709a3 919 if (enable)
AnnaBridge 189:f392fc9709a3 920 {
AnnaBridge 189:f392fc9709a3 921 base->PROCTL |= SDHC_PROCTL_CDSS_MASK;
AnnaBridge 189:f392fc9709a3 922 }
AnnaBridge 189:f392fc9709a3 923 else
AnnaBridge 189:f392fc9709a3 924 {
AnnaBridge 189:f392fc9709a3 925 base->PROCTL &= ~SDHC_PROCTL_CDSS_MASK;
AnnaBridge 189:f392fc9709a3 926 }
AnnaBridge 189:f392fc9709a3 927 }
AnnaBridge 189:f392fc9709a3 928
AnnaBridge 189:f392fc9709a3 929 /*!
AnnaBridge 189:f392fc9709a3 930 * @brief Sets the card detection test level.
AnnaBridge 189:f392fc9709a3 931 *
AnnaBridge 189:f392fc9709a3 932 * This function sets the card detection test level to indicate whether the card is inserted into the SDHC when DAT[3]/
AnnaBridge 189:f392fc9709a3 933 * CD pin is selected as a card detection pin. This function can also assert the pin logic when DAT[3]/CD pin is
AnnaBridge 189:f392fc9709a3 934 * selected
AnnaBridge 189:f392fc9709a3 935 * as the card detection pin.
AnnaBridge 189:f392fc9709a3 936 *
AnnaBridge 189:f392fc9709a3 937 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 938 * @param high True to set the card detect level to high.
AnnaBridge 189:f392fc9709a3 939 */
AnnaBridge 189:f392fc9709a3 940 static inline void SDHC_SetCardDetectTestLevel(SDHC_Type *base, bool high)
AnnaBridge 189:f392fc9709a3 941 {
AnnaBridge 189:f392fc9709a3 942 if (high)
AnnaBridge 189:f392fc9709a3 943 {
AnnaBridge 189:f392fc9709a3 944 base->PROCTL |= SDHC_PROCTL_CDTL_MASK;
AnnaBridge 189:f392fc9709a3 945 }
AnnaBridge 189:f392fc9709a3 946 else
AnnaBridge 189:f392fc9709a3 947 {
AnnaBridge 189:f392fc9709a3 948 base->PROCTL &= ~SDHC_PROCTL_CDTL_MASK;
AnnaBridge 189:f392fc9709a3 949 }
AnnaBridge 189:f392fc9709a3 950 }
AnnaBridge 189:f392fc9709a3 951
AnnaBridge 189:f392fc9709a3 952 /*!
AnnaBridge 189:f392fc9709a3 953 * @brief Enables or disables the SDIO card control.
AnnaBridge 189:f392fc9709a3 954 *
AnnaBridge 189:f392fc9709a3 955 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 956 * @param mask SDIO card control flags mask(_sdhc_sdio_control_flag).
AnnaBridge 189:f392fc9709a3 957 * @param enable True to enable, false to disable.
AnnaBridge 189:f392fc9709a3 958 */
AnnaBridge 189:f392fc9709a3 959 void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable);
AnnaBridge 189:f392fc9709a3 960
AnnaBridge 189:f392fc9709a3 961 /*!
AnnaBridge 189:f392fc9709a3 962 * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card.
AnnaBridge 189:f392fc9709a3 963 *
AnnaBridge 189:f392fc9709a3 964 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 965 */
AnnaBridge 189:f392fc9709a3 966 static inline void SDHC_SetContinueRequest(SDHC_Type *base)
AnnaBridge 189:f392fc9709a3 967 {
AnnaBridge 189:f392fc9709a3 968 base->PROCTL |= SDHC_PROCTL_CREQ_MASK;
AnnaBridge 189:f392fc9709a3 969 }
AnnaBridge 189:f392fc9709a3 970
AnnaBridge 189:f392fc9709a3 971 /*!
AnnaBridge 189:f392fc9709a3 972 * @brief Configures the MMC boot feature.
AnnaBridge 189:f392fc9709a3 973 *
AnnaBridge 189:f392fc9709a3 974 * Example:
AnnaBridge 189:f392fc9709a3 975 @code
AnnaBridge 189:f392fc9709a3 976 sdhc_boot_config_t config;
AnnaBridge 189:f392fc9709a3 977 config.ackTimeoutCount = 4;
AnnaBridge 189:f392fc9709a3 978 config.bootMode = kSDHC_BootModeNormal;
AnnaBridge 189:f392fc9709a3 979 config.blockCount = 5;
AnnaBridge 189:f392fc9709a3 980 config.enableBootAck = true;
AnnaBridge 189:f392fc9709a3 981 config.enableBoot = true;
AnnaBridge 189:f392fc9709a3 982 config.enableAutoStopAtBlockGap = true;
AnnaBridge 189:f392fc9709a3 983 SDHC_SetMmcBootConfig(SDHC, &config);
AnnaBridge 189:f392fc9709a3 984 @endcode
AnnaBridge 189:f392fc9709a3 985 *
AnnaBridge 189:f392fc9709a3 986 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 987 * @param config The MMC boot configuration information.
AnnaBridge 189:f392fc9709a3 988 */
AnnaBridge 189:f392fc9709a3 989 void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config);
AnnaBridge 189:f392fc9709a3 990
AnnaBridge 189:f392fc9709a3 991 /*!
AnnaBridge 189:f392fc9709a3 992 * @brief Forces generating events according to the given mask.
AnnaBridge 189:f392fc9709a3 993 *
AnnaBridge 189:f392fc9709a3 994 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 995 * @param mask The force events mask(_sdhc_force_event).
AnnaBridge 189:f392fc9709a3 996 */
AnnaBridge 189:f392fc9709a3 997 static inline void SDHC_SetForceEvent(SDHC_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 998 {
AnnaBridge 189:f392fc9709a3 999 base->FEVT = mask;
AnnaBridge 189:f392fc9709a3 1000 }
AnnaBridge 189:f392fc9709a3 1001
AnnaBridge 189:f392fc9709a3 1002 /* @} */
AnnaBridge 189:f392fc9709a3 1003
AnnaBridge 189:f392fc9709a3 1004 /*!
AnnaBridge 189:f392fc9709a3 1005 * @name Transactional
AnnaBridge 189:f392fc9709a3 1006 * @{
AnnaBridge 189:f392fc9709a3 1007 */
AnnaBridge 189:f392fc9709a3 1008
AnnaBridge 189:f392fc9709a3 1009 /*!
AnnaBridge 189:f392fc9709a3 1010 * @brief Transfers the command/data using a blocking method.
AnnaBridge 189:f392fc9709a3 1011 *
AnnaBridge 189:f392fc9709a3 1012 * This function waits until the command response/data is received or the SDHC encounters an error by polling the status
AnnaBridge 189:f392fc9709a3 1013 * flag.
AnnaBridge 189:f392fc9709a3 1014 * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
AnnaBridge 189:f392fc9709a3 1015 * the re-entry mechanism.
AnnaBridge 189:f392fc9709a3 1016 *
AnnaBridge 189:f392fc9709a3 1017 * @note There is no need to call the API 'SDHC_TransferCreateHandle' when calling this API.
AnnaBridge 189:f392fc9709a3 1018 *
AnnaBridge 189:f392fc9709a3 1019 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 1020 * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2.
AnnaBridge 189:f392fc9709a3 1021 * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2.
AnnaBridge 189:f392fc9709a3 1022 * @param transfer Transfer content.
AnnaBridge 189:f392fc9709a3 1023 * @retval kStatus_InvalidArgument Argument is invalid.
AnnaBridge 189:f392fc9709a3 1024 * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
AnnaBridge 189:f392fc9709a3 1025 * @retval kStatus_SDHC_SendCommandFailed Send command failed.
AnnaBridge 189:f392fc9709a3 1026 * @retval kStatus_SDHC_TransferDataFailed Transfer data failed.
AnnaBridge 189:f392fc9709a3 1027 * @retval kStatus_Success Operate successfully.
AnnaBridge 189:f392fc9709a3 1028 */
AnnaBridge 189:f392fc9709a3 1029 status_t SDHC_TransferBlocking(SDHC_Type *base,
AnnaBridge 189:f392fc9709a3 1030 uint32_t *admaTable,
AnnaBridge 189:f392fc9709a3 1031 uint32_t admaTableWords,
AnnaBridge 189:f392fc9709a3 1032 sdhc_transfer_t *transfer);
AnnaBridge 189:f392fc9709a3 1033
AnnaBridge 189:f392fc9709a3 1034 /*!
AnnaBridge 189:f392fc9709a3 1035 * @brief Creates the SDHC handle.
AnnaBridge 189:f392fc9709a3 1036 *
AnnaBridge 189:f392fc9709a3 1037 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 1038 * @param handle SDHC handle pointer.
AnnaBridge 189:f392fc9709a3 1039 * @param callback Structure pointer to contain all callback functions.
AnnaBridge 189:f392fc9709a3 1040 * @param userData Callback function parameter.
AnnaBridge 189:f392fc9709a3 1041 */
AnnaBridge 189:f392fc9709a3 1042 void SDHC_TransferCreateHandle(SDHC_Type *base,
AnnaBridge 189:f392fc9709a3 1043 sdhc_handle_t *handle,
AnnaBridge 189:f392fc9709a3 1044 const sdhc_transfer_callback_t *callback,
AnnaBridge 189:f392fc9709a3 1045 void *userData);
AnnaBridge 189:f392fc9709a3 1046
AnnaBridge 189:f392fc9709a3 1047 /*!
AnnaBridge 189:f392fc9709a3 1048 * @brief Transfers the command/data using an interrupt and an asynchronous method.
AnnaBridge 189:f392fc9709a3 1049 *
AnnaBridge 189:f392fc9709a3 1050 * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an
AnnaBridge 189:f392fc9709a3 1051 * error.
AnnaBridge 189:f392fc9709a3 1052 * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support
AnnaBridge 189:f392fc9709a3 1053 * the re-entry mechanism.
AnnaBridge 189:f392fc9709a3 1054 *
AnnaBridge 189:f392fc9709a3 1055 * @note Call the API 'SDHC_TransferCreateHandle' when calling this API.
AnnaBridge 189:f392fc9709a3 1056 *
AnnaBridge 189:f392fc9709a3 1057 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 1058 * @param handle SDHC handle.
AnnaBridge 189:f392fc9709a3 1059 * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2.
AnnaBridge 189:f392fc9709a3 1060 * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2.
AnnaBridge 189:f392fc9709a3 1061 * @param transfer Transfer content.
AnnaBridge 189:f392fc9709a3 1062 * @retval kStatus_InvalidArgument Argument is invalid.
AnnaBridge 189:f392fc9709a3 1063 * @retval kStatus_SDHC_BusyTransferring Busy transferring.
AnnaBridge 189:f392fc9709a3 1064 * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed.
AnnaBridge 189:f392fc9709a3 1065 * @retval kStatus_Success Operate successfully.
AnnaBridge 189:f392fc9709a3 1066 */
AnnaBridge 189:f392fc9709a3 1067 status_t SDHC_TransferNonBlocking(
AnnaBridge 189:f392fc9709a3 1068 SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer);
AnnaBridge 189:f392fc9709a3 1069
AnnaBridge 189:f392fc9709a3 1070 /*!
AnnaBridge 189:f392fc9709a3 1071 * @brief IRQ handler for the SDHC.
AnnaBridge 189:f392fc9709a3 1072 *
AnnaBridge 189:f392fc9709a3 1073 * This function deals with the IRQs on the given host controller.
AnnaBridge 189:f392fc9709a3 1074 *
AnnaBridge 189:f392fc9709a3 1075 * @param base SDHC peripheral base address.
AnnaBridge 189:f392fc9709a3 1076 * @param handle SDHC handle.
AnnaBridge 189:f392fc9709a3 1077 */
AnnaBridge 189:f392fc9709a3 1078 void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle);
AnnaBridge 189:f392fc9709a3 1079
AnnaBridge 189:f392fc9709a3 1080 /* @} */
AnnaBridge 189:f392fc9709a3 1081
AnnaBridge 189:f392fc9709a3 1082 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 1083 }
AnnaBridge 189:f392fc9709a3 1084 #endif
AnnaBridge 189:f392fc9709a3 1085 /*! @} */
AnnaBridge 189:f392fc9709a3 1086
AnnaBridge 189:f392fc9709a3 1087 #endif /* _FSL_SDHC_H_*/