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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/fsl_mpu.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 189:f392fc9709a3 1 /*
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 189:f392fc9709a3 3 * All rights reserved.
AnnaBridge 189:f392fc9709a3 4 *
AnnaBridge 189:f392fc9709a3 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 6 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 189:f392fc9709a3 9 * of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 189:f392fc9709a3 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 189:f392fc9709a3 13 * other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 14 *
AnnaBridge 189:f392fc9709a3 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 189:f392fc9709a3 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 189:f392fc9709a3 17 * software without specific prior written permission.
AnnaBridge 189:f392fc9709a3 18 *
AnnaBridge 189:f392fc9709a3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 189:f392fc9709a3 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 189:f392fc9709a3 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 189:f392fc9709a3 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 189:f392fc9709a3 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 189:f392fc9709a3 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 189:f392fc9709a3 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 189:f392fc9709a3 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 189:f392fc9709a3 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 29 */
AnnaBridge 189:f392fc9709a3 30 #ifndef _FSL_MPU_H_
AnnaBridge 189:f392fc9709a3 31 #define _FSL_MPU_H_
AnnaBridge 189:f392fc9709a3 32
AnnaBridge 189:f392fc9709a3 33 #include "fsl_common.h"
AnnaBridge 189:f392fc9709a3 34
AnnaBridge 189:f392fc9709a3 35 /*!
AnnaBridge 189:f392fc9709a3 36 * @addtogroup mpu
AnnaBridge 189:f392fc9709a3 37 * @{
AnnaBridge 189:f392fc9709a3 38 */
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40
AnnaBridge 189:f392fc9709a3 41 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 42 * Definitions
AnnaBridge 189:f392fc9709a3 43 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 44
AnnaBridge 189:f392fc9709a3 45 /*! @name Driver version */
AnnaBridge 189:f392fc9709a3 46 /*@{*/
AnnaBridge 189:f392fc9709a3 47 /*! @brief MPU driver version 2.1.0. */
AnnaBridge 189:f392fc9709a3 48 #define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
AnnaBridge 189:f392fc9709a3 49 /*@}*/
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 /*! @brief MPU the bit shift for masters with privilege rights: read write and execute. */
AnnaBridge 189:f392fc9709a3 52 #define MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6)
AnnaBridge 189:f392fc9709a3 53
AnnaBridge 189:f392fc9709a3 54 /*! @brief MPU masters with read, write and execute rights bit mask. */
AnnaBridge 189:f392fc9709a3 55 #define MPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))
AnnaBridge 189:f392fc9709a3 56
AnnaBridge 189:f392fc9709a3 57 /*! @brief MPU masters with read, write and execute rights bit width. */
AnnaBridge 189:f392fc9709a3 58 #define MPU_REGION_RWXRIGHTS_MASTER_WIDTH 5
AnnaBridge 189:f392fc9709a3 59
AnnaBridge 189:f392fc9709a3 60 /*! @brief MPU masters with read, write and execute rights priority setting. */
AnnaBridge 189:f392fc9709a3 61 #define MPU_REGION_RWXRIGHTS_MASTER(n, x) \
AnnaBridge 189:f392fc9709a3 62 (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_MASK(n))
AnnaBridge 189:f392fc9709a3 63
AnnaBridge 189:f392fc9709a3 64 /*! @brief MPU masters with read, write and execute rights process enable bit shift. */
AnnaBridge 189:f392fc9709a3 65 #define MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + MPU_REGION_RWXRIGHTS_MASTER_WIDTH)
AnnaBridge 189:f392fc9709a3 66
AnnaBridge 189:f392fc9709a3 67 /*! @brief MPU masters with read, write and execute rights process enable bit mask. */
AnnaBridge 189:f392fc9709a3 68 #define MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))
AnnaBridge 189:f392fc9709a3 69
AnnaBridge 189:f392fc9709a3 70 /*! @brief MPU masters with read, write and execute rights process enable setting. */
AnnaBridge 189:f392fc9709a3 71 #define MPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \
AnnaBridge 189:f392fc9709a3 72 (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n))
AnnaBridge 189:f392fc9709a3 73
AnnaBridge 189:f392fc9709a3 74 /*! @brief MPU masters with normal read write permission bit shift. */
AnnaBridge 189:f392fc9709a3 75 #define MPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT) * 2 + 24)
AnnaBridge 189:f392fc9709a3 76
AnnaBridge 189:f392fc9709a3 77 /*! @brief MPU masters with normal read write rights bit mask. */
AnnaBridge 189:f392fc9709a3 78 #define MPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))
AnnaBridge 189:f392fc9709a3 79
AnnaBridge 189:f392fc9709a3 80 /*! @brief MPU masters with normal read write rights priority setting. */
AnnaBridge 189:f392fc9709a3 81 #define MPU_REGION_RWRIGHTS_MASTER(n, x) \
AnnaBridge 189:f392fc9709a3 82 (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWRIGHTS_MASTER_MASK(n))
AnnaBridge 189:f392fc9709a3 83
AnnaBridge 189:f392fc9709a3 84 /*! @brief the Slave port numbers. */
AnnaBridge 189:f392fc9709a3 85 #define MPU_SLAVE_PORT_NUM (4u)
AnnaBridge 189:f392fc9709a3 86 /*! @brief define the maximum index of master with privileged rights. */
AnnaBridge 189:f392fc9709a3 87 #define MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX (3)
AnnaBridge 189:f392fc9709a3 88
AnnaBridge 189:f392fc9709a3 89 /*! @brief Describes the number of MPU regions. */
AnnaBridge 189:f392fc9709a3 90 typedef enum _mpu_region_total_num
AnnaBridge 189:f392fc9709a3 91 {
AnnaBridge 189:f392fc9709a3 92 kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */
AnnaBridge 189:f392fc9709a3 93 kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
AnnaBridge 189:f392fc9709a3 94 kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */
AnnaBridge 189:f392fc9709a3 95 } mpu_region_total_num_t;
AnnaBridge 189:f392fc9709a3 96
AnnaBridge 189:f392fc9709a3 97 /*! @brief MPU slave port number. */
AnnaBridge 189:f392fc9709a3 98 typedef enum _mpu_slave
AnnaBridge 189:f392fc9709a3 99 {
AnnaBridge 189:f392fc9709a3 100 kMPU_Slave0 = 0U, /*!< MPU slave port 0. */
AnnaBridge 189:f392fc9709a3 101 kMPU_Slave1 = 1U, /*!< MPU slave port 1. */
AnnaBridge 189:f392fc9709a3 102 kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
AnnaBridge 189:f392fc9709a3 103 kMPU_Slave3 = 3U, /*!< MPU slave port 3. */
AnnaBridge 189:f392fc9709a3 104 kMPU_Slave4 = 4U /*!< MPU slave port 4. */
AnnaBridge 189:f392fc9709a3 105 } mpu_slave_t;
AnnaBridge 189:f392fc9709a3 106
AnnaBridge 189:f392fc9709a3 107 /*! @brief MPU error access control detail. */
AnnaBridge 189:f392fc9709a3 108 typedef enum _mpu_err_access_control
AnnaBridge 189:f392fc9709a3 109 {
AnnaBridge 189:f392fc9709a3 110 kMPU_NoRegionHit = 0U, /*!< No region hit error. */
AnnaBridge 189:f392fc9709a3 111 kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
AnnaBridge 189:f392fc9709a3 112 kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */
AnnaBridge 189:f392fc9709a3 113 } mpu_err_access_control_t;
AnnaBridge 189:f392fc9709a3 114
AnnaBridge 189:f392fc9709a3 115 /*! @brief MPU error access type. */
AnnaBridge 189:f392fc9709a3 116 typedef enum _mpu_err_access_type
AnnaBridge 189:f392fc9709a3 117 {
AnnaBridge 189:f392fc9709a3 118 kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */
AnnaBridge 189:f392fc9709a3 119 kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
AnnaBridge 189:f392fc9709a3 120 } mpu_err_access_type_t;
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 /*! @brief MPU access error attributes.*/
AnnaBridge 189:f392fc9709a3 123 typedef enum _mpu_err_attributes
AnnaBridge 189:f392fc9709a3 124 {
AnnaBridge 189:f392fc9709a3 125 kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */
AnnaBridge 189:f392fc9709a3 126 kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */
AnnaBridge 189:f392fc9709a3 127 kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
AnnaBridge 189:f392fc9709a3 128 kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */
AnnaBridge 189:f392fc9709a3 129 } mpu_err_attributes_t;
AnnaBridge 189:f392fc9709a3 130
AnnaBridge 189:f392fc9709a3 131 /*! @brief MPU access rights in supervisor mode for bus master 0 ~ 3. */
AnnaBridge 189:f392fc9709a3 132 typedef enum _mpu_supervisor_access_rights
AnnaBridge 189:f392fc9709a3 133 {
AnnaBridge 189:f392fc9709a3 134 kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
AnnaBridge 189:f392fc9709a3 135 kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */
AnnaBridge 189:f392fc9709a3 136 kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */
AnnaBridge 189:f392fc9709a3 137 kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */
AnnaBridge 189:f392fc9709a3 138 } mpu_supervisor_access_rights_t;
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 /*! @brief MPU access rights in user mode for bus master 0 ~ 3. */
AnnaBridge 189:f392fc9709a3 141 typedef enum _mpu_user_access_rights
AnnaBridge 189:f392fc9709a3 142 {
AnnaBridge 189:f392fc9709a3 143 kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */
AnnaBridge 189:f392fc9709a3 144 kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */
AnnaBridge 189:f392fc9709a3 145 kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */
AnnaBridge 189:f392fc9709a3 146 kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */
AnnaBridge 189:f392fc9709a3 147 kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */
AnnaBridge 189:f392fc9709a3 148 kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */
AnnaBridge 189:f392fc9709a3 149 kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */
AnnaBridge 189:f392fc9709a3 150 kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
AnnaBridge 189:f392fc9709a3 151 } mpu_user_access_rights_t;
AnnaBridge 189:f392fc9709a3 152
AnnaBridge 189:f392fc9709a3 153 /*! @brief MPU hardware basic information. */
AnnaBridge 189:f392fc9709a3 154 typedef struct _mpu_hardware_info
AnnaBridge 189:f392fc9709a3 155 {
AnnaBridge 189:f392fc9709a3 156 uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */
AnnaBridge 189:f392fc9709a3 157 uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */
AnnaBridge 189:f392fc9709a3 158 mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
AnnaBridge 189:f392fc9709a3 159 } mpu_hardware_info_t;
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 /*! @brief MPU detail error access information. */
AnnaBridge 189:f392fc9709a3 162 typedef struct _mpu_access_err_info
AnnaBridge 189:f392fc9709a3 163 {
AnnaBridge 189:f392fc9709a3 164 uint32_t master; /*!< Access error master. */
AnnaBridge 189:f392fc9709a3 165 mpu_err_attributes_t attributes; /*!< Access error attributes. */
AnnaBridge 189:f392fc9709a3 166 mpu_err_access_type_t accessType; /*!< Access error type. */
AnnaBridge 189:f392fc9709a3 167 mpu_err_access_control_t accessControl; /*!< Access error control. */
AnnaBridge 189:f392fc9709a3 168 uint32_t address; /*!< Access error address. */
AnnaBridge 189:f392fc9709a3 169 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
AnnaBridge 189:f392fc9709a3 170 uint8_t processorIdentification; /*!< Access error processor identification. */
AnnaBridge 189:f392fc9709a3 171 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
AnnaBridge 189:f392fc9709a3 172 } mpu_access_err_info_t;
AnnaBridge 189:f392fc9709a3 173
AnnaBridge 189:f392fc9709a3 174 /*! @brief MPU read/write/execute rights control for bus master 0 ~ 3. */
AnnaBridge 189:f392fc9709a3 175 typedef struct _mpu_rwxrights_master_access_control
AnnaBridge 189:f392fc9709a3 176 {
AnnaBridge 189:f392fc9709a3 177 mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
AnnaBridge 189:f392fc9709a3 178 mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */
AnnaBridge 189:f392fc9709a3 179 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
AnnaBridge 189:f392fc9709a3 180 bool processIdentifierEnable; /*!< Enables or disables process identifier. */
AnnaBridge 189:f392fc9709a3 181 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
AnnaBridge 189:f392fc9709a3 182 } mpu_rwxrights_master_access_control_t;
AnnaBridge 189:f392fc9709a3 183
AnnaBridge 189:f392fc9709a3 184 /*! @brief MPU read/write access control for bus master 4 ~ 7. */
AnnaBridge 189:f392fc9709a3 185 typedef struct _mpu_rwrights_master_access_control
AnnaBridge 189:f392fc9709a3 186 {
AnnaBridge 189:f392fc9709a3 187 bool writeEnable; /*!< Enables or disables write permission. */
AnnaBridge 189:f392fc9709a3 188 bool readEnable; /*!< Enables or disables read permission. */
AnnaBridge 189:f392fc9709a3 189 } mpu_rwrights_master_access_control_t;
AnnaBridge 189:f392fc9709a3 190
AnnaBridge 189:f392fc9709a3 191 /*!
AnnaBridge 189:f392fc9709a3 192 * @brief MPU region configuration structure.
AnnaBridge 189:f392fc9709a3 193 *
AnnaBridge 189:f392fc9709a3 194 * This structure is used to configure the regionNum region.
AnnaBridge 189:f392fc9709a3 195 * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master
AnnaBridge 189:f392fc9709a3 196 * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3]
AnnaBridge 189:f392fc9709a3 197 * are used to configure the high master 4 ~ 7 with the normal read write permission.
AnnaBridge 189:f392fc9709a3 198 * The master port assignment is the chip configuration. Normally, the core is the
AnnaBridge 189:f392fc9709a3 199 * master 0, debugger is the master 1.
AnnaBridge 189:f392fc9709a3 200 * Note that the MPU assigns a priority scheme where the debugger is treated as the highest
AnnaBridge 189:f392fc9709a3 201 * priority master followed by the core and then all the remaining masters.
AnnaBridge 189:f392fc9709a3 202 * MPU protection does not allow writes from the core to affect the "regionNum 0" start
AnnaBridge 189:f392fc9709a3 203 * and end address nor the permissions associated with the debugger. It can only write
AnnaBridge 189:f392fc9709a3 204 * the permission fields associated with the other masters. This protection guarantees that
AnnaBridge 189:f392fc9709a3 205 * the debugger always has access to the entire address space and those rights can't
AnnaBridge 189:f392fc9709a3 206 * be changed by the core or any other bus master. Prepare
AnnaBridge 189:f392fc9709a3 207 * the region configuration when regionNum is 0.
AnnaBridge 189:f392fc9709a3 208 */
AnnaBridge 189:f392fc9709a3 209 typedef struct _mpu_region_config
AnnaBridge 189:f392fc9709a3 210 {
AnnaBridge 189:f392fc9709a3 211 uint32_t regionNum; /*!< MPU region number, range form 0 ~ FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. */
AnnaBridge 189:f392fc9709a3 212 uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
AnnaBridge 189:f392fc9709a3 213 start address is 0-modulo-32 byte address. */
AnnaBridge 189:f392fc9709a3 214 uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
AnnaBridge 189:f392fc9709a3 215 address is 31-modulo-32 byte address. */
AnnaBridge 189:f392fc9709a3 216 mpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */
AnnaBridge 189:f392fc9709a3 217 mpu_rwrights_master_access_control_t accessRights2[4]; /*!< Masters with normal read write rights setting. */
AnnaBridge 189:f392fc9709a3 218 #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
AnnaBridge 189:f392fc9709a3 219 uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
AnnaBridge 189:f392fc9709a3 220 uint8_t
AnnaBridge 189:f392fc9709a3 221 processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
AnnaBridge 189:f392fc9709a3 222 #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
AnnaBridge 189:f392fc9709a3 223 } mpu_region_config_t;
AnnaBridge 189:f392fc9709a3 224
AnnaBridge 189:f392fc9709a3 225 /*!
AnnaBridge 189:f392fc9709a3 226 * @brief The configuration structure for the MPU initialization.
AnnaBridge 189:f392fc9709a3 227 *
AnnaBridge 189:f392fc9709a3 228 * This structure is used when calling the MPU_Init function.
AnnaBridge 189:f392fc9709a3 229 */
AnnaBridge 189:f392fc9709a3 230 typedef struct _mpu_config
AnnaBridge 189:f392fc9709a3 231 {
AnnaBridge 189:f392fc9709a3 232 mpu_region_config_t regionConfig; /*!< Region access permission. */
AnnaBridge 189:f392fc9709a3 233 struct _mpu_config *next; /*!< Pointer to the next structure. */
AnnaBridge 189:f392fc9709a3 234 } mpu_config_t;
AnnaBridge 189:f392fc9709a3 235
AnnaBridge 189:f392fc9709a3 236 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 237 * API
AnnaBridge 189:f392fc9709a3 238 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 239
AnnaBridge 189:f392fc9709a3 240 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 241 extern "C" {
AnnaBridge 189:f392fc9709a3 242 #endif /* _cplusplus */
AnnaBridge 189:f392fc9709a3 243
AnnaBridge 189:f392fc9709a3 244 /*!
AnnaBridge 189:f392fc9709a3 245 * @name Initialization and deinitialization
AnnaBridge 189:f392fc9709a3 246 * @{
AnnaBridge 189:f392fc9709a3 247 */
AnnaBridge 189:f392fc9709a3 248
AnnaBridge 189:f392fc9709a3 249 /*!
AnnaBridge 189:f392fc9709a3 250 * @brief Initializes the MPU with the user configuration structure.
AnnaBridge 189:f392fc9709a3 251 *
AnnaBridge 189:f392fc9709a3 252 * This function configures the MPU module with the user-defined configuration.
AnnaBridge 189:f392fc9709a3 253 *
AnnaBridge 189:f392fc9709a3 254 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 255 * @param config The pointer to the configuration structure.
AnnaBridge 189:f392fc9709a3 256 */
AnnaBridge 189:f392fc9709a3 257 void MPU_Init(MPU_Type *base, const mpu_config_t *config);
AnnaBridge 189:f392fc9709a3 258
AnnaBridge 189:f392fc9709a3 259 /*!
AnnaBridge 189:f392fc9709a3 260 * @brief Deinitializes the MPU regions.
AnnaBridge 189:f392fc9709a3 261 *
AnnaBridge 189:f392fc9709a3 262 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 263 */
AnnaBridge 189:f392fc9709a3 264 void MPU_Deinit(MPU_Type *base);
AnnaBridge 189:f392fc9709a3 265
AnnaBridge 189:f392fc9709a3 266 /* @}*/
AnnaBridge 189:f392fc9709a3 267
AnnaBridge 189:f392fc9709a3 268 /*!
AnnaBridge 189:f392fc9709a3 269 * @name Basic Control Operations
AnnaBridge 189:f392fc9709a3 270 * @{
AnnaBridge 189:f392fc9709a3 271 */
AnnaBridge 189:f392fc9709a3 272
AnnaBridge 189:f392fc9709a3 273 /*!
AnnaBridge 189:f392fc9709a3 274 * @brief Enables/disables the MPU globally.
AnnaBridge 189:f392fc9709a3 275 *
AnnaBridge 189:f392fc9709a3 276 * Call this API to enable or disable the MPU module.
AnnaBridge 189:f392fc9709a3 277 *
AnnaBridge 189:f392fc9709a3 278 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 279 * @param enable True enable MPU, false disable MPU.
AnnaBridge 189:f392fc9709a3 280 */
AnnaBridge 189:f392fc9709a3 281 static inline void MPU_Enable(MPU_Type *base, bool enable)
AnnaBridge 189:f392fc9709a3 282 {
AnnaBridge 189:f392fc9709a3 283 if (enable)
AnnaBridge 189:f392fc9709a3 284 {
AnnaBridge 189:f392fc9709a3 285 /* Enable the MPU globally. */
AnnaBridge 189:f392fc9709a3 286 base->CESR |= MPU_CESR_VLD_MASK;
AnnaBridge 189:f392fc9709a3 287 }
AnnaBridge 189:f392fc9709a3 288 else
AnnaBridge 189:f392fc9709a3 289 { /* Disable the MPU globally. */
AnnaBridge 189:f392fc9709a3 290 base->CESR &= ~MPU_CESR_VLD_MASK;
AnnaBridge 189:f392fc9709a3 291 }
AnnaBridge 189:f392fc9709a3 292 }
AnnaBridge 189:f392fc9709a3 293
AnnaBridge 189:f392fc9709a3 294 /*!
AnnaBridge 189:f392fc9709a3 295 * @brief Enables/disables the MPU for a special region.
AnnaBridge 189:f392fc9709a3 296 *
AnnaBridge 189:f392fc9709a3 297 * When MPU is enabled, call this API to disable an unused region
AnnaBridge 189:f392fc9709a3 298 * of an enabled MPU. Call this API to minimize the power dissipation.
AnnaBridge 189:f392fc9709a3 299 *
AnnaBridge 189:f392fc9709a3 300 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 301 * @param number MPU region number.
AnnaBridge 189:f392fc9709a3 302 * @param enable True enable the special region MPU, false disable the special region MPU.
AnnaBridge 189:f392fc9709a3 303 */
AnnaBridge 189:f392fc9709a3 304 static inline void MPU_RegionEnable(MPU_Type *base, uint32_t number, bool enable)
AnnaBridge 189:f392fc9709a3 305 {
AnnaBridge 189:f392fc9709a3 306 if (enable)
AnnaBridge 189:f392fc9709a3 307 {
AnnaBridge 189:f392fc9709a3 308 /* Enable the #number region MPU. */
AnnaBridge 189:f392fc9709a3 309 base->WORD[number][3] |= MPU_WORD_VLD_MASK;
AnnaBridge 189:f392fc9709a3 310 }
AnnaBridge 189:f392fc9709a3 311 else
AnnaBridge 189:f392fc9709a3 312 { /* Disable the #number region MPU. */
AnnaBridge 189:f392fc9709a3 313 base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
AnnaBridge 189:f392fc9709a3 314 }
AnnaBridge 189:f392fc9709a3 315 }
AnnaBridge 189:f392fc9709a3 316
AnnaBridge 189:f392fc9709a3 317 /*!
AnnaBridge 189:f392fc9709a3 318 * @brief Gets the MPU basic hardware information.
AnnaBridge 189:f392fc9709a3 319 *
AnnaBridge 189:f392fc9709a3 320 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 321 * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
AnnaBridge 189:f392fc9709a3 322 */
AnnaBridge 189:f392fc9709a3 323 void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
AnnaBridge 189:f392fc9709a3 324
AnnaBridge 189:f392fc9709a3 325 /*!
AnnaBridge 189:f392fc9709a3 326 * @brief Sets the MPU region.
AnnaBridge 189:f392fc9709a3 327 *
AnnaBridge 189:f392fc9709a3 328 * Note: Due to the MPU protection, the region number 0 does not allow writes from
AnnaBridge 189:f392fc9709a3 329 * core to affect the start and end address nor the permissions associated with
AnnaBridge 189:f392fc9709a3 330 * the debugger. It can only write the permission fields associated
AnnaBridge 189:f392fc9709a3 331 * with the other masters.
AnnaBridge 189:f392fc9709a3 332 *
AnnaBridge 189:f392fc9709a3 333 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 334 * @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t".
AnnaBridge 189:f392fc9709a3 335 */
AnnaBridge 189:f392fc9709a3 336 void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
AnnaBridge 189:f392fc9709a3 337
AnnaBridge 189:f392fc9709a3 338 /*!
AnnaBridge 189:f392fc9709a3 339 * @brief Sets the region start and end address.
AnnaBridge 189:f392fc9709a3 340 *
AnnaBridge 189:f392fc9709a3 341 * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
AnnaBridge 189:f392fc9709a3 342 * The actual start address by MPU is 0-modulo-32 byte address.
AnnaBridge 189:f392fc9709a3 343 * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
AnnaBridge 189:f392fc9709a3 344 * The end address used by the MPU is 31-modulo-32 byte address.
AnnaBridge 189:f392fc9709a3 345 * Note: Due to the MPU protection, the startAddr and endAddr can't be
AnnaBridge 189:f392fc9709a3 346 * changed by the core when regionNum is 0.
AnnaBridge 189:f392fc9709a3 347 *
AnnaBridge 189:f392fc9709a3 348 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 349 * @param regionNum MPU region number. The range is from 0 to
AnnaBridge 189:f392fc9709a3 350 * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
AnnaBridge 189:f392fc9709a3 351 * @param startAddr Region start address.
AnnaBridge 189:f392fc9709a3 352 * @param endAddr Region end address.
AnnaBridge 189:f392fc9709a3 353 */
AnnaBridge 189:f392fc9709a3 354 void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr);
AnnaBridge 189:f392fc9709a3 355
AnnaBridge 189:f392fc9709a3 356 /*!
AnnaBridge 189:f392fc9709a3 357 * @brief Sets the MPU region access rights for masters with read, write, and execute rights.
AnnaBridge 189:f392fc9709a3 358 * The MPU access rights depend on two board classifications of bus masters.
AnnaBridge 189:f392fc9709a3 359 * The privilege rights masters and the normal rights masters.
AnnaBridge 189:f392fc9709a3 360 * The privilege rights masters have the read, write, and execute access rights.
AnnaBridge 189:f392fc9709a3 361 * Except the normal read and write rights, the execute rights are also
AnnaBridge 189:f392fc9709a3 362 * allowed for these masters. The privilege rights masters normally range from
AnnaBridge 189:f392fc9709a3 363 * bus masters 0 - 3. However, the maximum master number is device-specific.
AnnaBridge 189:f392fc9709a3 364 * See the "MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX".
AnnaBridge 189:f392fc9709a3 365 * The normal rights masters access rights control see
AnnaBridge 189:f392fc9709a3 366 * "MPU_SetRegionRwMasterAccessRights()".
AnnaBridge 189:f392fc9709a3 367 *
AnnaBridge 189:f392fc9709a3 368 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 369 * @param regionNum MPU region number. Should range from 0 to
AnnaBridge 189:f392fc9709a3 370 * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
AnnaBridge 189:f392fc9709a3 371 * @param masterNum MPU bus master number. Should range from 0 to
AnnaBridge 189:f392fc9709a3 372 * MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX.
AnnaBridge 189:f392fc9709a3 373 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwxrights_master_access_control_t".
AnnaBridge 189:f392fc9709a3 374 */
AnnaBridge 189:f392fc9709a3 375 void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base,
AnnaBridge 189:f392fc9709a3 376 uint32_t regionNum,
AnnaBridge 189:f392fc9709a3 377 uint32_t masterNum,
AnnaBridge 189:f392fc9709a3 378 const mpu_rwxrights_master_access_control_t *accessRights);
AnnaBridge 189:f392fc9709a3 379 #if FSL_FEATURE_MPU_HAS_MASTER_4_7
AnnaBridge 189:f392fc9709a3 380 /*!
AnnaBridge 189:f392fc9709a3 381 * @brief Sets the MPU region access rights for masters with read and write rights.
AnnaBridge 189:f392fc9709a3 382 * The MPU access rights depend on two board classifications of bus masters.
AnnaBridge 189:f392fc9709a3 383 * The privilege rights masters and the normal rights masters.
AnnaBridge 189:f392fc9709a3 384 * The normal rights masters only have the read and write access permissions.
AnnaBridge 189:f392fc9709a3 385 * The privilege rights access control see "MPU_SetRegionRwxMasterAccessRights".
AnnaBridge 189:f392fc9709a3 386 *
AnnaBridge 189:f392fc9709a3 387 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 388 * @param regionNum MPU region number. The range is from 0 to
AnnaBridge 189:f392fc9709a3 389 * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
AnnaBridge 189:f392fc9709a3 390 * @param masterNum MPU bus master number. Should range from FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT
AnnaBridge 189:f392fc9709a3 391 * to ~ FSL_FEATURE_MPU_MASTER_MAX_INDEX.
AnnaBridge 189:f392fc9709a3 392 * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwrights_master_access_control_t".
AnnaBridge 189:f392fc9709a3 393 */
AnnaBridge 189:f392fc9709a3 394 void MPU_SetRegionRwMasterAccessRights(MPU_Type *base,
AnnaBridge 189:f392fc9709a3 395 uint32_t regionNum,
AnnaBridge 189:f392fc9709a3 396 uint32_t masterNum,
AnnaBridge 189:f392fc9709a3 397 const mpu_rwrights_master_access_control_t *accessRights);
AnnaBridge 189:f392fc9709a3 398 #endif /* FSL_FEATURE_MPU_HAS_MASTER_4_7 */
AnnaBridge 189:f392fc9709a3 399 /*!
AnnaBridge 189:f392fc9709a3 400 * @brief Gets the numbers of slave ports where errors occur.
AnnaBridge 189:f392fc9709a3 401 *
AnnaBridge 189:f392fc9709a3 402 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 403 * @param slaveNum MPU slave port number.
AnnaBridge 189:f392fc9709a3 404 * @return The slave ports error status.
AnnaBridge 189:f392fc9709a3 405 * true - error happens in this slave port.
AnnaBridge 189:f392fc9709a3 406 * false - error didn't happen in this slave port.
AnnaBridge 189:f392fc9709a3 407 */
AnnaBridge 189:f392fc9709a3 408 bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
AnnaBridge 189:f392fc9709a3 409
AnnaBridge 189:f392fc9709a3 410 /*!
AnnaBridge 189:f392fc9709a3 411 * @brief Gets the MPU detailed error access information.
AnnaBridge 189:f392fc9709a3 412 *
AnnaBridge 189:f392fc9709a3 413 * @param base MPU peripheral base address.
AnnaBridge 189:f392fc9709a3 414 * @param slaveNum MPU slave port number.
AnnaBridge 189:f392fc9709a3 415 * @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t".
AnnaBridge 189:f392fc9709a3 416 */
AnnaBridge 189:f392fc9709a3 417 void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
AnnaBridge 189:f392fc9709a3 418
AnnaBridge 189:f392fc9709a3 419 /* @} */
AnnaBridge 189:f392fc9709a3 420
AnnaBridge 189:f392fc9709a3 421 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 422 }
AnnaBridge 189:f392fc9709a3 423 #endif
AnnaBridge 189:f392fc9709a3 424
AnnaBridge 189:f392fc9709a3 425 /*! @}*/
AnnaBridge 189:f392fc9709a3 426
AnnaBridge 189:f392fc9709a3 427 #endif /* _FSL_MPU_H_ */