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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/fsl_lmem_cache.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 189:f392fc9709a3 1 /*
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 189:f392fc9709a3 3 * All rights reserved.
AnnaBridge 189:f392fc9709a3 4 *
AnnaBridge 189:f392fc9709a3 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 6 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 189:f392fc9709a3 9 * of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 189:f392fc9709a3 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 189:f392fc9709a3 13 * other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 14 *
AnnaBridge 189:f392fc9709a3 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 189:f392fc9709a3 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 189:f392fc9709a3 17 * software without specific prior written permission.
AnnaBridge 189:f392fc9709a3 18 *
AnnaBridge 189:f392fc9709a3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 189:f392fc9709a3 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 189:f392fc9709a3 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 189:f392fc9709a3 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 189:f392fc9709a3 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 189:f392fc9709a3 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 189:f392fc9709a3 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 189:f392fc9709a3 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 189:f392fc9709a3 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 29 */
AnnaBridge 189:f392fc9709a3 30 #ifndef _FSL_LMEM_CACHE_H_
AnnaBridge 189:f392fc9709a3 31 #define _FSL_LMEM_CACHE_H_
AnnaBridge 189:f392fc9709a3 32
AnnaBridge 189:f392fc9709a3 33 #include "fsl_common.h"
AnnaBridge 189:f392fc9709a3 34
AnnaBridge 189:f392fc9709a3 35 /*!
AnnaBridge 189:f392fc9709a3 36 * @addtogroup lmem_cache
AnnaBridge 189:f392fc9709a3 37 * @{
AnnaBridge 189:f392fc9709a3 38 */
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40
AnnaBridge 189:f392fc9709a3 41 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 42 * Definitions
AnnaBridge 189:f392fc9709a3 43 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 44
AnnaBridge 189:f392fc9709a3 45 /*! @name Driver version */
AnnaBridge 189:f392fc9709a3 46 /*@{*/
AnnaBridge 189:f392fc9709a3 47 /*! @brief LMEM controller driver version 2.1.0. */
AnnaBridge 189:f392fc9709a3 48 #define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
AnnaBridge 189:f392fc9709a3 49 /*@}*/
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 #define LMEM_CACHE_LINE_SIZE (0x10U) /*!< Cache line is 16-bytes. */
AnnaBridge 189:f392fc9709a3 52 #define LMEM_CACHE_SIZE_ONEWAY (4096U) /*!< Cache size is 4K-bytes one way. */
AnnaBridge 189:f392fc9709a3 53
AnnaBridge 189:f392fc9709a3 54 /*! @brief LMEM cache mode options. */
AnnaBridge 189:f392fc9709a3 55 typedef enum _lmem_cache_mode
AnnaBridge 189:f392fc9709a3 56 {
AnnaBridge 189:f392fc9709a3 57 kLMEM_NonCacheable = 0x0U, /*!< Cache mode: non-cacheable. */
AnnaBridge 189:f392fc9709a3 58 kLMEM_CacheWriteThrough = 0x2U, /*!< Cache mode: write-through. */
AnnaBridge 189:f392fc9709a3 59 kLMEM_CacheWriteBack = 0x3U /*!< Cache mode: write-back. */
AnnaBridge 189:f392fc9709a3 60 } lmem_cache_mode_t;
AnnaBridge 189:f392fc9709a3 61
AnnaBridge 189:f392fc9709a3 62 /*! @brief LMEM cache regions. */
AnnaBridge 189:f392fc9709a3 63 typedef enum _lmem_cache_region
AnnaBridge 189:f392fc9709a3 64 {
AnnaBridge 189:f392fc9709a3 65 kLMEM_CacheRegion15 = 0U, /*!< Cache Region 15. */
AnnaBridge 189:f392fc9709a3 66 kLMEM_CacheRegion14, /*!< Cache Region 14. */
AnnaBridge 189:f392fc9709a3 67 kLMEM_CacheRegion13, /*!< Cache Region 13. */
AnnaBridge 189:f392fc9709a3 68 kLMEM_CacheRegion12, /*!< Cache Region 12. */
AnnaBridge 189:f392fc9709a3 69 kLMEM_CacheRegion11, /*!< Cache Region 11. */
AnnaBridge 189:f392fc9709a3 70 kLMEM_CacheRegion10, /*!< Cache Region 10. */
AnnaBridge 189:f392fc9709a3 71 kLMEM_CacheRegion9, /*!< Cache Region 9. */
AnnaBridge 189:f392fc9709a3 72 kLMEM_CacheRegion8, /*!< Cache Region 8. */
AnnaBridge 189:f392fc9709a3 73 kLMEM_CacheRegion7, /*!< Cache Region 7. */
AnnaBridge 189:f392fc9709a3 74 kLMEM_CacheRegion6, /*!< Cache Region 6. */
AnnaBridge 189:f392fc9709a3 75 kLMEM_CacheRegion5, /*!< Cache Region 5. */
AnnaBridge 189:f392fc9709a3 76 kLMEM_CacheRegion4, /*!< Cache Region 4. */
AnnaBridge 189:f392fc9709a3 77 kLMEM_CacheRegion3, /*!< Cache Region 3. */
AnnaBridge 189:f392fc9709a3 78 kLMEM_CacheRegion2, /*!< Cache Region 2. */
AnnaBridge 189:f392fc9709a3 79 kLMEM_CacheRegion1, /*!< Cache Region 1. */
AnnaBridge 189:f392fc9709a3 80 kLMEM_CacheRegion0 /*!< Cache Region 0. */
AnnaBridge 189:f392fc9709a3 81 } lmem_cache_region_t;
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 /*! @brief LMEM cache line command. */
AnnaBridge 189:f392fc9709a3 84 typedef enum _lmem_cache_line_command
AnnaBridge 189:f392fc9709a3 85 {
AnnaBridge 189:f392fc9709a3 86 kLMEM_CacheLineSearchReadOrWrite = 0U, /*!< Cache line search and read or write. */
AnnaBridge 189:f392fc9709a3 87 kLMEM_CacheLineInvalidate, /*!< Cache line invalidate. */
AnnaBridge 189:f392fc9709a3 88 kLMEM_CacheLinePush, /*!< Cache line push. */
AnnaBridge 189:f392fc9709a3 89 kLMEM_CacheLineClear, /*!< Cache line clear. */
AnnaBridge 189:f392fc9709a3 90 } lmem_cache_line_command_t;
AnnaBridge 189:f392fc9709a3 91
AnnaBridge 189:f392fc9709a3 92 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 93 * API
AnnaBridge 189:f392fc9709a3 94 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 95
AnnaBridge 189:f392fc9709a3 96 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 97 extern "C" {
AnnaBridge 189:f392fc9709a3 98 #endif
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 /*!
AnnaBridge 189:f392fc9709a3 101 * @name Local Memory Processor Code Bus Cache Control
AnnaBridge 189:f392fc9709a3 102 *@{
AnnaBridge 189:f392fc9709a3 103 */
AnnaBridge 189:f392fc9709a3 104
AnnaBridge 189:f392fc9709a3 105 /*!
AnnaBridge 189:f392fc9709a3 106 * @brief Enables/disables the processor code bus cache.
AnnaBridge 189:f392fc9709a3 107 * This function enables/disables the cache. The function first invalidates the entire cache
AnnaBridge 189:f392fc9709a3 108 * and then enables/disables both the cache and write buffers.
AnnaBridge 189:f392fc9709a3 109 *
AnnaBridge 189:f392fc9709a3 110 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 111 * @param enable The enable or disable flag.
AnnaBridge 189:f392fc9709a3 112 * true - enable the code cache.
AnnaBridge 189:f392fc9709a3 113 * false - disable the code cache.
AnnaBridge 189:f392fc9709a3 114 */
AnnaBridge 189:f392fc9709a3 115 void LMEM_EnableCodeCache(LMEM_Type *base, bool enable);
AnnaBridge 189:f392fc9709a3 116
AnnaBridge 189:f392fc9709a3 117 /*!
AnnaBridge 189:f392fc9709a3 118 * @brief Enables/disables the processor code bus write buffer.
AnnaBridge 189:f392fc9709a3 119 *
AnnaBridge 189:f392fc9709a3 120 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 121 * @param enable The enable or disable flag.
AnnaBridge 189:f392fc9709a3 122 * true - enable the code bus write buffer.
AnnaBridge 189:f392fc9709a3 123 * false - disable the code bus write buffer.
AnnaBridge 189:f392fc9709a3 124 */
AnnaBridge 189:f392fc9709a3 125 static inline void LMEM_EnableCodeWriteBuffer(LMEM_Type *base, bool enable)
AnnaBridge 189:f392fc9709a3 126 {
AnnaBridge 189:f392fc9709a3 127 if (enable)
AnnaBridge 189:f392fc9709a3 128 {
AnnaBridge 189:f392fc9709a3 129 base->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
AnnaBridge 189:f392fc9709a3 130 }
AnnaBridge 189:f392fc9709a3 131 else
AnnaBridge 189:f392fc9709a3 132 {
AnnaBridge 189:f392fc9709a3 133 base->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
AnnaBridge 189:f392fc9709a3 134 }
AnnaBridge 189:f392fc9709a3 135 }
AnnaBridge 189:f392fc9709a3 136
AnnaBridge 189:f392fc9709a3 137 /*!
AnnaBridge 189:f392fc9709a3 138 * @brief Invalidates the processor code bus cache.
AnnaBridge 189:f392fc9709a3 139 * This function invalidates the cache both ways, which means that
AnnaBridge 189:f392fc9709a3 140 * it unconditionally clears valid bits and modifies bits of a cache entry.
AnnaBridge 189:f392fc9709a3 141 *
AnnaBridge 189:f392fc9709a3 142 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 143 */
AnnaBridge 189:f392fc9709a3 144 void LMEM_CodeCacheInvalidateAll(LMEM_Type *base);
AnnaBridge 189:f392fc9709a3 145
AnnaBridge 189:f392fc9709a3 146 /*!
AnnaBridge 189:f392fc9709a3 147 * @brief Pushes all modified lines in the processor code bus cache.
AnnaBridge 189:f392fc9709a3 148 * This function pushes all modified lines in both ways in the entire cache.
AnnaBridge 189:f392fc9709a3 149 * It pushes a cache entry if it is valid and modified and clears the modified bit. If
AnnaBridge 189:f392fc9709a3 150 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 189:f392fc9709a3 151 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 189:f392fc9709a3 152 *
AnnaBridge 189:f392fc9709a3 153 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 154 */
AnnaBridge 189:f392fc9709a3 155 void LMEM_CodeCachePushAll(LMEM_Type *base);
AnnaBridge 189:f392fc9709a3 156
AnnaBridge 189:f392fc9709a3 157 /*!
AnnaBridge 189:f392fc9709a3 158 * @brief Clears the processor code bus cache.
AnnaBridge 189:f392fc9709a3 159 * This function clears the entire cache and pushes (flushes) and
AnnaBridge 189:f392fc9709a3 160 * invalidates the operation.
AnnaBridge 189:f392fc9709a3 161 * Clear - Pushes a cache entry if it is valid and modified, then clears the valid and
AnnaBridge 189:f392fc9709a3 162 * modified bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 189:f392fc9709a3 163 *
AnnaBridge 189:f392fc9709a3 164 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 165 */
AnnaBridge 189:f392fc9709a3 166 void LMEM_CodeCacheClearAll(LMEM_Type *base);
AnnaBridge 189:f392fc9709a3 167
AnnaBridge 189:f392fc9709a3 168 /*!
AnnaBridge 189:f392fc9709a3 169 * @brief Invalidates a specific line in the processor code bus cache.
AnnaBridge 189:f392fc9709a3 170 * This function invalidates a specific line in the cache
AnnaBridge 189:f392fc9709a3 171 * based on the physical address passed in by the user.
AnnaBridge 189:f392fc9709a3 172 * Invalidate - Unconditionally clears valid and modified bits of a cache entry.
AnnaBridge 189:f392fc9709a3 173 *
AnnaBridge 189:f392fc9709a3 174 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 175 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 176 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 177 */
AnnaBridge 189:f392fc9709a3 178 void LMEM_CodeCacheInvalidateLine(LMEM_Type *base, uint32_t address);
AnnaBridge 189:f392fc9709a3 179
AnnaBridge 189:f392fc9709a3 180 /*!
AnnaBridge 189:f392fc9709a3 181 * @brief Invalidates multiple lines in the processor code bus cache.
AnnaBridge 189:f392fc9709a3 182 * This function invalidates multiple lines in the cache
AnnaBridge 189:f392fc9709a3 183 * based on the physical address and length in bytes passed in by the
AnnaBridge 189:f392fc9709a3 184 * user. If the function detects that the length meets or exceeds half the
AnnaBridge 189:f392fc9709a3 185 * cache, the function performs an entire cache invalidate function, which is
AnnaBridge 189:f392fc9709a3 186 * more efficient than invalidating the cache line-by-line.
AnnaBridge 189:f392fc9709a3 187 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 189:f392fc9709a3 188 * check half the total amount of cache.
AnnaBridge 189:f392fc9709a3 189 * Invalidate - Unconditionally clear valid and modified bits of a cache entry.
AnnaBridge 189:f392fc9709a3 190 *
AnnaBridge 189:f392fc9709a3 191 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 192 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 193 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 194 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 189:f392fc9709a3 195 */
AnnaBridge 189:f392fc9709a3 196 void LMEM_CodeCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 189:f392fc9709a3 197
AnnaBridge 189:f392fc9709a3 198 /*!
AnnaBridge 189:f392fc9709a3 199 * @brief Pushes a specific modified line in the processor code bus cache.
AnnaBridge 189:f392fc9709a3 200 * This function pushes a specific modified line based on the physical address passed in
AnnaBridge 189:f392fc9709a3 201 * by the user.
AnnaBridge 189:f392fc9709a3 202 * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If the
AnnaBridge 189:f392fc9709a3 203 * entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 189:f392fc9709a3 204 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 189:f392fc9709a3 205 *
AnnaBridge 189:f392fc9709a3 206 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 207 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 208 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 209 */
AnnaBridge 189:f392fc9709a3 210 void LMEM_CodeCachePushLine(LMEM_Type *base, uint32_t address);
AnnaBridge 189:f392fc9709a3 211
AnnaBridge 189:f392fc9709a3 212 /*!
AnnaBridge 189:f392fc9709a3 213 * @brief Pushes multiple modified lines in the processor code bus cache.
AnnaBridge 189:f392fc9709a3 214 * This function pushes multiple modified lines in the cache
AnnaBridge 189:f392fc9709a3 215 * based on the physical address and length in bytes passed in by the
AnnaBridge 189:f392fc9709a3 216 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 189:f392fc9709a3 217 * cache, the function performs an cache push function, which is
AnnaBridge 189:f392fc9709a3 218 * more efficient than pushing the modified lines in the cache line-by-line.
AnnaBridge 189:f392fc9709a3 219 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 189:f392fc9709a3 220 * check half the total amount of cache.
AnnaBridge 189:f392fc9709a3 221 * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If
AnnaBridge 189:f392fc9709a3 222 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 189:f392fc9709a3 223 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 189:f392fc9709a3 224 *
AnnaBridge 189:f392fc9709a3 225 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 226 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 227 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 228 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 189:f392fc9709a3 229 */
AnnaBridge 189:f392fc9709a3 230 void LMEM_CodeCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 189:f392fc9709a3 231
AnnaBridge 189:f392fc9709a3 232 /*!
AnnaBridge 189:f392fc9709a3 233 * @brief Clears a specific line in the processor code bus cache.
AnnaBridge 189:f392fc9709a3 234 * This function clears a specific line based on the physical address passed in
AnnaBridge 189:f392fc9709a3 235 * by the user.
AnnaBridge 189:f392fc9709a3 236 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 189:f392fc9709a3 237 * modify bits. If entry not valid or not modified, clear the valid bit.
AnnaBridge 189:f392fc9709a3 238 *
AnnaBridge 189:f392fc9709a3 239 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 240 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 241 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 242 */
AnnaBridge 189:f392fc9709a3 243 void LMEM_CodeCacheClearLine(LMEM_Type *base, uint32_t address);
AnnaBridge 189:f392fc9709a3 244
AnnaBridge 189:f392fc9709a3 245 /*!
AnnaBridge 189:f392fc9709a3 246 * @brief Clears multiple lines in the processor code bus cache.
AnnaBridge 189:f392fc9709a3 247 * This function clears multiple lines in the cache
AnnaBridge 189:f392fc9709a3 248 * based on the physical address and length in bytes passed in by the
AnnaBridge 189:f392fc9709a3 249 * user. If the function detects that the length meets or exceeds half the total amount of
AnnaBridge 189:f392fc9709a3 250 * cache, the function performs a cache clear function which is
AnnaBridge 189:f392fc9709a3 251 * more efficient than clearing the lines in the cache line-by-line.
AnnaBridge 189:f392fc9709a3 252 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 189:f392fc9709a3 253 * check half the total amount of cache.
AnnaBridge 189:f392fc9709a3 254 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 189:f392fc9709a3 255 * modify bits. If entry not valid or not modified, clear the valid bit.
AnnaBridge 189:f392fc9709a3 256 *
AnnaBridge 189:f392fc9709a3 257 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 258 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 259 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 260 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 189:f392fc9709a3 261 */
AnnaBridge 189:f392fc9709a3 262 void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 189:f392fc9709a3 263
AnnaBridge 189:f392fc9709a3 264 #if (!defined(FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE)) || !FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE
AnnaBridge 189:f392fc9709a3 265 /*!
AnnaBridge 189:f392fc9709a3 266 * @brief Demotes the cache mode of a region in processor code bus cache.
AnnaBridge 189:f392fc9709a3 267 * This function allows the user to demote the cache mode of a region within the device's
AnnaBridge 189:f392fc9709a3 268 * memory map. Demoting the cache mode reduces the cache function applied to a memory
AnnaBridge 189:f392fc9709a3 269 * region from write-back to write-through to non-cacheable. The function checks to see
AnnaBridge 189:f392fc9709a3 270 * if the requested cache mode is higher than or equal to the current cache mode, and if
AnnaBridge 189:f392fc9709a3 271 * so, returns an error. After a region is demoted, its cache mode can only be raised
AnnaBridge 189:f392fc9709a3 272 * by a reset, which returns it to its default state which is the highest cache configure for
AnnaBridge 189:f392fc9709a3 273 * each region.
AnnaBridge 189:f392fc9709a3 274 * To maintain cache coherency, changes to the cache mode should be completed while the
AnnaBridge 189:f392fc9709a3 275 * address space being changed is not being accessed or the cache is disabled. Before a
AnnaBridge 189:f392fc9709a3 276 * cache mode change, this function completes a cache clear all command to push and invalidate any
AnnaBridge 189:f392fc9709a3 277 * cache entries that may have changed.
AnnaBridge 189:f392fc9709a3 278 *
AnnaBridge 189:f392fc9709a3 279 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 280 * @param region The desired region to demote of type lmem_cache_region_t.
AnnaBridge 189:f392fc9709a3 281 * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t.
AnnaBridge 189:f392fc9709a3 282 * @return The execution result.
AnnaBridge 189:f392fc9709a3 283 * kStatus_Success The cache demote operation is successful.
AnnaBridge 189:f392fc9709a3 284 * kStatus_Fail The cache demote operation is failure.
AnnaBridge 189:f392fc9709a3 285 */
AnnaBridge 189:f392fc9709a3 286 status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
AnnaBridge 189:f392fc9709a3 287 #endif /* FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE */
AnnaBridge 189:f392fc9709a3 288
AnnaBridge 189:f392fc9709a3 289 /*@}*/
AnnaBridge 189:f392fc9709a3 290
AnnaBridge 189:f392fc9709a3 291 #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
AnnaBridge 189:f392fc9709a3 292 /*!
AnnaBridge 189:f392fc9709a3 293 * @name Local Memory Processor System Bus Cache Control
AnnaBridge 189:f392fc9709a3 294 *@{
AnnaBridge 189:f392fc9709a3 295 */
AnnaBridge 189:f392fc9709a3 296
AnnaBridge 189:f392fc9709a3 297 /*!
AnnaBridge 189:f392fc9709a3 298 * @brief Enables/disables the processor system bus cache.
AnnaBridge 189:f392fc9709a3 299 * This function enables/disables the cache. It first invalidates the entire cache,
AnnaBridge 189:f392fc9709a3 300 * then enables /disable both the cache and write buffer.
AnnaBridge 189:f392fc9709a3 301 *
AnnaBridge 189:f392fc9709a3 302 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 303 * @param The enable or disable flag.
AnnaBridge 189:f392fc9709a3 304 * true - enable the system cache.
AnnaBridge 189:f392fc9709a3 305 * false - disable the system cache.
AnnaBridge 189:f392fc9709a3 306 */
AnnaBridge 189:f392fc9709a3 307 void LMEM_EnableSystemCache(LMEM_Type *base, bool enable);
AnnaBridge 189:f392fc9709a3 308
AnnaBridge 189:f392fc9709a3 309 /*!
AnnaBridge 189:f392fc9709a3 310 * @brief Enables/disables the processor system bus write buffer.
AnnaBridge 189:f392fc9709a3 311 *
AnnaBridge 189:f392fc9709a3 312 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 313 * @param enable The enable or disable flag.
AnnaBridge 189:f392fc9709a3 314 * true - enable the system bus write buffer.
AnnaBridge 189:f392fc9709a3 315 * false - disable the system bus write buffer.
AnnaBridge 189:f392fc9709a3 316 */
AnnaBridge 189:f392fc9709a3 317 static inline void LMEM_EnableSystemWriteBuffer(LMEM_Type *base, bool enable)
AnnaBridge 189:f392fc9709a3 318 {
AnnaBridge 189:f392fc9709a3 319 if (enable)
AnnaBridge 189:f392fc9709a3 320 {
AnnaBridge 189:f392fc9709a3 321 base->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;
AnnaBridge 189:f392fc9709a3 322 }
AnnaBridge 189:f392fc9709a3 323 else
AnnaBridge 189:f392fc9709a3 324 {
AnnaBridge 189:f392fc9709a3 325 base->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;
AnnaBridge 189:f392fc9709a3 326 }
AnnaBridge 189:f392fc9709a3 327 }
AnnaBridge 189:f392fc9709a3 328
AnnaBridge 189:f392fc9709a3 329 /*!
AnnaBridge 189:f392fc9709a3 330 * @brief Invalidates the processor system bus cache.
AnnaBridge 189:f392fc9709a3 331 * This function invalidates the entire cache both ways.
AnnaBridge 189:f392fc9709a3 332 * Invalidate - Unconditionally clear valid and modify bits of a cache entry
AnnaBridge 189:f392fc9709a3 333 *
AnnaBridge 189:f392fc9709a3 334 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 335 */
AnnaBridge 189:f392fc9709a3 336 void LMEM_SystemCacheInvalidateAll(LMEM_Type *base);
AnnaBridge 189:f392fc9709a3 337
AnnaBridge 189:f392fc9709a3 338 /*!
AnnaBridge 189:f392fc9709a3 339 * @brief Pushes all modified lines in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 340 * This function pushes all modified lines in both ways (the entire cache).
AnnaBridge 189:f392fc9709a3 341 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
AnnaBridge 189:f392fc9709a3 342 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 189:f392fc9709a3 343 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 189:f392fc9709a3 344 *
AnnaBridge 189:f392fc9709a3 345 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 346 */
AnnaBridge 189:f392fc9709a3 347 void LMEM_SystemCachePushAll(LMEM_Type *base);
AnnaBridge 189:f392fc9709a3 348
AnnaBridge 189:f392fc9709a3 349 /*!
AnnaBridge 189:f392fc9709a3 350 * @brief Clears the entire processor system bus cache.
AnnaBridge 189:f392fc9709a3 351 * This function clears the entire cache, which is a push (flush) and
AnnaBridge 189:f392fc9709a3 352 * invalidate operation.
AnnaBridge 189:f392fc9709a3 353 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 189:f392fc9709a3 354 * modify bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 189:f392fc9709a3 355 *
AnnaBridge 189:f392fc9709a3 356 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 357 */
AnnaBridge 189:f392fc9709a3 358 void LMEM_SystemCacheClearAll(LMEM_Type *base);
AnnaBridge 189:f392fc9709a3 359
AnnaBridge 189:f392fc9709a3 360 /*!
AnnaBridge 189:f392fc9709a3 361 * @brief Invalidates a specific line in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 362 * This function invalidates a specific line in the cache
AnnaBridge 189:f392fc9709a3 363 * based on the physical address passed in by the user.
AnnaBridge 189:f392fc9709a3 364 * Invalidate - Unconditionally clears valid and modify bits of a cache entry.
AnnaBridge 189:f392fc9709a3 365 *
AnnaBridge 189:f392fc9709a3 366 * @param base LMEM peripheral base address. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 367 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 368 * @param address The physical address of the cache line.
AnnaBridge 189:f392fc9709a3 369 */
AnnaBridge 189:f392fc9709a3 370 void LMEM_SystemCacheInvalidateLine(LMEM_Type *base, uint32_t address);
AnnaBridge 189:f392fc9709a3 371
AnnaBridge 189:f392fc9709a3 372 /*!
AnnaBridge 189:f392fc9709a3 373 * @brief Invalidates multiple lines in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 374 * This function invalidates multiple lines in the cache
AnnaBridge 189:f392fc9709a3 375 * based on the physical address and length in bytes passed in by the
AnnaBridge 189:f392fc9709a3 376 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 189:f392fc9709a3 377 * cache, the function performs an entire cache invalidate function (which is
AnnaBridge 189:f392fc9709a3 378 * more efficient than invalidating the cache line-by-line).
AnnaBridge 189:f392fc9709a3 379 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 189:f392fc9709a3 380 * check half the total amount of cache.
AnnaBridge 189:f392fc9709a3 381 * Invalidate - Unconditionally clear valid and modify bits of a cache entry
AnnaBridge 189:f392fc9709a3 382 *
AnnaBridge 189:f392fc9709a3 383 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 384 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 385 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 386 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 189:f392fc9709a3 387 */
AnnaBridge 189:f392fc9709a3 388 void LMEM_SystemCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 189:f392fc9709a3 389
AnnaBridge 189:f392fc9709a3 390 /*!
AnnaBridge 189:f392fc9709a3 391 * @brief Pushes a specific modified line in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 392 * This function pushes a specific modified line based on the physical address passed in
AnnaBridge 189:f392fc9709a3 393 * by the user.
AnnaBridge 189:f392fc9709a3 394 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
AnnaBridge 189:f392fc9709a3 395 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 189:f392fc9709a3 396 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 189:f392fc9709a3 397 *
AnnaBridge 189:f392fc9709a3 398 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 399 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 400 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 401 */
AnnaBridge 189:f392fc9709a3 402 void LMEM_SystemCachePushLine(LMEM_Type *base, uint32_t address);
AnnaBridge 189:f392fc9709a3 403
AnnaBridge 189:f392fc9709a3 404 /*!
AnnaBridge 189:f392fc9709a3 405 * @brief Pushes multiple modified lines in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 406 * This function pushes multiple modified lines in the cache
AnnaBridge 189:f392fc9709a3 407 * based on the physical address and length in bytes passed in by the
AnnaBridge 189:f392fc9709a3 408 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 189:f392fc9709a3 409 * cache, the function performs an entire cache push function (which is
AnnaBridge 189:f392fc9709a3 410 * more efficient than pushing the modified lines in the cache line-by-line).
AnnaBridge 189:f392fc9709a3 411 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 189:f392fc9709a3 412 * check half the total amount of cache.
AnnaBridge 189:f392fc9709a3 413 * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If
AnnaBridge 189:f392fc9709a3 414 * the entry is not valid or not modified, leave as is. This action does not clear the valid
AnnaBridge 189:f392fc9709a3 415 * bit. A cache push is synonymous with a cache flush.
AnnaBridge 189:f392fc9709a3 416 *
AnnaBridge 189:f392fc9709a3 417 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 418 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 419 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 420 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 189:f392fc9709a3 421 */
AnnaBridge 189:f392fc9709a3 422 void LMEM_SystemCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 189:f392fc9709a3 423
AnnaBridge 189:f392fc9709a3 424 /*!
AnnaBridge 189:f392fc9709a3 425 * @brief Clears a specific line in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 426 * This function clears a specific line based on the physical address passed in
AnnaBridge 189:f392fc9709a3 427 * by the user.
AnnaBridge 189:f392fc9709a3 428 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 189:f392fc9709a3 429 * modify bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 189:f392fc9709a3 430 *
AnnaBridge 189:f392fc9709a3 431 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 432 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 433 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 434 */
AnnaBridge 189:f392fc9709a3 435 void LMEM_SystemCacheClearLine(LMEM_Type *base, uint32_t address);
AnnaBridge 189:f392fc9709a3 436
AnnaBridge 189:f392fc9709a3 437 /*!
AnnaBridge 189:f392fc9709a3 438 * @brief Clears multiple lines in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 439 * This function clears multiple lines in the cache
AnnaBridge 189:f392fc9709a3 440 * based on the physical address and length in bytes passed in by the
AnnaBridge 189:f392fc9709a3 441 * user. If the function detects that the length meets or exceeds half of the
AnnaBridge 189:f392fc9709a3 442 * cache, the function performs an entire cache clear function (which is
AnnaBridge 189:f392fc9709a3 443 * more efficient than clearing the lines in the cache line-by-line).
AnnaBridge 189:f392fc9709a3 444 * Because the cache consists of two ways and line commands based on the physical address searches both ways,
AnnaBridge 189:f392fc9709a3 445 * check half the total amount of cache.
AnnaBridge 189:f392fc9709a3 446 * Clear - Push a cache entry if it is valid and modified, then clear the valid and
AnnaBridge 189:f392fc9709a3 447 * modify bits. If the entry is not valid or not modified, clear the valid bit.
AnnaBridge 189:f392fc9709a3 448 *
AnnaBridge 189:f392fc9709a3 449 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 450 * @param address The physical address of the cache line. Should be 16-byte aligned address.
AnnaBridge 189:f392fc9709a3 451 * If not, it is changed to the 16-byte aligned memory address.
AnnaBridge 189:f392fc9709a3 452 * @param length The length in bytes of the total amount of cache lines.
AnnaBridge 189:f392fc9709a3 453 */
AnnaBridge 189:f392fc9709a3 454 void LMEM_SystemCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length);
AnnaBridge 189:f392fc9709a3 455
AnnaBridge 189:f392fc9709a3 456 /*!
AnnaBridge 189:f392fc9709a3 457 * @brief Demotes the cache mode of a region in the processor system bus cache.
AnnaBridge 189:f392fc9709a3 458 * This function allows the user to demote the cache mode of a region within the device's
AnnaBridge 189:f392fc9709a3 459 * memory map. Demoting the cache mode reduces the cache function applied to a memory
AnnaBridge 189:f392fc9709a3 460 * region from write-back to write-through to non-cacheable. The function checks to see
AnnaBridge 189:f392fc9709a3 461 * if the requested cache mode is higher than or equal to the current cache mode, and if
AnnaBridge 189:f392fc9709a3 462 * so, returns an error. After a region is demoted, its cache mode can only be raised
AnnaBridge 189:f392fc9709a3 463 * by a reset, which returns it to its default state which is the highest cache configure
AnnaBridge 189:f392fc9709a3 464 * for each region.
AnnaBridge 189:f392fc9709a3 465 * To maintain cache coherency, changes to the cache mode should be completed while the
AnnaBridge 189:f392fc9709a3 466 * address space being changed is not being accessed or the cache is disabled. Before a
AnnaBridge 189:f392fc9709a3 467 * cache mode change, this function completes a cache clear all command to push and invalidate any
AnnaBridge 189:f392fc9709a3 468 * cache entries that may have changed.
AnnaBridge 189:f392fc9709a3 469 *
AnnaBridge 189:f392fc9709a3 470 * @param base LMEM peripheral base address.
AnnaBridge 189:f392fc9709a3 471 * @param region The desired region to demote of type lmem_cache_region_t.
AnnaBridge 189:f392fc9709a3 472 * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t.
AnnaBridge 189:f392fc9709a3 473 * @return The execution result.
AnnaBridge 189:f392fc9709a3 474 * kStatus_Success The cache demote operation is successful.
AnnaBridge 189:f392fc9709a3 475 * kStatus_Fail The cache demote operation is failure.
AnnaBridge 189:f392fc9709a3 476 */
AnnaBridge 189:f392fc9709a3 477 status_t LMEM_SystemCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode);
AnnaBridge 189:f392fc9709a3 478
AnnaBridge 189:f392fc9709a3 479 /*@}*/
AnnaBridge 189:f392fc9709a3 480 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
AnnaBridge 189:f392fc9709a3 481
AnnaBridge 189:f392fc9709a3 482 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 483 }
AnnaBridge 189:f392fc9709a3 484 #endif
AnnaBridge 189:f392fc9709a3 485
AnnaBridge 189:f392fc9709a3 486 /*! @}*/
AnnaBridge 189:f392fc9709a3 487
AnnaBridge 189:f392fc9709a3 488 #endif /* _FSL_LMEM_CACHE_H_*/