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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/fsl_dspi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 189:f392fc9709a3 1 /*
AnnaBridge 189:f392fc9709a3 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 189:f392fc9709a3 3 * All rights reserved.
AnnaBridge 189:f392fc9709a3 4 *
AnnaBridge 189:f392fc9709a3 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 6 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 7 *
AnnaBridge 189:f392fc9709a3 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 189:f392fc9709a3 9 * of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 189:f392fc9709a3 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 189:f392fc9709a3 13 * other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 14 *
AnnaBridge 189:f392fc9709a3 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 189:f392fc9709a3 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 189:f392fc9709a3 17 * software without specific prior written permission.
AnnaBridge 189:f392fc9709a3 18 *
AnnaBridge 189:f392fc9709a3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 189:f392fc9709a3 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 189:f392fc9709a3 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 189:f392fc9709a3 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 189:f392fc9709a3 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 189:f392fc9709a3 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 189:f392fc9709a3 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 189:f392fc9709a3 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 189:f392fc9709a3 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 29 */
AnnaBridge 189:f392fc9709a3 30 #ifndef _FSL_DSPI_H_
AnnaBridge 189:f392fc9709a3 31 #define _FSL_DSPI_H_
AnnaBridge 189:f392fc9709a3 32
AnnaBridge 189:f392fc9709a3 33 #include "fsl_common.h"
AnnaBridge 189:f392fc9709a3 34
AnnaBridge 189:f392fc9709a3 35 /*!
AnnaBridge 189:f392fc9709a3 36 * @addtogroup dspi_driver
AnnaBridge 189:f392fc9709a3 37 * @{
AnnaBridge 189:f392fc9709a3 38 */
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40
AnnaBridge 189:f392fc9709a3 41 /**********************************************************************************************************************
AnnaBridge 189:f392fc9709a3 42 * Definitions
AnnaBridge 189:f392fc9709a3 43 *********************************************************************************************************************/
AnnaBridge 189:f392fc9709a3 44
AnnaBridge 189:f392fc9709a3 45 /*! @name Driver version */
AnnaBridge 189:f392fc9709a3 46 /*@{*/
AnnaBridge 189:f392fc9709a3 47 /*! @brief DSPI driver version 2.1.3. */
AnnaBridge 189:f392fc9709a3 48 #define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
AnnaBridge 189:f392fc9709a3 49 /*@}*/
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 #ifndef DSPI_DUMMY_DATA
AnnaBridge 189:f392fc9709a3 52 /*! @brief DSPI dummy data if there is no Tx data.*/
AnnaBridge 189:f392fc9709a3 53 #define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */
AnnaBridge 189:f392fc9709a3 54 #endif
AnnaBridge 189:f392fc9709a3 55
AnnaBridge 189:f392fc9709a3 56 /*! @brief Status for the DSPI driver.*/
AnnaBridge 189:f392fc9709a3 57 enum _dspi_status
AnnaBridge 189:f392fc9709a3 58 {
AnnaBridge 189:f392fc9709a3 59 kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/
AnnaBridge 189:f392fc9709a3 60 kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */
AnnaBridge 189:f392fc9709a3 61 kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/
AnnaBridge 189:f392fc9709a3 62 kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */
AnnaBridge 189:f392fc9709a3 63 };
AnnaBridge 189:f392fc9709a3 64
AnnaBridge 189:f392fc9709a3 65 /*! @brief DSPI status flags in SPIx_SR register.*/
AnnaBridge 189:f392fc9709a3 66 enum _dspi_flags
AnnaBridge 189:f392fc9709a3 67 {
AnnaBridge 189:f392fc9709a3 68 kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */
AnnaBridge 189:f392fc9709a3 69 kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/
AnnaBridge 189:f392fc9709a3 70 kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/
AnnaBridge 189:f392fc9709a3 71 kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/
AnnaBridge 189:f392fc9709a3 72 kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/
AnnaBridge 189:f392fc9709a3 73 kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/
AnnaBridge 189:f392fc9709a3 74 kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/
AnnaBridge 189:f392fc9709a3 75 kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK |
AnnaBridge 189:f392fc9709a3 76 SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All statuses above.*/
AnnaBridge 189:f392fc9709a3 77 };
AnnaBridge 189:f392fc9709a3 78
AnnaBridge 189:f392fc9709a3 79 /*! @brief DSPI interrupt source.*/
AnnaBridge 189:f392fc9709a3 80 enum _dspi_interrupt_enable
AnnaBridge 189:f392fc9709a3 81 {
AnnaBridge 189:f392fc9709a3 82 kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/
AnnaBridge 189:f392fc9709a3 83 kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/
AnnaBridge 189:f392fc9709a3 84 kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/
AnnaBridge 189:f392fc9709a3 85 kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/
AnnaBridge 189:f392fc9709a3 86 kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/
AnnaBridge 189:f392fc9709a3 87 kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/
AnnaBridge 189:f392fc9709a3 88 kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK |
AnnaBridge 189:f392fc9709a3 89 SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK
AnnaBridge 189:f392fc9709a3 90 /*!< All above interrupts enable.*/
AnnaBridge 189:f392fc9709a3 91 };
AnnaBridge 189:f392fc9709a3 92
AnnaBridge 189:f392fc9709a3 93 /*! @brief DSPI DMA source.*/
AnnaBridge 189:f392fc9709a3 94 enum _dspi_dma_enable
AnnaBridge 189:f392fc9709a3 95 {
AnnaBridge 189:f392fc9709a3 96 kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests.
AnnaBridge 189:f392fc9709a3 97 No Tx interrupt request. */
AnnaBridge 189:f392fc9709a3 98 kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests.
AnnaBridge 189:f392fc9709a3 99 No Rx interrupt request. */
AnnaBridge 189:f392fc9709a3 100 };
AnnaBridge 189:f392fc9709a3 101
AnnaBridge 189:f392fc9709a3 102 /*! @brief DSPI master or slave mode configuration.*/
AnnaBridge 189:f392fc9709a3 103 typedef enum _dspi_master_slave_mode
AnnaBridge 189:f392fc9709a3 104 {
AnnaBridge 189:f392fc9709a3 105 kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/
AnnaBridge 189:f392fc9709a3 106 kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/
AnnaBridge 189:f392fc9709a3 107 } dspi_master_slave_mode_t;
AnnaBridge 189:f392fc9709a3 108
AnnaBridge 189:f392fc9709a3 109 /*!
AnnaBridge 189:f392fc9709a3 110 * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is valid
AnnaBridge 189:f392fc9709a3 111 * only when the CPHA bit in the CTAR register is 0.
AnnaBridge 189:f392fc9709a3 112 */
AnnaBridge 189:f392fc9709a3 113 typedef enum _dspi_master_sample_point
AnnaBridge 189:f392fc9709a3 114 {
AnnaBridge 189:f392fc9709a3 115 kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/
AnnaBridge 189:f392fc9709a3 116 kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/
AnnaBridge 189:f392fc9709a3 117 kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/
AnnaBridge 189:f392fc9709a3 118 } dspi_master_sample_point_t;
AnnaBridge 189:f392fc9709a3 119
AnnaBridge 189:f392fc9709a3 120 /*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/
AnnaBridge 189:f392fc9709a3 121 typedef enum _dspi_which_pcs_config
AnnaBridge 189:f392fc9709a3 122 {
AnnaBridge 189:f392fc9709a3 123 kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */
AnnaBridge 189:f392fc9709a3 124 kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */
AnnaBridge 189:f392fc9709a3 125 kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */
AnnaBridge 189:f392fc9709a3 126 kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */
AnnaBridge 189:f392fc9709a3 127 kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */
AnnaBridge 189:f392fc9709a3 128 kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */
AnnaBridge 189:f392fc9709a3 129 } dspi_which_pcs_t;
AnnaBridge 189:f392fc9709a3 130
AnnaBridge 189:f392fc9709a3 131 /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/
AnnaBridge 189:f392fc9709a3 132 typedef enum _dspi_pcs_polarity_config
AnnaBridge 189:f392fc9709a3 133 {
AnnaBridge 189:f392fc9709a3 134 kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */
AnnaBridge 189:f392fc9709a3 135 kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 136 } dspi_pcs_polarity_config_t;
AnnaBridge 189:f392fc9709a3 137
AnnaBridge 189:f392fc9709a3 138 /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/
AnnaBridge 189:f392fc9709a3 139 enum _dspi_pcs_polarity
AnnaBridge 189:f392fc9709a3 140 {
AnnaBridge 189:f392fc9709a3 141 kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 142 kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 143 kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 144 kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 145 kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 146 kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 147 kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */
AnnaBridge 189:f392fc9709a3 148 };
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 /*! @brief DSPI clock polarity configuration for a given CTAR.*/
AnnaBridge 189:f392fc9709a3 151 typedef enum _dspi_clock_polarity
AnnaBridge 189:f392fc9709a3 152 {
AnnaBridge 189:f392fc9709a3 153 kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/
AnnaBridge 189:f392fc9709a3 154 kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/
AnnaBridge 189:f392fc9709a3 155 } dspi_clock_polarity_t;
AnnaBridge 189:f392fc9709a3 156
AnnaBridge 189:f392fc9709a3 157 /*! @brief DSPI clock phase configuration for a given CTAR.*/
AnnaBridge 189:f392fc9709a3 158 typedef enum _dspi_clock_phase
AnnaBridge 189:f392fc9709a3 159 {
AnnaBridge 189:f392fc9709a3 160 kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
AnnaBridge 189:f392fc9709a3 161 following edge.*/
AnnaBridge 189:f392fc9709a3 162 kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
AnnaBridge 189:f392fc9709a3 163 following edge.*/
AnnaBridge 189:f392fc9709a3 164 } dspi_clock_phase_t;
AnnaBridge 189:f392fc9709a3 165
AnnaBridge 189:f392fc9709a3 166 /*! @brief DSPI data shifter direction options for a given CTAR.*/
AnnaBridge 189:f392fc9709a3 167 typedef enum _dspi_shift_direction
AnnaBridge 189:f392fc9709a3 168 {
AnnaBridge 189:f392fc9709a3 169 kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
AnnaBridge 189:f392fc9709a3 170 kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.
AnnaBridge 189:f392fc9709a3 171 Shifting out of LSB is not supported for slave */
AnnaBridge 189:f392fc9709a3 172 } dspi_shift_direction_t;
AnnaBridge 189:f392fc9709a3 173
AnnaBridge 189:f392fc9709a3 174 /*! @brief DSPI delay type selection.*/
AnnaBridge 189:f392fc9709a3 175 typedef enum _dspi_delay_type
AnnaBridge 189:f392fc9709a3 176 {
AnnaBridge 189:f392fc9709a3 177 kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */
AnnaBridge 189:f392fc9709a3 178 kDSPI_LastSckToPcs, /*!< The last SCK edge to Pcs delay. */
AnnaBridge 189:f392fc9709a3 179 kDSPI_BetweenTransfer /*!< Delay between transfers. */
AnnaBridge 189:f392fc9709a3 180 } dspi_delay_type_t;
AnnaBridge 189:f392fc9709a3 181
AnnaBridge 189:f392fc9709a3 182 /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/
AnnaBridge 189:f392fc9709a3 183 typedef enum _dspi_ctar_selection
AnnaBridge 189:f392fc9709a3 184 {
AnnaBridge 189:f392fc9709a3 185 kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the
AnnaBridge 189:f392fc9709a3 186 same register address. */
AnnaBridge 189:f392fc9709a3 187 kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */
AnnaBridge 189:f392fc9709a3 188 kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */
AnnaBridge 189:f392fc9709a3 189 kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */
AnnaBridge 189:f392fc9709a3 190 kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */
AnnaBridge 189:f392fc9709a3 191 kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */
AnnaBridge 189:f392fc9709a3 192 kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */
AnnaBridge 189:f392fc9709a3 193 kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */
AnnaBridge 189:f392fc9709a3 194 } dspi_ctar_selection_t;
AnnaBridge 189:f392fc9709a3 195
AnnaBridge 189:f392fc9709a3 196 #define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro; used internally. */
AnnaBridge 189:f392fc9709a3 197 #define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */
AnnaBridge 189:f392fc9709a3 198 #define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro; used internally. */
AnnaBridge 189:f392fc9709a3 199 #define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro; used internally. */
AnnaBridge 189:f392fc9709a3 200 /*! @brief Use this enumeration for the DSPI master transfer configFlags. */
AnnaBridge 189:f392fc9709a3 201 enum _dspi_transfer_config_flag_for_master
AnnaBridge 189:f392fc9709a3 202 {
AnnaBridge 189:f392fc9709a3 203 kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */
AnnaBridge 189:f392fc9709a3 204 kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */
AnnaBridge 189:f392fc9709a3 205 kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */
AnnaBridge 189:f392fc9709a3 206 kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */
AnnaBridge 189:f392fc9709a3 207 kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */
AnnaBridge 189:f392fc9709a3 208 kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */
AnnaBridge 189:f392fc9709a3 209 kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */
AnnaBridge 189:f392fc9709a3 210 kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */
AnnaBridge 189:f392fc9709a3 211
AnnaBridge 189:f392fc9709a3 212 kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */
AnnaBridge 189:f392fc9709a3 213 kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */
AnnaBridge 189:f392fc9709a3 214 kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/
AnnaBridge 189:f392fc9709a3 215 kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */
AnnaBridge 189:f392fc9709a3 216 kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
AnnaBridge 189:f392fc9709a3 217 kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
AnnaBridge 189:f392fc9709a3 218
AnnaBridge 189:f392fc9709a3 219 kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */
AnnaBridge 189:f392fc9709a3 220 kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
AnnaBridge 189:f392fc9709a3 221 };
AnnaBridge 189:f392fc9709a3 222
AnnaBridge 189:f392fc9709a3 223 #define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */
AnnaBridge 189:f392fc9709a3 224 #define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */
AnnaBridge 189:f392fc9709a3 225 /*! @brief Use this enumeration for the DSPI slave transfer configFlags. */
AnnaBridge 189:f392fc9709a3 226 enum _dspi_transfer_config_flag_for_slave
AnnaBridge 189:f392fc9709a3 227 {
AnnaBridge 189:f392fc9709a3 228 kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */
AnnaBridge 189:f392fc9709a3 229 /*!< DSPI slave can only use PCS0. */
AnnaBridge 189:f392fc9709a3 230 };
AnnaBridge 189:f392fc9709a3 231
AnnaBridge 189:f392fc9709a3 232 /*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */
AnnaBridge 189:f392fc9709a3 233 enum _dspi_transfer_state
AnnaBridge 189:f392fc9709a3 234 {
AnnaBridge 189:f392fc9709a3 235 kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
AnnaBridge 189:f392fc9709a3 236 kDSPI_Busy, /*!< Transfer queue is not finished. */
AnnaBridge 189:f392fc9709a3 237 kDSPI_Error /*!< Transfer error. */
AnnaBridge 189:f392fc9709a3 238 };
AnnaBridge 189:f392fc9709a3 239
AnnaBridge 189:f392fc9709a3 240 /*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/
AnnaBridge 189:f392fc9709a3 241 typedef struct _dspi_command_data_config
AnnaBridge 189:f392fc9709a3 242 {
AnnaBridge 189:f392fc9709a3 243 bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/
AnnaBridge 189:f392fc9709a3 244 dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
AnnaBridge 189:f392fc9709a3 245 Register (CTAR) to use for CTAS.*/
AnnaBridge 189:f392fc9709a3 246 dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/
AnnaBridge 189:f392fc9709a3 247 bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/
AnnaBridge 189:f392fc9709a3 248 bool clearTransferCount; /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/
AnnaBridge 189:f392fc9709a3 249 } dspi_command_data_config_t;
AnnaBridge 189:f392fc9709a3 250
AnnaBridge 189:f392fc9709a3 251 /*! @brief DSPI master ctar configuration structure.*/
AnnaBridge 189:f392fc9709a3 252 typedef struct _dspi_master_ctar_config
AnnaBridge 189:f392fc9709a3 253 {
AnnaBridge 189:f392fc9709a3 254 uint32_t baudRate; /*!< Baud Rate for DSPI. */
AnnaBridge 189:f392fc9709a3 255 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/
AnnaBridge 189:f392fc9709a3 256 dspi_clock_polarity_t cpol; /*!< Clock polarity. */
AnnaBridge 189:f392fc9709a3 257 dspi_clock_phase_t cpha; /*!< Clock phase. */
AnnaBridge 189:f392fc9709a3 258 dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
AnnaBridge 189:f392fc9709a3 259
AnnaBridge 189:f392fc9709a3 260 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
AnnaBridge 189:f392fc9709a3 261 delay. It also sets the boundary value if out of range.*/
AnnaBridge 189:f392fc9709a3 262 uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
AnnaBridge 189:f392fc9709a3 263 minimum delay. It also sets the boundary value if out of range.*/
AnnaBridge 189:f392fc9709a3 264
AnnaBridge 189:f392fc9709a3 265 uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum
AnnaBridge 189:f392fc9709a3 266 delay. It also sets the boundary value if out of range.*/
AnnaBridge 189:f392fc9709a3 267 } dspi_master_ctar_config_t;
AnnaBridge 189:f392fc9709a3 268
AnnaBridge 189:f392fc9709a3 269 /*! @brief DSPI master configuration structure.*/
AnnaBridge 189:f392fc9709a3 270 typedef struct _dspi_master_config
AnnaBridge 189:f392fc9709a3 271 {
AnnaBridge 189:f392fc9709a3 272 dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */
AnnaBridge 189:f392fc9709a3 273 dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
AnnaBridge 189:f392fc9709a3 274
AnnaBridge 189:f392fc9709a3 275 dspi_which_pcs_t whichPcs; /*!< The desired Peripheral Chip Select (pcs). */
AnnaBridge 189:f392fc9709a3 276 dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */
AnnaBridge 189:f392fc9709a3 277
AnnaBridge 189:f392fc9709a3 278 bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
AnnaBridge 189:f392fc9709a3 279 supported for CPHA = 1.*/
AnnaBridge 189:f392fc9709a3 280 bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
AnnaBridge 189:f392fc9709a3 281 data is ignored and the data from the transfer that generated the overflow
AnnaBridge 189:f392fc9709a3 282 is also ignored. If ROOE = 1, the incoming data is shifted to the
AnnaBridge 189:f392fc9709a3 283 shift register. */
AnnaBridge 189:f392fc9709a3 284
AnnaBridge 189:f392fc9709a3 285 bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/
AnnaBridge 189:f392fc9709a3 286 dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
AnnaBridge 189:f392fc9709a3 287 Format. It's valid only when CPHA=0. */
AnnaBridge 189:f392fc9709a3 288 } dspi_master_config_t;
AnnaBridge 189:f392fc9709a3 289
AnnaBridge 189:f392fc9709a3 290 /*! @brief DSPI slave ctar configuration structure.*/
AnnaBridge 189:f392fc9709a3 291 typedef struct _dspi_slave_ctar_config
AnnaBridge 189:f392fc9709a3 292 {
AnnaBridge 189:f392fc9709a3 293 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/
AnnaBridge 189:f392fc9709a3 294 dspi_clock_polarity_t cpol; /*!< Clock polarity. */
AnnaBridge 189:f392fc9709a3 295 dspi_clock_phase_t cpha; /*!< Clock phase. */
AnnaBridge 189:f392fc9709a3 296 /*!< Slave only supports MSB and does not support LSB.*/
AnnaBridge 189:f392fc9709a3 297 } dspi_slave_ctar_config_t;
AnnaBridge 189:f392fc9709a3 298
AnnaBridge 189:f392fc9709a3 299 /*! @brief DSPI slave configuration structure.*/
AnnaBridge 189:f392fc9709a3 300 typedef struct _dspi_slave_config
AnnaBridge 189:f392fc9709a3 301 {
AnnaBridge 189:f392fc9709a3 302 dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */
AnnaBridge 189:f392fc9709a3 303 dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */
AnnaBridge 189:f392fc9709a3 304
AnnaBridge 189:f392fc9709a3 305 bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only
AnnaBridge 189:f392fc9709a3 306 supported for CPHA = 1.*/
AnnaBridge 189:f392fc9709a3 307 bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming
AnnaBridge 189:f392fc9709a3 308 data is ignored and the data from the transfer that generated the overflow
AnnaBridge 189:f392fc9709a3 309 is also ignored. If ROOE = 1, the incoming data is shifted to the
AnnaBridge 189:f392fc9709a3 310 shift register. */
AnnaBridge 189:f392fc9709a3 311 bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/
AnnaBridge 189:f392fc9709a3 312 dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer
AnnaBridge 189:f392fc9709a3 313 Format. It's valid only when CPHA=0. */
AnnaBridge 189:f392fc9709a3 314 } dspi_slave_config_t;
AnnaBridge 189:f392fc9709a3 315
AnnaBridge 189:f392fc9709a3 316 /*!
AnnaBridge 189:f392fc9709a3 317 * @brief Forward declaration of the _dspi_master_handle typedefs.
AnnaBridge 189:f392fc9709a3 318 */
AnnaBridge 189:f392fc9709a3 319 typedef struct _dspi_master_handle dspi_master_handle_t;
AnnaBridge 189:f392fc9709a3 320
AnnaBridge 189:f392fc9709a3 321 /*!
AnnaBridge 189:f392fc9709a3 322 * @brief Forward declaration of the _dspi_slave_handle typedefs.
AnnaBridge 189:f392fc9709a3 323 */
AnnaBridge 189:f392fc9709a3 324 typedef struct _dspi_slave_handle dspi_slave_handle_t;
AnnaBridge 189:f392fc9709a3 325
AnnaBridge 189:f392fc9709a3 326 /*!
AnnaBridge 189:f392fc9709a3 327 * @brief Completion callback function pointer type.
AnnaBridge 189:f392fc9709a3 328 *
AnnaBridge 189:f392fc9709a3 329 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 330 * @param handle Pointer to the handle for the DSPI master.
AnnaBridge 189:f392fc9709a3 331 * @param status Success or error code describing whether the transfer completed.
AnnaBridge 189:f392fc9709a3 332 * @param userData Arbitrary pointer-dataSized value passed from the application.
AnnaBridge 189:f392fc9709a3 333 */
AnnaBridge 189:f392fc9709a3 334 typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base,
AnnaBridge 189:f392fc9709a3 335 dspi_master_handle_t *handle,
AnnaBridge 189:f392fc9709a3 336 status_t status,
AnnaBridge 189:f392fc9709a3 337 void *userData);
AnnaBridge 189:f392fc9709a3 338 /*!
AnnaBridge 189:f392fc9709a3 339 * @brief Completion callback function pointer type.
AnnaBridge 189:f392fc9709a3 340 *
AnnaBridge 189:f392fc9709a3 341 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 342 * @param handle Pointer to the handle for the DSPI slave.
AnnaBridge 189:f392fc9709a3 343 * @param status Success or error code describing whether the transfer completed.
AnnaBridge 189:f392fc9709a3 344 * @param userData Arbitrary pointer-dataSized value passed from the application.
AnnaBridge 189:f392fc9709a3 345 */
AnnaBridge 189:f392fc9709a3 346 typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base,
AnnaBridge 189:f392fc9709a3 347 dspi_slave_handle_t *handle,
AnnaBridge 189:f392fc9709a3 348 status_t status,
AnnaBridge 189:f392fc9709a3 349 void *userData);
AnnaBridge 189:f392fc9709a3 350
AnnaBridge 189:f392fc9709a3 351 /*! @brief DSPI master/slave transfer structure.*/
AnnaBridge 189:f392fc9709a3 352 typedef struct _dspi_transfer
AnnaBridge 189:f392fc9709a3 353 {
AnnaBridge 189:f392fc9709a3 354 uint8_t *txData; /*!< Send buffer. */
AnnaBridge 189:f392fc9709a3 355 uint8_t *rxData; /*!< Receive buffer. */
AnnaBridge 189:f392fc9709a3 356 volatile size_t dataSize; /*!< Transfer bytes. */
AnnaBridge 189:f392fc9709a3 357
AnnaBridge 189:f392fc9709a3 358 uint32_t
AnnaBridge 189:f392fc9709a3 359 configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if the
AnnaBridge 189:f392fc9709a3 360 transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
AnnaBridge 189:f392fc9709a3 361 is used for slave.*/
AnnaBridge 189:f392fc9709a3 362 } dspi_transfer_t;
AnnaBridge 189:f392fc9709a3 363
AnnaBridge 189:f392fc9709a3 364 /*! @brief DSPI master transfer handle structure used for transactional API. */
AnnaBridge 189:f392fc9709a3 365 struct _dspi_master_handle
AnnaBridge 189:f392fc9709a3 366 {
AnnaBridge 189:f392fc9709a3 367 uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */
AnnaBridge 189:f392fc9709a3 368 volatile uint32_t command; /*!< The desired data command. */
AnnaBridge 189:f392fc9709a3 369 volatile uint32_t lastCommand; /*!< The desired last data command. */
AnnaBridge 189:f392fc9709a3 370
AnnaBridge 189:f392fc9709a3 371 uint8_t fifoSize; /*!< FIFO dataSize. */
AnnaBridge 189:f392fc9709a3 372
AnnaBridge 189:f392fc9709a3 373 volatile bool isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
AnnaBridge 189:f392fc9709a3 374 volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
AnnaBridge 189:f392fc9709a3 375
AnnaBridge 189:f392fc9709a3 376 uint8_t *volatile txData; /*!< Send buffer. */
AnnaBridge 189:f392fc9709a3 377 uint8_t *volatile rxData; /*!< Receive buffer. */
AnnaBridge 189:f392fc9709a3 378 volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/
AnnaBridge 189:f392fc9709a3 379 volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
AnnaBridge 189:f392fc9709a3 380 size_t totalByteCount; /*!< A number of transfer bytes*/
AnnaBridge 189:f392fc9709a3 381
AnnaBridge 189:f392fc9709a3 382 volatile uint8_t state; /*!< DSPI transfer state, see _dspi_transfer_state.*/
AnnaBridge 189:f392fc9709a3 383
AnnaBridge 189:f392fc9709a3 384 dspi_master_transfer_callback_t callback; /*!< Completion callback. */
AnnaBridge 189:f392fc9709a3 385 void *userData; /*!< Callback user data. */
AnnaBridge 189:f392fc9709a3 386 };
AnnaBridge 189:f392fc9709a3 387
AnnaBridge 189:f392fc9709a3 388 /*! @brief DSPI slave transfer handle structure used for the transactional API. */
AnnaBridge 189:f392fc9709a3 389 struct _dspi_slave_handle
AnnaBridge 189:f392fc9709a3 390 {
AnnaBridge 189:f392fc9709a3 391 uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */
AnnaBridge 189:f392fc9709a3 392 volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
AnnaBridge 189:f392fc9709a3 393
AnnaBridge 189:f392fc9709a3 394 uint8_t *volatile txData; /*!< Send buffer. */
AnnaBridge 189:f392fc9709a3 395 uint8_t *volatile rxData; /*!< Receive buffer. */
AnnaBridge 189:f392fc9709a3 396 volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/
AnnaBridge 189:f392fc9709a3 397 volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/
AnnaBridge 189:f392fc9709a3 398 size_t totalByteCount; /*!< A number of transfer bytes*/
AnnaBridge 189:f392fc9709a3 399
AnnaBridge 189:f392fc9709a3 400 volatile uint8_t state; /*!< DSPI transfer state.*/
AnnaBridge 189:f392fc9709a3 401
AnnaBridge 189:f392fc9709a3 402 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
AnnaBridge 189:f392fc9709a3 403
AnnaBridge 189:f392fc9709a3 404 dspi_slave_transfer_callback_t callback; /*!< Completion callback. */
AnnaBridge 189:f392fc9709a3 405 void *userData; /*!< Callback user data. */
AnnaBridge 189:f392fc9709a3 406 };
AnnaBridge 189:f392fc9709a3 407
AnnaBridge 189:f392fc9709a3 408 /**********************************************************************************************************************
AnnaBridge 189:f392fc9709a3 409 * API
AnnaBridge 189:f392fc9709a3 410 *********************************************************************************************************************/
AnnaBridge 189:f392fc9709a3 411 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 412 extern "C" {
AnnaBridge 189:f392fc9709a3 413 #endif /*_cplusplus*/
AnnaBridge 189:f392fc9709a3 414
AnnaBridge 189:f392fc9709a3 415 /*!
AnnaBridge 189:f392fc9709a3 416 * @name Initialization and deinitialization
AnnaBridge 189:f392fc9709a3 417 * @{
AnnaBridge 189:f392fc9709a3 418 */
AnnaBridge 189:f392fc9709a3 419
AnnaBridge 189:f392fc9709a3 420 /*!
AnnaBridge 189:f392fc9709a3 421 * @brief Initializes the DSPI master.
AnnaBridge 189:f392fc9709a3 422 *
AnnaBridge 189:f392fc9709a3 423 * This function initializes the DSPI master configuration. This is an example use case.
AnnaBridge 189:f392fc9709a3 424 * @code
AnnaBridge 189:f392fc9709a3 425 * dspi_master_config_t masterConfig;
AnnaBridge 189:f392fc9709a3 426 * masterConfig.whichCtar = kDSPI_Ctar0;
AnnaBridge 189:f392fc9709a3 427 * masterConfig.ctarConfig.baudRate = 500000000U;
AnnaBridge 189:f392fc9709a3 428 * masterConfig.ctarConfig.bitsPerFrame = 8;
AnnaBridge 189:f392fc9709a3 429 * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
AnnaBridge 189:f392fc9709a3 430 * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
AnnaBridge 189:f392fc9709a3 431 * masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
AnnaBridge 189:f392fc9709a3 432 * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
AnnaBridge 189:f392fc9709a3 433 * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
AnnaBridge 189:f392fc9709a3 434 * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ;
AnnaBridge 189:f392fc9709a3 435 * masterConfig.whichPcs = kDSPI_Pcs0;
AnnaBridge 189:f392fc9709a3 436 * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
AnnaBridge 189:f392fc9709a3 437 * masterConfig.enableContinuousSCK = false;
AnnaBridge 189:f392fc9709a3 438 * masterConfig.enableRxFifoOverWrite = false;
AnnaBridge 189:f392fc9709a3 439 * masterConfig.enableModifiedTimingFormat = false;
AnnaBridge 189:f392fc9709a3 440 * masterConfig.samplePoint = kDSPI_SckToSin0Clock;
AnnaBridge 189:f392fc9709a3 441 * DSPI_MasterInit(base, &masterConfig, srcClock_Hz);
AnnaBridge 189:f392fc9709a3 442 * @endcode
AnnaBridge 189:f392fc9709a3 443 *
AnnaBridge 189:f392fc9709a3 444 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 445 * @param masterConfig Pointer to the structure dspi_master_config_t.
AnnaBridge 189:f392fc9709a3 446 * @param srcClock_Hz Module source input clock in Hertz.
AnnaBridge 189:f392fc9709a3 447 */
AnnaBridge 189:f392fc9709a3 448 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
AnnaBridge 189:f392fc9709a3 449
AnnaBridge 189:f392fc9709a3 450 /*!
AnnaBridge 189:f392fc9709a3 451 * @brief Sets the dspi_master_config_t structure to default values.
AnnaBridge 189:f392fc9709a3 452 *
AnnaBridge 189:f392fc9709a3 453 * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
AnnaBridge 189:f392fc9709a3 454 * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure
AnnaBridge 189:f392fc9709a3 455 * before calling the DSPI_MasterInit().
AnnaBridge 189:f392fc9709a3 456 * Example:
AnnaBridge 189:f392fc9709a3 457 * @code
AnnaBridge 189:f392fc9709a3 458 * dspi_master_config_t masterConfig;
AnnaBridge 189:f392fc9709a3 459 * DSPI_MasterGetDefaultConfig(&masterConfig);
AnnaBridge 189:f392fc9709a3 460 * @endcode
AnnaBridge 189:f392fc9709a3 461 * @param masterConfig pointer to dspi_master_config_t structure
AnnaBridge 189:f392fc9709a3 462 */
AnnaBridge 189:f392fc9709a3 463 void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
AnnaBridge 189:f392fc9709a3 464
AnnaBridge 189:f392fc9709a3 465 /*!
AnnaBridge 189:f392fc9709a3 466 * @brief DSPI slave configuration.
AnnaBridge 189:f392fc9709a3 467 *
AnnaBridge 189:f392fc9709a3 468 * This function initializes the DSPI slave configuration. This is an example use case.
AnnaBridge 189:f392fc9709a3 469 * @code
AnnaBridge 189:f392fc9709a3 470 * dspi_slave_config_t slaveConfig;
AnnaBridge 189:f392fc9709a3 471 * slaveConfig->whichCtar = kDSPI_Ctar0;
AnnaBridge 189:f392fc9709a3 472 * slaveConfig->ctarConfig.bitsPerFrame = 8;
AnnaBridge 189:f392fc9709a3 473 * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
AnnaBridge 189:f392fc9709a3 474 * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
AnnaBridge 189:f392fc9709a3 475 * slaveConfig->enableContinuousSCK = false;
AnnaBridge 189:f392fc9709a3 476 * slaveConfig->enableRxFifoOverWrite = false;
AnnaBridge 189:f392fc9709a3 477 * slaveConfig->enableModifiedTimingFormat = false;
AnnaBridge 189:f392fc9709a3 478 * slaveConfig->samplePoint = kDSPI_SckToSin0Clock;
AnnaBridge 189:f392fc9709a3 479 * DSPI_SlaveInit(base, &slaveConfig);
AnnaBridge 189:f392fc9709a3 480 * @endcode
AnnaBridge 189:f392fc9709a3 481 *
AnnaBridge 189:f392fc9709a3 482 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 483 * @param slaveConfig Pointer to the structure dspi_master_config_t.
AnnaBridge 189:f392fc9709a3 484 */
AnnaBridge 189:f392fc9709a3 485 void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig);
AnnaBridge 189:f392fc9709a3 486
AnnaBridge 189:f392fc9709a3 487 /*!
AnnaBridge 189:f392fc9709a3 488 * @brief Sets the dspi_slave_config_t structure to a default value.
AnnaBridge 189:f392fc9709a3 489 *
AnnaBridge 189:f392fc9709a3 490 * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
AnnaBridge 189:f392fc9709a3 491 * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure
AnnaBridge 189:f392fc9709a3 492 * before calling the DSPI_SlaveInit().
AnnaBridge 189:f392fc9709a3 493 * This is an example.
AnnaBridge 189:f392fc9709a3 494 * @code
AnnaBridge 189:f392fc9709a3 495 * dspi_slave_config_t slaveConfig;
AnnaBridge 189:f392fc9709a3 496 * DSPI_SlaveGetDefaultConfig(&slaveConfig);
AnnaBridge 189:f392fc9709a3 497 * @endcode
AnnaBridge 189:f392fc9709a3 498 * @param slaveConfig Pointer to the dspi_slave_config_t structure.
AnnaBridge 189:f392fc9709a3 499 */
AnnaBridge 189:f392fc9709a3 500 void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
AnnaBridge 189:f392fc9709a3 501
AnnaBridge 189:f392fc9709a3 502 /*!
AnnaBridge 189:f392fc9709a3 503 * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock.
AnnaBridge 189:f392fc9709a3 504 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 505 */
AnnaBridge 189:f392fc9709a3 506 void DSPI_Deinit(SPI_Type *base);
AnnaBridge 189:f392fc9709a3 507
AnnaBridge 189:f392fc9709a3 508 /*!
AnnaBridge 189:f392fc9709a3 509 * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
AnnaBridge 189:f392fc9709a3 510 *
AnnaBridge 189:f392fc9709a3 511 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 512 * @param enable Pass true to enable module, false to disable module.
AnnaBridge 189:f392fc9709a3 513 */
AnnaBridge 189:f392fc9709a3 514 static inline void DSPI_Enable(SPI_Type *base, bool enable)
AnnaBridge 189:f392fc9709a3 515 {
AnnaBridge 189:f392fc9709a3 516 if (enable)
AnnaBridge 189:f392fc9709a3 517 {
AnnaBridge 189:f392fc9709a3 518 base->MCR &= ~SPI_MCR_MDIS_MASK;
AnnaBridge 189:f392fc9709a3 519 }
AnnaBridge 189:f392fc9709a3 520 else
AnnaBridge 189:f392fc9709a3 521 {
AnnaBridge 189:f392fc9709a3 522 base->MCR |= SPI_MCR_MDIS_MASK;
AnnaBridge 189:f392fc9709a3 523 }
AnnaBridge 189:f392fc9709a3 524 }
AnnaBridge 189:f392fc9709a3 525
AnnaBridge 189:f392fc9709a3 526 /*!
AnnaBridge 189:f392fc9709a3 527 *@}
AnnaBridge 189:f392fc9709a3 528 */
AnnaBridge 189:f392fc9709a3 529
AnnaBridge 189:f392fc9709a3 530 /*!
AnnaBridge 189:f392fc9709a3 531 * @name Status
AnnaBridge 189:f392fc9709a3 532 * @{
AnnaBridge 189:f392fc9709a3 533 */
AnnaBridge 189:f392fc9709a3 534
AnnaBridge 189:f392fc9709a3 535 /*!
AnnaBridge 189:f392fc9709a3 536 * @brief Gets the DSPI status flag state.
AnnaBridge 189:f392fc9709a3 537 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 538 * @return DSPI status (in SR register).
AnnaBridge 189:f392fc9709a3 539 */
AnnaBridge 189:f392fc9709a3 540 static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 541 {
AnnaBridge 189:f392fc9709a3 542 return (base->SR);
AnnaBridge 189:f392fc9709a3 543 }
AnnaBridge 189:f392fc9709a3 544
AnnaBridge 189:f392fc9709a3 545 /*!
AnnaBridge 189:f392fc9709a3 546 * @brief Clears the DSPI status flag.
AnnaBridge 189:f392fc9709a3 547 *
AnnaBridge 189:f392fc9709a3 548 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
AnnaBridge 189:f392fc9709a3 549 * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The
AnnaBridge 189:f392fc9709a3 550 * function uses these bit positions in its algorithm to clear the desired flag state.
AnnaBridge 189:f392fc9709a3 551 * This is an example.
AnnaBridge 189:f392fc9709a3 552 * @code
AnnaBridge 189:f392fc9709a3 553 * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag);
AnnaBridge 189:f392fc9709a3 554 * @endcode
AnnaBridge 189:f392fc9709a3 555 *
AnnaBridge 189:f392fc9709a3 556 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 557 * @param statusFlags The status flag used from the type dspi_flags.
AnnaBridge 189:f392fc9709a3 558 */
AnnaBridge 189:f392fc9709a3 559 static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
AnnaBridge 189:f392fc9709a3 560 {
AnnaBridge 189:f392fc9709a3 561 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
AnnaBridge 189:f392fc9709a3 562 }
AnnaBridge 189:f392fc9709a3 563
AnnaBridge 189:f392fc9709a3 564 /*!
AnnaBridge 189:f392fc9709a3 565 *@}
AnnaBridge 189:f392fc9709a3 566 */
AnnaBridge 189:f392fc9709a3 567
AnnaBridge 189:f392fc9709a3 568 /*!
AnnaBridge 189:f392fc9709a3 569 * @name Interrupts
AnnaBridge 189:f392fc9709a3 570 * @{
AnnaBridge 189:f392fc9709a3 571 */
AnnaBridge 189:f392fc9709a3 572
AnnaBridge 189:f392fc9709a3 573 /*!
AnnaBridge 189:f392fc9709a3 574 * @brief Enables the DSPI interrupts.
AnnaBridge 189:f392fc9709a3 575 *
AnnaBridge 189:f392fc9709a3 576 * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask.
AnnaBridge 189:f392fc9709a3 577 * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
AnnaBridge 189:f392fc9709a3 578 *
AnnaBridge 189:f392fc9709a3 579 * @code
AnnaBridge 189:f392fc9709a3 580 * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
AnnaBridge 189:f392fc9709a3 581 * @endcode
AnnaBridge 189:f392fc9709a3 582 *
AnnaBridge 189:f392fc9709a3 583 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 584 * @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
AnnaBridge 189:f392fc9709a3 585 */
AnnaBridge 189:f392fc9709a3 586 void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
AnnaBridge 189:f392fc9709a3 587
AnnaBridge 189:f392fc9709a3 588 /*!
AnnaBridge 189:f392fc9709a3 589 * @brief Disables the DSPI interrupts.
AnnaBridge 189:f392fc9709a3 590 *
AnnaBridge 189:f392fc9709a3 591 * @code
AnnaBridge 189:f392fc9709a3 592 * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
AnnaBridge 189:f392fc9709a3 593 * @endcode
AnnaBridge 189:f392fc9709a3 594 *
AnnaBridge 189:f392fc9709a3 595 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 596 * @param mask The interrupt mask; use the enum _dspi_interrupt_enable.
AnnaBridge 189:f392fc9709a3 597 */
AnnaBridge 189:f392fc9709a3 598 static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 599 {
AnnaBridge 189:f392fc9709a3 600 base->RSER &= ~mask;
AnnaBridge 189:f392fc9709a3 601 }
AnnaBridge 189:f392fc9709a3 602
AnnaBridge 189:f392fc9709a3 603 /*!
AnnaBridge 189:f392fc9709a3 604 *@}
AnnaBridge 189:f392fc9709a3 605 */
AnnaBridge 189:f392fc9709a3 606
AnnaBridge 189:f392fc9709a3 607 /*!
AnnaBridge 189:f392fc9709a3 608 * @name DMA Control
AnnaBridge 189:f392fc9709a3 609 * @{
AnnaBridge 189:f392fc9709a3 610 */
AnnaBridge 189:f392fc9709a3 611
AnnaBridge 189:f392fc9709a3 612 /*!
AnnaBridge 189:f392fc9709a3 613 * @brief Enables the DSPI DMA request.
AnnaBridge 189:f392fc9709a3 614 *
AnnaBridge 189:f392fc9709a3 615 * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask.
AnnaBridge 189:f392fc9709a3 616 * @code
AnnaBridge 189:f392fc9709a3 617 * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
AnnaBridge 189:f392fc9709a3 618 * @endcode
AnnaBridge 189:f392fc9709a3 619 *
AnnaBridge 189:f392fc9709a3 620 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 621 * @param mask The interrupt mask; use the enum dspi_dma_enable.
AnnaBridge 189:f392fc9709a3 622 */
AnnaBridge 189:f392fc9709a3 623 static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 624 {
AnnaBridge 189:f392fc9709a3 625 base->RSER |= mask;
AnnaBridge 189:f392fc9709a3 626 }
AnnaBridge 189:f392fc9709a3 627
AnnaBridge 189:f392fc9709a3 628 /*!
AnnaBridge 189:f392fc9709a3 629 * @brief Disables the DSPI DMA request.
AnnaBridge 189:f392fc9709a3 630 *
AnnaBridge 189:f392fc9709a3 631 * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask.
AnnaBridge 189:f392fc9709a3 632 * @code
AnnaBridge 189:f392fc9709a3 633 * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable);
AnnaBridge 189:f392fc9709a3 634 * @endcode
AnnaBridge 189:f392fc9709a3 635 *
AnnaBridge 189:f392fc9709a3 636 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 637 * @param mask The interrupt mask; use the enum dspi_dma_enable.
AnnaBridge 189:f392fc9709a3 638 */
AnnaBridge 189:f392fc9709a3 639 static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 640 {
AnnaBridge 189:f392fc9709a3 641 base->RSER &= ~mask;
AnnaBridge 189:f392fc9709a3 642 }
AnnaBridge 189:f392fc9709a3 643
AnnaBridge 189:f392fc9709a3 644 /*!
AnnaBridge 189:f392fc9709a3 645 * @brief Gets the DSPI master PUSHR data register address for the DMA operation.
AnnaBridge 189:f392fc9709a3 646 *
AnnaBridge 189:f392fc9709a3 647 * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation.
AnnaBridge 189:f392fc9709a3 648 *
AnnaBridge 189:f392fc9709a3 649 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 650 * @return The DSPI master PUSHR data register address.
AnnaBridge 189:f392fc9709a3 651 */
AnnaBridge 189:f392fc9709a3 652 static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 653 {
AnnaBridge 189:f392fc9709a3 654 return (uint32_t) & (base->PUSHR);
AnnaBridge 189:f392fc9709a3 655 }
AnnaBridge 189:f392fc9709a3 656
AnnaBridge 189:f392fc9709a3 657 /*!
AnnaBridge 189:f392fc9709a3 658 * @brief Gets the DSPI slave PUSHR data register address for the DMA operation.
AnnaBridge 189:f392fc9709a3 659 *
AnnaBridge 189:f392fc9709a3 660 * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation.
AnnaBridge 189:f392fc9709a3 661 *
AnnaBridge 189:f392fc9709a3 662 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 663 * @return The DSPI slave PUSHR data register address.
AnnaBridge 189:f392fc9709a3 664 */
AnnaBridge 189:f392fc9709a3 665 static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 666 {
AnnaBridge 189:f392fc9709a3 667 return (uint32_t) & (base->PUSHR_SLAVE);
AnnaBridge 189:f392fc9709a3 668 }
AnnaBridge 189:f392fc9709a3 669
AnnaBridge 189:f392fc9709a3 670 /*!
AnnaBridge 189:f392fc9709a3 671 * @brief Gets the DSPI POPR data register address for the DMA operation.
AnnaBridge 189:f392fc9709a3 672 *
AnnaBridge 189:f392fc9709a3 673 * This function gets the DSPI POPR data register address as this value is needed for the DMA operation.
AnnaBridge 189:f392fc9709a3 674 *
AnnaBridge 189:f392fc9709a3 675 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 676 * @return The DSPI POPR data register address.
AnnaBridge 189:f392fc9709a3 677 */
AnnaBridge 189:f392fc9709a3 678 static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 679 {
AnnaBridge 189:f392fc9709a3 680 return (uint32_t) & (base->POPR);
AnnaBridge 189:f392fc9709a3 681 }
AnnaBridge 189:f392fc9709a3 682
AnnaBridge 189:f392fc9709a3 683 /*!
AnnaBridge 189:f392fc9709a3 684 *@}
AnnaBridge 189:f392fc9709a3 685 */
AnnaBridge 189:f392fc9709a3 686
AnnaBridge 189:f392fc9709a3 687 /*!
AnnaBridge 189:f392fc9709a3 688 * @name Bus Operations
AnnaBridge 189:f392fc9709a3 689 * @{
AnnaBridge 189:f392fc9709a3 690 */
AnnaBridge 189:f392fc9709a3 691
AnnaBridge 189:f392fc9709a3 692 /*!
AnnaBridge 189:f392fc9709a3 693 * @brief Configures the DSPI for master or slave.
AnnaBridge 189:f392fc9709a3 694 *
AnnaBridge 189:f392fc9709a3 695 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 696 * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t.
AnnaBridge 189:f392fc9709a3 697 */
AnnaBridge 189:f392fc9709a3 698 static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
AnnaBridge 189:f392fc9709a3 699 {
AnnaBridge 189:f392fc9709a3 700 base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode);
AnnaBridge 189:f392fc9709a3 701 }
AnnaBridge 189:f392fc9709a3 702
AnnaBridge 189:f392fc9709a3 703 /*!
AnnaBridge 189:f392fc9709a3 704 * @brief Returns whether the DSPI module is in master mode.
AnnaBridge 189:f392fc9709a3 705 *
AnnaBridge 189:f392fc9709a3 706 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 707 * @return Returns true if the module is in master mode or false if the module is in slave mode.
AnnaBridge 189:f392fc9709a3 708 */
AnnaBridge 189:f392fc9709a3 709 static inline bool DSPI_IsMaster(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 710 {
AnnaBridge 189:f392fc9709a3 711 return (bool)((base->MCR) & SPI_MCR_MSTR_MASK);
AnnaBridge 189:f392fc9709a3 712 }
AnnaBridge 189:f392fc9709a3 713 /*!
AnnaBridge 189:f392fc9709a3 714 * @brief Starts the DSPI transfers and clears HALT bit in MCR.
AnnaBridge 189:f392fc9709a3 715 *
AnnaBridge 189:f392fc9709a3 716 * This function sets the module to start data transfer in either master or slave mode.
AnnaBridge 189:f392fc9709a3 717 *
AnnaBridge 189:f392fc9709a3 718 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 719 */
AnnaBridge 189:f392fc9709a3 720 static inline void DSPI_StartTransfer(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 721 {
AnnaBridge 189:f392fc9709a3 722 base->MCR &= ~SPI_MCR_HALT_MASK;
AnnaBridge 189:f392fc9709a3 723 }
AnnaBridge 189:f392fc9709a3 724 /*!
AnnaBridge 189:f392fc9709a3 725 * @brief Stops DSPI transfers and sets the HALT bit in MCR.
AnnaBridge 189:f392fc9709a3 726 *
AnnaBridge 189:f392fc9709a3 727 * This function stops data transfers in either master or slave modes.
AnnaBridge 189:f392fc9709a3 728 *
AnnaBridge 189:f392fc9709a3 729 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 730 */
AnnaBridge 189:f392fc9709a3 731 static inline void DSPI_StopTransfer(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 732 {
AnnaBridge 189:f392fc9709a3 733 base->MCR |= SPI_MCR_HALT_MASK;
AnnaBridge 189:f392fc9709a3 734 }
AnnaBridge 189:f392fc9709a3 735
AnnaBridge 189:f392fc9709a3 736 /*!
AnnaBridge 189:f392fc9709a3 737 * @brief Enables or disables the DSPI FIFOs.
AnnaBridge 189:f392fc9709a3 738 *
AnnaBridge 189:f392fc9709a3 739 * This function allows the caller to disable/enable the Tx and Rx FIFOs independently.
AnnaBridge 189:f392fc9709a3 740 * Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration. To enable,
AnnaBridge 189:f392fc9709a3 741 * pass in a logic 1 (true).
AnnaBridge 189:f392fc9709a3 742 *
AnnaBridge 189:f392fc9709a3 743 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 744 * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO
AnnaBridge 189:f392fc9709a3 745 * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO
AnnaBridge 189:f392fc9709a3 746 */
AnnaBridge 189:f392fc9709a3 747 static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
AnnaBridge 189:f392fc9709a3 748 {
AnnaBridge 189:f392fc9709a3 749 base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) |
AnnaBridge 189:f392fc9709a3 750 SPI_MCR_DIS_RXF(!enableRxFifo);
AnnaBridge 189:f392fc9709a3 751 }
AnnaBridge 189:f392fc9709a3 752
AnnaBridge 189:f392fc9709a3 753 /*!
AnnaBridge 189:f392fc9709a3 754 * @brief Flushes the DSPI FIFOs.
AnnaBridge 189:f392fc9709a3 755 *
AnnaBridge 189:f392fc9709a3 756 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 757 * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO
AnnaBridge 189:f392fc9709a3 758 * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO
AnnaBridge 189:f392fc9709a3 759 */
AnnaBridge 189:f392fc9709a3 760 static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
AnnaBridge 189:f392fc9709a3 761 {
AnnaBridge 189:f392fc9709a3 762 base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) |
AnnaBridge 189:f392fc9709a3 763 SPI_MCR_CLR_RXF(flushRxFifo);
AnnaBridge 189:f392fc9709a3 764 }
AnnaBridge 189:f392fc9709a3 765
AnnaBridge 189:f392fc9709a3 766 /*!
AnnaBridge 189:f392fc9709a3 767 * @brief Configures the DSPI peripheral chip select polarity simultaneously.
AnnaBridge 189:f392fc9709a3 768 * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of
AnnaBridge 189:f392fc9709a3 769 * PCSs is specific to the device.
AnnaBridge 189:f392fc9709a3 770 * @code
AnnaBridge 189:f392fc9709a3 771 * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow);
AnnaBridge 189:f392fc9709a3 772 @endcode
AnnaBridge 189:f392fc9709a3 773 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 774 * @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity.
AnnaBridge 189:f392fc9709a3 775 */
AnnaBridge 189:f392fc9709a3 776 static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
AnnaBridge 189:f392fc9709a3 777 {
AnnaBridge 189:f392fc9709a3 778 base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask);
AnnaBridge 189:f392fc9709a3 779 }
AnnaBridge 189:f392fc9709a3 780
AnnaBridge 189:f392fc9709a3 781 /*!
AnnaBridge 189:f392fc9709a3 782 * @brief Sets the DSPI baud rate in bits per second.
AnnaBridge 189:f392fc9709a3 783 *
AnnaBridge 189:f392fc9709a3 784 * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without
AnnaBridge 189:f392fc9709a3 785 * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the
AnnaBridge 189:f392fc9709a3 786 * caller also provide the frequency of the module source clock (in Hertz).
AnnaBridge 189:f392fc9709a3 787 *
AnnaBridge 189:f392fc9709a3 788 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 789 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t
AnnaBridge 189:f392fc9709a3 790 * @param baudRate_Bps The desired baud rate in bits per second
AnnaBridge 189:f392fc9709a3 791 * @param srcClock_Hz Module source input clock in Hertz
AnnaBridge 189:f392fc9709a3 792 * @return The actual calculated baud rate
AnnaBridge 189:f392fc9709a3 793 */
AnnaBridge 189:f392fc9709a3 794 uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
AnnaBridge 189:f392fc9709a3 795 dspi_ctar_selection_t whichCtar,
AnnaBridge 189:f392fc9709a3 796 uint32_t baudRate_Bps,
AnnaBridge 189:f392fc9709a3 797 uint32_t srcClock_Hz);
AnnaBridge 189:f392fc9709a3 798
AnnaBridge 189:f392fc9709a3 799 /*!
AnnaBridge 189:f392fc9709a3 800 * @brief Manually configures the delay prescaler and scaler for a particular CTAR.
AnnaBridge 189:f392fc9709a3 801 *
AnnaBridge 189:f392fc9709a3 802 * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
AnnaBridge 189:f392fc9709a3 803 * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT).
AnnaBridge 189:f392fc9709a3 804 *
AnnaBridge 189:f392fc9709a3 805 * These delay names are available in the type dspi_delay_type_t.
AnnaBridge 189:f392fc9709a3 806 *
AnnaBridge 189:f392fc9709a3 807 * The user passes the delay to the configuration along with the prescaler and scaler value.
AnnaBridge 189:f392fc9709a3 808 * This allows the user to directly set the prescaler/scaler values if pre-calculated or
AnnaBridge 189:f392fc9709a3 809 * to manually increment either value.
AnnaBridge 189:f392fc9709a3 810 *
AnnaBridge 189:f392fc9709a3 811 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 812 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
AnnaBridge 189:f392fc9709a3 813 * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
AnnaBridge 189:f392fc9709a3 814 * @param scaler The scaler delay value (can be any integer between 0 to 15).
AnnaBridge 189:f392fc9709a3 815 * @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t
AnnaBridge 189:f392fc9709a3 816 */
AnnaBridge 189:f392fc9709a3 817 void DSPI_MasterSetDelayScaler(
AnnaBridge 189:f392fc9709a3 818 SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
AnnaBridge 189:f392fc9709a3 819
AnnaBridge 189:f392fc9709a3 820 /*!
AnnaBridge 189:f392fc9709a3 821 * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
AnnaBridge 189:f392fc9709a3 822 *
AnnaBridge 189:f392fc9709a3 823 * This function calculates the values for the following.
AnnaBridge 189:f392fc9709a3 824 * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
AnnaBridge 189:f392fc9709a3 825 * After SCK delay pre-scalar (PASC) and scalar (ASC), or
AnnaBridge 189:f392fc9709a3 826 * Delay after transfer pre-scalar (PDT) and scalar (DT).
AnnaBridge 189:f392fc9709a3 827 *
AnnaBridge 189:f392fc9709a3 828 * These delay names are available in the type dspi_delay_type_t.
AnnaBridge 189:f392fc9709a3 829 *
AnnaBridge 189:f392fc9709a3 830 * The user passes which delay to configure along with the desired delay value in nanoseconds. The function
AnnaBridge 189:f392fc9709a3 831 * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact
AnnaBridge 189:f392fc9709a3 832 * delay match may not be possible. In this case, the closest match is calculated without going below the desired
AnnaBridge 189:f392fc9709a3 833 * delay value input.
AnnaBridge 189:f392fc9709a3 834 * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
AnnaBridge 189:f392fc9709a3 835 * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay
AnnaBridge 189:f392fc9709a3 836 * input.
AnnaBridge 189:f392fc9709a3 837 *
AnnaBridge 189:f392fc9709a3 838 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 839 * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
AnnaBridge 189:f392fc9709a3 840 * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
AnnaBridge 189:f392fc9709a3 841 * @param srcClock_Hz Module source input clock in Hertz
AnnaBridge 189:f392fc9709a3 842 * @param delayTimeInNanoSec The desired delay value in nanoseconds.
AnnaBridge 189:f392fc9709a3 843 * @return The actual calculated delay value.
AnnaBridge 189:f392fc9709a3 844 */
AnnaBridge 189:f392fc9709a3 845 uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
AnnaBridge 189:f392fc9709a3 846 dspi_ctar_selection_t whichCtar,
AnnaBridge 189:f392fc9709a3 847 dspi_delay_type_t whichDelay,
AnnaBridge 189:f392fc9709a3 848 uint32_t srcClock_Hz,
AnnaBridge 189:f392fc9709a3 849 uint32_t delayTimeInNanoSec);
AnnaBridge 189:f392fc9709a3 850
AnnaBridge 189:f392fc9709a3 851 /*!
AnnaBridge 189:f392fc9709a3 852 * @brief Writes data into the data buffer for master mode.
AnnaBridge 189:f392fc9709a3 853 *
AnnaBridge 189:f392fc9709a3 854 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
AnnaBridge 189:f392fc9709a3 855 * provides characteristics of the data, such as the optional continuous chip select
AnnaBridge 189:f392fc9709a3 856 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
AnnaBridge 189:f392fc9709a3 857 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
AnnaBridge 189:f392fc9709a3 858 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
AnnaBridge 189:f392fc9709a3 859 * sending the first frame of a data packet). This is an example.
AnnaBridge 189:f392fc9709a3 860 * @code
AnnaBridge 189:f392fc9709a3 861 * dspi_command_data_config_t commandConfig;
AnnaBridge 189:f392fc9709a3 862 * commandConfig.isPcsContinuous = true;
AnnaBridge 189:f392fc9709a3 863 * commandConfig.whichCtar = kDSPICtar0;
AnnaBridge 189:f392fc9709a3 864 * commandConfig.whichPcs = kDSPIPcs0;
AnnaBridge 189:f392fc9709a3 865 * commandConfig.clearTransferCount = false;
AnnaBridge 189:f392fc9709a3 866 * commandConfig.isEndOfQueue = false;
AnnaBridge 189:f392fc9709a3 867 * DSPI_MasterWriteData(base, &commandConfig, dataWord);
AnnaBridge 189:f392fc9709a3 868 @endcode
AnnaBridge 189:f392fc9709a3 869 *
AnnaBridge 189:f392fc9709a3 870 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 871 * @param command Pointer to the command structure.
AnnaBridge 189:f392fc9709a3 872 * @param data The data word to be sent.
AnnaBridge 189:f392fc9709a3 873 */
AnnaBridge 189:f392fc9709a3 874 static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data)
AnnaBridge 189:f392fc9709a3 875 {
AnnaBridge 189:f392fc9709a3 876 base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
AnnaBridge 189:f392fc9709a3 877 SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
AnnaBridge 189:f392fc9709a3 878 SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data);
AnnaBridge 189:f392fc9709a3 879 }
AnnaBridge 189:f392fc9709a3 880
AnnaBridge 189:f392fc9709a3 881 /*!
AnnaBridge 189:f392fc9709a3 882 * @brief Sets the dspi_command_data_config_t structure to default values.
AnnaBridge 189:f392fc9709a3 883 *
AnnaBridge 189:f392fc9709a3 884 * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx().
AnnaBridge 189:f392fc9709a3 885 * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure
AnnaBridge 189:f392fc9709a3 886 * before calling the DSPI_MasterWrite_xx().
AnnaBridge 189:f392fc9709a3 887 * This is an example.
AnnaBridge 189:f392fc9709a3 888 * @code
AnnaBridge 189:f392fc9709a3 889 * dspi_command_data_config_t command;
AnnaBridge 189:f392fc9709a3 890 * DSPI_GetDefaultDataCommandConfig(&command);
AnnaBridge 189:f392fc9709a3 891 * @endcode
AnnaBridge 189:f392fc9709a3 892 * @param command Pointer to the dspi_command_data_config_t structure.
AnnaBridge 189:f392fc9709a3 893 */
AnnaBridge 189:f392fc9709a3 894 void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
AnnaBridge 189:f392fc9709a3 895
AnnaBridge 189:f392fc9709a3 896 /*!
AnnaBridge 189:f392fc9709a3 897 * @brief Writes data into the data buffer master mode and waits till complete to return.
AnnaBridge 189:f392fc9709a3 898 *
AnnaBridge 189:f392fc9709a3 899 * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
AnnaBridge 189:f392fc9709a3 900 * provides characteristics of the data, such as the optional continuous chip select
AnnaBridge 189:f392fc9709a3 901 * operation between transfers, the desired Clock and Transfer Attributes register to use for the
AnnaBridge 189:f392fc9709a3 902 * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
AnnaBridge 189:f392fc9709a3 903 * transfer is the last in the queue, and whether to clear the transfer count (normally needed when
AnnaBridge 189:f392fc9709a3 904 * sending the first frame of a data packet). This is an example.
AnnaBridge 189:f392fc9709a3 905 * @code
AnnaBridge 189:f392fc9709a3 906 * dspi_command_config_t commandConfig;
AnnaBridge 189:f392fc9709a3 907 * commandConfig.isPcsContinuous = true;
AnnaBridge 189:f392fc9709a3 908 * commandConfig.whichCtar = kDSPICtar0;
AnnaBridge 189:f392fc9709a3 909 * commandConfig.whichPcs = kDSPIPcs1;
AnnaBridge 189:f392fc9709a3 910 * commandConfig.clearTransferCount = false;
AnnaBridge 189:f392fc9709a3 911 * commandConfig.isEndOfQueue = false;
AnnaBridge 189:f392fc9709a3 912 * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord);
AnnaBridge 189:f392fc9709a3 913 * @endcode
AnnaBridge 189:f392fc9709a3 914 *
AnnaBridge 189:f392fc9709a3 915 * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
AnnaBridge 189:f392fc9709a3 916 * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
AnnaBridge 189:f392fc9709a3 917 * the received data is available when the transmit completes.
AnnaBridge 189:f392fc9709a3 918 *
AnnaBridge 189:f392fc9709a3 919 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 920 * @param command Pointer to the command structure.
AnnaBridge 189:f392fc9709a3 921 * @param data The data word to be sent.
AnnaBridge 189:f392fc9709a3 922 */
AnnaBridge 189:f392fc9709a3 923 void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data);
AnnaBridge 189:f392fc9709a3 924
AnnaBridge 189:f392fc9709a3 925 /*!
AnnaBridge 189:f392fc9709a3 926 * @brief Returns the DSPI command word formatted to the PUSHR data register bit field.
AnnaBridge 189:f392fc9709a3 927 *
AnnaBridge 189:f392fc9709a3 928 * This function allows the caller to pass in the data command structure and returns the command word formatted
AnnaBridge 189:f392fc9709a3 929 * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the
AnnaBridge 189:f392fc9709a3 930 * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or
AnnaBridge 189:f392fc9709a3 931 * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps
AnnaBridge 189:f392fc9709a3 932 * improve performance in cases where the command structure is constant. For example, the user calls this function
AnnaBridge 189:f392fc9709a3 933 * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
AnnaBridge 189:f392fc9709a3 934 * this formatted command word with the desired data to transmit. This process increases transmit performance when
AnnaBridge 189:f392fc9709a3 935 * compared to calling send functions, such as DSPI_HAL_WriteDataMastermode, which format the command word each time a
AnnaBridge 189:f392fc9709a3 936 * data word is to be sent.
AnnaBridge 189:f392fc9709a3 937 *
AnnaBridge 189:f392fc9709a3 938 * @param command Pointer to the command structure.
AnnaBridge 189:f392fc9709a3 939 * @return The command word formatted to the PUSHR data register bit field.
AnnaBridge 189:f392fc9709a3 940 */
AnnaBridge 189:f392fc9709a3 941 static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
AnnaBridge 189:f392fc9709a3 942 {
AnnaBridge 189:f392fc9709a3 943 /* Format the 16-bit command word according to the PUSHR data register bit field*/
AnnaBridge 189:f392fc9709a3 944 return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) |
AnnaBridge 189:f392fc9709a3 945 SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) |
AnnaBridge 189:f392fc9709a3 946 SPI_PUSHR_CTCNT(command->clearTransferCount));
AnnaBridge 189:f392fc9709a3 947 }
AnnaBridge 189:f392fc9709a3 948
AnnaBridge 189:f392fc9709a3 949 /*!
AnnaBridge 189:f392fc9709a3 950 * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
AnnaBridge 189:f392fc9709a3 951 * buffer master mode and waits till complete to return.
AnnaBridge 189:f392fc9709a3 952 *
AnnaBridge 189:f392fc9709a3 953 * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total 32-bit word
AnnaBridge 189:f392fc9709a3 954 * as the data to send.
AnnaBridge 189:f392fc9709a3 955 * The command portion provides characteristics of the data, such as the optional continuous chip select operation
AnnaBridge 189:f392fc9709a3 956 * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
AnnaBridge 189:f392fc9709a3 957 * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
AnnaBridge 189:f392fc9709a3 958 * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
AnnaBridge 189:f392fc9709a3 959 * appending this command with the data to send. This is an example:
AnnaBridge 189:f392fc9709a3 960 * @code
AnnaBridge 189:f392fc9709a3 961 * dataWord = <16-bit command> | <16-bit data>;
AnnaBridge 189:f392fc9709a3 962 * DSPI_MasterWriteCommandDataBlocking(base, dataWord);
AnnaBridge 189:f392fc9709a3 963 * @endcode
AnnaBridge 189:f392fc9709a3 964 *
AnnaBridge 189:f392fc9709a3 965 * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
AnnaBridge 189:f392fc9709a3 966 * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
AnnaBridge 189:f392fc9709a3 967 * Because the SPI is a synchronous protocol, the received data is available when the transmit completes.
AnnaBridge 189:f392fc9709a3 968 *
AnnaBridge 189:f392fc9709a3 969 * For a blocking polling transfer, see methods below.
AnnaBridge 189:f392fc9709a3 970 * Option 1:
AnnaBridge 189:f392fc9709a3 971 * uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command);
AnnaBridge 189:f392fc9709a3 972 * uint32_t data0 = command_to_send | data_need_to_send_0;
AnnaBridge 189:f392fc9709a3 973 * uint32_t data1 = command_to_send | data_need_to_send_1;
AnnaBridge 189:f392fc9709a3 974 * uint32_t data2 = command_to_send | data_need_to_send_2;
AnnaBridge 189:f392fc9709a3 975 *
AnnaBridge 189:f392fc9709a3 976 * DSPI_MasterWriteCommandDataBlocking(base,data0);
AnnaBridge 189:f392fc9709a3 977 * DSPI_MasterWriteCommandDataBlocking(base,data1);
AnnaBridge 189:f392fc9709a3 978 * DSPI_MasterWriteCommandDataBlocking(base,data2);
AnnaBridge 189:f392fc9709a3 979 *
AnnaBridge 189:f392fc9709a3 980 * Option 2:
AnnaBridge 189:f392fc9709a3 981 * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0);
AnnaBridge 189:f392fc9709a3 982 * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1);
AnnaBridge 189:f392fc9709a3 983 * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
AnnaBridge 189:f392fc9709a3 984 *
AnnaBridge 189:f392fc9709a3 985 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 986 * @param data The data word (command and data combined) to be sent.
AnnaBridge 189:f392fc9709a3 987 */
AnnaBridge 189:f392fc9709a3 988 void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
AnnaBridge 189:f392fc9709a3 989
AnnaBridge 189:f392fc9709a3 990 /*!
AnnaBridge 189:f392fc9709a3 991 * @brief Writes data into the data buffer in slave mode.
AnnaBridge 189:f392fc9709a3 992 *
AnnaBridge 189:f392fc9709a3 993 * In slave mode, up to 16-bit words may be written.
AnnaBridge 189:f392fc9709a3 994 *
AnnaBridge 189:f392fc9709a3 995 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 996 * @param data The data to send.
AnnaBridge 189:f392fc9709a3 997 */
AnnaBridge 189:f392fc9709a3 998 static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
AnnaBridge 189:f392fc9709a3 999 {
AnnaBridge 189:f392fc9709a3 1000 base->PUSHR_SLAVE = data;
AnnaBridge 189:f392fc9709a3 1001 }
AnnaBridge 189:f392fc9709a3 1002
AnnaBridge 189:f392fc9709a3 1003 /*!
AnnaBridge 189:f392fc9709a3 1004 * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns.
AnnaBridge 189:f392fc9709a3 1005 *
AnnaBridge 189:f392fc9709a3 1006 * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data
AnnaBridge 189:f392fc9709a3 1007 * into data register, and finally waits until the data is transmitted.
AnnaBridge 189:f392fc9709a3 1008 *
AnnaBridge 189:f392fc9709a3 1009 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 1010 * @param data The data to send.
AnnaBridge 189:f392fc9709a3 1011 */
AnnaBridge 189:f392fc9709a3 1012 void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);
AnnaBridge 189:f392fc9709a3 1013
AnnaBridge 189:f392fc9709a3 1014 /*!
AnnaBridge 189:f392fc9709a3 1015 * @brief Reads data from the data buffer.
AnnaBridge 189:f392fc9709a3 1016 *
AnnaBridge 189:f392fc9709a3 1017 * @param base DSPI peripheral address.
AnnaBridge 189:f392fc9709a3 1018 * @return The data from the read data buffer.
AnnaBridge 189:f392fc9709a3 1019 */
AnnaBridge 189:f392fc9709a3 1020 static inline uint32_t DSPI_ReadData(SPI_Type *base)
AnnaBridge 189:f392fc9709a3 1021 {
AnnaBridge 189:f392fc9709a3 1022 return (base->POPR);
AnnaBridge 189:f392fc9709a3 1023 }
AnnaBridge 189:f392fc9709a3 1024
AnnaBridge 189:f392fc9709a3 1025 /*!
AnnaBridge 189:f392fc9709a3 1026 *@}
AnnaBridge 189:f392fc9709a3 1027 */
AnnaBridge 189:f392fc9709a3 1028
AnnaBridge 189:f392fc9709a3 1029 /*!
AnnaBridge 189:f392fc9709a3 1030 * @name Transactional
AnnaBridge 189:f392fc9709a3 1031 * @{
AnnaBridge 189:f392fc9709a3 1032 */
AnnaBridge 189:f392fc9709a3 1033 /*Transactional APIs*/
AnnaBridge 189:f392fc9709a3 1034
AnnaBridge 189:f392fc9709a3 1035 /*!
AnnaBridge 189:f392fc9709a3 1036 * @brief Initializes the DSPI master handle.
AnnaBridge 189:f392fc9709a3 1037 *
AnnaBridge 189:f392fc9709a3 1038 * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
AnnaBridge 189:f392fc9709a3 1039 * specified DSPI instance, call this API once to get the initialized handle.
AnnaBridge 189:f392fc9709a3 1040 *
AnnaBridge 189:f392fc9709a3 1041 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1042 * @param handle DSPI handle pointer to dspi_master_handle_t.
AnnaBridge 189:f392fc9709a3 1043 * @param callback DSPI callback.
AnnaBridge 189:f392fc9709a3 1044 * @param userData Callback function parameter.
AnnaBridge 189:f392fc9709a3 1045 */
AnnaBridge 189:f392fc9709a3 1046 void DSPI_MasterTransferCreateHandle(SPI_Type *base,
AnnaBridge 189:f392fc9709a3 1047 dspi_master_handle_t *handle,
AnnaBridge 189:f392fc9709a3 1048 dspi_master_transfer_callback_t callback,
AnnaBridge 189:f392fc9709a3 1049 void *userData);
AnnaBridge 189:f392fc9709a3 1050
AnnaBridge 189:f392fc9709a3 1051 /*!
AnnaBridge 189:f392fc9709a3 1052 * @brief DSPI master transfer data using polling.
AnnaBridge 189:f392fc9709a3 1053 *
AnnaBridge 189:f392fc9709a3 1054 * This function transfers data using polling. This is a blocking function, which does not return until all transfers
AnnaBridge 189:f392fc9709a3 1055 * have been completed.
AnnaBridge 189:f392fc9709a3 1056 *
AnnaBridge 189:f392fc9709a3 1057 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1058 * @param transfer Pointer to the dspi_transfer_t structure.
AnnaBridge 189:f392fc9709a3 1059 * @return status of status_t.
AnnaBridge 189:f392fc9709a3 1060 */
AnnaBridge 189:f392fc9709a3 1061 status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer);
AnnaBridge 189:f392fc9709a3 1062
AnnaBridge 189:f392fc9709a3 1063 /*!
AnnaBridge 189:f392fc9709a3 1064 * @brief DSPI master transfer data using interrupts.
AnnaBridge 189:f392fc9709a3 1065 *
AnnaBridge 189:f392fc9709a3 1066 * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
AnnaBridge 189:f392fc9709a3 1067 * data is transferred, the callback function is called.
AnnaBridge 189:f392fc9709a3 1068
AnnaBridge 189:f392fc9709a3 1069 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1070 * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1071 * @param transfer Pointer to the dspi_transfer_t structure.
AnnaBridge 189:f392fc9709a3 1072 * @return status of status_t.
AnnaBridge 189:f392fc9709a3 1073 */
AnnaBridge 189:f392fc9709a3 1074 status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
AnnaBridge 189:f392fc9709a3 1075
AnnaBridge 189:f392fc9709a3 1076 /*!
AnnaBridge 189:f392fc9709a3 1077 * @brief Gets the master transfer count.
AnnaBridge 189:f392fc9709a3 1078 *
AnnaBridge 189:f392fc9709a3 1079 * This function gets the master transfer count.
AnnaBridge 189:f392fc9709a3 1080 *
AnnaBridge 189:f392fc9709a3 1081 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1082 * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1083 * @param count The number of bytes transferred by using the non-blocking transaction.
AnnaBridge 189:f392fc9709a3 1084 * @return status of status_t.
AnnaBridge 189:f392fc9709a3 1085 */
AnnaBridge 189:f392fc9709a3 1086 status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count);
AnnaBridge 189:f392fc9709a3 1087
AnnaBridge 189:f392fc9709a3 1088 /*!
AnnaBridge 189:f392fc9709a3 1089 * @brief DSPI master aborts a transfer using an interrupt.
AnnaBridge 189:f392fc9709a3 1090 *
AnnaBridge 189:f392fc9709a3 1091 * This function aborts a transfer using an interrupt.
AnnaBridge 189:f392fc9709a3 1092 *
AnnaBridge 189:f392fc9709a3 1093 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1094 * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1095 */
AnnaBridge 189:f392fc9709a3 1096 void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle);
AnnaBridge 189:f392fc9709a3 1097
AnnaBridge 189:f392fc9709a3 1098 /*!
AnnaBridge 189:f392fc9709a3 1099 * @brief DSPI Master IRQ handler function.
AnnaBridge 189:f392fc9709a3 1100 *
AnnaBridge 189:f392fc9709a3 1101 * This function processes the DSPI transmit and receive IRQ.
AnnaBridge 189:f392fc9709a3 1102
AnnaBridge 189:f392fc9709a3 1103 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1104 * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1105 */
AnnaBridge 189:f392fc9709a3 1106 void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle);
AnnaBridge 189:f392fc9709a3 1107
AnnaBridge 189:f392fc9709a3 1108 /*!
AnnaBridge 189:f392fc9709a3 1109 * @brief Initializes the DSPI slave handle.
AnnaBridge 189:f392fc9709a3 1110 *
AnnaBridge 189:f392fc9709a3 1111 * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
AnnaBridge 189:f392fc9709a3 1112 * specified DSPI instance, call this API once to get the initialized handle.
AnnaBridge 189:f392fc9709a3 1113 *
AnnaBridge 189:f392fc9709a3 1114 * @param handle DSPI handle pointer to the dspi_slave_handle_t.
AnnaBridge 189:f392fc9709a3 1115 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1116 * @param callback DSPI callback.
AnnaBridge 189:f392fc9709a3 1117 * @param userData Callback function parameter.
AnnaBridge 189:f392fc9709a3 1118 */
AnnaBridge 189:f392fc9709a3 1119 void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
AnnaBridge 189:f392fc9709a3 1120 dspi_slave_handle_t *handle,
AnnaBridge 189:f392fc9709a3 1121 dspi_slave_transfer_callback_t callback,
AnnaBridge 189:f392fc9709a3 1122 void *userData);
AnnaBridge 189:f392fc9709a3 1123
AnnaBridge 189:f392fc9709a3 1124 /*!
AnnaBridge 189:f392fc9709a3 1125 * @brief DSPI slave transfers data using an interrupt.
AnnaBridge 189:f392fc9709a3 1126 *
AnnaBridge 189:f392fc9709a3 1127 * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
AnnaBridge 189:f392fc9709a3 1128 * data is transferred, the callback function is called.
AnnaBridge 189:f392fc9709a3 1129 *
AnnaBridge 189:f392fc9709a3 1130 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1131 * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1132 * @param transfer Pointer to the dspi_transfer_t structure.
AnnaBridge 189:f392fc9709a3 1133 * @return status of status_t.
AnnaBridge 189:f392fc9709a3 1134 */
AnnaBridge 189:f392fc9709a3 1135 status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer);
AnnaBridge 189:f392fc9709a3 1136
AnnaBridge 189:f392fc9709a3 1137 /*!
AnnaBridge 189:f392fc9709a3 1138 * @brief Gets the slave transfer count.
AnnaBridge 189:f392fc9709a3 1139 *
AnnaBridge 189:f392fc9709a3 1140 * This function gets the slave transfer count.
AnnaBridge 189:f392fc9709a3 1141 *
AnnaBridge 189:f392fc9709a3 1142 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1143 * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1144 * @param count The number of bytes transferred by using the non-blocking transaction.
AnnaBridge 189:f392fc9709a3 1145 * @return status of status_t.
AnnaBridge 189:f392fc9709a3 1146 */
AnnaBridge 189:f392fc9709a3 1147 status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count);
AnnaBridge 189:f392fc9709a3 1148
AnnaBridge 189:f392fc9709a3 1149 /*!
AnnaBridge 189:f392fc9709a3 1150 * @brief DSPI slave aborts a transfer using an interrupt.
AnnaBridge 189:f392fc9709a3 1151 *
AnnaBridge 189:f392fc9709a3 1152 * This function aborts a transfer using an interrupt.
AnnaBridge 189:f392fc9709a3 1153 *
AnnaBridge 189:f392fc9709a3 1154 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1155 * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1156 */
AnnaBridge 189:f392fc9709a3 1157 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle);
AnnaBridge 189:f392fc9709a3 1158
AnnaBridge 189:f392fc9709a3 1159 /*!
AnnaBridge 189:f392fc9709a3 1160 * @brief DSPI Master IRQ handler function.
AnnaBridge 189:f392fc9709a3 1161 *
AnnaBridge 189:f392fc9709a3 1162 * This function processes the DSPI transmit and receive IRQ.
AnnaBridge 189:f392fc9709a3 1163 *
AnnaBridge 189:f392fc9709a3 1164 * @param base DSPI peripheral base address.
AnnaBridge 189:f392fc9709a3 1165 * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge 189:f392fc9709a3 1166 */
AnnaBridge 189:f392fc9709a3 1167 void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle);
AnnaBridge 189:f392fc9709a3 1168
AnnaBridge 189:f392fc9709a3 1169 /*!
AnnaBridge 189:f392fc9709a3 1170 *@}
AnnaBridge 189:f392fc9709a3 1171 */
AnnaBridge 189:f392fc9709a3 1172
AnnaBridge 189:f392fc9709a3 1173 #if defined(__cplusplus)
AnnaBridge 189:f392fc9709a3 1174 }
AnnaBridge 189:f392fc9709a3 1175 #endif /*_cplusplus*/
AnnaBridge 189:f392fc9709a3 1176 /*!
AnnaBridge 189:f392fc9709a3 1177 *@}
AnnaBridge 189:f392fc9709a3 1178 */
AnnaBridge 189:f392fc9709a3 1179
AnnaBridge 189:f392fc9709a3 1180 #endif /*_FSL_DSPI_H_*/