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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/fsl_clock.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/*
AnnaBridge	189:f392fc9709a3	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge	189:f392fc9709a3	3	* All rights reserved.
AnnaBridge	189:f392fc9709a3	4	*
AnnaBridge	189:f392fc9709a3	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	6	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	7	*
AnnaBridge	189:f392fc9709a3	8	* o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	189:f392fc9709a3	9	* of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	189:f392fc9709a3	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	189:f392fc9709a3	13	* other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	14	*
AnnaBridge	189:f392fc9709a3	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge	189:f392fc9709a3	16	* contributors may be used to endorse or promote products derived from this
AnnaBridge	189:f392fc9709a3	17	* software without specific prior written permission.
AnnaBridge	189:f392fc9709a3	18	*
AnnaBridge	189:f392fc9709a3	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	189:f392fc9709a3	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	189:f392fc9709a3	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	189:f392fc9709a3	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	189:f392fc9709a3	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	189:f392fc9709a3	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	189:f392fc9709a3	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	189:f392fc9709a3	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	189:f392fc9709a3	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	29	*/
AnnaBridge	189:f392fc9709a3	30
AnnaBridge	189:f392fc9709a3	31	#ifndef _FSL_CLOCK_H_
AnnaBridge	189:f392fc9709a3	32	#define _FSL_CLOCK_H_
AnnaBridge	189:f392fc9709a3	33
AnnaBridge	189:f392fc9709a3	34	#include "fsl_common.h"
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/! @addtogroup clock /
AnnaBridge	189:f392fc9709a3	37	/! @{ /
AnnaBridge	189:f392fc9709a3	38
AnnaBridge	189:f392fc9709a3	39	/! @file /
AnnaBridge	189:f392fc9709a3	40
AnnaBridge	189:f392fc9709a3	41	/*******************************************************************************
AnnaBridge	189:f392fc9709a3	42	* Definitions
AnnaBridge	189:f392fc9709a3	43	******************************************************************************/
AnnaBridge	189:f392fc9709a3	44
AnnaBridge	189:f392fc9709a3	45	/*! @brief Configure whether driver controls clock
AnnaBridge	189:f392fc9709a3	46	*
AnnaBridge	189:f392fc9709a3	47	* When set to 0, peripheral drivers will enable clock in initialize function
AnnaBridge	189:f392fc9709a3	48	* and disable clock in de-initialize function. When set to 1, peripheral
AnnaBridge	189:f392fc9709a3	49	* driver will not control the clock, application could contol the clock out of
AnnaBridge	189:f392fc9709a3	50	* the driver.
AnnaBridge	189:f392fc9709a3	51	*
AnnaBridge	189:f392fc9709a3	52	* @note All drivers share this feature switcher. If it is set to 1, application
AnnaBridge	189:f392fc9709a3	53	* should handle clock enable and disable for all drivers.
AnnaBridge	189:f392fc9709a3	54	*/
AnnaBridge	189:f392fc9709a3	55	#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
AnnaBridge	189:f392fc9709a3	56	#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
AnnaBridge	189:f392fc9709a3	57	#endif
AnnaBridge	189:f392fc9709a3	58
AnnaBridge	189:f392fc9709a3	59	/! @name Driver version /
AnnaBridge	189:f392fc9709a3	60	/@{/
AnnaBridge	189:f392fc9709a3	61	/! @brief CLOCK driver version 2.2.0. /
AnnaBridge	189:f392fc9709a3	62	#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
AnnaBridge	189:f392fc9709a3	63	/@}/
AnnaBridge	189:f392fc9709a3	64
AnnaBridge	189:f392fc9709a3	65	/*! @brief External XTAL0 (OSC0) clock frequency.
AnnaBridge	189:f392fc9709a3	66	*
AnnaBridge	189:f392fc9709a3	67	* The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
AnnaBridge	189:f392fc9709a3	68	* function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
AnnaBridge	189:f392fc9709a3	69	* if XTAL0 is 8 MHz:
AnnaBridge	189:f392fc9709a3	70	* @code
AnnaBridge	189:f392fc9709a3	71	* CLOCK_InitOsc0(...); // Set up the OSC0
AnnaBridge	189:f392fc9709a3	72	* CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
AnnaBridge	189:f392fc9709a3	73	* @endcode
AnnaBridge	189:f392fc9709a3	74	*
AnnaBridge	189:f392fc9709a3	75	* This is important for the multicore platforms where only one core needs to set up the
AnnaBridge	189:f392fc9709a3	76	* OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
AnnaBridge	189:f392fc9709a3	77	* to get a valid clock frequency.
AnnaBridge	189:f392fc9709a3	78	*/
AnnaBridge	189:f392fc9709a3	79	extern uint32_t g_xtal0Freq;
AnnaBridge	189:f392fc9709a3	80
AnnaBridge	189:f392fc9709a3	81	/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
AnnaBridge	189:f392fc9709a3	82	*
AnnaBridge	189:f392fc9709a3	83	* The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
AnnaBridge	189:f392fc9709a3	84	* function CLOCK_SetXtal32Freq to set the value in the clock driver.
AnnaBridge	189:f392fc9709a3	85	*
AnnaBridge	189:f392fc9709a3	86	* This is important for the multicore platforms where only one core needs to set up
AnnaBridge	189:f392fc9709a3	87	* the clock. All other cores need to call the CLOCK_SetXtal32Freq
AnnaBridge	189:f392fc9709a3	88	* to get a valid clock frequency.
AnnaBridge	189:f392fc9709a3	89	*/
AnnaBridge	189:f392fc9709a3	90	extern uint32_t g_xtal32Freq;
AnnaBridge	189:f392fc9709a3	91
AnnaBridge	189:f392fc9709a3	92	/! @brief IRC48M clock frequency in Hz. /
AnnaBridge	189:f392fc9709a3	93	#define MCG_INTERNAL_IRC_48M 48000000U
AnnaBridge	189:f392fc9709a3	94
AnnaBridge	189:f392fc9709a3	95	#if (defined(OSC) && !(defined(OSC0)))
AnnaBridge	189:f392fc9709a3	96	#define OSC0 OSC
AnnaBridge	189:f392fc9709a3	97	#endif
AnnaBridge	189:f392fc9709a3	98
AnnaBridge	189:f392fc9709a3	99	/! @brief Clock ip name array for DMAMUX. /
AnnaBridge	189:f392fc9709a3	100	#define DMAMUX_CLOCKS \
AnnaBridge	189:f392fc9709a3	101	{ \
AnnaBridge	189:f392fc9709a3	102	kCLOCK_Dmamux0 \
AnnaBridge	189:f392fc9709a3	103	}
AnnaBridge	189:f392fc9709a3	104
AnnaBridge	189:f392fc9709a3	105	/! @brief Clock ip name array for RTC. /
AnnaBridge	189:f392fc9709a3	106	#define RTC_CLOCKS \
AnnaBridge	189:f392fc9709a3	107	{ \
AnnaBridge	189:f392fc9709a3	108	kCLOCK_Rtc0 \
AnnaBridge	189:f392fc9709a3	109	}
AnnaBridge	189:f392fc9709a3	110
AnnaBridge	189:f392fc9709a3	111	/! @brief Clock ip name array for SAI. /
AnnaBridge	189:f392fc9709a3	112	#define SAI_CLOCKS \
AnnaBridge	189:f392fc9709a3	113	{ \
AnnaBridge	189:f392fc9709a3	114	kCLOCK_Sai0 \
AnnaBridge	189:f392fc9709a3	115	}
AnnaBridge	189:f392fc9709a3	116
AnnaBridge	189:f392fc9709a3	117	/! @brief Clock ip name array for PORT. /
AnnaBridge	189:f392fc9709a3	118	#define PORT_CLOCKS \
AnnaBridge	189:f392fc9709a3	119	{ \
AnnaBridge	189:f392fc9709a3	120	kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
AnnaBridge	189:f392fc9709a3	121	}
AnnaBridge	189:f392fc9709a3	122
AnnaBridge	189:f392fc9709a3	123	/! @brief Clock ip name array for FLEXBUS. /
AnnaBridge	189:f392fc9709a3	124	#define FLEXBUS_CLOCKS \
AnnaBridge	189:f392fc9709a3	125	{ \
AnnaBridge	189:f392fc9709a3	126	kCLOCK_Flexbus0 \
AnnaBridge	189:f392fc9709a3	127	}
AnnaBridge	189:f392fc9709a3	128
AnnaBridge	189:f392fc9709a3	129	/! @brief Clock ip name array for EWM. /
AnnaBridge	189:f392fc9709a3	130	#define EWM_CLOCKS \
AnnaBridge	189:f392fc9709a3	131	{ \
AnnaBridge	189:f392fc9709a3	132	kCLOCK_Ewm0 \
AnnaBridge	189:f392fc9709a3	133	}
AnnaBridge	189:f392fc9709a3	134
AnnaBridge	189:f392fc9709a3	135	/! @brief Clock ip name array for PIT. /
AnnaBridge	189:f392fc9709a3	136	#define PIT_CLOCKS \
AnnaBridge	189:f392fc9709a3	137	{ \
AnnaBridge	189:f392fc9709a3	138	kCLOCK_Pit0 \
AnnaBridge	189:f392fc9709a3	139	}
AnnaBridge	189:f392fc9709a3	140
AnnaBridge	189:f392fc9709a3	141	/! @brief Clock ip name array for DSPI. /
AnnaBridge	189:f392fc9709a3	142	#define DSPI_CLOCKS \
AnnaBridge	189:f392fc9709a3	143	{ \
AnnaBridge	189:f392fc9709a3	144	kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
AnnaBridge	189:f392fc9709a3	145	}
AnnaBridge	189:f392fc9709a3	146
AnnaBridge	189:f392fc9709a3	147	/! @brief Clock ip name array for EMVSIM. /
AnnaBridge	189:f392fc9709a3	148	#define EMVSIM_CLOCKS \
AnnaBridge	189:f392fc9709a3	149	{ \
AnnaBridge	189:f392fc9709a3	150	kCLOCK_Emvsim0, kCLOCK_Emvsim1 \
AnnaBridge	189:f392fc9709a3	151	}
AnnaBridge	189:f392fc9709a3	152
AnnaBridge	189:f392fc9709a3	153	/! @brief Clock ip name array for QSPI. /
AnnaBridge	189:f392fc9709a3	154	#define QSPI_CLOCKS \
AnnaBridge	189:f392fc9709a3	155	{ \
AnnaBridge	189:f392fc9709a3	156	kCLOCK_Qspi0 \
AnnaBridge	189:f392fc9709a3	157	}
AnnaBridge	189:f392fc9709a3	158
AnnaBridge	189:f392fc9709a3	159	/! @brief Clock ip name array for SDHC. /
AnnaBridge	189:f392fc9709a3	160	#define SDHC_CLOCKS \
AnnaBridge	189:f392fc9709a3	161	{ \
AnnaBridge	189:f392fc9709a3	162	kCLOCK_Sdhc0 \
AnnaBridge	189:f392fc9709a3	163	}
AnnaBridge	189:f392fc9709a3	164
AnnaBridge	189:f392fc9709a3	165	/! @brief Clock ip name array for FTM. /
AnnaBridge	189:f392fc9709a3	166	#define FTM_CLOCKS \
AnnaBridge	189:f392fc9709a3	167	{ \
AnnaBridge	189:f392fc9709a3	168	kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
AnnaBridge	189:f392fc9709a3	169	}
AnnaBridge	189:f392fc9709a3	170
AnnaBridge	189:f392fc9709a3	171	/! @brief Clock ip name array for EDMA. /
AnnaBridge	189:f392fc9709a3	172	#define EDMA_CLOCKS \
AnnaBridge	189:f392fc9709a3	173	{ \
AnnaBridge	189:f392fc9709a3	174	kCLOCK_Dma0 \
AnnaBridge	189:f392fc9709a3	175	}
AnnaBridge	189:f392fc9709a3	176
AnnaBridge	189:f392fc9709a3	177	/! @brief Clock ip name array for LPUART. /
AnnaBridge	189:f392fc9709a3	178	#define LPUART_CLOCKS \
AnnaBridge	189:f392fc9709a3	179	{ \
AnnaBridge	189:f392fc9709a3	180	kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \
AnnaBridge	189:f392fc9709a3	181	}
AnnaBridge	189:f392fc9709a3	182
AnnaBridge	189:f392fc9709a3	183	/! @brief Clock ip name array for DAC. /
AnnaBridge	189:f392fc9709a3	184	#define DAC_CLOCKS \
AnnaBridge	189:f392fc9709a3	185	{ \
AnnaBridge	189:f392fc9709a3	186	kCLOCK_Dac0 \
AnnaBridge	189:f392fc9709a3	187	}
AnnaBridge	189:f392fc9709a3	188
AnnaBridge	189:f392fc9709a3	189	/! @brief Clock ip name array for LPTMR. /
AnnaBridge	189:f392fc9709a3	190	#define LPTMR_CLOCKS \
AnnaBridge	189:f392fc9709a3	191	{ \
AnnaBridge	189:f392fc9709a3	192	kCLOCK_Lptmr0, kCLOCK_Lptmr1 \
AnnaBridge	189:f392fc9709a3	193	}
AnnaBridge	189:f392fc9709a3	194
AnnaBridge	189:f392fc9709a3	195	/! @brief Clock ip name array for ADC16. /
AnnaBridge	189:f392fc9709a3	196	#define ADC16_CLOCKS \
AnnaBridge	189:f392fc9709a3	197	{ \
AnnaBridge	189:f392fc9709a3	198	kCLOCK_Adc0 \
AnnaBridge	189:f392fc9709a3	199	}
AnnaBridge	189:f392fc9709a3	200
AnnaBridge	189:f392fc9709a3	201	/! @brief Clock ip name array for SDRAM. /
AnnaBridge	189:f392fc9709a3	202	#define SDRAM_CLOCKS \
AnnaBridge	189:f392fc9709a3	203	{ \
AnnaBridge	189:f392fc9709a3	204	kCLOCK_Sdramc0 \
AnnaBridge	189:f392fc9709a3	205	}
AnnaBridge	189:f392fc9709a3	206
AnnaBridge	189:f392fc9709a3	207	/! @brief Clock ip name array for TRNG. /
AnnaBridge	189:f392fc9709a3	208	#define TRNG_CLOCKS \
AnnaBridge	189:f392fc9709a3	209	{ \
AnnaBridge	189:f392fc9709a3	210	kCLOCK_Trng0 \
AnnaBridge	189:f392fc9709a3	211	}
AnnaBridge	189:f392fc9709a3	212
AnnaBridge	189:f392fc9709a3	213	/! @brief Clock ip name array for MPU. /
AnnaBridge	189:f392fc9709a3	214	#define MPU_CLOCKS \
AnnaBridge	189:f392fc9709a3	215	{ \
AnnaBridge	189:f392fc9709a3	216	kCLOCK_Mpu0 \
AnnaBridge	189:f392fc9709a3	217	}
AnnaBridge	189:f392fc9709a3	218
AnnaBridge	189:f392fc9709a3	219	/! @brief Clock ip name array for FLEXIO. /
AnnaBridge	189:f392fc9709a3	220	#define FLEXIO_CLOCKS \
AnnaBridge	189:f392fc9709a3	221	{ \
AnnaBridge	189:f392fc9709a3	222	kCLOCK_Flexio0 \
AnnaBridge	189:f392fc9709a3	223	}
AnnaBridge	189:f392fc9709a3	224
AnnaBridge	189:f392fc9709a3	225	/! @brief Clock ip name array for VREF. /
AnnaBridge	189:f392fc9709a3	226	#define VREF_CLOCKS \
AnnaBridge	189:f392fc9709a3	227	{ \
AnnaBridge	189:f392fc9709a3	228	kCLOCK_Vref0 \
AnnaBridge	189:f392fc9709a3	229	}
AnnaBridge	189:f392fc9709a3	230
AnnaBridge	189:f392fc9709a3	231	/! @brief Clock ip name array for CMT. /
AnnaBridge	189:f392fc9709a3	232	#define CMT_CLOCKS \
AnnaBridge	189:f392fc9709a3	233	{ \
AnnaBridge	189:f392fc9709a3	234	kCLOCK_Cmt0 \
AnnaBridge	189:f392fc9709a3	235	}
AnnaBridge	189:f392fc9709a3	236
AnnaBridge	189:f392fc9709a3	237	/! @brief Clock ip name array for TPM. /
AnnaBridge	189:f392fc9709a3	238	#define TPM_CLOCKS \
AnnaBridge	189:f392fc9709a3	239	{ \
AnnaBridge	189:f392fc9709a3	240	kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \
AnnaBridge	189:f392fc9709a3	241	}
AnnaBridge	189:f392fc9709a3	242
AnnaBridge	189:f392fc9709a3	243	/! @brief Clock ip name array for TSI. /
AnnaBridge	189:f392fc9709a3	244	#define TSI_CLOCKS \
AnnaBridge	189:f392fc9709a3	245	{ \
AnnaBridge	189:f392fc9709a3	246	kCLOCK_Tsi0 \
AnnaBridge	189:f392fc9709a3	247	}
AnnaBridge	189:f392fc9709a3	248
AnnaBridge	189:f392fc9709a3	249	/! @brief Clock ip name array for LTC. /
AnnaBridge	189:f392fc9709a3	250	#define LTC_CLOCKS \
AnnaBridge	189:f392fc9709a3	251	{ \
AnnaBridge	189:f392fc9709a3	252	kCLOCK_Ltc0 \
AnnaBridge	189:f392fc9709a3	253	}
AnnaBridge	189:f392fc9709a3	254
AnnaBridge	189:f392fc9709a3	255	/! @brief Clock ip name array for CRC. /
AnnaBridge	189:f392fc9709a3	256	#define CRC_CLOCKS \
AnnaBridge	189:f392fc9709a3	257	{ \
AnnaBridge	189:f392fc9709a3	258	kCLOCK_Crc0 \
AnnaBridge	189:f392fc9709a3	259	}
AnnaBridge	189:f392fc9709a3	260
AnnaBridge	189:f392fc9709a3	261	/! @brief Clock ip name array for I2C. /
AnnaBridge	189:f392fc9709a3	262	#define I2C_CLOCKS \
AnnaBridge	189:f392fc9709a3	263	{ \
AnnaBridge	189:f392fc9709a3	264	kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \
AnnaBridge	189:f392fc9709a3	265	}
AnnaBridge	189:f392fc9709a3	266
AnnaBridge	189:f392fc9709a3	267	/! @brief Clock ip name array for PDB. /
AnnaBridge	189:f392fc9709a3	268	#define PDB_CLOCKS \
AnnaBridge	189:f392fc9709a3	269	{ \
AnnaBridge	189:f392fc9709a3	270	kCLOCK_Pdb0 \
AnnaBridge	189:f392fc9709a3	271	}
AnnaBridge	189:f392fc9709a3	272
AnnaBridge	189:f392fc9709a3	273	/! @brief Clock ip name array for FTF. /
AnnaBridge	189:f392fc9709a3	274	#define FTF_CLOCKS \
AnnaBridge	189:f392fc9709a3	275	{ \
AnnaBridge	189:f392fc9709a3	276	kCLOCK_Ftf0 \
AnnaBridge	189:f392fc9709a3	277	}
AnnaBridge	189:f392fc9709a3	278
AnnaBridge	189:f392fc9709a3	279	/! @brief Clock ip name array for CMP. /
AnnaBridge	189:f392fc9709a3	280	#define CMP_CLOCKS \
AnnaBridge	189:f392fc9709a3	281	{ \
AnnaBridge	189:f392fc9709a3	282	kCLOCK_Cmp0, kCLOCK_Cmp1 \
AnnaBridge	189:f392fc9709a3	283	}
AnnaBridge	189:f392fc9709a3	284
AnnaBridge	189:f392fc9709a3	285	/*!
AnnaBridge	189:f392fc9709a3	286	* @brief LPO clock frequency.
AnnaBridge	189:f392fc9709a3	287	*/
AnnaBridge	189:f392fc9709a3	288	#define LPO_CLK_FREQ 1000U
AnnaBridge	189:f392fc9709a3	289
AnnaBridge	189:f392fc9709a3	290	/! @brief Peripherals clock source definition. /
AnnaBridge	189:f392fc9709a3	291	#define SYS_CLK kCLOCK_CoreSysClk
AnnaBridge	189:f392fc9709a3	292	#define BUS_CLK kCLOCK_BusClk
AnnaBridge	189:f392fc9709a3	293
AnnaBridge	189:f392fc9709a3	294	#define I2C0_CLK_SRC BUS_CLK
AnnaBridge	189:f392fc9709a3	295	#define I2C1_CLK_SRC BUS_CLK
AnnaBridge	189:f392fc9709a3	296	#define I2C2_CLK_SRC BUS_CLK
AnnaBridge	189:f392fc9709a3	297	#define I2C3_CLK_SRC BUS_CLK
AnnaBridge	189:f392fc9709a3	298	#define DSPI0_CLK_SRC BUS_CLK
AnnaBridge	189:f392fc9709a3	299	#define DSPI1_CLK_SRC BUS_CLK
AnnaBridge	189:f392fc9709a3	300	#define DSPI2_CLK_SRC BUS_CLK
AnnaBridge	189:f392fc9709a3	301
AnnaBridge	189:f392fc9709a3	302	/! @brief Clock name used to get clock frequency. /
AnnaBridge	189:f392fc9709a3	303	typedef enum _clock_name
AnnaBridge	189:f392fc9709a3	304	{
AnnaBridge	189:f392fc9709a3	305
AnnaBridge	189:f392fc9709a3	306	/* ----------------------------- System layer clock -------------------------------*/
AnnaBridge	189:f392fc9709a3	307	kCLOCK_CoreSysClk, /!< Core/system clock /
AnnaBridge	189:f392fc9709a3	308	kCLOCK_PlatClk, /!< Platform clock /
AnnaBridge	189:f392fc9709a3	309	kCLOCK_BusClk, /!< Bus clock /
AnnaBridge	189:f392fc9709a3	310	kCLOCK_FlexBusClk, /!< FlexBus clock /
AnnaBridge	189:f392fc9709a3	311	kCLOCK_FlashClk, /!< Flash clock /
AnnaBridge	189:f392fc9709a3	312	kCLOCK_FastPeriphClk, /!< Fast peripheral clock /
AnnaBridge	189:f392fc9709a3	313	kCLOCK_PllFllSelClk, /!< The clock after SIM[PLLFLLSEL]. /
AnnaBridge	189:f392fc9709a3	314
AnnaBridge	189:f392fc9709a3	315	/* ---------------------------------- OSC clock -----------------------------------*/
AnnaBridge	189:f392fc9709a3	316	kCLOCK_Er32kClk, /!< External reference 32K clock (ERCLK32K) /
AnnaBridge	189:f392fc9709a3	317	kCLOCK_Osc0ErClk, /!< OSC0 external reference clock (OSC0ERCLK) /
AnnaBridge	189:f392fc9709a3	318	kCLOCK_Osc1ErClk, /!< OSC1 external reference clock (OSC1ERCLK) /
AnnaBridge	189:f392fc9709a3	319	kCLOCK_Osc0ErClkUndiv, /!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). /
AnnaBridge	189:f392fc9709a3	320
AnnaBridge	189:f392fc9709a3	321	/* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
AnnaBridge	189:f392fc9709a3	322	kCLOCK_McgFixedFreqClk, /!< MCG fixed frequency clock (MCGFFCLK) /
AnnaBridge	189:f392fc9709a3	323	kCLOCK_McgInternalRefClk, /!< MCG internal reference clock (MCGIRCLK) /
AnnaBridge	189:f392fc9709a3	324	kCLOCK_McgFllClk, /!< MCGFLLCLK /
AnnaBridge	189:f392fc9709a3	325	kCLOCK_McgPll0Clk, /!< MCGPLL0CLK /
AnnaBridge	189:f392fc9709a3	326	kCLOCK_McgPll1Clk, /!< MCGPLL1CLK /
AnnaBridge	189:f392fc9709a3	327	kCLOCK_McgExtPllClk, /!< EXT_PLLCLK /
AnnaBridge	189:f392fc9709a3	328	kCLOCK_McgPeriphClk, /!< MCG peripheral clock (MCGPCLK) /
AnnaBridge	189:f392fc9709a3	329	kCLOCK_McgIrc48MClk, /!< MCG IRC48M clock /
AnnaBridge	189:f392fc9709a3	330
AnnaBridge	189:f392fc9709a3	331	/* --------------------------------- Other clock ----------------------------------*/
AnnaBridge	189:f392fc9709a3	332	kCLOCK_LpoClk, /!< LPO clock /
AnnaBridge	189:f392fc9709a3	333
AnnaBridge	189:f392fc9709a3	334	} clock_name_t;
AnnaBridge	189:f392fc9709a3	335
AnnaBridge	189:f392fc9709a3	336	/! @brief USB clock source definition. /
AnnaBridge	189:f392fc9709a3	337	typedef enum _clock_usb_src
AnnaBridge	189:f392fc9709a3	338	{
AnnaBridge	189:f392fc9709a3	339	kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(1U), /!< Use PLL0. /
AnnaBridge	189:f392fc9709a3	340	kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) \| SIM_SOPT2_PLLFLLSEL(3U), /!< Use IRC48M. /
AnnaBridge	189:f392fc9709a3	341	kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /!< Use USB_CLKIN. /
AnnaBridge	189:f392fc9709a3	342	} clock_usb_src_t;
AnnaBridge	189:f392fc9709a3	343	/*------------------------------------------------------------------------------
AnnaBridge	189:f392fc9709a3	344
AnnaBridge	189:f392fc9709a3	345	clock_gate_t definition:
AnnaBridge	189:f392fc9709a3	346
AnnaBridge	189:f392fc9709a3	347	31 16 0
AnnaBridge	189:f392fc9709a3	348	-----------------------------------------------------------------
AnnaBridge	189:f392fc9709a3	349	\| SIM_SCGC register offset \| control bit offset in SCGC \|
AnnaBridge	189:f392fc9709a3	350	-----------------------------------------------------------------
AnnaBridge	189:f392fc9709a3	351
AnnaBridge	189:f392fc9709a3	352	For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
AnnaBridge	189:f392fc9709a3	353	SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
AnnaBridge	189:f392fc9709a3	354
AnnaBridge	189:f392fc9709a3	355	kClockGateSdhc0 = (0x1030 << 16) \| 17;
AnnaBridge	189:f392fc9709a3	356
AnnaBridge	189:f392fc9709a3	357	------------------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	358
AnnaBridge	189:f392fc9709a3	359	#define CLK_GATE_REG_OFFSET_SHIFT 16U
AnnaBridge	189:f392fc9709a3	360	#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
AnnaBridge	189:f392fc9709a3	361	#define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge	189:f392fc9709a3	362	#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
AnnaBridge	189:f392fc9709a3	363
AnnaBridge	189:f392fc9709a3	364	#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge	189:f392fc9709a3	365	((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) \| \
AnnaBridge	189:f392fc9709a3	366	(((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge	189:f392fc9709a3	367
AnnaBridge	189:f392fc9709a3	368	#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge	189:f392fc9709a3	369	#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge	189:f392fc9709a3	370
AnnaBridge	189:f392fc9709a3	371	/! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. /
AnnaBridge	189:f392fc9709a3	372	typedef enum _clock_ip_name
AnnaBridge	189:f392fc9709a3	373	{
AnnaBridge	189:f392fc9709a3	374	kCLOCK_IpInvalid = 0U,
AnnaBridge	189:f392fc9709a3	375	kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
AnnaBridge	189:f392fc9709a3	376	kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U),
AnnaBridge	189:f392fc9709a3	377
AnnaBridge	189:f392fc9709a3	378	kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U),
AnnaBridge	189:f392fc9709a3	379	kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x102CU, 5U),
AnnaBridge	189:f392fc9709a3	380	kCLOCK_Lpuart2 = CLK_GATE_DEFINE(0x102CU, 6U),
AnnaBridge	189:f392fc9709a3	381	kCLOCK_Lpuart3 = CLK_GATE_DEFINE(0x102CU, 7U),
AnnaBridge	189:f392fc9709a3	382	kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U),
AnnaBridge	189:f392fc9709a3	383	kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U),
AnnaBridge	189:f392fc9709a3	384	kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
AnnaBridge	189:f392fc9709a3	385	kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x102CU, 17U),
AnnaBridge	189:f392fc9709a3	386	kCLOCK_Emvsim0 = CLK_GATE_DEFINE(0x102CU, 20U),
AnnaBridge	189:f392fc9709a3	387	kCLOCK_Emvsim1 = CLK_GATE_DEFINE(0x102CU, 21U),
AnnaBridge	189:f392fc9709a3	388	kCLOCK_Lpuart4 = CLK_GATE_DEFINE(0x102CU, 22U),
AnnaBridge	189:f392fc9709a3	389	kCLOCK_Qspi0 = CLK_GATE_DEFINE(0x102CU, 26U),
AnnaBridge	189:f392fc9709a3	390	kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x102CU, 31U),
AnnaBridge	189:f392fc9709a3	391
AnnaBridge	189:f392fc9709a3	392	kCLOCK_Trng0 = CLK_GATE_DEFINE(0x1030U, 0U),
AnnaBridge	189:f392fc9709a3	393	kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
AnnaBridge	189:f392fc9709a3	394	kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
AnnaBridge	189:f392fc9709a3	395	kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
AnnaBridge	189:f392fc9709a3	396
AnnaBridge	189:f392fc9709a3	397	kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
AnnaBridge	189:f392fc9709a3	398	kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
AnnaBridge	189:f392fc9709a3	399	kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
AnnaBridge	189:f392fc9709a3	400	kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
AnnaBridge	189:f392fc9709a3	401	kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
AnnaBridge	189:f392fc9709a3	402	kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge	189:f392fc9709a3	403	kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge	189:f392fc9709a3	404	kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
AnnaBridge	189:f392fc9709a3	405
AnnaBridge	189:f392fc9709a3	406	kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
AnnaBridge	189:f392fc9709a3	407	kCLOCK_Lptmr1 = CLK_GATE_DEFINE(0x1038U, 4U),
AnnaBridge	189:f392fc9709a3	408	kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
AnnaBridge	189:f392fc9709a3	409	kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
AnnaBridge	189:f392fc9709a3	410	kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
AnnaBridge	189:f392fc9709a3	411	kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
AnnaBridge	189:f392fc9709a3	412	kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
AnnaBridge	189:f392fc9709a3	413	kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
AnnaBridge	189:f392fc9709a3	414
AnnaBridge	189:f392fc9709a3	415	kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
AnnaBridge	189:f392fc9709a3	416	kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
AnnaBridge	189:f392fc9709a3	417	kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
AnnaBridge	189:f392fc9709a3	418	kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
AnnaBridge	189:f392fc9709a3	419	kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
AnnaBridge	189:f392fc9709a3	420	kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
AnnaBridge	189:f392fc9709a3	421	kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
AnnaBridge	189:f392fc9709a3	422	kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
AnnaBridge	189:f392fc9709a3	423	kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
AnnaBridge	189:f392fc9709a3	424	kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
AnnaBridge	189:f392fc9709a3	425	kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
AnnaBridge	189:f392fc9709a3	426	kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
AnnaBridge	189:f392fc9709a3	427	kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
AnnaBridge	189:f392fc9709a3	428	kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
AnnaBridge	189:f392fc9709a3	429
AnnaBridge	189:f392fc9709a3	430	kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
AnnaBridge	189:f392fc9709a3	431	kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
AnnaBridge	189:f392fc9709a3	432	kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
AnnaBridge	189:f392fc9709a3	433	kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
AnnaBridge	189:f392fc9709a3	434	} clock_ip_name_t;
AnnaBridge	189:f392fc9709a3	435
AnnaBridge	189:f392fc9709a3	436	/!@brief SIM configuration structure for clock setting. /
AnnaBridge	189:f392fc9709a3	437	typedef struct _sim_clock_config
AnnaBridge	189:f392fc9709a3	438	{
AnnaBridge	189:f392fc9709a3	439	uint8_t pllFllSel; /!< PLL/FLL/IRC48M selection. /
AnnaBridge	189:f392fc9709a3	440	uint8_t pllFllDiv; /!< PLLFLLSEL clock divider divisor. /
AnnaBridge	189:f392fc9709a3	441	uint8_t pllFllFrac; /!< PLLFLLSEL clock divider fraction. /
AnnaBridge	189:f392fc9709a3	442	uint8_t er32kSrc; /!< ERCLK32K source selection. /
AnnaBridge	189:f392fc9709a3	443	uint32_t clkdiv1; /!< SIM_CLKDIV1. /
AnnaBridge	189:f392fc9709a3	444	} sim_clock_config_t;
AnnaBridge	189:f392fc9709a3	445
AnnaBridge	189:f392fc9709a3	446	/! @brief OSC work mode. /
AnnaBridge	189:f392fc9709a3	447	typedef enum _osc_mode
AnnaBridge	189:f392fc9709a3	448	{
AnnaBridge	189:f392fc9709a3	449	kOSC_ModeExt = 0U, /!< Use an external clock. /
AnnaBridge	189:f392fc9709a3	450	#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge	189:f392fc9709a3	451	kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /!< Oscillator low power. /
AnnaBridge	189:f392fc9709a3	452	#else
AnnaBridge	189:f392fc9709a3	453	kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /!< Oscillator low power. /
AnnaBridge	189:f392fc9709a3	454	#endif
AnnaBridge	189:f392fc9709a3	455	kOSC_ModeOscHighGain = 0U
AnnaBridge	189:f392fc9709a3	456	#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge	189:f392fc9709a3	457	\|
AnnaBridge	189:f392fc9709a3	458	MCG_C2_EREFS_MASK
AnnaBridge	189:f392fc9709a3	459	#else
AnnaBridge	189:f392fc9709a3	460	\|
AnnaBridge	189:f392fc9709a3	461	MCG_C2_EREFS0_MASK
AnnaBridge	189:f392fc9709a3	462	#endif
AnnaBridge	189:f392fc9709a3	463	#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
AnnaBridge	189:f392fc9709a3	464	\|
AnnaBridge	189:f392fc9709a3	465	MCG_C2_HGO_MASK, /!< Oscillator high gain. /
AnnaBridge	189:f392fc9709a3	466	#else
AnnaBridge	189:f392fc9709a3	467	\|
AnnaBridge	189:f392fc9709a3	468	MCG_C2_HGO0_MASK, /!< Oscillator high gain. /
AnnaBridge	189:f392fc9709a3	469	#endif
AnnaBridge	189:f392fc9709a3	470	} osc_mode_t;
AnnaBridge	189:f392fc9709a3	471
AnnaBridge	189:f392fc9709a3	472	/! @brief Oscillator capacitor load setting./
AnnaBridge	189:f392fc9709a3	473	enum _osc_cap_load
AnnaBridge	189:f392fc9709a3	474	{
AnnaBridge	189:f392fc9709a3	475	kOSC_Cap2P = OSC_CR_SC2P_MASK, /!< 2 pF capacitor load /
AnnaBridge	189:f392fc9709a3	476	kOSC_Cap4P = OSC_CR_SC4P_MASK, /!< 4 pF capacitor load /
AnnaBridge	189:f392fc9709a3	477	kOSC_Cap8P = OSC_CR_SC8P_MASK, /!< 8 pF capacitor load /
AnnaBridge	189:f392fc9709a3	478	kOSC_Cap16P = OSC_CR_SC16P_MASK /!< 16 pF capacitor load /
AnnaBridge	189:f392fc9709a3	479	};
AnnaBridge	189:f392fc9709a3	480
AnnaBridge	189:f392fc9709a3	481	/! @brief OSCERCLK enable mode. /
AnnaBridge	189:f392fc9709a3	482	enum _oscer_enable_mode
AnnaBridge	189:f392fc9709a3	483	{
AnnaBridge	189:f392fc9709a3	484	kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /!< Enable. /
AnnaBridge	189:f392fc9709a3	485	kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /!< Enable in stop mode. /
AnnaBridge	189:f392fc9709a3	486	};
AnnaBridge	189:f392fc9709a3	487
AnnaBridge	189:f392fc9709a3	488	/! @brief OSC configuration for OSCERCLK. /
AnnaBridge	189:f392fc9709a3	489	typedef struct _oscer_config
AnnaBridge	189:f392fc9709a3	490	{
AnnaBridge	189:f392fc9709a3	491	uint8_t enableMode; /!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. /
AnnaBridge	189:f392fc9709a3	492
AnnaBridge	189:f392fc9709a3	493	uint8_t erclkDiv; /!< Divider for OSCERCLK./
AnnaBridge	189:f392fc9709a3	494	} oscer_config_t;
AnnaBridge	189:f392fc9709a3	495
AnnaBridge	189:f392fc9709a3	496	/*!
AnnaBridge	189:f392fc9709a3	497	* @brief OSC Initialization Configuration Structure
AnnaBridge	189:f392fc9709a3	498	*
AnnaBridge	189:f392fc9709a3	499	* Defines the configuration data structure to initialize the OSC.
AnnaBridge	189:f392fc9709a3	500	* When porting to a new board, set the following members
AnnaBridge	189:f392fc9709a3	501	* according to the board setting:
AnnaBridge	189:f392fc9709a3	502	* 1. freq: The external frequency.
AnnaBridge	189:f392fc9709a3	503	* 2. workMode: The OSC module mode.
AnnaBridge	189:f392fc9709a3	504	*/
AnnaBridge	189:f392fc9709a3	505	typedef struct _osc_config
AnnaBridge	189:f392fc9709a3	506	{
AnnaBridge	189:f392fc9709a3	507	uint32_t freq; /!< External clock frequency. /
AnnaBridge	189:f392fc9709a3	508	uint8_t capLoad; /!< Capacitor load setting. /
AnnaBridge	189:f392fc9709a3	509	osc_mode_t workMode; /!< OSC work mode setting. /
AnnaBridge	189:f392fc9709a3	510	oscer_config_t oscerConfig; /!< Configuration for OSCERCLK. /
AnnaBridge	189:f392fc9709a3	511	} osc_config_t;
AnnaBridge	189:f392fc9709a3	512
AnnaBridge	189:f392fc9709a3	513	/! @brief MCG FLL reference clock source select. /
AnnaBridge	189:f392fc9709a3	514	typedef enum _mcg_fll_src
AnnaBridge	189:f392fc9709a3	515	{
AnnaBridge	189:f392fc9709a3	516	kMCG_FllSrcExternal, /!< External reference clock is selected /
AnnaBridge	189:f392fc9709a3	517	kMCG_FllSrcInternal /!< The slow internal reference clock is selected /
AnnaBridge	189:f392fc9709a3	518	} mcg_fll_src_t;
AnnaBridge	189:f392fc9709a3	519
AnnaBridge	189:f392fc9709a3	520	/! @brief MCG internal reference clock select /
AnnaBridge	189:f392fc9709a3	521	typedef enum _mcg_irc_mode
AnnaBridge	189:f392fc9709a3	522	{
AnnaBridge	189:f392fc9709a3	523	kMCG_IrcSlow, /!< Slow internal reference clock selected /
AnnaBridge	189:f392fc9709a3	524	kMCG_IrcFast /!< Fast internal reference clock selected /
AnnaBridge	189:f392fc9709a3	525	} mcg_irc_mode_t;
AnnaBridge	189:f392fc9709a3	526
AnnaBridge	189:f392fc9709a3	527	/! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference /
AnnaBridge	189:f392fc9709a3	528	typedef enum _mcg_dmx32
AnnaBridge	189:f392fc9709a3	529	{
AnnaBridge	189:f392fc9709a3	530	kMCG_Dmx32Default, /!< DCO has a default range of 25% /
AnnaBridge	189:f392fc9709a3	531	kMCG_Dmx32Fine /!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference /
AnnaBridge	189:f392fc9709a3	532	} mcg_dmx32_t;
AnnaBridge	189:f392fc9709a3	533
AnnaBridge	189:f392fc9709a3	534	/! @brief MCG DCO range select /
AnnaBridge	189:f392fc9709a3	535	typedef enum _mcg_drs
AnnaBridge	189:f392fc9709a3	536	{
AnnaBridge	189:f392fc9709a3	537	kMCG_DrsLow, /!< Low frequency range /
AnnaBridge	189:f392fc9709a3	538	kMCG_DrsMid, /!< Mid frequency range /
AnnaBridge	189:f392fc9709a3	539	kMCG_DrsMidHigh, /!< Mid-High frequency range /
AnnaBridge	189:f392fc9709a3	540	kMCG_DrsHigh /!< High frequency range /
AnnaBridge	189:f392fc9709a3	541	} mcg_drs_t;
AnnaBridge	189:f392fc9709a3	542
AnnaBridge	189:f392fc9709a3	543	/! @brief MCG PLL reference clock select /
AnnaBridge	189:f392fc9709a3	544	typedef enum _mcg_pll_ref_src
AnnaBridge	189:f392fc9709a3	545	{
AnnaBridge	189:f392fc9709a3	546	kMCG_PllRefOsc0, /!< Selects OSC0 as PLL reference clock /
AnnaBridge	189:f392fc9709a3	547	kMCG_PllRefOsc1 /!< Selects OSC1 as PLL reference clock /
AnnaBridge	189:f392fc9709a3	548	} mcg_pll_ref_src_t;
AnnaBridge	189:f392fc9709a3	549
AnnaBridge	189:f392fc9709a3	550	/! @brief MCGOUT clock source. /
AnnaBridge	189:f392fc9709a3	551	typedef enum _mcg_clkout_src
AnnaBridge	189:f392fc9709a3	552	{
AnnaBridge	189:f392fc9709a3	553	kMCG_ClkOutSrcOut, /!< Output of the FLL is selected (reset default) /
AnnaBridge	189:f392fc9709a3	554	kMCG_ClkOutSrcInternal, /!< Internal reference clock is selected /
AnnaBridge	189:f392fc9709a3	555	kMCG_ClkOutSrcExternal, /!< External reference clock is selected /
AnnaBridge	189:f392fc9709a3	556	} mcg_clkout_src_t;
AnnaBridge	189:f392fc9709a3	557
AnnaBridge	189:f392fc9709a3	558	/! @brief MCG Automatic Trim Machine Select /
AnnaBridge	189:f392fc9709a3	559	typedef enum _mcg_atm_select
AnnaBridge	189:f392fc9709a3	560	{
AnnaBridge	189:f392fc9709a3	561	kMCG_AtmSel32k, /!< 32 kHz Internal Reference Clock selected /
AnnaBridge	189:f392fc9709a3	562	kMCG_AtmSel4m /!< 4 MHz Internal Reference Clock selected /
AnnaBridge	189:f392fc9709a3	563	} mcg_atm_select_t;
AnnaBridge	189:f392fc9709a3	564
AnnaBridge	189:f392fc9709a3	565	/! @brief MCG OSC Clock Select /
AnnaBridge	189:f392fc9709a3	566	typedef enum _mcg_oscsel
AnnaBridge	189:f392fc9709a3	567	{
AnnaBridge	189:f392fc9709a3	568	kMCG_OscselOsc, /!< Selects System Oscillator (OSCCLK) /
AnnaBridge	189:f392fc9709a3	569	kMCG_OscselRtc, /!< Selects 32 kHz RTC Oscillator /
AnnaBridge	189:f392fc9709a3	570	kMCG_OscselIrc /!< Selects 48 MHz IRC Oscillator /
AnnaBridge	189:f392fc9709a3	571	} mcg_oscsel_t;
AnnaBridge	189:f392fc9709a3	572
AnnaBridge	189:f392fc9709a3	573	/! @brief MCG PLLCS select /
AnnaBridge	189:f392fc9709a3	574	typedef enum _mcg_pll_clk_select
AnnaBridge	189:f392fc9709a3	575	{
AnnaBridge	189:f392fc9709a3	576	kMCG_PllClkSelPll0, /!< PLL0 output clock is selected /
AnnaBridge	189:f392fc9709a3	577	kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
AnnaBridge	189:f392fc9709a3	578	} mcg_pll_clk_select_t;
AnnaBridge	189:f392fc9709a3	579
AnnaBridge	189:f392fc9709a3	580	/! @brief MCG clock monitor mode. /
AnnaBridge	189:f392fc9709a3	581	typedef enum _mcg_monitor_mode
AnnaBridge	189:f392fc9709a3	582	{
AnnaBridge	189:f392fc9709a3	583	kMCG_MonitorNone, /!< Clock monitor is disabled. /
AnnaBridge	189:f392fc9709a3	584	kMCG_MonitorInt, /!< Trigger interrupt when clock lost. /
AnnaBridge	189:f392fc9709a3	585	kMCG_MonitorReset /!< System reset when clock lost. /
AnnaBridge	189:f392fc9709a3	586	} mcg_monitor_mode_t;
AnnaBridge	189:f392fc9709a3	587
AnnaBridge	189:f392fc9709a3	588	/! @brief MCG status. /
AnnaBridge	189:f392fc9709a3	589	enum _mcg_status
AnnaBridge	189:f392fc9709a3	590	{
AnnaBridge	189:f392fc9709a3	591	kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /!< Can't switch to target mode. /
AnnaBridge	189:f392fc9709a3	592	kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
AnnaBridge	189:f392fc9709a3	593	function. */
AnnaBridge	189:f392fc9709a3	594	kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /!< Invalid bus clock for ATM. /
AnnaBridge	189:f392fc9709a3	595	kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /!< Invalid desired frequency for ATM. /
AnnaBridge	189:f392fc9709a3	596	kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /!< IRC is used when using ATM. /
AnnaBridge	189:f392fc9709a3	597	kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /!< Hardware fail occurs during ATM. /
AnnaBridge	189:f392fc9709a3	598	kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
AnnaBridge	189:f392fc9709a3	599	it is in use. */
AnnaBridge	189:f392fc9709a3	600	};
AnnaBridge	189:f392fc9709a3	601
AnnaBridge	189:f392fc9709a3	602	/! @brief MCG status flags. /
AnnaBridge	189:f392fc9709a3	603	enum _mcg_status_flags_t
AnnaBridge	189:f392fc9709a3	604	{
AnnaBridge	189:f392fc9709a3	605	kMCG_Osc0LostFlag = (1U << 0U), /!< OSC0 lost. /
AnnaBridge	189:f392fc9709a3	606	kMCG_Osc0InitFlag = (1U << 1U), /!< OSC0 crystal initialized. /
AnnaBridge	189:f392fc9709a3	607	kMCG_RtcOscLostFlag = (1U << 4U), /!< RTC OSC lost. /
AnnaBridge	189:f392fc9709a3	608	kMCG_Pll0LostFlag = (1U << 5U), /!< PLL0 lost. /
AnnaBridge	189:f392fc9709a3	609	kMCG_Pll0LockFlag = (1U << 6U), /!< PLL0 locked. /
AnnaBridge	189:f392fc9709a3	610	};
AnnaBridge	189:f392fc9709a3	611
AnnaBridge	189:f392fc9709a3	612	/! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. /
AnnaBridge	189:f392fc9709a3	613	enum _mcg_irclk_enable_mode
AnnaBridge	189:f392fc9709a3	614	{
AnnaBridge	189:f392fc9709a3	615	kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /!< MCGIRCLK enable. /
AnnaBridge	189:f392fc9709a3	616	kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /!< MCGIRCLK enable in stop mode. /
AnnaBridge	189:f392fc9709a3	617	};
AnnaBridge	189:f392fc9709a3	618
AnnaBridge	189:f392fc9709a3	619	/! @brief MCG PLL clock enable mode definition. /
AnnaBridge	189:f392fc9709a3	620	enum _mcg_pll_enable_mode
AnnaBridge	189:f392fc9709a3	621	{
AnnaBridge	189:f392fc9709a3	622	kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
AnnaBridge	189:f392fc9709a3	623	MCG clock mode. Generally, the PLL
AnnaBridge	189:f392fc9709a3	624	is disabled in FLL modes
AnnaBridge	189:f392fc9709a3	625	(FEI/FBI/FEE/FBE). Setting the PLL clock
AnnaBridge	189:f392fc9709a3	626	enable independent, enables the
AnnaBridge	189:f392fc9709a3	627	PLL in the FLL modes. */
AnnaBridge	189:f392fc9709a3	628	kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /!< MCGPLLCLK enable in STOP mode. /
AnnaBridge	189:f392fc9709a3	629	};
AnnaBridge	189:f392fc9709a3	630
AnnaBridge	189:f392fc9709a3	631	/! @brief MCG mode definitions /
AnnaBridge	189:f392fc9709a3	632	typedef enum _mcg_mode
AnnaBridge	189:f392fc9709a3	633	{
AnnaBridge	189:f392fc9709a3	634	kMCG_ModeFEI = 0U, /!< FEI - FLL Engaged Internal /
AnnaBridge	189:f392fc9709a3	635	kMCG_ModeFBI, /!< FBI - FLL Bypassed Internal /
AnnaBridge	189:f392fc9709a3	636	kMCG_ModeBLPI, /!< BLPI - Bypassed Low Power Internal /
AnnaBridge	189:f392fc9709a3	637	kMCG_ModeFEE, /!< FEE - FLL Engaged External /
AnnaBridge	189:f392fc9709a3	638	kMCG_ModeFBE, /!< FBE - FLL Bypassed External /
AnnaBridge	189:f392fc9709a3	639	kMCG_ModeBLPE, /!< BLPE - Bypassed Low Power External /
AnnaBridge	189:f392fc9709a3	640	kMCG_ModePBE, /!< PBE - PLL Bypassed External /
AnnaBridge	189:f392fc9709a3	641	kMCG_ModePEE, /!< PEE - PLL Engaged External /
AnnaBridge	189:f392fc9709a3	642	kMCG_ModeError /!< Unknown mode /
AnnaBridge	189:f392fc9709a3	643	} mcg_mode_t;
AnnaBridge	189:f392fc9709a3	644
AnnaBridge	189:f392fc9709a3	645	/! @brief MCG PLL configuration. /
AnnaBridge	189:f392fc9709a3	646	typedef struct _mcg_pll_config
AnnaBridge	189:f392fc9709a3	647	{
AnnaBridge	189:f392fc9709a3	648	uint8_t enableMode; /!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. /
AnnaBridge	189:f392fc9709a3	649	uint8_t prdiv; /!< Reference divider PRDIV. /
AnnaBridge	189:f392fc9709a3	650	uint8_t vdiv; /!< VCO divider VDIV. /
AnnaBridge	189:f392fc9709a3	651	} mcg_pll_config_t;
AnnaBridge	189:f392fc9709a3	652
AnnaBridge	189:f392fc9709a3	653	/*! @brief MCG mode change configuration structure
AnnaBridge	189:f392fc9709a3	654	*
AnnaBridge	189:f392fc9709a3	655	* When porting to a new board, set the following members
AnnaBridge	189:f392fc9709a3	656	* according to the board setting:
AnnaBridge	189:f392fc9709a3	657	* 1. frdiv: If the FLL uses the external reference clock, set this
AnnaBridge	189:f392fc9709a3	658	* value to ensure that the external reference clock divided by frdiv is
AnnaBridge	189:f392fc9709a3	659	* in the 31.25 kHz to 39.0625 kHz range.
AnnaBridge	189:f392fc9709a3	660	* 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
AnnaBridge	189:f392fc9709a3	661	* PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
AnnaBridge	189:f392fc9709a3	662	* FSL_FEATURE_MCG_PLL_REF_MAX range.
AnnaBridge	189:f392fc9709a3	663	*/
AnnaBridge	189:f392fc9709a3	664	typedef struct _mcg_config
AnnaBridge	189:f392fc9709a3	665	{
AnnaBridge	189:f392fc9709a3	666	mcg_mode_t mcgMode; /!< MCG mode. /
AnnaBridge	189:f392fc9709a3	667
AnnaBridge	189:f392fc9709a3	668	/* ----------------------- MCGIRCCLK settings ------------------------ */
AnnaBridge	189:f392fc9709a3	669	uint8_t irclkEnableMode; /!< MCGIRCLK enable mode. /
AnnaBridge	189:f392fc9709a3	670	mcg_irc_mode_t ircs; /!< Source, MCG_C2[IRCS]. /
AnnaBridge	189:f392fc9709a3	671	uint8_t fcrdiv; /!< Divider, MCG_SC[FCRDIV]. /
AnnaBridge	189:f392fc9709a3	672
AnnaBridge	189:f392fc9709a3	673	/* ------------------------ MCG FLL settings ------------------------- */
AnnaBridge	189:f392fc9709a3	674	uint8_t frdiv; /!< Divider MCG_C1[FRDIV]. /
AnnaBridge	189:f392fc9709a3	675	mcg_drs_t drs; /!< DCO range MCG_C4[DRST_DRS]. /
AnnaBridge	189:f392fc9709a3	676	mcg_dmx32_t dmx32; /!< MCG_C4[DMX32]. /
AnnaBridge	189:f392fc9709a3	677	mcg_oscsel_t oscsel; /!< OSC select MCG_C7[OSCSEL]. /
AnnaBridge	189:f392fc9709a3	678
AnnaBridge	189:f392fc9709a3	679	/* ------------------------ MCG PLL settings ------------------------- */
AnnaBridge	189:f392fc9709a3	680	mcg_pll_config_t pll0Config; /!< MCGPLL0CLK configuration. /
AnnaBridge	189:f392fc9709a3	681
AnnaBridge	189:f392fc9709a3	682	} mcg_config_t;
AnnaBridge	189:f392fc9709a3	683
AnnaBridge	189:f392fc9709a3	684	/*******************************************************************************
AnnaBridge	189:f392fc9709a3	685	* API
AnnaBridge	189:f392fc9709a3	686	******************************************************************************/
AnnaBridge	189:f392fc9709a3	687
AnnaBridge	189:f392fc9709a3	688	#if defined(__cplusplus)
AnnaBridge	189:f392fc9709a3	689	extern "C" {
AnnaBridge	189:f392fc9709a3	690	#endif /* __cplusplus */
AnnaBridge	189:f392fc9709a3	691
AnnaBridge	189:f392fc9709a3	692	/*!
AnnaBridge	189:f392fc9709a3	693	* @brief Enable the clock for specific IP.
AnnaBridge	189:f392fc9709a3	694	*
AnnaBridge	189:f392fc9709a3	695	* @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge	189:f392fc9709a3	696	*/
AnnaBridge	189:f392fc9709a3	697	static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge	189:f392fc9709a3	698	{
AnnaBridge	189:f392fc9709a3	699	uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge	189:f392fc9709a3	700	((volatile uint32_t )regAddr) \|= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge	189:f392fc9709a3	701	}
AnnaBridge	189:f392fc9709a3	702
AnnaBridge	189:f392fc9709a3	703	/*!
AnnaBridge	189:f392fc9709a3	704	* @brief Disable the clock for specific IP.
AnnaBridge	189:f392fc9709a3	705	*
AnnaBridge	189:f392fc9709a3	706	* @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge	189:f392fc9709a3	707	*/
AnnaBridge	189:f392fc9709a3	708	static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge	189:f392fc9709a3	709	{
AnnaBridge	189:f392fc9709a3	710	uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge	189:f392fc9709a3	711	((volatile uint32_t )regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge	189:f392fc9709a3	712	}
AnnaBridge	189:f392fc9709a3	713
AnnaBridge	189:f392fc9709a3	714	/*!
AnnaBridge	189:f392fc9709a3	715	* @brief Set ERCLK32K source.
AnnaBridge	189:f392fc9709a3	716	*
AnnaBridge	189:f392fc9709a3	717	* @param src The value to set ERCLK32K clock source.
AnnaBridge	189:f392fc9709a3	718	*/
AnnaBridge	189:f392fc9709a3	719	static inline void CLOCK_SetEr32kClock(uint32_t src)
AnnaBridge	189:f392fc9709a3	720	{
AnnaBridge	189:f392fc9709a3	721	SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) \| SIM_SOPT1_OSC32KSEL(src));
AnnaBridge	189:f392fc9709a3	722	}
AnnaBridge	189:f392fc9709a3	723
AnnaBridge	189:f392fc9709a3	724	/*!
AnnaBridge	189:f392fc9709a3	725	* @brief Set SDHC0 clock source.
AnnaBridge	189:f392fc9709a3	726	*
AnnaBridge	189:f392fc9709a3	727	* @param src The value to set SDHC0 clock source.
AnnaBridge	189:f392fc9709a3	728	*/
AnnaBridge	189:f392fc9709a3	729	static inline void CLOCK_SetSdhc0Clock(uint32_t src)
AnnaBridge	189:f392fc9709a3	730	{
AnnaBridge	189:f392fc9709a3	731	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) \| SIM_SOPT2_SDHCSRC(src));
AnnaBridge	189:f392fc9709a3	732	}
AnnaBridge	189:f392fc9709a3	733
AnnaBridge	189:f392fc9709a3	734	/*!
AnnaBridge	189:f392fc9709a3	735	* @brief Set EMVSIM clock source.
AnnaBridge	189:f392fc9709a3	736	*
AnnaBridge	189:f392fc9709a3	737	* @param src The value to set EMVSIM clock source.
AnnaBridge	189:f392fc9709a3	738	*/
AnnaBridge	189:f392fc9709a3	739	static inline void CLOCK_SetEmvsimClock(uint32_t src)
AnnaBridge	189:f392fc9709a3	740	{
AnnaBridge	189:f392fc9709a3	741	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_EMVSIMSRC_MASK) \| SIM_SOPT2_EMVSIMSRC(src));
AnnaBridge	189:f392fc9709a3	742	}
AnnaBridge	189:f392fc9709a3	743
AnnaBridge	189:f392fc9709a3	744	/*!
AnnaBridge	189:f392fc9709a3	745	* @brief Set LPUART clock source.
AnnaBridge	189:f392fc9709a3	746	*
AnnaBridge	189:f392fc9709a3	747	* @param src The value to set LPUART clock source.
AnnaBridge	189:f392fc9709a3	748	*/
AnnaBridge	189:f392fc9709a3	749	static inline void CLOCK_SetLpuartClock(uint32_t src)
AnnaBridge	189:f392fc9709a3	750	{
AnnaBridge	189:f392fc9709a3	751	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) \| SIM_SOPT2_LPUARTSRC(src));
AnnaBridge	189:f392fc9709a3	752	}
AnnaBridge	189:f392fc9709a3	753
AnnaBridge	189:f392fc9709a3	754	/*!
AnnaBridge	189:f392fc9709a3	755	* @brief Set TPM clock source.
AnnaBridge	189:f392fc9709a3	756	*
AnnaBridge	189:f392fc9709a3	757	* @param src The value to set TPM clock source.
AnnaBridge	189:f392fc9709a3	758	*/
AnnaBridge	189:f392fc9709a3	759	static inline void CLOCK_SetTpmClock(uint32_t src)
AnnaBridge	189:f392fc9709a3	760	{
AnnaBridge	189:f392fc9709a3	761	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) \| SIM_SOPT2_TPMSRC(src));
AnnaBridge	189:f392fc9709a3	762	}
AnnaBridge	189:f392fc9709a3	763
AnnaBridge	189:f392fc9709a3	764	/*!
AnnaBridge	189:f392fc9709a3	765	* @brief Set FLEXIO clock source.
AnnaBridge	189:f392fc9709a3	766	*
AnnaBridge	189:f392fc9709a3	767	* @param src The value to set FLEXIO clock source.
AnnaBridge	189:f392fc9709a3	768	*/
AnnaBridge	189:f392fc9709a3	769	static inline void CLOCK_SetFlexio0Clock(uint32_t src)
AnnaBridge	189:f392fc9709a3	770	{
AnnaBridge	189:f392fc9709a3	771	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) \| SIM_SOPT2_FLEXIOSRC(src));
AnnaBridge	189:f392fc9709a3	772	}
AnnaBridge	189:f392fc9709a3	773
AnnaBridge	189:f392fc9709a3	774	/*!
AnnaBridge	189:f392fc9709a3	775	* @brief Set debug trace clock source.
AnnaBridge	189:f392fc9709a3	776	*
AnnaBridge	189:f392fc9709a3	777	* @param src The value to set debug trace clock source.
AnnaBridge	189:f392fc9709a3	778	*/
AnnaBridge	189:f392fc9709a3	779	static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
AnnaBridge	189:f392fc9709a3	780	{
AnnaBridge	189:f392fc9709a3	781	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) \| SIM_SOPT2_TRACECLKSEL(src));
AnnaBridge	189:f392fc9709a3	782	SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) \| SIM_CLKDIV4_TRACEFRAC(fracValue);
AnnaBridge	189:f392fc9709a3	783	}
AnnaBridge	189:f392fc9709a3	784
AnnaBridge	189:f392fc9709a3	785	/*!
AnnaBridge	189:f392fc9709a3	786	* @brief Set PLLFLLSEL clock source.
AnnaBridge	189:f392fc9709a3	787	*
AnnaBridge	189:f392fc9709a3	788	* @param src The value to set PLLFLLSEL clock source.
AnnaBridge	189:f392fc9709a3	789	*/
AnnaBridge	189:f392fc9709a3	790	static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
AnnaBridge	189:f392fc9709a3	791	{
AnnaBridge	189:f392fc9709a3	792	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) \| SIM_SOPT2_PLLFLLSEL(src));
AnnaBridge	189:f392fc9709a3	793	SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) \| SIM_CLKDIV3_PLLFLLFRAC(fracValue);
AnnaBridge	189:f392fc9709a3	794	}
AnnaBridge	189:f392fc9709a3	795
AnnaBridge	189:f392fc9709a3	796	/*!
AnnaBridge	189:f392fc9709a3	797	* @brief Set CLKOUT source.
AnnaBridge	189:f392fc9709a3	798	*
AnnaBridge	189:f392fc9709a3	799	* @param src The value to set CLKOUT source.
AnnaBridge	189:f392fc9709a3	800	*/
AnnaBridge	189:f392fc9709a3	801	static inline void CLOCK_SetClkOutClock(uint32_t src)
AnnaBridge	189:f392fc9709a3	802	{
AnnaBridge	189:f392fc9709a3	803	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) \| SIM_SOPT2_CLKOUTSEL(src));
AnnaBridge	189:f392fc9709a3	804	}
AnnaBridge	189:f392fc9709a3	805
AnnaBridge	189:f392fc9709a3	806	/*!
AnnaBridge	189:f392fc9709a3	807	* @brief Set RTC_CLKOUT source.
AnnaBridge	189:f392fc9709a3	808	*
AnnaBridge	189:f392fc9709a3	809	* @param src The value to set RTC_CLKOUT source.
AnnaBridge	189:f392fc9709a3	810	*/
AnnaBridge	189:f392fc9709a3	811	static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
AnnaBridge	189:f392fc9709a3	812	{
AnnaBridge	189:f392fc9709a3	813	SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) \| SIM_SOPT2_RTCCLKOUTSEL(src));
AnnaBridge	189:f392fc9709a3	814	}
AnnaBridge	189:f392fc9709a3	815
AnnaBridge	189:f392fc9709a3	816	/*! @brief Enable USB FS clock.
AnnaBridge	189:f392fc9709a3	817	*
AnnaBridge	189:f392fc9709a3	818	* @param src USB FS clock source.
AnnaBridge	189:f392fc9709a3	819	* @param freq The frequency specified by src.
AnnaBridge	189:f392fc9709a3	820	* @retval true The clock is set successfully.
AnnaBridge	189:f392fc9709a3	821	* @retval false The clock source is invalid to get proper USB FS clock.
AnnaBridge	189:f392fc9709a3	822	*/
AnnaBridge	189:f392fc9709a3	823	bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
AnnaBridge	189:f392fc9709a3	824
AnnaBridge	189:f392fc9709a3	825	/*! @brief Disable USB FS clock.
AnnaBridge	189:f392fc9709a3	826	*
AnnaBridge	189:f392fc9709a3	827	* Disable USB FS clock.
AnnaBridge	189:f392fc9709a3	828	*/
AnnaBridge	189:f392fc9709a3	829	static inline void CLOCK_DisableUsbfs0Clock(void)
AnnaBridge	189:f392fc9709a3	830	{
AnnaBridge	189:f392fc9709a3	831	CLOCK_DisableClock(kCLOCK_Usbfs0);
AnnaBridge	189:f392fc9709a3	832	}
AnnaBridge	189:f392fc9709a3	833
AnnaBridge	189:f392fc9709a3	834	/*!
AnnaBridge	189:f392fc9709a3	835	* @brief System clock divider
AnnaBridge	189:f392fc9709a3	836	*
AnnaBridge	189:f392fc9709a3	837	* Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
AnnaBridge	189:f392fc9709a3	838	*
AnnaBridge	189:f392fc9709a3	839	* @param outdiv1 Clock 1 output divider value.
AnnaBridge	189:f392fc9709a3	840	*
AnnaBridge	189:f392fc9709a3	841	* @param outdiv2 Clock 2 output divider value.
AnnaBridge	189:f392fc9709a3	842	*
AnnaBridge	189:f392fc9709a3	843	* @param outdiv3 Clock 3 output divider value.
AnnaBridge	189:f392fc9709a3	844	*
AnnaBridge	189:f392fc9709a3	845	* @param outdiv4 Clock 4 output divider value.
AnnaBridge	189:f392fc9709a3	846	*/
AnnaBridge	189:f392fc9709a3	847	static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
AnnaBridge	189:f392fc9709a3	848	{
AnnaBridge	189:f392fc9709a3	849	SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) \| SIM_CLKDIV1_OUTDIV2(outdiv2) \| SIM_CLKDIV1_OUTDIV3(outdiv3) \|
AnnaBridge	189:f392fc9709a3	850	SIM_CLKDIV1_OUTDIV4(outdiv4);
AnnaBridge	189:f392fc9709a3	851	}
AnnaBridge	189:f392fc9709a3	852
AnnaBridge	189:f392fc9709a3	853	/*!
AnnaBridge	189:f392fc9709a3	854	* @brief Gets the clock frequency for a specific clock name.
AnnaBridge	189:f392fc9709a3	855	*
AnnaBridge	189:f392fc9709a3	856	* This function checks the current clock configurations and then calculates
AnnaBridge	189:f392fc9709a3	857	* the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge	189:f392fc9709a3	858	* The MCG must be properly configured before using this function.
AnnaBridge	189:f392fc9709a3	859	*
AnnaBridge	189:f392fc9709a3	860	* @param clockName Clock names defined in clock_name_t
AnnaBridge	189:f392fc9709a3	861	* @return Clock frequency value in Hertz
AnnaBridge	189:f392fc9709a3	862	*/
AnnaBridge	189:f392fc9709a3	863	uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge	189:f392fc9709a3	864
AnnaBridge	189:f392fc9709a3	865	/*!
AnnaBridge	189:f392fc9709a3	866	* @brief Get the core clock or system clock frequency.
AnnaBridge	189:f392fc9709a3	867	*
AnnaBridge	189:f392fc9709a3	868	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	869	*/
AnnaBridge	189:f392fc9709a3	870	uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge	189:f392fc9709a3	871
AnnaBridge	189:f392fc9709a3	872	/*!
AnnaBridge	189:f392fc9709a3	873	* @brief Get the platform clock frequency.
AnnaBridge	189:f392fc9709a3	874	*
AnnaBridge	189:f392fc9709a3	875	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	876	*/
AnnaBridge	189:f392fc9709a3	877	uint32_t CLOCK_GetPlatClkFreq(void);
AnnaBridge	189:f392fc9709a3	878
AnnaBridge	189:f392fc9709a3	879	/*!
AnnaBridge	189:f392fc9709a3	880	* @brief Get the bus clock frequency.
AnnaBridge	189:f392fc9709a3	881	*
AnnaBridge	189:f392fc9709a3	882	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	883	*/
AnnaBridge	189:f392fc9709a3	884	uint32_t CLOCK_GetBusClkFreq(void);
AnnaBridge	189:f392fc9709a3	885
AnnaBridge	189:f392fc9709a3	886	/*!
AnnaBridge	189:f392fc9709a3	887	* @brief Get the flexbus clock frequency.
AnnaBridge	189:f392fc9709a3	888	*
AnnaBridge	189:f392fc9709a3	889	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	890	*/
AnnaBridge	189:f392fc9709a3	891	uint32_t CLOCK_GetFlexBusClkFreq(void);
AnnaBridge	189:f392fc9709a3	892
AnnaBridge	189:f392fc9709a3	893	/*!
AnnaBridge	189:f392fc9709a3	894	* @brief Get the flash clock frequency.
AnnaBridge	189:f392fc9709a3	895	*
AnnaBridge	189:f392fc9709a3	896	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	897	*/
AnnaBridge	189:f392fc9709a3	898	uint32_t CLOCK_GetFlashClkFreq(void);
AnnaBridge	189:f392fc9709a3	899
AnnaBridge	189:f392fc9709a3	900	/*!
AnnaBridge	189:f392fc9709a3	901	* @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
AnnaBridge	189:f392fc9709a3	902	*
AnnaBridge	189:f392fc9709a3	903	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	904	*/
AnnaBridge	189:f392fc9709a3	905	uint32_t CLOCK_GetPllFllSelClkFreq(void);
AnnaBridge	189:f392fc9709a3	906
AnnaBridge	189:f392fc9709a3	907	/*!
AnnaBridge	189:f392fc9709a3	908	* @brief Get the external reference 32K clock frequency (ERCLK32K).
AnnaBridge	189:f392fc9709a3	909	*
AnnaBridge	189:f392fc9709a3	910	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	911	*/
AnnaBridge	189:f392fc9709a3	912	uint32_t CLOCK_GetEr32kClkFreq(void);
AnnaBridge	189:f392fc9709a3	913
AnnaBridge	189:f392fc9709a3	914	/*!
AnnaBridge	189:f392fc9709a3	915	* @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
AnnaBridge	189:f392fc9709a3	916	*
AnnaBridge	189:f392fc9709a3	917	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	918	*/
AnnaBridge	189:f392fc9709a3	919	uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
AnnaBridge	189:f392fc9709a3	920
AnnaBridge	189:f392fc9709a3	921	/*!
AnnaBridge	189:f392fc9709a3	922	* @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
AnnaBridge	189:f392fc9709a3	923	*
AnnaBridge	189:f392fc9709a3	924	* @return Clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	925	*/
AnnaBridge	189:f392fc9709a3	926	uint32_t CLOCK_GetOsc0ErClkFreq(void);
AnnaBridge	189:f392fc9709a3	927
AnnaBridge	189:f392fc9709a3	928	/*!
AnnaBridge	189:f392fc9709a3	929	* @brief Set the clock configure in SIM module.
AnnaBridge	189:f392fc9709a3	930	*
AnnaBridge	189:f392fc9709a3	931	* This function sets system layer clock settings in SIM module.
AnnaBridge	189:f392fc9709a3	932	*
AnnaBridge	189:f392fc9709a3	933	* @param config Pointer to the configure structure.
AnnaBridge	189:f392fc9709a3	934	*/
AnnaBridge	189:f392fc9709a3	935	void CLOCK_SetSimConfig(sim_clock_config_t const *config);
AnnaBridge	189:f392fc9709a3	936
AnnaBridge	189:f392fc9709a3	937	/*!
AnnaBridge	189:f392fc9709a3	938	* @brief Set the system clock dividers in SIM to safe value.
AnnaBridge	189:f392fc9709a3	939	*
AnnaBridge	189:f392fc9709a3	940	* The system level clocks (core clock, bus clock, flexbus clock and flash clock)
AnnaBridge	189:f392fc9709a3	941	* must be in allowed ranges. During MCG clock mode switch, the MCG output clock
AnnaBridge	189:f392fc9709a3	942	* changes then the system level clocks may be out of range. This function could
AnnaBridge	189:f392fc9709a3	943	* be used before MCG mode change, to make sure system level clocks are in allowed
AnnaBridge	189:f392fc9709a3	944	* range.
AnnaBridge	189:f392fc9709a3	945	*
AnnaBridge	189:f392fc9709a3	946	* @param config Pointer to the configure structure.
AnnaBridge	189:f392fc9709a3	947	*/
AnnaBridge	189:f392fc9709a3	948	static inline void CLOCK_SetSimSafeDivs(void)
AnnaBridge	189:f392fc9709a3	949	{
AnnaBridge	189:f392fc9709a3	950	SIM->CLKDIV1 = 0x01140000U;
AnnaBridge	189:f392fc9709a3	951	}
AnnaBridge	189:f392fc9709a3	952
AnnaBridge	189:f392fc9709a3	953	/! @name MCG frequency functions. /
AnnaBridge	189:f392fc9709a3	954	/@{/
AnnaBridge	189:f392fc9709a3	955
AnnaBridge	189:f392fc9709a3	956	/*!
AnnaBridge	189:f392fc9709a3	957	* @brief Gets the MCG output clock (MCGOUTCLK) frequency.
AnnaBridge	189:f392fc9709a3	958	*
AnnaBridge	189:f392fc9709a3	959	* This function gets the MCG output clock frequency in Hz based on the current MCG
AnnaBridge	189:f392fc9709a3	960	* register value.
AnnaBridge	189:f392fc9709a3	961	*
AnnaBridge	189:f392fc9709a3	962	* @return The frequency of MCGOUTCLK.
AnnaBridge	189:f392fc9709a3	963	*/
AnnaBridge	189:f392fc9709a3	964	uint32_t CLOCK_GetOutClkFreq(void);
AnnaBridge	189:f392fc9709a3	965
AnnaBridge	189:f392fc9709a3	966	/*!
AnnaBridge	189:f392fc9709a3	967	* @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
AnnaBridge	189:f392fc9709a3	968	*
AnnaBridge	189:f392fc9709a3	969	* This function gets the MCG FLL clock frequency in Hz based on the current MCG
AnnaBridge	189:f392fc9709a3	970	* register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
AnnaBridge	189:f392fc9709a3	971	* disabled in low power state in other modes.
AnnaBridge	189:f392fc9709a3	972	*
AnnaBridge	189:f392fc9709a3	973	* @return The frequency of MCGFLLCLK.
AnnaBridge	189:f392fc9709a3	974	*/
AnnaBridge	189:f392fc9709a3	975	uint32_t CLOCK_GetFllFreq(void);
AnnaBridge	189:f392fc9709a3	976
AnnaBridge	189:f392fc9709a3	977	/*!
AnnaBridge	189:f392fc9709a3	978	* @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
AnnaBridge	189:f392fc9709a3	979	*
AnnaBridge	189:f392fc9709a3	980	* This function gets the MCG internal reference clock frequency in Hz based
AnnaBridge	189:f392fc9709a3	981	* on the current MCG register value.
AnnaBridge	189:f392fc9709a3	982	*
AnnaBridge	189:f392fc9709a3	983	* @return The frequency of MCGIRCLK.
AnnaBridge	189:f392fc9709a3	984	*/
AnnaBridge	189:f392fc9709a3	985	uint32_t CLOCK_GetInternalRefClkFreq(void);
AnnaBridge	189:f392fc9709a3	986
AnnaBridge	189:f392fc9709a3	987	/*!
AnnaBridge	189:f392fc9709a3	988	* @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
AnnaBridge	189:f392fc9709a3	989	*
AnnaBridge	189:f392fc9709a3	990	* This function gets the MCG fixed frequency clock frequency in Hz based
AnnaBridge	189:f392fc9709a3	991	* on the current MCG register value.
AnnaBridge	189:f392fc9709a3	992	*
AnnaBridge	189:f392fc9709a3	993	* @return The frequency of MCGFFCLK.
AnnaBridge	189:f392fc9709a3	994	*/
AnnaBridge	189:f392fc9709a3	995	uint32_t CLOCK_GetFixedFreqClkFreq(void);
AnnaBridge	189:f392fc9709a3	996
AnnaBridge	189:f392fc9709a3	997	/*!
AnnaBridge	189:f392fc9709a3	998	* @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
AnnaBridge	189:f392fc9709a3	999	*
AnnaBridge	189:f392fc9709a3	1000	* This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
AnnaBridge	189:f392fc9709a3	1001	* register value.
AnnaBridge	189:f392fc9709a3	1002	*
AnnaBridge	189:f392fc9709a3	1003	* @return The frequency of MCGPLL0CLK.
AnnaBridge	189:f392fc9709a3	1004	*/
AnnaBridge	189:f392fc9709a3	1005	uint32_t CLOCK_GetPll0Freq(void);
AnnaBridge	189:f392fc9709a3	1006
AnnaBridge	189:f392fc9709a3	1007	/@}/
AnnaBridge	189:f392fc9709a3	1008
AnnaBridge	189:f392fc9709a3	1009	/! @name MCG clock configuration. /
AnnaBridge	189:f392fc9709a3	1010	/@{/
AnnaBridge	189:f392fc9709a3	1011
AnnaBridge	189:f392fc9709a3	1012	/*!
AnnaBridge	189:f392fc9709a3	1013	* @brief Enables or disables the MCG low power.
AnnaBridge	189:f392fc9709a3	1014	*
AnnaBridge	189:f392fc9709a3	1015	* Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
AnnaBridge	189:f392fc9709a3	1016	* in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
AnnaBridge	189:f392fc9709a3	1017	* PBI modes, enabling low power sets the MCG to BLPI mode.
AnnaBridge	189:f392fc9709a3	1018	* When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
AnnaBridge	189:f392fc9709a3	1019	*
AnnaBridge	189:f392fc9709a3	1020	* @param enable True to enable MCG low power, false to disable MCG low power.
AnnaBridge	189:f392fc9709a3	1021	*/
AnnaBridge	189:f392fc9709a3	1022	static inline void CLOCK_SetLowPowerEnable(bool enable)
AnnaBridge	189:f392fc9709a3	1023	{
AnnaBridge	189:f392fc9709a3	1024	if (enable)
AnnaBridge	189:f392fc9709a3	1025	{
AnnaBridge	189:f392fc9709a3	1026	MCG->C2 \|= MCG_C2_LP_MASK;
AnnaBridge	189:f392fc9709a3	1027	}
AnnaBridge	189:f392fc9709a3	1028	else
AnnaBridge	189:f392fc9709a3	1029	{
AnnaBridge	189:f392fc9709a3	1030	MCG->C2 &= ~MCG_C2_LP_MASK;
AnnaBridge	189:f392fc9709a3	1031	}
AnnaBridge	189:f392fc9709a3	1032	}
AnnaBridge	189:f392fc9709a3	1033
AnnaBridge	189:f392fc9709a3	1034	/*!
AnnaBridge	189:f392fc9709a3	1035	* @brief Configures the Internal Reference clock (MCGIRCLK).
AnnaBridge	189:f392fc9709a3	1036	*
AnnaBridge	189:f392fc9709a3	1037	* This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
AnnaBridge	189:f392fc9709a3	1038	* source. If the fast IRC is used, this function sets the fast IRC divider.
AnnaBridge	189:f392fc9709a3	1039	* This function also sets whether the \c MCGIRCLK is enabled in stop mode.
AnnaBridge	189:f392fc9709a3	1040	* Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
AnnaBridge	189:f392fc9709a3	1041	* using the function in these modes it is not allowed.
AnnaBridge	189:f392fc9709a3	1042	*
AnnaBridge	189:f392fc9709a3	1043	* @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge	189:f392fc9709a3	1044	* @param ircs MCGIRCLK clock source, choose fast or slow.
AnnaBridge	189:f392fc9709a3	1045	* @param fcrdiv Fast IRC divider setting (\c FCRDIV).
AnnaBridge	189:f392fc9709a3	1046	* @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
AnnaBridge	189:f392fc9709a3	1047	* the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge	189:f392fc9709a3	1048	* @retval kStatus_Success MCGIRCLK configuration finished successfully.
AnnaBridge	189:f392fc9709a3	1049	*/
AnnaBridge	189:f392fc9709a3	1050	status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
AnnaBridge	189:f392fc9709a3	1051
AnnaBridge	189:f392fc9709a3	1052	/*!
AnnaBridge	189:f392fc9709a3	1053	* @brief Selects the MCG external reference clock.
AnnaBridge	189:f392fc9709a3	1054	*
AnnaBridge	189:f392fc9709a3	1055	* Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
AnnaBridge	189:f392fc9709a3	1056	* and waits for the clock source to be stable. Because the external reference
AnnaBridge	189:f392fc9709a3	1057	* clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
AnnaBridge	189:f392fc9709a3	1058	*
AnnaBridge	189:f392fc9709a3	1059	* @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
AnnaBridge	189:f392fc9709a3	1060	* @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
AnnaBridge	189:f392fc9709a3	1061	* the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge	189:f392fc9709a3	1062	* @retval kStatus_Success External reference clock set successfully.
AnnaBridge	189:f392fc9709a3	1063	*/
AnnaBridge	189:f392fc9709a3	1064	status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
AnnaBridge	189:f392fc9709a3	1065
AnnaBridge	189:f392fc9709a3	1066	/*!
AnnaBridge	189:f392fc9709a3	1067	* @brief Set the FLL external reference clock divider value.
AnnaBridge	189:f392fc9709a3	1068	*
AnnaBridge	189:f392fc9709a3	1069	* Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
AnnaBridge	189:f392fc9709a3	1070	*
AnnaBridge	189:f392fc9709a3	1071	* @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
AnnaBridge	189:f392fc9709a3	1072	*/
AnnaBridge	189:f392fc9709a3	1073	static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
AnnaBridge	189:f392fc9709a3	1074	{
AnnaBridge	189:f392fc9709a3	1075	MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) \| MCG_C1_FRDIV(frdiv);
AnnaBridge	189:f392fc9709a3	1076	}
AnnaBridge	189:f392fc9709a3	1077
AnnaBridge	189:f392fc9709a3	1078	/*!
AnnaBridge	189:f392fc9709a3	1079	* @brief Enables the PLL0 in FLL mode.
AnnaBridge	189:f392fc9709a3	1080	*
AnnaBridge	189:f392fc9709a3	1081	* This function sets us the PLL0 in FLL mode and reconfigures
AnnaBridge	189:f392fc9709a3	1082	* the PLL0. Ensure that the PLL reference
AnnaBridge	189:f392fc9709a3	1083	* clock is enabled before calling this function and that the PLL0 is not used as a clock source.
AnnaBridge	189:f392fc9709a3	1084	* The function CLOCK_CalcPllDiv gets the correct PLL
AnnaBridge	189:f392fc9709a3	1085	* divider values.
AnnaBridge	189:f392fc9709a3	1086	*
AnnaBridge	189:f392fc9709a3	1087	* @param config Pointer to the configuration structure.
AnnaBridge	189:f392fc9709a3	1088	*/
AnnaBridge	189:f392fc9709a3	1089	void CLOCK_EnablePll0(mcg_pll_config_t const *config);
AnnaBridge	189:f392fc9709a3	1090
AnnaBridge	189:f392fc9709a3	1091	/*!
AnnaBridge	189:f392fc9709a3	1092	* @brief Disables the PLL0 in FLL mode.
AnnaBridge	189:f392fc9709a3	1093	*
AnnaBridge	189:f392fc9709a3	1094	* This function disables the PLL0 in FLL mode. It should be used together with the
AnnaBridge	189:f392fc9709a3	1095	* @ref CLOCK_EnablePll0.
AnnaBridge	189:f392fc9709a3	1096	*/
AnnaBridge	189:f392fc9709a3	1097	static inline void CLOCK_DisablePll0(void)
AnnaBridge	189:f392fc9709a3	1098	{
AnnaBridge	189:f392fc9709a3	1099	MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK \| MCG_C5_PLLSTEN0_MASK);
AnnaBridge	189:f392fc9709a3	1100	}
AnnaBridge	189:f392fc9709a3	1101
AnnaBridge	189:f392fc9709a3	1102	/*!
AnnaBridge	189:f392fc9709a3	1103	* @brief Calculates the PLL divider setting for a desired output frequency.
AnnaBridge	189:f392fc9709a3	1104	*
AnnaBridge	189:f392fc9709a3	1105	* This function calculates the correct reference clock divider (\c PRDIV) and
AnnaBridge	189:f392fc9709a3	1106	* VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
AnnaBridge	189:f392fc9709a3	1107	* closest frequency match with the corresponding \c PRDIV/VDIV
AnnaBridge	189:f392fc9709a3	1108	* returned from parameters. If a desired frequency is not valid, this function
AnnaBridge	189:f392fc9709a3	1109	* returns 0.
AnnaBridge	189:f392fc9709a3	1110	*
AnnaBridge	189:f392fc9709a3	1111	* @param refFreq PLL reference clock frequency.
AnnaBridge	189:f392fc9709a3	1112	* @param desireFreq Desired PLL output frequency.
AnnaBridge	189:f392fc9709a3	1113	* @param prdiv PRDIV value to generate desired PLL frequency.
AnnaBridge	189:f392fc9709a3	1114	* @param vdiv VDIV value to generate desired PLL frequency.
AnnaBridge	189:f392fc9709a3	1115	* @return Closest frequency match that the PLL was able generate.
AnnaBridge	189:f392fc9709a3	1116	*/
AnnaBridge	189:f392fc9709a3	1117	uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t prdiv, uint8_t vdiv);
AnnaBridge	189:f392fc9709a3	1118
AnnaBridge	189:f392fc9709a3	1119	/@}/
AnnaBridge	189:f392fc9709a3	1120
AnnaBridge	189:f392fc9709a3	1121	/! @name MCG clock lock monitor functions. /
AnnaBridge	189:f392fc9709a3	1122	/@{/
AnnaBridge	189:f392fc9709a3	1123
AnnaBridge	189:f392fc9709a3	1124	/*!
AnnaBridge	189:f392fc9709a3	1125	* @brief Sets the OSC0 clock monitor mode.
AnnaBridge	189:f392fc9709a3	1126	*
AnnaBridge	189:f392fc9709a3	1127	* This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	189:f392fc9709a3	1128	*
AnnaBridge	189:f392fc9709a3	1129	* @param mode Monitor mode to set.
AnnaBridge	189:f392fc9709a3	1130	*/
AnnaBridge	189:f392fc9709a3	1131	void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	189:f392fc9709a3	1132
AnnaBridge	189:f392fc9709a3	1133	/*!
AnnaBridge	189:f392fc9709a3	1134	* @brief Sets the RTC OSC clock monitor mode.
AnnaBridge	189:f392fc9709a3	1135	*
AnnaBridge	189:f392fc9709a3	1136	* This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	189:f392fc9709a3	1137	*
AnnaBridge	189:f392fc9709a3	1138	* @param mode Monitor mode to set.
AnnaBridge	189:f392fc9709a3	1139	*/
AnnaBridge	189:f392fc9709a3	1140	void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	189:f392fc9709a3	1141
AnnaBridge	189:f392fc9709a3	1142	/*!
AnnaBridge	189:f392fc9709a3	1143	* @brief Sets the PLL0 clock monitor mode.
AnnaBridge	189:f392fc9709a3	1144	*
AnnaBridge	189:f392fc9709a3	1145	* This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge	189:f392fc9709a3	1146	*
AnnaBridge	189:f392fc9709a3	1147	* @param mode Monitor mode to set.
AnnaBridge	189:f392fc9709a3	1148	*/
AnnaBridge	189:f392fc9709a3	1149	void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
AnnaBridge	189:f392fc9709a3	1150
AnnaBridge	189:f392fc9709a3	1151	/*!
AnnaBridge	189:f392fc9709a3	1152	* @brief Gets the MCG status flags.
AnnaBridge	189:f392fc9709a3	1153	*
AnnaBridge	189:f392fc9709a3	1154	* This function gets the MCG clock status flags. All status flags are
AnnaBridge	189:f392fc9709a3	1155	* returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
AnnaBridge	189:f392fc9709a3	1156	* check a specific flag, compare the return value with the flag.
AnnaBridge	189:f392fc9709a3	1157	*
AnnaBridge	189:f392fc9709a3	1158	* Example:
AnnaBridge	189:f392fc9709a3	1159	* @code
AnnaBridge	189:f392fc9709a3	1160	// To check the clock lost lock status of OSC0 and PLL0.
AnnaBridge	189:f392fc9709a3	1161	uint32_t mcgFlags;
AnnaBridge	189:f392fc9709a3	1162
AnnaBridge	189:f392fc9709a3	1163	mcgFlags = CLOCK_GetStatusFlags();
AnnaBridge	189:f392fc9709a3	1164
AnnaBridge	189:f392fc9709a3	1165	if (mcgFlags & kMCG_Osc0LostFlag)
AnnaBridge	189:f392fc9709a3	1166	{
AnnaBridge	189:f392fc9709a3	1167	// OSC0 clock lock lost. Do something.
AnnaBridge	189:f392fc9709a3	1168	}
AnnaBridge	189:f392fc9709a3	1169	if (mcgFlags & kMCG_Pll0LostFlag)
AnnaBridge	189:f392fc9709a3	1170	{
AnnaBridge	189:f392fc9709a3	1171	// PLL0 clock lock lost. Do something.
AnnaBridge	189:f392fc9709a3	1172	}
AnnaBridge	189:f392fc9709a3	1173	@endcode
AnnaBridge	189:f392fc9709a3	1174	*
AnnaBridge	189:f392fc9709a3	1175	* @return Logical OR value of the @ref _mcg_status_flags_t.
AnnaBridge	189:f392fc9709a3	1176	*/
AnnaBridge	189:f392fc9709a3	1177	uint32_t CLOCK_GetStatusFlags(void);
AnnaBridge	189:f392fc9709a3	1178
AnnaBridge	189:f392fc9709a3	1179	/*!
AnnaBridge	189:f392fc9709a3	1180	* @brief Clears the MCG status flags.
AnnaBridge	189:f392fc9709a3	1181	*
AnnaBridge	189:f392fc9709a3	1182	* This function clears the MCG clock lock lost status. The parameter is a logical
AnnaBridge	189:f392fc9709a3	1183	* OR value of the flags to clear. See @ref _mcg_status_flags_t.
AnnaBridge	189:f392fc9709a3	1184	*
AnnaBridge	189:f392fc9709a3	1185	* Example:
AnnaBridge	189:f392fc9709a3	1186	* @code
AnnaBridge	189:f392fc9709a3	1187	// To clear the clock lost lock status flags of OSC0 and PLL0.
AnnaBridge	189:f392fc9709a3	1188
AnnaBridge	189:f392fc9709a3	1189	CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag \| kMCG_Pll0LostFlag);
AnnaBridge	189:f392fc9709a3	1190	@endcode
AnnaBridge	189:f392fc9709a3	1191	*
AnnaBridge	189:f392fc9709a3	1192	* @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge	189:f392fc9709a3	1193	* enumeration @ref _mcg_status_flags_t.
AnnaBridge	189:f392fc9709a3	1194	*/
AnnaBridge	189:f392fc9709a3	1195	void CLOCK_ClearStatusFlags(uint32_t mask);
AnnaBridge	189:f392fc9709a3	1196
AnnaBridge	189:f392fc9709a3	1197	/@}/
AnnaBridge	189:f392fc9709a3	1198
AnnaBridge	189:f392fc9709a3	1199	/*!
AnnaBridge	189:f392fc9709a3	1200	* @name OSC configuration
AnnaBridge	189:f392fc9709a3	1201	* @{
AnnaBridge	189:f392fc9709a3	1202	*/
AnnaBridge	189:f392fc9709a3	1203
AnnaBridge	189:f392fc9709a3	1204	/*!
AnnaBridge	189:f392fc9709a3	1205	* @brief Configures the OSC external reference clock (OSCERCLK).
AnnaBridge	189:f392fc9709a3	1206	*
AnnaBridge	189:f392fc9709a3	1207	* This function configures the OSC external reference clock (OSCERCLK).
AnnaBridge	189:f392fc9709a3	1208	* This is an example to enable the OSCERCLK in normal and stop modes and also set
AnnaBridge	189:f392fc9709a3	1209	* the output divider to 1:
AnnaBridge	189:f392fc9709a3	1210	*
AnnaBridge	189:f392fc9709a3	1211	@code
AnnaBridge	189:f392fc9709a3	1212	oscer_config_t config =
AnnaBridge	189:f392fc9709a3	1213	{
AnnaBridge	189:f392fc9709a3	1214	.enableMode = kOSC_ErClkEnable \| kOSC_ErClkEnableInStop,
AnnaBridge	189:f392fc9709a3	1215	.erclkDiv = 1U,
AnnaBridge	189:f392fc9709a3	1216	};
AnnaBridge	189:f392fc9709a3	1217
AnnaBridge	189:f392fc9709a3	1218	OSC_SetExtRefClkConfig(OSC, &config);
AnnaBridge	189:f392fc9709a3	1219	@endcode
AnnaBridge	189:f392fc9709a3	1220	*
AnnaBridge	189:f392fc9709a3	1221	* @param base OSC peripheral address.
AnnaBridge	189:f392fc9709a3	1222	* @param config Pointer to the configuration structure.
AnnaBridge	189:f392fc9709a3	1223	*/
AnnaBridge	189:f392fc9709a3	1224	static inline void OSC_SetExtRefClkConfig(OSC_Type base, oscer_config_t const config)
AnnaBridge	189:f392fc9709a3	1225	{
AnnaBridge	189:f392fc9709a3	1226	uint8_t reg = base->CR;
AnnaBridge	189:f392fc9709a3	1227
AnnaBridge	189:f392fc9709a3	1228	reg &= ~(OSC_CR_ERCLKEN_MASK \| OSC_CR_EREFSTEN_MASK);
AnnaBridge	189:f392fc9709a3	1229	reg \|= config->enableMode;
AnnaBridge	189:f392fc9709a3	1230
AnnaBridge	189:f392fc9709a3	1231	base->CR = reg;
AnnaBridge	189:f392fc9709a3	1232
AnnaBridge	189:f392fc9709a3	1233	base->DIV = OSC_DIV_ERPS(config->erclkDiv);
AnnaBridge	189:f392fc9709a3	1234	}
AnnaBridge	189:f392fc9709a3	1235
AnnaBridge	189:f392fc9709a3	1236	/*!
AnnaBridge	189:f392fc9709a3	1237	* @brief Sets the capacitor load configuration for the oscillator.
AnnaBridge	189:f392fc9709a3	1238	*
AnnaBridge	189:f392fc9709a3	1239	* This function sets the specified capacitors configuration for the oscillator.
AnnaBridge	189:f392fc9709a3	1240	* This should be done in the early system level initialization function call
AnnaBridge	189:f392fc9709a3	1241	* based on the system configuration.
AnnaBridge	189:f392fc9709a3	1242	*
AnnaBridge	189:f392fc9709a3	1243	* @param base OSC peripheral address.
AnnaBridge	189:f392fc9709a3	1244	* @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
AnnaBridge	189:f392fc9709a3	1245	*
AnnaBridge	189:f392fc9709a3	1246	* Example:
AnnaBridge	189:f392fc9709a3	1247	@code
AnnaBridge	189:f392fc9709a3	1248	// To enable only 2 pF and 8 pF capacitor load, please use like this.
AnnaBridge	189:f392fc9709a3	1249	OSC_SetCapLoad(OSC, kOSC_Cap2P \| kOSC_Cap8P);
AnnaBridge	189:f392fc9709a3	1250	@endcode
AnnaBridge	189:f392fc9709a3	1251	*/
AnnaBridge	189:f392fc9709a3	1252	static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
AnnaBridge	189:f392fc9709a3	1253	{
AnnaBridge	189:f392fc9709a3	1254	uint8_t reg = base->CR;
AnnaBridge	189:f392fc9709a3	1255
AnnaBridge	189:f392fc9709a3	1256	reg &= ~(OSC_CR_SC2P_MASK \| OSC_CR_SC4P_MASK \| OSC_CR_SC8P_MASK \| OSC_CR_SC16P_MASK);
AnnaBridge	189:f392fc9709a3	1257	reg \|= capLoad;
AnnaBridge	189:f392fc9709a3	1258
AnnaBridge	189:f392fc9709a3	1259	base->CR = reg;
AnnaBridge	189:f392fc9709a3	1260	}
AnnaBridge	189:f392fc9709a3	1261
AnnaBridge	189:f392fc9709a3	1262	/*!
AnnaBridge	189:f392fc9709a3	1263	* @brief Initializes the OSC0.
AnnaBridge	189:f392fc9709a3	1264	*
AnnaBridge	189:f392fc9709a3	1265	* This function initializes the OSC0 according to the board configuration.
AnnaBridge	189:f392fc9709a3	1266	*
AnnaBridge	189:f392fc9709a3	1267	* @param config Pointer to the OSC0 configuration structure.
AnnaBridge	189:f392fc9709a3	1268	*/
AnnaBridge	189:f392fc9709a3	1269	void CLOCK_InitOsc0(osc_config_t const *config);
AnnaBridge	189:f392fc9709a3	1270
AnnaBridge	189:f392fc9709a3	1271	/*!
AnnaBridge	189:f392fc9709a3	1272	* @brief Deinitializes the OSC0.
AnnaBridge	189:f392fc9709a3	1273	*
AnnaBridge	189:f392fc9709a3	1274	* This function deinitializes the OSC0.
AnnaBridge	189:f392fc9709a3	1275	*/
AnnaBridge	189:f392fc9709a3	1276	void CLOCK_DeinitOsc0(void);
AnnaBridge	189:f392fc9709a3	1277
AnnaBridge	189:f392fc9709a3	1278	/* @} */
AnnaBridge	189:f392fc9709a3	1279
AnnaBridge	189:f392fc9709a3	1280	/*!
AnnaBridge	189:f392fc9709a3	1281	* @name External clock frequency
AnnaBridge	189:f392fc9709a3	1282	* @{
AnnaBridge	189:f392fc9709a3	1283	*/
AnnaBridge	189:f392fc9709a3	1284
AnnaBridge	189:f392fc9709a3	1285	/*!
AnnaBridge	189:f392fc9709a3	1286	* @brief Sets the XTAL0 frequency based on board settings.
AnnaBridge	189:f392fc9709a3	1287	*
AnnaBridge	189:f392fc9709a3	1288	* @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	1289	*/
AnnaBridge	189:f392fc9709a3	1290	static inline void CLOCK_SetXtal0Freq(uint32_t freq)
AnnaBridge	189:f392fc9709a3	1291	{
AnnaBridge	189:f392fc9709a3	1292	g_xtal0Freq = freq;
AnnaBridge	189:f392fc9709a3	1293	}
AnnaBridge	189:f392fc9709a3	1294
AnnaBridge	189:f392fc9709a3	1295	/*!
AnnaBridge	189:f392fc9709a3	1296	* @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
AnnaBridge	189:f392fc9709a3	1297	*
AnnaBridge	189:f392fc9709a3	1298	* @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
AnnaBridge	189:f392fc9709a3	1299	*/
AnnaBridge	189:f392fc9709a3	1300	static inline void CLOCK_SetXtal32Freq(uint32_t freq)
AnnaBridge	189:f392fc9709a3	1301	{
AnnaBridge	189:f392fc9709a3	1302	g_xtal32Freq = freq;
AnnaBridge	189:f392fc9709a3	1303	}
AnnaBridge	189:f392fc9709a3	1304	/* @} */
AnnaBridge	189:f392fc9709a3	1305
AnnaBridge	189:f392fc9709a3	1306	/*!
AnnaBridge	189:f392fc9709a3	1307	* @name MCG auto-trim machine.
AnnaBridge	189:f392fc9709a3	1308	* @{
AnnaBridge	189:f392fc9709a3	1309	*/
AnnaBridge	189:f392fc9709a3	1310
AnnaBridge	189:f392fc9709a3	1311	/*!
AnnaBridge	189:f392fc9709a3	1312	* @brief Auto trims the internal reference clock.
AnnaBridge	189:f392fc9709a3	1313	*
AnnaBridge	189:f392fc9709a3	1314	* This function trims the internal reference clock by using the external clock. If
AnnaBridge	189:f392fc9709a3	1315	* successful, it returns the kStatus_Success and the frequency after
AnnaBridge	189:f392fc9709a3	1316	* trimming is received in the parameter @p actualFreq. If an error occurs,
AnnaBridge	189:f392fc9709a3	1317	* the error code is returned.
AnnaBridge	189:f392fc9709a3	1318	*
AnnaBridge	189:f392fc9709a3	1319	* @param extFreq External clock frequency, which should be a bus clock.
AnnaBridge	189:f392fc9709a3	1320	* @param desireFreq Frequency to trim to.
AnnaBridge	189:f392fc9709a3	1321	* @param actualFreq Actual frequency after trimming.
AnnaBridge	189:f392fc9709a3	1322	* @param atms Trim fast or slow internal reference clock.
AnnaBridge	189:f392fc9709a3	1323	* @retval kStatus_Success ATM success.
AnnaBridge	189:f392fc9709a3	1324	* @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
AnnaBridge	189:f392fc9709a3	1325	* @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
AnnaBridge	189:f392fc9709a3	1326	* @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
AnnaBridge	189:f392fc9709a3	1327	* @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
AnnaBridge	189:f392fc9709a3	1328	*/
AnnaBridge	189:f392fc9709a3	1329	status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
AnnaBridge	189:f392fc9709a3	1330	/* @} */
AnnaBridge	189:f392fc9709a3	1331
AnnaBridge	189:f392fc9709a3	1332	/! @name MCG mode functions. /
AnnaBridge	189:f392fc9709a3	1333	/@{/
AnnaBridge	189:f392fc9709a3	1334
AnnaBridge	189:f392fc9709a3	1335	/*!
AnnaBridge	189:f392fc9709a3	1336	* @brief Gets the current MCG mode.
AnnaBridge	189:f392fc9709a3	1337	*
AnnaBridge	189:f392fc9709a3	1338	* This function checks the MCG registers and determines the current MCG mode.
AnnaBridge	189:f392fc9709a3	1339	*
AnnaBridge	189:f392fc9709a3	1340	* @return Current MCG mode or error code; See @ref mcg_mode_t.
AnnaBridge	189:f392fc9709a3	1341	*/
AnnaBridge	189:f392fc9709a3	1342	mcg_mode_t CLOCK_GetMode(void);
AnnaBridge	189:f392fc9709a3	1343
AnnaBridge	189:f392fc9709a3	1344	/*!
AnnaBridge	189:f392fc9709a3	1345	* @brief Sets the MCG to FEI mode.
AnnaBridge	189:f392fc9709a3	1346	*
AnnaBridge	189:f392fc9709a3	1347	* This function sets the MCG to FEI mode. If setting to FEI mode fails
AnnaBridge	189:f392fc9709a3	1348	* from the current mode, this function returns an error.
AnnaBridge	189:f392fc9709a3	1349	*
AnnaBridge	189:f392fc9709a3	1350	* @param dmx32 DMX32 in FEI mode.
AnnaBridge	189:f392fc9709a3	1351	* @param drs The DCO range selection.
AnnaBridge	189:f392fc9709a3	1352	* @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
AnnaBridge	189:f392fc9709a3	1353	* NULL does not cause a delay.
AnnaBridge	189:f392fc9709a3	1354	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1355	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1356	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	189:f392fc9709a3	1357	* to a frequency above 32768 Hz.
AnnaBridge	189:f392fc9709a3	1358	*/
AnnaBridge	189:f392fc9709a3	1359	status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	189:f392fc9709a3	1360
AnnaBridge	189:f392fc9709a3	1361	/*!
AnnaBridge	189:f392fc9709a3	1362	* @brief Sets the MCG to FEE mode.
AnnaBridge	189:f392fc9709a3	1363	*
AnnaBridge	189:f392fc9709a3	1364	* This function sets the MCG to FEE mode. If setting to FEE mode fails
AnnaBridge	189:f392fc9709a3	1365	* from the current mode, this function returns an error.
AnnaBridge	189:f392fc9709a3	1366	*
AnnaBridge	189:f392fc9709a3	1367	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	189:f392fc9709a3	1368	* @param dmx32 DMX32 in FEE mode.
AnnaBridge	189:f392fc9709a3	1369	* @param drs The DCO range selection.
AnnaBridge	189:f392fc9709a3	1370	* @param fllStableDelay Delay function to make sure FLL is stable. Passing
AnnaBridge	189:f392fc9709a3	1371	* NULL does not cause a delay.
AnnaBridge	189:f392fc9709a3	1372	*
AnnaBridge	189:f392fc9709a3	1373	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1374	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1375	*/
AnnaBridge	189:f392fc9709a3	1376	status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	189:f392fc9709a3	1377
AnnaBridge	189:f392fc9709a3	1378	/*!
AnnaBridge	189:f392fc9709a3	1379	* @brief Sets the MCG to FBI mode.
AnnaBridge	189:f392fc9709a3	1380	*
AnnaBridge	189:f392fc9709a3	1381	* This function sets the MCG to FBI mode. If setting to FBI mode fails
AnnaBridge	189:f392fc9709a3	1382	* from the current mode, this function returns an error.
AnnaBridge	189:f392fc9709a3	1383	*
AnnaBridge	189:f392fc9709a3	1384	* @param dmx32 DMX32 in FBI mode.
AnnaBridge	189:f392fc9709a3	1385	* @param drs The DCO range selection.
AnnaBridge	189:f392fc9709a3	1386	* @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge	189:f392fc9709a3	1387	* is not used in FBI mode, this parameter can be NULL. Passing
AnnaBridge	189:f392fc9709a3	1388	* NULL does not cause a delay.
AnnaBridge	189:f392fc9709a3	1389	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1390	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1391	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	189:f392fc9709a3	1392	* to frequency above 32768 Hz.
AnnaBridge	189:f392fc9709a3	1393	*/
AnnaBridge	189:f392fc9709a3	1394	status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	189:f392fc9709a3	1395
AnnaBridge	189:f392fc9709a3	1396	/*!
AnnaBridge	189:f392fc9709a3	1397	* @brief Sets the MCG to FBE mode.
AnnaBridge	189:f392fc9709a3	1398	*
AnnaBridge	189:f392fc9709a3	1399	* This function sets the MCG to FBE mode. If setting to FBE mode fails
AnnaBridge	189:f392fc9709a3	1400	* from the current mode, this function returns an error.
AnnaBridge	189:f392fc9709a3	1401	*
AnnaBridge	189:f392fc9709a3	1402	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	189:f392fc9709a3	1403	* @param dmx32 DMX32 in FBE mode.
AnnaBridge	189:f392fc9709a3	1404	* @param drs The DCO range selection.
AnnaBridge	189:f392fc9709a3	1405	* @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge	189:f392fc9709a3	1406	* is not used in FBE mode, this parameter can be NULL. Passing NULL
AnnaBridge	189:f392fc9709a3	1407	* does not cause a delay.
AnnaBridge	189:f392fc9709a3	1408	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1409	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1410	*/
AnnaBridge	189:f392fc9709a3	1411	status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	189:f392fc9709a3	1412
AnnaBridge	189:f392fc9709a3	1413	/*!
AnnaBridge	189:f392fc9709a3	1414	* @brief Sets the MCG to BLPI mode.
AnnaBridge	189:f392fc9709a3	1415	*
AnnaBridge	189:f392fc9709a3	1416	* This function sets the MCG to BLPI mode. If setting to BLPI mode fails
AnnaBridge	189:f392fc9709a3	1417	* from the current mode, this function returns an error.
AnnaBridge	189:f392fc9709a3	1418	*
AnnaBridge	189:f392fc9709a3	1419	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1420	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1421	*/
AnnaBridge	189:f392fc9709a3	1422	status_t CLOCK_SetBlpiMode(void);
AnnaBridge	189:f392fc9709a3	1423
AnnaBridge	189:f392fc9709a3	1424	/*!
AnnaBridge	189:f392fc9709a3	1425	* @brief Sets the MCG to BLPE mode.
AnnaBridge	189:f392fc9709a3	1426	*
AnnaBridge	189:f392fc9709a3	1427	* This function sets the MCG to BLPE mode. If setting to BLPE mode fails
AnnaBridge	189:f392fc9709a3	1428	* from the current mode, this function returns an error.
AnnaBridge	189:f392fc9709a3	1429	*
AnnaBridge	189:f392fc9709a3	1430	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1431	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1432	*/
AnnaBridge	189:f392fc9709a3	1433	status_t CLOCK_SetBlpeMode(void);
AnnaBridge	189:f392fc9709a3	1434
AnnaBridge	189:f392fc9709a3	1435	/*!
AnnaBridge	189:f392fc9709a3	1436	* @brief Sets the MCG to PBE mode.
AnnaBridge	189:f392fc9709a3	1437	*
AnnaBridge	189:f392fc9709a3	1438	* This function sets the MCG to PBE mode. If setting to PBE mode fails
AnnaBridge	189:f392fc9709a3	1439	* from the current mode, this function returns an error.
AnnaBridge	189:f392fc9709a3	1440	*
AnnaBridge	189:f392fc9709a3	1441	* @param pllcs The PLL selection, PLLCS.
AnnaBridge	189:f392fc9709a3	1442	* @param config Pointer to the PLL configuration.
AnnaBridge	189:f392fc9709a3	1443	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1444	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1445	*
AnnaBridge	189:f392fc9709a3	1446	* @note
AnnaBridge	189:f392fc9709a3	1447	* 1. The parameter \c pllcs selects the PLL. For platforms with
AnnaBridge	189:f392fc9709a3	1448	* only one PLL, the parameter pllcs is kept for interface compatibility.
AnnaBridge	189:f392fc9709a3	1449	* 2. The parameter \c config is the PLL configuration structure. On some
AnnaBridge	189:f392fc9709a3	1450	* platforms, it is possible to choose the external PLL directly, which renders the
AnnaBridge	189:f392fc9709a3	1451	* configuration structure not necessary. In this case, pass in NULL.
AnnaBridge	189:f392fc9709a3	1452	* For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
AnnaBridge	189:f392fc9709a3	1453	*/
AnnaBridge	189:f392fc9709a3	1454	status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge	189:f392fc9709a3	1455
AnnaBridge	189:f392fc9709a3	1456	/*!
AnnaBridge	189:f392fc9709a3	1457	* @brief Sets the MCG to PEE mode.
AnnaBridge	189:f392fc9709a3	1458	*
AnnaBridge	189:f392fc9709a3	1459	* This function sets the MCG to PEE mode.
AnnaBridge	189:f392fc9709a3	1460	*
AnnaBridge	189:f392fc9709a3	1461	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1462	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1463	*
AnnaBridge	189:f392fc9709a3	1464	* @note This function only changes the CLKS to use the PLL/FLL output. If the
AnnaBridge	189:f392fc9709a3	1465	* PRDIV/VDIV are different than in the PBE mode, set them up
AnnaBridge	189:f392fc9709a3	1466	* in PBE mode and wait. When the clock is stable, switch to PEE mode.
AnnaBridge	189:f392fc9709a3	1467	*/
AnnaBridge	189:f392fc9709a3	1468	status_t CLOCK_SetPeeMode(void);
AnnaBridge	189:f392fc9709a3	1469
AnnaBridge	189:f392fc9709a3	1470	/*!
AnnaBridge	189:f392fc9709a3	1471	* @brief Switches the MCG to FBE mode from the external mode.
AnnaBridge	189:f392fc9709a3	1472	*
AnnaBridge	189:f392fc9709a3	1473	* This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
AnnaBridge	189:f392fc9709a3	1474	* The external clock is used as the system clock souce and PLL is disabled. However,
AnnaBridge	189:f392fc9709a3	1475	* the FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge	189:f392fc9709a3	1476	* during the mode switch. For example, to switch from PEE mode to FEI mode:
AnnaBridge	189:f392fc9709a3	1477	*
AnnaBridge	189:f392fc9709a3	1478	* @code
AnnaBridge	189:f392fc9709a3	1479	* CLOCK_ExternalModeToFbeModeQuick();
AnnaBridge	189:f392fc9709a3	1480	* CLOCK_SetFeiMode(...);
AnnaBridge	189:f392fc9709a3	1481	* @endcode
AnnaBridge	189:f392fc9709a3	1482	*
AnnaBridge	189:f392fc9709a3	1483	* @retval kStatus_Success Switched successfully.
AnnaBridge	189:f392fc9709a3	1484	* @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
AnnaBridge	189:f392fc9709a3	1485	*/
AnnaBridge	189:f392fc9709a3	1486	status_t CLOCK_ExternalModeToFbeModeQuick(void);
AnnaBridge	189:f392fc9709a3	1487
AnnaBridge	189:f392fc9709a3	1488	/*!
AnnaBridge	189:f392fc9709a3	1489	* @brief Switches the MCG to FBI mode from internal modes.
AnnaBridge	189:f392fc9709a3	1490	*
AnnaBridge	189:f392fc9709a3	1491	* This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
AnnaBridge	189:f392fc9709a3	1492	* The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
AnnaBridge	189:f392fc9709a3	1493	* FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge	189:f392fc9709a3	1494	* during the mode switch. For example, to switch from PEI mode to FEE mode:
AnnaBridge	189:f392fc9709a3	1495	*
AnnaBridge	189:f392fc9709a3	1496	* @code
AnnaBridge	189:f392fc9709a3	1497	* CLOCK_InternalModeToFbiModeQuick();
AnnaBridge	189:f392fc9709a3	1498	* CLOCK_SetFeeMode(...);
AnnaBridge	189:f392fc9709a3	1499	* @endcode
AnnaBridge	189:f392fc9709a3	1500	*
AnnaBridge	189:f392fc9709a3	1501	* @retval kStatus_Success Switched successfully.
AnnaBridge	189:f392fc9709a3	1502	* @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
AnnaBridge	189:f392fc9709a3	1503	*/
AnnaBridge	189:f392fc9709a3	1504	status_t CLOCK_InternalModeToFbiModeQuick(void);
AnnaBridge	189:f392fc9709a3	1505
AnnaBridge	189:f392fc9709a3	1506	/*!
AnnaBridge	189:f392fc9709a3	1507	* @brief Sets the MCG to FEI mode during system boot up.
AnnaBridge	189:f392fc9709a3	1508	*
AnnaBridge	189:f392fc9709a3	1509	* This function sets the MCG to FEI mode from the reset mode. It can also be used to
AnnaBridge	189:f392fc9709a3	1510	* set up MCG during system boot up.
AnnaBridge	189:f392fc9709a3	1511	*
AnnaBridge	189:f392fc9709a3	1512	* @param dmx32 DMX32 in FEI mode.
AnnaBridge	189:f392fc9709a3	1513	* @param drs The DCO range selection.
AnnaBridge	189:f392fc9709a3	1514	* @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge	189:f392fc9709a3	1515	*
AnnaBridge	189:f392fc9709a3	1516	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1517	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1518	* @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge	189:f392fc9709a3	1519	* to frequency above 32768 Hz.
AnnaBridge	189:f392fc9709a3	1520	*/
AnnaBridge	189:f392fc9709a3	1521	status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	189:f392fc9709a3	1522
AnnaBridge	189:f392fc9709a3	1523	/*!
AnnaBridge	189:f392fc9709a3	1524	* @brief Sets the MCG to FEE mode during system bootup.
AnnaBridge	189:f392fc9709a3	1525	*
AnnaBridge	189:f392fc9709a3	1526	* This function sets MCG to FEE mode from the reset mode. It can also be used to
AnnaBridge	189:f392fc9709a3	1527	* set up the MCG during system boot up.
AnnaBridge	189:f392fc9709a3	1528	*
AnnaBridge	189:f392fc9709a3	1529	* @param oscsel OSC clock select, OSCSEL.
AnnaBridge	189:f392fc9709a3	1530	* @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge	189:f392fc9709a3	1531	* @param dmx32 DMX32 in FEE mode.
AnnaBridge	189:f392fc9709a3	1532	* @param drs The DCO range selection.
AnnaBridge	189:f392fc9709a3	1533	* @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge	189:f392fc9709a3	1534	*
AnnaBridge	189:f392fc9709a3	1535	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1536	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1537	*/
AnnaBridge	189:f392fc9709a3	1538	status_t CLOCK_BootToFeeMode(
AnnaBridge	189:f392fc9709a3	1539	mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge	189:f392fc9709a3	1540
AnnaBridge	189:f392fc9709a3	1541	/*!
AnnaBridge	189:f392fc9709a3	1542	* @brief Sets the MCG to BLPI mode during system boot up.
AnnaBridge	189:f392fc9709a3	1543	*
AnnaBridge	189:f392fc9709a3	1544	* This function sets the MCG to BLPI mode from the reset mode. It can also be used to
AnnaBridge	189:f392fc9709a3	1545	* set up the MCG during sytem boot up.
AnnaBridge	189:f392fc9709a3	1546	*
AnnaBridge	189:f392fc9709a3	1547	* @param fcrdiv Fast IRC divider, FCRDIV.
AnnaBridge	189:f392fc9709a3	1548	* @param ircs The internal reference clock to select, IRCS.
AnnaBridge	189:f392fc9709a3	1549	* @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge	189:f392fc9709a3	1550	*
AnnaBridge	189:f392fc9709a3	1551	* @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
AnnaBridge	189:f392fc9709a3	1552	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1553	*/
AnnaBridge	189:f392fc9709a3	1554	status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
AnnaBridge	189:f392fc9709a3	1555
AnnaBridge	189:f392fc9709a3	1556	/*!
AnnaBridge	189:f392fc9709a3	1557	* @brief Sets the MCG to BLPE mode during sytem boot up.
AnnaBridge	189:f392fc9709a3	1558	*
AnnaBridge	189:f392fc9709a3	1559	* This function sets the MCG to BLPE mode from the reset mode. It can also be used to
AnnaBridge	189:f392fc9709a3	1560	* set up the MCG during sytem boot up.
AnnaBridge	189:f392fc9709a3	1561	*
AnnaBridge	189:f392fc9709a3	1562	* @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge	189:f392fc9709a3	1563	*
AnnaBridge	189:f392fc9709a3	1564	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1565	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1566	*/
AnnaBridge	189:f392fc9709a3	1567	status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
AnnaBridge	189:f392fc9709a3	1568
AnnaBridge	189:f392fc9709a3	1569	/*!
AnnaBridge	189:f392fc9709a3	1570	* @brief Sets the MCG to PEE mode during system boot up.
AnnaBridge	189:f392fc9709a3	1571	*
AnnaBridge	189:f392fc9709a3	1572	* This function sets the MCG to PEE mode from reset mode. It can also be used to
AnnaBridge	189:f392fc9709a3	1573	* set up the MCG during system boot up.
AnnaBridge	189:f392fc9709a3	1574	*
AnnaBridge	189:f392fc9709a3	1575	* @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge	189:f392fc9709a3	1576	* @param pllcs The PLL selection, PLLCS.
AnnaBridge	189:f392fc9709a3	1577	* @param config Pointer to the PLL configuration.
AnnaBridge	189:f392fc9709a3	1578	*
AnnaBridge	189:f392fc9709a3	1579	* @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge	189:f392fc9709a3	1580	* @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge	189:f392fc9709a3	1581	*/
AnnaBridge	189:f392fc9709a3	1582	status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
AnnaBridge	189:f392fc9709a3	1583
AnnaBridge	189:f392fc9709a3	1584	/*!
AnnaBridge	189:f392fc9709a3	1585	* @brief Sets the MCG to a target mode.
AnnaBridge	189:f392fc9709a3	1586	*
AnnaBridge	189:f392fc9709a3	1587	* This function sets MCG to a target mode defined by the configuration
AnnaBridge	189:f392fc9709a3	1588	* structure. If switching to the target mode fails, this function
AnnaBridge	189:f392fc9709a3	1589	* chooses the correct path.
AnnaBridge	189:f392fc9709a3	1590	*
AnnaBridge	189:f392fc9709a3	1591	* @param config Pointer to the target MCG mode configuration structure.
AnnaBridge	189:f392fc9709a3	1592	* @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
AnnaBridge	189:f392fc9709a3	1593	*
AnnaBridge	189:f392fc9709a3	1594	* @note If the external clock is used in the target mode, ensure that it is
AnnaBridge	189:f392fc9709a3	1595	* enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
AnnaBridge	189:f392fc9709a3	1596	* function.
AnnaBridge	189:f392fc9709a3	1597	*/
AnnaBridge	189:f392fc9709a3	1598	status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
AnnaBridge	189:f392fc9709a3	1599
AnnaBridge	189:f392fc9709a3	1600	/@}/
AnnaBridge	189:f392fc9709a3	1601
AnnaBridge	189:f392fc9709a3	1602	#if defined(__cplusplus)
AnnaBridge	189:f392fc9709a3	1603	}
AnnaBridge	189:f392fc9709a3	1604	#endif /* __cplusplus */
AnnaBridge	189:f392fc9709a3	1605
AnnaBridge	189:f392fc9709a3	1606	/! @} /
AnnaBridge	189:f392fc9709a3	1607
AnnaBridge	189:f392fc9709a3	1608	#endif /* _FSL_CLOCK_H_ */