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cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/core_cm0plus.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**************************************************************************//**
AnnaBridge 189:f392fc9709a3 2 * @file core_cm0plus.h
AnnaBridge 189:f392fc9709a3 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
AnnaBridge 189:f392fc9709a3 4 * @version V5.0.6
AnnaBridge 189:f392fc9709a3 5 * @date 28. May 2018
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 7 /*
AnnaBridge 189:f392fc9709a3 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 189:f392fc9709a3 9 *
AnnaBridge 189:f392fc9709a3 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 189:f392fc9709a3 11 *
AnnaBridge 189:f392fc9709a3 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 189:f392fc9709a3 13 * not use this file except in compliance with the License.
AnnaBridge 189:f392fc9709a3 14 * You may obtain a copy of the License at
AnnaBridge 189:f392fc9709a3 15 *
AnnaBridge 189:f392fc9709a3 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 189:f392fc9709a3 17 *
AnnaBridge 189:f392fc9709a3 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 189:f392fc9709a3 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 189:f392fc9709a3 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 189:f392fc9709a3 21 * See the License for the specific language governing permissions and
AnnaBridge 189:f392fc9709a3 22 * limitations under the License.
AnnaBridge 189:f392fc9709a3 23 */
AnnaBridge 189:f392fc9709a3 24
AnnaBridge 189:f392fc9709a3 25 #if defined ( __ICCARM__ )
AnnaBridge 189:f392fc9709a3 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 189:f392fc9709a3 27 #elif defined (__clang__)
AnnaBridge 189:f392fc9709a3 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 189:f392fc9709a3 29 #endif
AnnaBridge 189:f392fc9709a3 30
AnnaBridge 189:f392fc9709a3 31 #ifndef __CORE_CM0PLUS_H_GENERIC
AnnaBridge 189:f392fc9709a3 32 #define __CORE_CM0PLUS_H_GENERIC
AnnaBridge 189:f392fc9709a3 33
AnnaBridge 189:f392fc9709a3 34 #include <stdint.h>
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 37 extern "C" {
AnnaBridge 189:f392fc9709a3 38 #endif
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 /**
AnnaBridge 189:f392fc9709a3 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 189:f392fc9709a3 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 189:f392fc9709a3 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 189:f392fc9709a3 48 Unions are used for effective representation of core registers.
AnnaBridge 189:f392fc9709a3 49
AnnaBridge 189:f392fc9709a3 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 189:f392fc9709a3 51 Function-like macros are used to allow more efficient code.
AnnaBridge 189:f392fc9709a3 52 */
AnnaBridge 189:f392fc9709a3 53
AnnaBridge 189:f392fc9709a3 54
AnnaBridge 189:f392fc9709a3 55 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 56 * CMSIS definitions
AnnaBridge 189:f392fc9709a3 57 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 58 /**
AnnaBridge 189:f392fc9709a3 59 \ingroup Cortex-M0+
AnnaBridge 189:f392fc9709a3 60 @{
AnnaBridge 189:f392fc9709a3 61 */
AnnaBridge 189:f392fc9709a3 62
AnnaBridge 189:f392fc9709a3 63 #include "cmsis_version.h"
AnnaBridge 189:f392fc9709a3 64
AnnaBridge 189:f392fc9709a3 65 /* CMSIS CM0+ definitions */
AnnaBridge 189:f392fc9709a3 66 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 189:f392fc9709a3 67 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 189:f392fc9709a3 68 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 189:f392fc9709a3 69 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 189:f392fc9709a3 70
AnnaBridge 189:f392fc9709a3 71 #define __CORTEX_M (0U) /*!< Cortex-M Core */
AnnaBridge 189:f392fc9709a3 72
AnnaBridge 189:f392fc9709a3 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 189:f392fc9709a3 74 This core does not support an FPU at all
AnnaBridge 189:f392fc9709a3 75 */
AnnaBridge 189:f392fc9709a3 76 #define __FPU_USED 0U
AnnaBridge 189:f392fc9709a3 77
AnnaBridge 189:f392fc9709a3 78 #if defined ( __CC_ARM )
AnnaBridge 189:f392fc9709a3 79 #if defined __TARGET_FPU_VFP
AnnaBridge 189:f392fc9709a3 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 81 #endif
AnnaBridge 189:f392fc9709a3 82
AnnaBridge 189:f392fc9709a3 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 189:f392fc9709a3 84 #if defined __ARM_FP
AnnaBridge 189:f392fc9709a3 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 86 #endif
AnnaBridge 189:f392fc9709a3 87
AnnaBridge 189:f392fc9709a3 88 #elif defined ( __GNUC__ )
AnnaBridge 189:f392fc9709a3 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 189:f392fc9709a3 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 91 #endif
AnnaBridge 189:f392fc9709a3 92
AnnaBridge 189:f392fc9709a3 93 #elif defined ( __ICCARM__ )
AnnaBridge 189:f392fc9709a3 94 #if defined __ARMVFP__
AnnaBridge 189:f392fc9709a3 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 96 #endif
AnnaBridge 189:f392fc9709a3 97
AnnaBridge 189:f392fc9709a3 98 #elif defined ( __TI_ARM__ )
AnnaBridge 189:f392fc9709a3 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 189:f392fc9709a3 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 101 #endif
AnnaBridge 189:f392fc9709a3 102
AnnaBridge 189:f392fc9709a3 103 #elif defined ( __TASKING__ )
AnnaBridge 189:f392fc9709a3 104 #if defined __FPU_VFP__
AnnaBridge 189:f392fc9709a3 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 106 #endif
AnnaBridge 189:f392fc9709a3 107
AnnaBridge 189:f392fc9709a3 108 #elif defined ( __CSMC__ )
AnnaBridge 189:f392fc9709a3 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 189:f392fc9709a3 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 189:f392fc9709a3 111 #endif
AnnaBridge 189:f392fc9709a3 112
AnnaBridge 189:f392fc9709a3 113 #endif
AnnaBridge 189:f392fc9709a3 114
AnnaBridge 189:f392fc9709a3 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 189:f392fc9709a3 116
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 119 }
AnnaBridge 189:f392fc9709a3 120 #endif
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 #endif /* __CORE_CM0PLUS_H_GENERIC */
AnnaBridge 189:f392fc9709a3 123
AnnaBridge 189:f392fc9709a3 124 #ifndef __CMSIS_GENERIC
AnnaBridge 189:f392fc9709a3 125
AnnaBridge 189:f392fc9709a3 126 #ifndef __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 189:f392fc9709a3 127 #define __CORE_CM0PLUS_H_DEPENDANT
AnnaBridge 189:f392fc9709a3 128
AnnaBridge 189:f392fc9709a3 129 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 130 extern "C" {
AnnaBridge 189:f392fc9709a3 131 #endif
AnnaBridge 189:f392fc9709a3 132
AnnaBridge 189:f392fc9709a3 133 /* check device defines and use defaults */
AnnaBridge 189:f392fc9709a3 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 189:f392fc9709a3 135 #ifndef __CM0PLUS_REV
AnnaBridge 189:f392fc9709a3 136 #define __CM0PLUS_REV 0x0000U
AnnaBridge 189:f392fc9709a3 137 #warning "__CM0PLUS_REV not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 138 #endif
AnnaBridge 189:f392fc9709a3 139
AnnaBridge 189:f392fc9709a3 140 #ifndef __MPU_PRESENT
AnnaBridge 189:f392fc9709a3 141 #define __MPU_PRESENT 0U
AnnaBridge 189:f392fc9709a3 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 143 #endif
AnnaBridge 189:f392fc9709a3 144
AnnaBridge 189:f392fc9709a3 145 #ifndef __VTOR_PRESENT
AnnaBridge 189:f392fc9709a3 146 #define __VTOR_PRESENT 0U
AnnaBridge 189:f392fc9709a3 147 #warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 148 #endif
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 #ifndef __NVIC_PRIO_BITS
AnnaBridge 189:f392fc9709a3 151 #define __NVIC_PRIO_BITS 2U
AnnaBridge 189:f392fc9709a3 152 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 153 #endif
AnnaBridge 189:f392fc9709a3 154
AnnaBridge 189:f392fc9709a3 155 #ifndef __Vendor_SysTickConfig
AnnaBridge 189:f392fc9709a3 156 #define __Vendor_SysTickConfig 0U
AnnaBridge 189:f392fc9709a3 157 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 189:f392fc9709a3 158 #endif
AnnaBridge 189:f392fc9709a3 159 #endif
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 189:f392fc9709a3 162 /**
AnnaBridge 189:f392fc9709a3 163 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 189:f392fc9709a3 164
AnnaBridge 189:f392fc9709a3 165 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 189:f392fc9709a3 166 \li to specify the access to peripheral variables.
AnnaBridge 189:f392fc9709a3 167 \li for automatic generation of peripheral register debug information.
AnnaBridge 189:f392fc9709a3 168 */
AnnaBridge 189:f392fc9709a3 169 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 170 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 189:f392fc9709a3 171 #else
AnnaBridge 189:f392fc9709a3 172 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 189:f392fc9709a3 173 #endif
AnnaBridge 189:f392fc9709a3 174 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 189:f392fc9709a3 175 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 189:f392fc9709a3 176
AnnaBridge 189:f392fc9709a3 177 /* following defines should be used for structure members */
AnnaBridge 189:f392fc9709a3 178 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 189:f392fc9709a3 179 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 189:f392fc9709a3 180 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 189:f392fc9709a3 181
AnnaBridge 189:f392fc9709a3 182 /*@} end of group Cortex-M0+ */
AnnaBridge 189:f392fc9709a3 183
AnnaBridge 189:f392fc9709a3 184
AnnaBridge 189:f392fc9709a3 185
AnnaBridge 189:f392fc9709a3 186 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 187 * Register Abstraction
AnnaBridge 189:f392fc9709a3 188 Core Register contain:
AnnaBridge 189:f392fc9709a3 189 - Core Register
AnnaBridge 189:f392fc9709a3 190 - Core NVIC Register
AnnaBridge 189:f392fc9709a3 191 - Core SCB Register
AnnaBridge 189:f392fc9709a3 192 - Core SysTick Register
AnnaBridge 189:f392fc9709a3 193 - Core MPU Register
AnnaBridge 189:f392fc9709a3 194 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 195 /**
AnnaBridge 189:f392fc9709a3 196 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 189:f392fc9709a3 197 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 189:f392fc9709a3 198 */
AnnaBridge 189:f392fc9709a3 199
AnnaBridge 189:f392fc9709a3 200 /**
AnnaBridge 189:f392fc9709a3 201 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 202 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 189:f392fc9709a3 203 \brief Core Register type definitions.
AnnaBridge 189:f392fc9709a3 204 @{
AnnaBridge 189:f392fc9709a3 205 */
AnnaBridge 189:f392fc9709a3 206
AnnaBridge 189:f392fc9709a3 207 /**
AnnaBridge 189:f392fc9709a3 208 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 189:f392fc9709a3 209 */
AnnaBridge 189:f392fc9709a3 210 typedef union
AnnaBridge 189:f392fc9709a3 211 {
AnnaBridge 189:f392fc9709a3 212 struct
AnnaBridge 189:f392fc9709a3 213 {
AnnaBridge 189:f392fc9709a3 214 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 189:f392fc9709a3 215 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 189:f392fc9709a3 216 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 189:f392fc9709a3 217 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 189:f392fc9709a3 218 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 189:f392fc9709a3 219 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 220 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 221 } APSR_Type;
AnnaBridge 189:f392fc9709a3 222
AnnaBridge 189:f392fc9709a3 223 /* APSR Register Definitions */
AnnaBridge 189:f392fc9709a3 224 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 189:f392fc9709a3 225 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 189:f392fc9709a3 226
AnnaBridge 189:f392fc9709a3 227 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 189:f392fc9709a3 228 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 189:f392fc9709a3 229
AnnaBridge 189:f392fc9709a3 230 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 189:f392fc9709a3 231 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 189:f392fc9709a3 232
AnnaBridge 189:f392fc9709a3 233 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 189:f392fc9709a3 234 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 189:f392fc9709a3 235
AnnaBridge 189:f392fc9709a3 236
AnnaBridge 189:f392fc9709a3 237 /**
AnnaBridge 189:f392fc9709a3 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 189:f392fc9709a3 239 */
AnnaBridge 189:f392fc9709a3 240 typedef union
AnnaBridge 189:f392fc9709a3 241 {
AnnaBridge 189:f392fc9709a3 242 struct
AnnaBridge 189:f392fc9709a3 243 {
AnnaBridge 189:f392fc9709a3 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 189:f392fc9709a3 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 189:f392fc9709a3 246 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 247 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 248 } IPSR_Type;
AnnaBridge 189:f392fc9709a3 249
AnnaBridge 189:f392fc9709a3 250 /* IPSR Register Definitions */
AnnaBridge 189:f392fc9709a3 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 189:f392fc9709a3 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 189:f392fc9709a3 253
AnnaBridge 189:f392fc9709a3 254
AnnaBridge 189:f392fc9709a3 255 /**
AnnaBridge 189:f392fc9709a3 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 189:f392fc9709a3 257 */
AnnaBridge 189:f392fc9709a3 258 typedef union
AnnaBridge 189:f392fc9709a3 259 {
AnnaBridge 189:f392fc9709a3 260 struct
AnnaBridge 189:f392fc9709a3 261 {
AnnaBridge 189:f392fc9709a3 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 189:f392fc9709a3 263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 189:f392fc9709a3 264 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 189:f392fc9709a3 265 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 189:f392fc9709a3 266 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 189:f392fc9709a3 267 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 189:f392fc9709a3 268 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 189:f392fc9709a3 269 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 189:f392fc9709a3 270 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 271 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 272 } xPSR_Type;
AnnaBridge 189:f392fc9709a3 273
AnnaBridge 189:f392fc9709a3 274 /* xPSR Register Definitions */
AnnaBridge 189:f392fc9709a3 275 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 189:f392fc9709a3 276 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 189:f392fc9709a3 277
AnnaBridge 189:f392fc9709a3 278 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 189:f392fc9709a3 279 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 189:f392fc9709a3 280
AnnaBridge 189:f392fc9709a3 281 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 189:f392fc9709a3 282 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 189:f392fc9709a3 283
AnnaBridge 189:f392fc9709a3 284 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 189:f392fc9709a3 285 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 189:f392fc9709a3 286
AnnaBridge 189:f392fc9709a3 287 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 189:f392fc9709a3 288 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 189:f392fc9709a3 289
AnnaBridge 189:f392fc9709a3 290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 189:f392fc9709a3 291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 189:f392fc9709a3 292
AnnaBridge 189:f392fc9709a3 293
AnnaBridge 189:f392fc9709a3 294 /**
AnnaBridge 189:f392fc9709a3 295 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 189:f392fc9709a3 296 */
AnnaBridge 189:f392fc9709a3 297 typedef union
AnnaBridge 189:f392fc9709a3 298 {
AnnaBridge 189:f392fc9709a3 299 struct
AnnaBridge 189:f392fc9709a3 300 {
AnnaBridge 189:f392fc9709a3 301 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 189:f392fc9709a3 302 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 189:f392fc9709a3 303 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 189:f392fc9709a3 304 } b; /*!< Structure used for bit access */
AnnaBridge 189:f392fc9709a3 305 uint32_t w; /*!< Type used for word access */
AnnaBridge 189:f392fc9709a3 306 } CONTROL_Type;
AnnaBridge 189:f392fc9709a3 307
AnnaBridge 189:f392fc9709a3 308 /* CONTROL Register Definitions */
AnnaBridge 189:f392fc9709a3 309 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 189:f392fc9709a3 310 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 189:f392fc9709a3 311
AnnaBridge 189:f392fc9709a3 312 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 189:f392fc9709a3 313 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 189:f392fc9709a3 314
AnnaBridge 189:f392fc9709a3 315 /*@} end of group CMSIS_CORE */
AnnaBridge 189:f392fc9709a3 316
AnnaBridge 189:f392fc9709a3 317
AnnaBridge 189:f392fc9709a3 318 /**
AnnaBridge 189:f392fc9709a3 319 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 320 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 189:f392fc9709a3 321 \brief Type definitions for the NVIC Registers
AnnaBridge 189:f392fc9709a3 322 @{
AnnaBridge 189:f392fc9709a3 323 */
AnnaBridge 189:f392fc9709a3 324
AnnaBridge 189:f392fc9709a3 325 /**
AnnaBridge 189:f392fc9709a3 326 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 189:f392fc9709a3 327 */
AnnaBridge 189:f392fc9709a3 328 typedef struct
AnnaBridge 189:f392fc9709a3 329 {
AnnaBridge 189:f392fc9709a3 330 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 189:f392fc9709a3 331 uint32_t RESERVED0[31U];
AnnaBridge 189:f392fc9709a3 332 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 189:f392fc9709a3 333 uint32_t RSERVED1[31U];
AnnaBridge 189:f392fc9709a3 334 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 189:f392fc9709a3 335 uint32_t RESERVED2[31U];
AnnaBridge 189:f392fc9709a3 336 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 189:f392fc9709a3 337 uint32_t RESERVED3[31U];
AnnaBridge 189:f392fc9709a3 338 uint32_t RESERVED4[64U];
AnnaBridge 189:f392fc9709a3 339 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 189:f392fc9709a3 340 } NVIC_Type;
AnnaBridge 189:f392fc9709a3 341
AnnaBridge 189:f392fc9709a3 342 /*@} end of group CMSIS_NVIC */
AnnaBridge 189:f392fc9709a3 343
AnnaBridge 189:f392fc9709a3 344
AnnaBridge 189:f392fc9709a3 345 /**
AnnaBridge 189:f392fc9709a3 346 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 347 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 189:f392fc9709a3 348 \brief Type definitions for the System Control Block Registers
AnnaBridge 189:f392fc9709a3 349 @{
AnnaBridge 189:f392fc9709a3 350 */
AnnaBridge 189:f392fc9709a3 351
AnnaBridge 189:f392fc9709a3 352 /**
AnnaBridge 189:f392fc9709a3 353 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 189:f392fc9709a3 354 */
AnnaBridge 189:f392fc9709a3 355 typedef struct
AnnaBridge 189:f392fc9709a3 356 {
AnnaBridge 189:f392fc9709a3 357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 189:f392fc9709a3 358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 189:f392fc9709a3 359 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 360 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 189:f392fc9709a3 361 #else
AnnaBridge 189:f392fc9709a3 362 uint32_t RESERVED0;
AnnaBridge 189:f392fc9709a3 363 #endif
AnnaBridge 189:f392fc9709a3 364 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 189:f392fc9709a3 365 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 189:f392fc9709a3 366 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 189:f392fc9709a3 367 uint32_t RESERVED1;
AnnaBridge 189:f392fc9709a3 368 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 189:f392fc9709a3 369 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 189:f392fc9709a3 370 } SCB_Type;
AnnaBridge 189:f392fc9709a3 371
AnnaBridge 189:f392fc9709a3 372 /* SCB CPUID Register Definitions */
AnnaBridge 189:f392fc9709a3 373 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 189:f392fc9709a3 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 189:f392fc9709a3 375
AnnaBridge 189:f392fc9709a3 376 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 189:f392fc9709a3 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 189:f392fc9709a3 378
AnnaBridge 189:f392fc9709a3 379 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 189:f392fc9709a3 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 189:f392fc9709a3 381
AnnaBridge 189:f392fc9709a3 382 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 189:f392fc9709a3 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 189:f392fc9709a3 384
AnnaBridge 189:f392fc9709a3 385 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 189:f392fc9709a3 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 189:f392fc9709a3 387
AnnaBridge 189:f392fc9709a3 388 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 189:f392fc9709a3 389 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 189:f392fc9709a3 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 189:f392fc9709a3 391
AnnaBridge 189:f392fc9709a3 392 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 189:f392fc9709a3 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 189:f392fc9709a3 394
AnnaBridge 189:f392fc9709a3 395 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 189:f392fc9709a3 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 189:f392fc9709a3 397
AnnaBridge 189:f392fc9709a3 398 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 189:f392fc9709a3 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 189:f392fc9709a3 400
AnnaBridge 189:f392fc9709a3 401 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 189:f392fc9709a3 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 189:f392fc9709a3 403
AnnaBridge 189:f392fc9709a3 404 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 189:f392fc9709a3 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 189:f392fc9709a3 406
AnnaBridge 189:f392fc9709a3 407 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 189:f392fc9709a3 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 189:f392fc9709a3 409
AnnaBridge 189:f392fc9709a3 410 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 189:f392fc9709a3 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 189:f392fc9709a3 412
AnnaBridge 189:f392fc9709a3 413 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 189:f392fc9709a3 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 189:f392fc9709a3 415
AnnaBridge 189:f392fc9709a3 416 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 417 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 189:f392fc9709a3 418 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 189:f392fc9709a3 419 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 189:f392fc9709a3 420 #endif
AnnaBridge 189:f392fc9709a3 421
AnnaBridge 189:f392fc9709a3 422 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 189:f392fc9709a3 423 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 189:f392fc9709a3 424 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 189:f392fc9709a3 425
AnnaBridge 189:f392fc9709a3 426 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 189:f392fc9709a3 427 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 189:f392fc9709a3 428
AnnaBridge 189:f392fc9709a3 429 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 189:f392fc9709a3 430 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 189:f392fc9709a3 431
AnnaBridge 189:f392fc9709a3 432 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 189:f392fc9709a3 433 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 189:f392fc9709a3 434
AnnaBridge 189:f392fc9709a3 435 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 189:f392fc9709a3 436 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 189:f392fc9709a3 437
AnnaBridge 189:f392fc9709a3 438 /* SCB System Control Register Definitions */
AnnaBridge 189:f392fc9709a3 439 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 189:f392fc9709a3 440 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 189:f392fc9709a3 441
AnnaBridge 189:f392fc9709a3 442 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 189:f392fc9709a3 443 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 189:f392fc9709a3 444
AnnaBridge 189:f392fc9709a3 445 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 189:f392fc9709a3 446 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 189:f392fc9709a3 447
AnnaBridge 189:f392fc9709a3 448 /* SCB Configuration Control Register Definitions */
AnnaBridge 189:f392fc9709a3 449 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 189:f392fc9709a3 450 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 189:f392fc9709a3 451
AnnaBridge 189:f392fc9709a3 452 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 189:f392fc9709a3 453 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 189:f392fc9709a3 454
AnnaBridge 189:f392fc9709a3 455 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 189:f392fc9709a3 456 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 189:f392fc9709a3 457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 189:f392fc9709a3 458
AnnaBridge 189:f392fc9709a3 459 /*@} end of group CMSIS_SCB */
AnnaBridge 189:f392fc9709a3 460
AnnaBridge 189:f392fc9709a3 461
AnnaBridge 189:f392fc9709a3 462 /**
AnnaBridge 189:f392fc9709a3 463 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 464 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 189:f392fc9709a3 465 \brief Type definitions for the System Timer Registers.
AnnaBridge 189:f392fc9709a3 466 @{
AnnaBridge 189:f392fc9709a3 467 */
AnnaBridge 189:f392fc9709a3 468
AnnaBridge 189:f392fc9709a3 469 /**
AnnaBridge 189:f392fc9709a3 470 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 189:f392fc9709a3 471 */
AnnaBridge 189:f392fc9709a3 472 typedef struct
AnnaBridge 189:f392fc9709a3 473 {
AnnaBridge 189:f392fc9709a3 474 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 189:f392fc9709a3 475 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 189:f392fc9709a3 476 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 189:f392fc9709a3 477 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 189:f392fc9709a3 478 } SysTick_Type;
AnnaBridge 189:f392fc9709a3 479
AnnaBridge 189:f392fc9709a3 480 /* SysTick Control / Status Register Definitions */
AnnaBridge 189:f392fc9709a3 481 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 189:f392fc9709a3 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 189:f392fc9709a3 483
AnnaBridge 189:f392fc9709a3 484 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 189:f392fc9709a3 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 189:f392fc9709a3 486
AnnaBridge 189:f392fc9709a3 487 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 189:f392fc9709a3 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 189:f392fc9709a3 489
AnnaBridge 189:f392fc9709a3 490 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 189:f392fc9709a3 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 189:f392fc9709a3 492
AnnaBridge 189:f392fc9709a3 493 /* SysTick Reload Register Definitions */
AnnaBridge 189:f392fc9709a3 494 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 189:f392fc9709a3 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 189:f392fc9709a3 496
AnnaBridge 189:f392fc9709a3 497 /* SysTick Current Register Definitions */
AnnaBridge 189:f392fc9709a3 498 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 189:f392fc9709a3 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 189:f392fc9709a3 500
AnnaBridge 189:f392fc9709a3 501 /* SysTick Calibration Register Definitions */
AnnaBridge 189:f392fc9709a3 502 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 189:f392fc9709a3 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 189:f392fc9709a3 504
AnnaBridge 189:f392fc9709a3 505 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 189:f392fc9709a3 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 189:f392fc9709a3 507
AnnaBridge 189:f392fc9709a3 508 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 189:f392fc9709a3 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 189:f392fc9709a3 510
AnnaBridge 189:f392fc9709a3 511 /*@} end of group CMSIS_SysTick */
AnnaBridge 189:f392fc9709a3 512
AnnaBridge 189:f392fc9709a3 513 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 514 /**
AnnaBridge 189:f392fc9709a3 515 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 516 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 189:f392fc9709a3 517 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 189:f392fc9709a3 518 @{
AnnaBridge 189:f392fc9709a3 519 */
AnnaBridge 189:f392fc9709a3 520
AnnaBridge 189:f392fc9709a3 521 /**
AnnaBridge 189:f392fc9709a3 522 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 189:f392fc9709a3 523 */
AnnaBridge 189:f392fc9709a3 524 typedef struct
AnnaBridge 189:f392fc9709a3 525 {
AnnaBridge 189:f392fc9709a3 526 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 189:f392fc9709a3 527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 189:f392fc9709a3 528 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 189:f392fc9709a3 529 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 189:f392fc9709a3 530 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 189:f392fc9709a3 531 } MPU_Type;
AnnaBridge 189:f392fc9709a3 532
AnnaBridge 189:f392fc9709a3 533 #define MPU_TYPE_RALIASES 1U
AnnaBridge 189:f392fc9709a3 534
AnnaBridge 189:f392fc9709a3 535 /* MPU Type Register Definitions */
AnnaBridge 189:f392fc9709a3 536 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 189:f392fc9709a3 537 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 189:f392fc9709a3 538
AnnaBridge 189:f392fc9709a3 539 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 189:f392fc9709a3 540 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 189:f392fc9709a3 541
AnnaBridge 189:f392fc9709a3 542 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 189:f392fc9709a3 543 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 189:f392fc9709a3 544
AnnaBridge 189:f392fc9709a3 545 /* MPU Control Register Definitions */
AnnaBridge 189:f392fc9709a3 546 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 189:f392fc9709a3 547 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 189:f392fc9709a3 548
AnnaBridge 189:f392fc9709a3 549 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 189:f392fc9709a3 550 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 189:f392fc9709a3 551
AnnaBridge 189:f392fc9709a3 552 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 189:f392fc9709a3 553 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 189:f392fc9709a3 554
AnnaBridge 189:f392fc9709a3 555 /* MPU Region Number Register Definitions */
AnnaBridge 189:f392fc9709a3 556 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 189:f392fc9709a3 557 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 189:f392fc9709a3 558
AnnaBridge 189:f392fc9709a3 559 /* MPU Region Base Address Register Definitions */
AnnaBridge 189:f392fc9709a3 560 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
AnnaBridge 189:f392fc9709a3 561 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 189:f392fc9709a3 562
AnnaBridge 189:f392fc9709a3 563 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 189:f392fc9709a3 564 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 189:f392fc9709a3 565
AnnaBridge 189:f392fc9709a3 566 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 189:f392fc9709a3 567 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 189:f392fc9709a3 568
AnnaBridge 189:f392fc9709a3 569 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 189:f392fc9709a3 570 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 189:f392fc9709a3 571 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 189:f392fc9709a3 572
AnnaBridge 189:f392fc9709a3 573 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 189:f392fc9709a3 574 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 189:f392fc9709a3 575
AnnaBridge 189:f392fc9709a3 576 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 189:f392fc9709a3 577 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 189:f392fc9709a3 578
AnnaBridge 189:f392fc9709a3 579 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 189:f392fc9709a3 580 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 189:f392fc9709a3 581
AnnaBridge 189:f392fc9709a3 582 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 189:f392fc9709a3 583 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 189:f392fc9709a3 584
AnnaBridge 189:f392fc9709a3 585 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 189:f392fc9709a3 586 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 189:f392fc9709a3 587
AnnaBridge 189:f392fc9709a3 588 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 189:f392fc9709a3 589 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 189:f392fc9709a3 590
AnnaBridge 189:f392fc9709a3 591 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 189:f392fc9709a3 592 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 189:f392fc9709a3 593
AnnaBridge 189:f392fc9709a3 594 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 189:f392fc9709a3 595 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 189:f392fc9709a3 596
AnnaBridge 189:f392fc9709a3 597 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 189:f392fc9709a3 598 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 189:f392fc9709a3 599
AnnaBridge 189:f392fc9709a3 600 /*@} end of group CMSIS_MPU */
AnnaBridge 189:f392fc9709a3 601 #endif
AnnaBridge 189:f392fc9709a3 602
AnnaBridge 189:f392fc9709a3 603
AnnaBridge 189:f392fc9709a3 604 /**
AnnaBridge 189:f392fc9709a3 605 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 606 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 189:f392fc9709a3 607 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 189:f392fc9709a3 608 Therefore they are not covered by the Cortex-M0+ header file.
AnnaBridge 189:f392fc9709a3 609 @{
AnnaBridge 189:f392fc9709a3 610 */
AnnaBridge 189:f392fc9709a3 611 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 189:f392fc9709a3 612
AnnaBridge 189:f392fc9709a3 613
AnnaBridge 189:f392fc9709a3 614 /**
AnnaBridge 189:f392fc9709a3 615 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 616 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 189:f392fc9709a3 617 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 189:f392fc9709a3 618 @{
AnnaBridge 189:f392fc9709a3 619 */
AnnaBridge 189:f392fc9709a3 620
AnnaBridge 189:f392fc9709a3 621 /**
AnnaBridge 189:f392fc9709a3 622 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 189:f392fc9709a3 623 \param[in] field Name of the register bit field.
AnnaBridge 189:f392fc9709a3 624 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 189:f392fc9709a3 625 \return Masked and shifted value.
AnnaBridge 189:f392fc9709a3 626 */
AnnaBridge 189:f392fc9709a3 627 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 189:f392fc9709a3 628
AnnaBridge 189:f392fc9709a3 629 /**
AnnaBridge 189:f392fc9709a3 630 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 189:f392fc9709a3 631 \param[in] field Name of the register bit field.
AnnaBridge 189:f392fc9709a3 632 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 189:f392fc9709a3 633 \return Masked and shifted bit field value.
AnnaBridge 189:f392fc9709a3 634 */
AnnaBridge 189:f392fc9709a3 635 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 189:f392fc9709a3 636
AnnaBridge 189:f392fc9709a3 637 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 189:f392fc9709a3 638
AnnaBridge 189:f392fc9709a3 639
AnnaBridge 189:f392fc9709a3 640 /**
AnnaBridge 189:f392fc9709a3 641 \ingroup CMSIS_core_register
AnnaBridge 189:f392fc9709a3 642 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 189:f392fc9709a3 643 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 189:f392fc9709a3 644 @{
AnnaBridge 189:f392fc9709a3 645 */
AnnaBridge 189:f392fc9709a3 646
AnnaBridge 189:f392fc9709a3 647 /* Memory mapping of Core Hardware */
AnnaBridge 189:f392fc9709a3 648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 189:f392fc9709a3 649 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 189:f392fc9709a3 650 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 189:f392fc9709a3 651 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 189:f392fc9709a3 652
AnnaBridge 189:f392fc9709a3 653 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 189:f392fc9709a3 654 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 189:f392fc9709a3 655 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 189:f392fc9709a3 656
AnnaBridge 189:f392fc9709a3 657 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 658 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 189:f392fc9709a3 659 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 189:f392fc9709a3 660 #endif
AnnaBridge 189:f392fc9709a3 661
AnnaBridge 189:f392fc9709a3 662 /*@} */
AnnaBridge 189:f392fc9709a3 663
AnnaBridge 189:f392fc9709a3 664
AnnaBridge 189:f392fc9709a3 665
AnnaBridge 189:f392fc9709a3 666 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 667 * Hardware Abstraction Layer
AnnaBridge 189:f392fc9709a3 668 Core Function Interface contains:
AnnaBridge 189:f392fc9709a3 669 - Core NVIC Functions
AnnaBridge 189:f392fc9709a3 670 - Core SysTick Functions
AnnaBridge 189:f392fc9709a3 671 - Core Register Access Functions
AnnaBridge 189:f392fc9709a3 672 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 673 /**
AnnaBridge 189:f392fc9709a3 674 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 189:f392fc9709a3 675 */
AnnaBridge 189:f392fc9709a3 676
AnnaBridge 189:f392fc9709a3 677
AnnaBridge 189:f392fc9709a3 678
AnnaBridge 189:f392fc9709a3 679 /* ########################## NVIC functions #################################### */
AnnaBridge 189:f392fc9709a3 680 /**
AnnaBridge 189:f392fc9709a3 681 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 189:f392fc9709a3 682 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 189:f392fc9709a3 683 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 189:f392fc9709a3 684 @{
AnnaBridge 189:f392fc9709a3 685 */
AnnaBridge 189:f392fc9709a3 686
AnnaBridge 189:f392fc9709a3 687 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 189:f392fc9709a3 688 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 689 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 189:f392fc9709a3 690 #endif
AnnaBridge 189:f392fc9709a3 691 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 692 #else
AnnaBridge 189:f392fc9709a3 693 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 189:f392fc9709a3 694 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge 189:f392fc9709a3 695 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 189:f392fc9709a3 696 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 189:f392fc9709a3 697 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 189:f392fc9709a3 698 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 189:f392fc9709a3 699 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 189:f392fc9709a3 700 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 189:f392fc9709a3 701 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
AnnaBridge 189:f392fc9709a3 702 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 189:f392fc9709a3 703 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 189:f392fc9709a3 704 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 189:f392fc9709a3 705 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 189:f392fc9709a3 706
AnnaBridge 189:f392fc9709a3 707 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 189:f392fc9709a3 708 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 709 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 189:f392fc9709a3 710 #endif
AnnaBridge 189:f392fc9709a3 711 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 189:f392fc9709a3 712 #else
AnnaBridge 189:f392fc9709a3 713 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 189:f392fc9709a3 714 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 189:f392fc9709a3 715 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 189:f392fc9709a3 716
AnnaBridge 189:f392fc9709a3 717 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 189:f392fc9709a3 718
AnnaBridge 189:f392fc9709a3 719
AnnaBridge 189:f392fc9709a3 720 /* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge 189:f392fc9709a3 721 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge 189:f392fc9709a3 722 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge 189:f392fc9709a3 723 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge 189:f392fc9709a3 724
AnnaBridge 189:f392fc9709a3 725
AnnaBridge 189:f392fc9709a3 726 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 189:f392fc9709a3 727 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 189:f392fc9709a3 728 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 189:f392fc9709a3 729 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 189:f392fc9709a3 730 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 189:f392fc9709a3 731
AnnaBridge 189:f392fc9709a3 732 #define __NVIC_SetPriorityGrouping(X) (void)(X)
AnnaBridge 189:f392fc9709a3 733 #define __NVIC_GetPriorityGrouping() (0U)
AnnaBridge 189:f392fc9709a3 734
AnnaBridge 189:f392fc9709a3 735 /**
AnnaBridge 189:f392fc9709a3 736 \brief Enable Interrupt
AnnaBridge 189:f392fc9709a3 737 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 189:f392fc9709a3 738 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 739 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 740 */
AnnaBridge 189:f392fc9709a3 741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 742 {
AnnaBridge 189:f392fc9709a3 743 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 744 {
AnnaBridge 189:f392fc9709a3 745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 746 }
AnnaBridge 189:f392fc9709a3 747 }
AnnaBridge 189:f392fc9709a3 748
AnnaBridge 189:f392fc9709a3 749
AnnaBridge 189:f392fc9709a3 750 /**
AnnaBridge 189:f392fc9709a3 751 \brief Get Interrupt Enable status
AnnaBridge 189:f392fc9709a3 752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 189:f392fc9709a3 753 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 754 \return 0 Interrupt is not enabled.
AnnaBridge 189:f392fc9709a3 755 \return 1 Interrupt is enabled.
AnnaBridge 189:f392fc9709a3 756 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 757 */
AnnaBridge 189:f392fc9709a3 758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 759 {
AnnaBridge 189:f392fc9709a3 760 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 761 {
AnnaBridge 189:f392fc9709a3 762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 763 }
AnnaBridge 189:f392fc9709a3 764 else
AnnaBridge 189:f392fc9709a3 765 {
AnnaBridge 189:f392fc9709a3 766 return(0U);
AnnaBridge 189:f392fc9709a3 767 }
AnnaBridge 189:f392fc9709a3 768 }
AnnaBridge 189:f392fc9709a3 769
AnnaBridge 189:f392fc9709a3 770
AnnaBridge 189:f392fc9709a3 771 /**
AnnaBridge 189:f392fc9709a3 772 \brief Disable Interrupt
AnnaBridge 189:f392fc9709a3 773 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 189:f392fc9709a3 774 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 775 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 776 */
AnnaBridge 189:f392fc9709a3 777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 778 {
AnnaBridge 189:f392fc9709a3 779 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 780 {
AnnaBridge 189:f392fc9709a3 781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 782 __DSB();
AnnaBridge 189:f392fc9709a3 783 __ISB();
AnnaBridge 189:f392fc9709a3 784 }
AnnaBridge 189:f392fc9709a3 785 }
AnnaBridge 189:f392fc9709a3 786
AnnaBridge 189:f392fc9709a3 787
AnnaBridge 189:f392fc9709a3 788 /**
AnnaBridge 189:f392fc9709a3 789 \brief Get Pending Interrupt
AnnaBridge 189:f392fc9709a3 790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 189:f392fc9709a3 791 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 792 \return 0 Interrupt status is not pending.
AnnaBridge 189:f392fc9709a3 793 \return 1 Interrupt status is pending.
AnnaBridge 189:f392fc9709a3 794 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 795 */
AnnaBridge 189:f392fc9709a3 796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 797 {
AnnaBridge 189:f392fc9709a3 798 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 799 {
AnnaBridge 189:f392fc9709a3 800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 189:f392fc9709a3 801 }
AnnaBridge 189:f392fc9709a3 802 else
AnnaBridge 189:f392fc9709a3 803 {
AnnaBridge 189:f392fc9709a3 804 return(0U);
AnnaBridge 189:f392fc9709a3 805 }
AnnaBridge 189:f392fc9709a3 806 }
AnnaBridge 189:f392fc9709a3 807
AnnaBridge 189:f392fc9709a3 808
AnnaBridge 189:f392fc9709a3 809 /**
AnnaBridge 189:f392fc9709a3 810 \brief Set Pending Interrupt
AnnaBridge 189:f392fc9709a3 811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 189:f392fc9709a3 812 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 813 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 814 */
AnnaBridge 189:f392fc9709a3 815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 816 {
AnnaBridge 189:f392fc9709a3 817 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 818 {
AnnaBridge 189:f392fc9709a3 819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 820 }
AnnaBridge 189:f392fc9709a3 821 }
AnnaBridge 189:f392fc9709a3 822
AnnaBridge 189:f392fc9709a3 823
AnnaBridge 189:f392fc9709a3 824 /**
AnnaBridge 189:f392fc9709a3 825 \brief Clear Pending Interrupt
AnnaBridge 189:f392fc9709a3 826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 189:f392fc9709a3 827 \param [in] IRQn Device specific interrupt number.
AnnaBridge 189:f392fc9709a3 828 \note IRQn must not be negative.
AnnaBridge 189:f392fc9709a3 829 */
AnnaBridge 189:f392fc9709a3 830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 831 {
AnnaBridge 189:f392fc9709a3 832 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 833 {
AnnaBridge 189:f392fc9709a3 834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 189:f392fc9709a3 835 }
AnnaBridge 189:f392fc9709a3 836 }
AnnaBridge 189:f392fc9709a3 837
AnnaBridge 189:f392fc9709a3 838
AnnaBridge 189:f392fc9709a3 839 /**
AnnaBridge 189:f392fc9709a3 840 \brief Set Interrupt Priority
AnnaBridge 189:f392fc9709a3 841 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 189:f392fc9709a3 842 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 843 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 844 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 845 \param [in] priority Priority to set.
AnnaBridge 189:f392fc9709a3 846 \note The priority cannot be set for every processor exception.
AnnaBridge 189:f392fc9709a3 847 */
AnnaBridge 189:f392fc9709a3 848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 189:f392fc9709a3 849 {
AnnaBridge 189:f392fc9709a3 850 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 851 {
AnnaBridge 189:f392fc9709a3 852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 189:f392fc9709a3 853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 189:f392fc9709a3 854 }
AnnaBridge 189:f392fc9709a3 855 else
AnnaBridge 189:f392fc9709a3 856 {
AnnaBridge 189:f392fc9709a3 857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 189:f392fc9709a3 858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 189:f392fc9709a3 859 }
AnnaBridge 189:f392fc9709a3 860 }
AnnaBridge 189:f392fc9709a3 861
AnnaBridge 189:f392fc9709a3 862
AnnaBridge 189:f392fc9709a3 863 /**
AnnaBridge 189:f392fc9709a3 864 \brief Get Interrupt Priority
AnnaBridge 189:f392fc9709a3 865 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 189:f392fc9709a3 866 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 867 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 868 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 869 \return Interrupt Priority.
AnnaBridge 189:f392fc9709a3 870 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 189:f392fc9709a3 871 */
AnnaBridge 189:f392fc9709a3 872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 873 {
AnnaBridge 189:f392fc9709a3 874
AnnaBridge 189:f392fc9709a3 875 if ((int32_t)(IRQn) >= 0)
AnnaBridge 189:f392fc9709a3 876 {
AnnaBridge 189:f392fc9709a3 877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 189:f392fc9709a3 878 }
AnnaBridge 189:f392fc9709a3 879 else
AnnaBridge 189:f392fc9709a3 880 {
AnnaBridge 189:f392fc9709a3 881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 189:f392fc9709a3 882 }
AnnaBridge 189:f392fc9709a3 883 }
AnnaBridge 189:f392fc9709a3 884
AnnaBridge 189:f392fc9709a3 885
AnnaBridge 189:f392fc9709a3 886 /**
AnnaBridge 189:f392fc9709a3 887 \brief Encode Priority
AnnaBridge 189:f392fc9709a3 888 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 189:f392fc9709a3 889 preemptive priority value, and subpriority value.
AnnaBridge 189:f392fc9709a3 890 In case of a conflict between priority grouping and available
AnnaBridge 189:f392fc9709a3 891 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 189:f392fc9709a3 892 \param [in] PriorityGroup Used priority group.
AnnaBridge 189:f392fc9709a3 893 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 189:f392fc9709a3 894 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 189:f392fc9709a3 895 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 189:f392fc9709a3 896 */
AnnaBridge 189:f392fc9709a3 897 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 189:f392fc9709a3 898 {
AnnaBridge 189:f392fc9709a3 899 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 189:f392fc9709a3 900 uint32_t PreemptPriorityBits;
AnnaBridge 189:f392fc9709a3 901 uint32_t SubPriorityBits;
AnnaBridge 189:f392fc9709a3 902
AnnaBridge 189:f392fc9709a3 903 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 189:f392fc9709a3 904 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 189:f392fc9709a3 905
AnnaBridge 189:f392fc9709a3 906 return (
AnnaBridge 189:f392fc9709a3 907 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 189:f392fc9709a3 908 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 189:f392fc9709a3 909 );
AnnaBridge 189:f392fc9709a3 910 }
AnnaBridge 189:f392fc9709a3 911
AnnaBridge 189:f392fc9709a3 912
AnnaBridge 189:f392fc9709a3 913 /**
AnnaBridge 189:f392fc9709a3 914 \brief Decode Priority
AnnaBridge 189:f392fc9709a3 915 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 189:f392fc9709a3 916 preemptive priority value and subpriority value.
AnnaBridge 189:f392fc9709a3 917 In case of a conflict between priority grouping and available
AnnaBridge 189:f392fc9709a3 918 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 189:f392fc9709a3 919 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 189:f392fc9709a3 920 \param [in] PriorityGroup Used priority group.
AnnaBridge 189:f392fc9709a3 921 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 189:f392fc9709a3 922 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 189:f392fc9709a3 923 */
AnnaBridge 189:f392fc9709a3 924 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 189:f392fc9709a3 925 {
AnnaBridge 189:f392fc9709a3 926 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 189:f392fc9709a3 927 uint32_t PreemptPriorityBits;
AnnaBridge 189:f392fc9709a3 928 uint32_t SubPriorityBits;
AnnaBridge 189:f392fc9709a3 929
AnnaBridge 189:f392fc9709a3 930 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 189:f392fc9709a3 931 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 189:f392fc9709a3 932
AnnaBridge 189:f392fc9709a3 933 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 189:f392fc9709a3 934 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 189:f392fc9709a3 935 }
AnnaBridge 189:f392fc9709a3 936
AnnaBridge 189:f392fc9709a3 937
AnnaBridge 189:f392fc9709a3 938 /**
AnnaBridge 189:f392fc9709a3 939 \brief Set Interrupt Vector
AnnaBridge 189:f392fc9709a3 940 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 189:f392fc9709a3 941 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 942 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 943 VTOR must been relocated to SRAM before.
AnnaBridge 189:f392fc9709a3 944 If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge 189:f392fc9709a3 945 \param [in] IRQn Interrupt number
AnnaBridge 189:f392fc9709a3 946 \param [in] vector Address of interrupt handler function
AnnaBridge 189:f392fc9709a3 947 */
AnnaBridge 189:f392fc9709a3 948 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 189:f392fc9709a3 949 {
AnnaBridge 189:f392fc9709a3 950 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 951 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 189:f392fc9709a3 952 #else
AnnaBridge 189:f392fc9709a3 953 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 189:f392fc9709a3 954 #endif
AnnaBridge 189:f392fc9709a3 955 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 189:f392fc9709a3 956 }
AnnaBridge 189:f392fc9709a3 957
AnnaBridge 189:f392fc9709a3 958
AnnaBridge 189:f392fc9709a3 959 /**
AnnaBridge 189:f392fc9709a3 960 \brief Get Interrupt Vector
AnnaBridge 189:f392fc9709a3 961 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 189:f392fc9709a3 962 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 189:f392fc9709a3 963 or negative to specify a processor exception.
AnnaBridge 189:f392fc9709a3 964 \param [in] IRQn Interrupt number.
AnnaBridge 189:f392fc9709a3 965 \return Address of interrupt handler function
AnnaBridge 189:f392fc9709a3 966 */
AnnaBridge 189:f392fc9709a3 967 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 189:f392fc9709a3 968 {
AnnaBridge 189:f392fc9709a3 969 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 970 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 189:f392fc9709a3 971 #else
AnnaBridge 189:f392fc9709a3 972 uint32_t *vectors = (uint32_t *)0x0U;
AnnaBridge 189:f392fc9709a3 973 #endif
AnnaBridge 189:f392fc9709a3 974 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 189:f392fc9709a3 975
AnnaBridge 189:f392fc9709a3 976 }
AnnaBridge 189:f392fc9709a3 977
AnnaBridge 189:f392fc9709a3 978
AnnaBridge 189:f392fc9709a3 979 /**
AnnaBridge 189:f392fc9709a3 980 \brief System Reset
AnnaBridge 189:f392fc9709a3 981 \details Initiates a system reset request to reset the MCU.
AnnaBridge 189:f392fc9709a3 982 */
AnnaBridge 189:f392fc9709a3 983 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 189:f392fc9709a3 984 {
AnnaBridge 189:f392fc9709a3 985 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 189:f392fc9709a3 986 buffered write are completed before reset */
AnnaBridge 189:f392fc9709a3 987 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 189:f392fc9709a3 988 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 189:f392fc9709a3 989 __DSB(); /* Ensure completion of memory access */
AnnaBridge 189:f392fc9709a3 990
AnnaBridge 189:f392fc9709a3 991 for(;;) /* wait until reset */
AnnaBridge 189:f392fc9709a3 992 {
AnnaBridge 189:f392fc9709a3 993 __NOP();
AnnaBridge 189:f392fc9709a3 994 }
AnnaBridge 189:f392fc9709a3 995 }
AnnaBridge 189:f392fc9709a3 996
AnnaBridge 189:f392fc9709a3 997 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 189:f392fc9709a3 998
AnnaBridge 189:f392fc9709a3 999 /* ########################## MPU functions #################################### */
AnnaBridge 189:f392fc9709a3 1000
AnnaBridge 189:f392fc9709a3 1001 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 189:f392fc9709a3 1002
AnnaBridge 189:f392fc9709a3 1003 #include "mpu_armv7.h"
AnnaBridge 189:f392fc9709a3 1004
AnnaBridge 189:f392fc9709a3 1005 #endif
AnnaBridge 189:f392fc9709a3 1006
AnnaBridge 189:f392fc9709a3 1007 /* ########################## FPU functions #################################### */
AnnaBridge 189:f392fc9709a3 1008 /**
AnnaBridge 189:f392fc9709a3 1009 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 189:f392fc9709a3 1010 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 189:f392fc9709a3 1011 \brief Function that provides FPU type.
AnnaBridge 189:f392fc9709a3 1012 @{
AnnaBridge 189:f392fc9709a3 1013 */
AnnaBridge 189:f392fc9709a3 1014
AnnaBridge 189:f392fc9709a3 1015 /**
AnnaBridge 189:f392fc9709a3 1016 \brief get FPU type
AnnaBridge 189:f392fc9709a3 1017 \details returns the FPU type
AnnaBridge 189:f392fc9709a3 1018 \returns
AnnaBridge 189:f392fc9709a3 1019 - \b 0: No FPU
AnnaBridge 189:f392fc9709a3 1020 - \b 1: Single precision FPU
AnnaBridge 189:f392fc9709a3 1021 - \b 2: Double + Single precision FPU
AnnaBridge 189:f392fc9709a3 1022 */
AnnaBridge 189:f392fc9709a3 1023 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 189:f392fc9709a3 1024 {
AnnaBridge 189:f392fc9709a3 1025 return 0U; /* No FPU */
AnnaBridge 189:f392fc9709a3 1026 }
AnnaBridge 189:f392fc9709a3 1027
AnnaBridge 189:f392fc9709a3 1028
AnnaBridge 189:f392fc9709a3 1029 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 189:f392fc9709a3 1030
AnnaBridge 189:f392fc9709a3 1031
AnnaBridge 189:f392fc9709a3 1032
AnnaBridge 189:f392fc9709a3 1033 /* ################################## SysTick function ############################################ */
AnnaBridge 189:f392fc9709a3 1034 /**
AnnaBridge 189:f392fc9709a3 1035 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 189:f392fc9709a3 1036 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 189:f392fc9709a3 1037 \brief Functions that configure the System.
AnnaBridge 189:f392fc9709a3 1038 @{
AnnaBridge 189:f392fc9709a3 1039 */
AnnaBridge 189:f392fc9709a3 1040
AnnaBridge 189:f392fc9709a3 1041 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 189:f392fc9709a3 1042
AnnaBridge 189:f392fc9709a3 1043 /**
AnnaBridge 189:f392fc9709a3 1044 \brief System Tick Configuration
AnnaBridge 189:f392fc9709a3 1045 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 189:f392fc9709a3 1046 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 189:f392fc9709a3 1047 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 189:f392fc9709a3 1048 \return 0 Function succeeded.
AnnaBridge 189:f392fc9709a3 1049 \return 1 Function failed.
AnnaBridge 189:f392fc9709a3 1050 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 189:f392fc9709a3 1051 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 189:f392fc9709a3 1052 must contain a vendor-specific implementation of this function.
AnnaBridge 189:f392fc9709a3 1053 */
AnnaBridge 189:f392fc9709a3 1054 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 189:f392fc9709a3 1055 {
AnnaBridge 189:f392fc9709a3 1056 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 189:f392fc9709a3 1057 {
AnnaBridge 189:f392fc9709a3 1058 return (1UL); /* Reload value impossible */
AnnaBridge 189:f392fc9709a3 1059 }
AnnaBridge 189:f392fc9709a3 1060
AnnaBridge 189:f392fc9709a3 1061 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 189:f392fc9709a3 1062 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 189:f392fc9709a3 1063 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 189:f392fc9709a3 1064 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 189:f392fc9709a3 1065 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 189:f392fc9709a3 1066 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 189:f392fc9709a3 1067 return (0UL); /* Function successful */
AnnaBridge 189:f392fc9709a3 1068 }
AnnaBridge 189:f392fc9709a3 1069
AnnaBridge 189:f392fc9709a3 1070 #endif
AnnaBridge 189:f392fc9709a3 1071
AnnaBridge 189:f392fc9709a3 1072 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 189:f392fc9709a3 1073
AnnaBridge 189:f392fc9709a3 1074
AnnaBridge 189:f392fc9709a3 1075
AnnaBridge 189:f392fc9709a3 1076
AnnaBridge 189:f392fc9709a3 1077 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 1078 }
AnnaBridge 189:f392fc9709a3 1079 #endif
AnnaBridge 189:f392fc9709a3 1080
AnnaBridge 189:f392fc9709a3 1081 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
AnnaBridge 189:f392fc9709a3 1082
AnnaBridge 189:f392fc9709a3 1083 #endif /* __CMSIS_GENERIC */