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mbed library sources. Supersedes mbed-src.

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cmsis/BUILD/mbed/TARGET_K82F/TOOLCHAIN_IAR/MK82F25615.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /*
AnnaBridge 189:f392fc9709a3 2 ** ###################################################################
AnnaBridge 189:f392fc9709a3 3 ** Processors: MK82FN256CAx15
AnnaBridge 189:f392fc9709a3 4 ** MK82FN256VDC15
AnnaBridge 189:f392fc9709a3 5 ** MK82FN256VLL15
AnnaBridge 189:f392fc9709a3 6 ** MK82FN256VLQ15
AnnaBridge 189:f392fc9709a3 7 **
AnnaBridge 189:f392fc9709a3 8 ** Compilers: Keil ARM C/C++ Compiler
AnnaBridge 189:f392fc9709a3 9 ** Freescale C/C++ for Embedded ARM
AnnaBridge 189:f392fc9709a3 10 ** GNU C Compiler
AnnaBridge 189:f392fc9709a3 11 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 189:f392fc9709a3 12 **
AnnaBridge 189:f392fc9709a3 13 ** Reference manual: K82P121M150SF5RM, Rev. 0, May 2015
AnnaBridge 189:f392fc9709a3 14 ** Version: rev. 1.2, 2015-07-29
AnnaBridge 189:f392fc9709a3 15 ** Build: b151218
AnnaBridge 189:f392fc9709a3 16 **
AnnaBridge 189:f392fc9709a3 17 ** Abstract:
AnnaBridge 189:f392fc9709a3 18 ** CMSIS Peripheral Access Layer for MK82F25615
AnnaBridge 189:f392fc9709a3 19 **
AnnaBridge 189:f392fc9709a3 20 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
AnnaBridge 189:f392fc9709a3 21 ** All rights reserved.
AnnaBridge 189:f392fc9709a3 22 **
AnnaBridge 189:f392fc9709a3 23 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 24 ** are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 25 **
AnnaBridge 189:f392fc9709a3 26 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 189:f392fc9709a3 27 ** of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 28 **
AnnaBridge 189:f392fc9709a3 29 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 189:f392fc9709a3 30 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 189:f392fc9709a3 31 ** other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 32 **
AnnaBridge 189:f392fc9709a3 33 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 189:f392fc9709a3 34 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 189:f392fc9709a3 35 ** software without specific prior written permission.
AnnaBridge 189:f392fc9709a3 36 **
AnnaBridge 189:f392fc9709a3 37 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 189:f392fc9709a3 38 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 189:f392fc9709a3 39 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 40 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 189:f392fc9709a3 41 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 189:f392fc9709a3 42 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 189:f392fc9709a3 43 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 189:f392fc9709a3 44 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 189:f392fc9709a3 45 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 189:f392fc9709a3 46 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 47 **
AnnaBridge 189:f392fc9709a3 48 ** http: www.freescale.com
AnnaBridge 189:f392fc9709a3 49 ** mail: support@freescale.com
AnnaBridge 189:f392fc9709a3 50 **
AnnaBridge 189:f392fc9709a3 51 ** Revisions:
AnnaBridge 189:f392fc9709a3 52 ** - rev. 1.0 (2015-04-09)
AnnaBridge 189:f392fc9709a3 53 ** Initial version
AnnaBridge 189:f392fc9709a3 54 ** - rev. 1.1 (2015-05-28)
AnnaBridge 189:f392fc9709a3 55 ** Update according to the reference manual Rev. 0.
AnnaBridge 189:f392fc9709a3 56 ** - rev. 1.2 (2015-07-29)
AnnaBridge 189:f392fc9709a3 57 ** Correction of backward compatibility.
AnnaBridge 189:f392fc9709a3 58 **
AnnaBridge 189:f392fc9709a3 59 ** ###################################################################
AnnaBridge 189:f392fc9709a3 60 */
AnnaBridge 189:f392fc9709a3 61
AnnaBridge 189:f392fc9709a3 62 /*!
AnnaBridge 189:f392fc9709a3 63 * @file MK82F25615.h
AnnaBridge 189:f392fc9709a3 64 * @version 1.2
AnnaBridge 189:f392fc9709a3 65 * @date 2015-07-29
AnnaBridge 189:f392fc9709a3 66 * @brief CMSIS Peripheral Access Layer for MK82F25615
AnnaBridge 189:f392fc9709a3 67 *
AnnaBridge 189:f392fc9709a3 68 * CMSIS Peripheral Access Layer for MK82F25615
AnnaBridge 189:f392fc9709a3 69 */
AnnaBridge 189:f392fc9709a3 70
AnnaBridge 189:f392fc9709a3 71 #ifndef _MK82F25615_H_
AnnaBridge 189:f392fc9709a3 72 #define _MK82F25615_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 189:f392fc9709a3 73
AnnaBridge 189:f392fc9709a3 74 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 189:f392fc9709a3 75 * compatible) */
AnnaBridge 189:f392fc9709a3 76 #define MCU_MEM_MAP_VERSION 0x0100U
AnnaBridge 189:f392fc9709a3 77 /** Memory map minor version */
AnnaBridge 189:f392fc9709a3 78 #define MCU_MEM_MAP_VERSION_MINOR 0x0002U
AnnaBridge 189:f392fc9709a3 79
AnnaBridge 189:f392fc9709a3 80 /**
AnnaBridge 189:f392fc9709a3 81 * @brief Macro to calculate address of an aliased word in the peripheral
AnnaBridge 189:f392fc9709a3 82 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
AnnaBridge 189:f392fc9709a3 83 * 0x400FFFFF).
AnnaBridge 189:f392fc9709a3 84 * @param Reg Register to access.
AnnaBridge 189:f392fc9709a3 85 * @param Bit Bit number to access.
AnnaBridge 189:f392fc9709a3 86 * @return Address of the aliased word in the peripheral bitband area.
AnnaBridge 189:f392fc9709a3 87 */
AnnaBridge 189:f392fc9709a3 88 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
AnnaBridge 189:f392fc9709a3 89 /**
AnnaBridge 189:f392fc9709a3 90 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 189:f392fc9709a3 91 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 189:f392fc9709a3 92 * be used for peripherals with 32bit access allowed.
AnnaBridge 189:f392fc9709a3 93 * @param Reg Register to access.
AnnaBridge 189:f392fc9709a3 94 * @param Bit Bit number to access.
AnnaBridge 189:f392fc9709a3 95 * @return Value of the targeted bit in the bit band region.
AnnaBridge 189:f392fc9709a3 96 */
AnnaBridge 189:f392fc9709a3 97 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 189:f392fc9709a3 98 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
AnnaBridge 189:f392fc9709a3 99 /**
AnnaBridge 189:f392fc9709a3 100 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 189:f392fc9709a3 101 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 189:f392fc9709a3 102 * be used for peripherals with 16bit access allowed.
AnnaBridge 189:f392fc9709a3 103 * @param Reg Register to access.
AnnaBridge 189:f392fc9709a3 104 * @param Bit Bit number to access.
AnnaBridge 189:f392fc9709a3 105 * @return Value of the targeted bit in the bit band region.
AnnaBridge 189:f392fc9709a3 106 */
AnnaBridge 189:f392fc9709a3 107 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 189:f392fc9709a3 108 /**
AnnaBridge 189:f392fc9709a3 109 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 189:f392fc9709a3 110 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 189:f392fc9709a3 111 * be used for peripherals with 8bit access allowed.
AnnaBridge 189:f392fc9709a3 112 * @param Reg Register to access.
AnnaBridge 189:f392fc9709a3 113 * @param Bit Bit number to access.
AnnaBridge 189:f392fc9709a3 114 * @return Value of the targeted bit in the bit band region.
AnnaBridge 189:f392fc9709a3 115 */
AnnaBridge 189:f392fc9709a3 116 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 119 -- Interrupt vector numbers
AnnaBridge 189:f392fc9709a3 120 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 121
AnnaBridge 189:f392fc9709a3 122 /*!
AnnaBridge 189:f392fc9709a3 123 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 189:f392fc9709a3 124 * @{
AnnaBridge 189:f392fc9709a3 125 */
AnnaBridge 189:f392fc9709a3 126
AnnaBridge 189:f392fc9709a3 127 /** Interrupt Number Definitions */
AnnaBridge 189:f392fc9709a3 128 #define NUMBER_OF_INT_VECTORS 123 /**< Number of interrupts in the Vector table */
AnnaBridge 189:f392fc9709a3 129
AnnaBridge 189:f392fc9709a3 130 typedef enum IRQn {
AnnaBridge 189:f392fc9709a3 131 /* Auxiliary constants */
AnnaBridge 189:f392fc9709a3 132 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
AnnaBridge 189:f392fc9709a3 133
AnnaBridge 189:f392fc9709a3 134 /* Core interrupts */
AnnaBridge 189:f392fc9709a3 135 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 189:f392fc9709a3 136 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
AnnaBridge 189:f392fc9709a3 137 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
AnnaBridge 189:f392fc9709a3 138 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
AnnaBridge 189:f392fc9709a3 139 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
AnnaBridge 189:f392fc9709a3 140 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
AnnaBridge 189:f392fc9709a3 141 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 189:f392fc9709a3 142 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
AnnaBridge 189:f392fc9709a3 143 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
AnnaBridge 189:f392fc9709a3 144
AnnaBridge 189:f392fc9709a3 145 /* Device specific interrupts */
AnnaBridge 189:f392fc9709a3 146 DMA0_DMA16_IRQn = 0, /**< DMA channel 0,16 transfer complete */
AnnaBridge 189:f392fc9709a3 147 DMA1_DMA17_IRQn = 1, /**< DMA channel 1,17 transfer complete */
AnnaBridge 189:f392fc9709a3 148 DMA2_DMA18_IRQn = 2, /**< DMA channel 2,18 transfer complete */
AnnaBridge 189:f392fc9709a3 149 DMA3_DMA19_IRQn = 3, /**< DMA channel 3,19 transfer complete */
AnnaBridge 189:f392fc9709a3 150 DMA4_DMA20_IRQn = 4, /**< DMA channel 4,20 transfer complete */
AnnaBridge 189:f392fc9709a3 151 DMA5_DMA21_IRQn = 5, /**< DMA channel 5,21 transfer complete */
AnnaBridge 189:f392fc9709a3 152 DMA6_DMA22_IRQn = 6, /**< DMA channel 6,22 transfer complete */
AnnaBridge 189:f392fc9709a3 153 DMA7_DMA23_IRQn = 7, /**< DMA channel 7,23 transfer complete */
AnnaBridge 189:f392fc9709a3 154 DMA8_DMA24_IRQn = 8, /**< DMA channel 8,24 transfer complete */
AnnaBridge 189:f392fc9709a3 155 DMA9_DMA25_IRQn = 9, /**< DMA channel 9,25 transfer complete */
AnnaBridge 189:f392fc9709a3 156 DMA10_DMA26_IRQn = 10, /**< DMA channel 10,26 transfer complete */
AnnaBridge 189:f392fc9709a3 157 DMA11_DMA27_IRQn = 11, /**< DMA channel 11,27 transfer complete */
AnnaBridge 189:f392fc9709a3 158 DMA12_DMA28_IRQn = 12, /**< DMA channel 12,28 transfer complete */
AnnaBridge 189:f392fc9709a3 159 DMA13_DMA29_IRQn = 13, /**< DMA channel 13,29 transfer complete */
AnnaBridge 189:f392fc9709a3 160 DMA14_DMA30_IRQn = 14, /**< DMA channel 14,30 transfer complete */
AnnaBridge 189:f392fc9709a3 161 DMA15_DMA31_IRQn = 15, /**< DMA channel 15,31 transfer complete */
AnnaBridge 189:f392fc9709a3 162 DMA_Error_IRQn = 16, /**< DMA channel 0 - 31 error */
AnnaBridge 189:f392fc9709a3 163 MCM_IRQn = 17, /**< MCM normal interrupt */
AnnaBridge 189:f392fc9709a3 164 FTFA_IRQn = 18, /**< FTFA command complete */
AnnaBridge 189:f392fc9709a3 165 Read_Collision_IRQn = 19, /**< FTFA read collision */
AnnaBridge 189:f392fc9709a3 166 LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */
AnnaBridge 189:f392fc9709a3 167 LLWU_IRQn = 21, /**< Low leakage wakeup unit */
AnnaBridge 189:f392fc9709a3 168 WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */
AnnaBridge 189:f392fc9709a3 169 TRNG0_IRQn = 23, /**< True randon number generator */
AnnaBridge 189:f392fc9709a3 170 I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */
AnnaBridge 189:f392fc9709a3 171 I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */
AnnaBridge 189:f392fc9709a3 172 SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */
AnnaBridge 189:f392fc9709a3 173 SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */
AnnaBridge 189:f392fc9709a3 174 I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */
AnnaBridge 189:f392fc9709a3 175 I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */
AnnaBridge 189:f392fc9709a3 176 LPUART0_IRQn = 30, /**< LPUART0 receive/transmit/error interrupt */
AnnaBridge 189:f392fc9709a3 177 LPUART1_IRQn = 31, /**< LPUART1 receive/transmit/error interrupt */
AnnaBridge 189:f392fc9709a3 178 LPUART2_IRQn = 32, /**< LPUART2 receive/transmit/error interrupt */
AnnaBridge 189:f392fc9709a3 179 LPUART3_IRQn = 33, /**< LPUART3 receive/transmit/error interrupt */
AnnaBridge 189:f392fc9709a3 180 LPUART4_IRQn = 34, /**< LPUART4 receive/transmit/error interrupt */
AnnaBridge 189:f392fc9709a3 181 Reserved51_IRQn = 35, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 182 Reserved52_IRQn = 36, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 183 EMVSIM0_IRQn = 37, /**< EMVSIM0 common interrupt */
AnnaBridge 189:f392fc9709a3 184 EMVSIM1_IRQn = 38, /**< EMVSIM1 common interrupt */
AnnaBridge 189:f392fc9709a3 185 ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */
AnnaBridge 189:f392fc9709a3 186 CMP0_IRQn = 40, /**< Comparator 0 */
AnnaBridge 189:f392fc9709a3 187 CMP1_IRQn = 41, /**< Comparator 1 */
AnnaBridge 189:f392fc9709a3 188 FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */
AnnaBridge 189:f392fc9709a3 189 FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */
AnnaBridge 189:f392fc9709a3 190 FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */
AnnaBridge 189:f392fc9709a3 191 CMT_IRQn = 45, /**< Carrier modulator transmitter */
AnnaBridge 189:f392fc9709a3 192 RTC_IRQn = 46, /**< Real time clock */
AnnaBridge 189:f392fc9709a3 193 RTC_Seconds_IRQn = 47, /**< Real time clock seconds */
AnnaBridge 189:f392fc9709a3 194 PIT0CH0_IRQn = 48, /**< Periodic interrupt timer 0 channel 0 */
AnnaBridge 189:f392fc9709a3 195 PIT0CH1_IRQn = 49, /**< Periodic interrupt timer 0 channel 1 */
AnnaBridge 189:f392fc9709a3 196 PIT0CH2_IRQn = 50, /**< Periodic interrupt timer 0 channel 2 */
AnnaBridge 189:f392fc9709a3 197 PIT0CH3_IRQn = 51, /**< Periodic interrupt timer 0 channel 3 */
AnnaBridge 189:f392fc9709a3 198 PDB0_IRQn = 52, /**< Programmable delay block */
AnnaBridge 189:f392fc9709a3 199 USB0_IRQn = 53, /**< USB OTG interrupt */
AnnaBridge 189:f392fc9709a3 200 USBDCD_IRQn = 54, /**< USB charger detect */
AnnaBridge 189:f392fc9709a3 201 Reserved71_IRQn = 55, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 202 DAC0_IRQn = 56, /**< Digital-to-analog converter 0 */
AnnaBridge 189:f392fc9709a3 203 MCG_IRQn = 57, /**< Multipurpose clock generator */
AnnaBridge 189:f392fc9709a3 204 LPTMR0_LPTMR1_IRQn = 58, /**< Single interrupt vector for Low Power Timer 0 and 1 */
AnnaBridge 189:f392fc9709a3 205 PORTA_IRQn = 59, /**< Port A pin detect interrupt */
AnnaBridge 189:f392fc9709a3 206 PORTB_IRQn = 60, /**< Port B pin detect interrupt */
AnnaBridge 189:f392fc9709a3 207 PORTC_IRQn = 61, /**< Port C pin detect interrupt */
AnnaBridge 189:f392fc9709a3 208 PORTD_IRQn = 62, /**< Port D pin detect interrupt */
AnnaBridge 189:f392fc9709a3 209 PORTE_IRQn = 63, /**< Port E pin detect interrupt */
AnnaBridge 189:f392fc9709a3 210 SWI_IRQn = 64, /**< Software interrupt */
AnnaBridge 189:f392fc9709a3 211 SPI2_IRQn = 65, /**< Serial peripheral Interface 2 */
AnnaBridge 189:f392fc9709a3 212 Reserved82_IRQn = 66, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 213 Reserved83_IRQn = 67, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 214 Reserved84_IRQn = 68, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 215 Reserved85_IRQn = 69, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 216 FLEXIO0_IRQn = 70, /**< FLEXIO0 */
AnnaBridge 189:f392fc9709a3 217 FTM3_IRQn = 71, /**< FlexTimer module 3 fault, overflow and channels interrupt */
AnnaBridge 189:f392fc9709a3 218 Reserved88_IRQn = 72, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 219 Reserved89_IRQn = 73, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 220 I2C2_IRQn = 74, /**< Inter-integrated circuit 2 */
AnnaBridge 189:f392fc9709a3 221 Reserved91_IRQn = 75, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 222 Reserved92_IRQn = 76, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 223 Reserved93_IRQn = 77, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 224 Reserved94_IRQn = 78, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 225 Reserved95_IRQn = 79, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 226 Reserved96_IRQn = 80, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 227 SDHC_IRQn = 81, /**< Secured digital host controller */
AnnaBridge 189:f392fc9709a3 228 Reserved98_IRQn = 82, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 229 Reserved99_IRQn = 83, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 230 Reserved100_IRQn = 84, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 231 Reserved101_IRQn = 85, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 232 Reserved102_IRQn = 86, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 233 TSI0_IRQn = 87, /**< Touch Sensing Input */
AnnaBridge 189:f392fc9709a3 234 TPM1_IRQn = 88, /**< TPM1 single interrupt vector for all sources */
AnnaBridge 189:f392fc9709a3 235 TPM2_IRQn = 89, /**< TPM2 single interrupt vector for all sources */
AnnaBridge 189:f392fc9709a3 236 Reserved106_IRQn = 90, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 237 I2C3_IRQn = 91, /**< Inter-integrated circuit 3 */
AnnaBridge 189:f392fc9709a3 238 Reserved108_IRQn = 92, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 239 Reserved109_IRQn = 93, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 240 Reserved110_IRQn = 94, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 241 Reserved111_IRQn = 95, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 242 Reserved112_IRQn = 96, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 243 Reserved113_IRQn = 97, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 244 Reserved114_IRQn = 98, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 245 Reserved115_IRQn = 99, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 246 QuadSPI0_IRQn = 100, /**< qspi */
AnnaBridge 189:f392fc9709a3 247 Reserved117_IRQn = 101, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 248 Reserved118_IRQn = 102, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 249 Reserved119_IRQn = 103, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 250 LTC0_IRQn = 104, /**< LP Trusted Cryptography */
AnnaBridge 189:f392fc9709a3 251 Reserved121_IRQn = 105, /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 252 Reserved122_IRQn = 106 /**< Reserved interrupt */
AnnaBridge 189:f392fc9709a3 253 } IRQn_Type;
AnnaBridge 189:f392fc9709a3 254
AnnaBridge 189:f392fc9709a3 255 /*!
AnnaBridge 189:f392fc9709a3 256 * @}
AnnaBridge 189:f392fc9709a3 257 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 189:f392fc9709a3 258
AnnaBridge 189:f392fc9709a3 259
AnnaBridge 189:f392fc9709a3 260 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 261 -- Cortex M4 Core Configuration
AnnaBridge 189:f392fc9709a3 262 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 263
AnnaBridge 189:f392fc9709a3 264 /*!
AnnaBridge 189:f392fc9709a3 265 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
AnnaBridge 189:f392fc9709a3 266 * @{
AnnaBridge 189:f392fc9709a3 267 */
AnnaBridge 189:f392fc9709a3 268
AnnaBridge 189:f392fc9709a3 269 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 189:f392fc9709a3 270 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 189:f392fc9709a3 271 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 189:f392fc9709a3 272 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
AnnaBridge 189:f392fc9709a3 273
AnnaBridge 189:f392fc9709a3 274 #include "core_cm4.h" /* Core Peripheral Access Layer */
AnnaBridge 189:f392fc9709a3 275 #include "system_MK82F25615.h" /* Device specific configuration file */
AnnaBridge 189:f392fc9709a3 276
AnnaBridge 189:f392fc9709a3 277 /*!
AnnaBridge 189:f392fc9709a3 278 * @}
AnnaBridge 189:f392fc9709a3 279 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 189:f392fc9709a3 280
AnnaBridge 189:f392fc9709a3 281
AnnaBridge 189:f392fc9709a3 282 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 283 -- Mapping Information
AnnaBridge 189:f392fc9709a3 284 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 285
AnnaBridge 189:f392fc9709a3 286 /*!
AnnaBridge 189:f392fc9709a3 287 * @addtogroup Mapping_Information Mapping Information
AnnaBridge 189:f392fc9709a3 288 * @{
AnnaBridge 189:f392fc9709a3 289 */
AnnaBridge 189:f392fc9709a3 290
AnnaBridge 189:f392fc9709a3 291 /** Mapping Information */
AnnaBridge 189:f392fc9709a3 292 /*!
AnnaBridge 189:f392fc9709a3 293 * @addtogroup edma_request
AnnaBridge 189:f392fc9709a3 294 * @{
AnnaBridge 189:f392fc9709a3 295 */
AnnaBridge 189:f392fc9709a3 296
AnnaBridge 189:f392fc9709a3 297 /*******************************************************************************
AnnaBridge 189:f392fc9709a3 298 * Definitions
AnnaBridge 189:f392fc9709a3 299 ******************************************************************************/
AnnaBridge 189:f392fc9709a3 300
AnnaBridge 189:f392fc9709a3 301 /*!
AnnaBridge 189:f392fc9709a3 302 * @brief Structure for the DMA hardware request
AnnaBridge 189:f392fc9709a3 303 *
AnnaBridge 189:f392fc9709a3 304 * Defines the structure for the DMA hardware request collections. The user can configure the
AnnaBridge 189:f392fc9709a3 305 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
AnnaBridge 189:f392fc9709a3 306 * of the hardware request varies according to the to SoC.
AnnaBridge 189:f392fc9709a3 307 */
AnnaBridge 189:f392fc9709a3 308 typedef enum _dma_request_source
AnnaBridge 189:f392fc9709a3 309 {
AnnaBridge 189:f392fc9709a3 310 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 189:f392fc9709a3 311 kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */
AnnaBridge 189:f392fc9709a3 312 kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */
AnnaBridge 189:f392fc9709a3 313 kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */
AnnaBridge 189:f392fc9709a3 314 kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */
AnnaBridge 189:f392fc9709a3 315 kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */
AnnaBridge 189:f392fc9709a3 316 kDmaRequestMux0LPUART2Rx = 6|0x100U, /**< LPUART2 Receive. */
AnnaBridge 189:f392fc9709a3 317 kDmaRequestMux0LPUART2Tx = 7|0x100U, /**< LPUART2 Transmit. */
AnnaBridge 189:f392fc9709a3 318 kDmaRequestMux0LPUART3Rx = 8|0x100U, /**< LPUART3 Receive. */
AnnaBridge 189:f392fc9709a3 319 kDmaRequestMux0LPUART3Tx = 9|0x100U, /**< LPUART3 Transmit. */
AnnaBridge 189:f392fc9709a3 320 kDmaRequestMux0LPUART4Rx = 10|0x100U, /**< LPUART4 Receive. */
AnnaBridge 189:f392fc9709a3 321 kDmaRequestMux0LPUART4Tx = 11|0x100U, /**< LPUART4 Transmit. */
AnnaBridge 189:f392fc9709a3 322 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
AnnaBridge 189:f392fc9709a3 323 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
AnnaBridge 189:f392fc9709a3 324 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
AnnaBridge 189:f392fc9709a3 325 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
AnnaBridge 189:f392fc9709a3 326 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
AnnaBridge 189:f392fc9709a3 327 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
AnnaBridge 189:f392fc9709a3 328 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
AnnaBridge 189:f392fc9709a3 329 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
AnnaBridge 189:f392fc9709a3 330 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
AnnaBridge 189:f392fc9709a3 331 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 189:f392fc9709a3 332 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 189:f392fc9709a3 333 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 189:f392fc9709a3 334 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
AnnaBridge 189:f392fc9709a3 335 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
AnnaBridge 189:f392fc9709a3 336 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
AnnaBridge 189:f392fc9709a3 337 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
AnnaBridge 189:f392fc9709a3 338 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
AnnaBridge 189:f392fc9709a3 339 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
AnnaBridge 189:f392fc9709a3 340 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
AnnaBridge 189:f392fc9709a3 341 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
AnnaBridge 189:f392fc9709a3 342 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
AnnaBridge 189:f392fc9709a3 343 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
AnnaBridge 189:f392fc9709a3 344 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
AnnaBridge 189:f392fc9709a3 345 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
AnnaBridge 189:f392fc9709a3 346 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
AnnaBridge 189:f392fc9709a3 347 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
AnnaBridge 189:f392fc9709a3 348 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
AnnaBridge 189:f392fc9709a3 349 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
AnnaBridge 189:f392fc9709a3 350 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
AnnaBridge 189:f392fc9709a3 351 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
AnnaBridge 189:f392fc9709a3 352 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
AnnaBridge 189:f392fc9709a3 353 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
AnnaBridge 189:f392fc9709a3 354 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
AnnaBridge 189:f392fc9709a3 355 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
AnnaBridge 189:f392fc9709a3 356 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
AnnaBridge 189:f392fc9709a3 357 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
AnnaBridge 189:f392fc9709a3 358 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
AnnaBridge 189:f392fc9709a3 359 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
AnnaBridge 189:f392fc9709a3 360 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
AnnaBridge 189:f392fc9709a3 361 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
AnnaBridge 189:f392fc9709a3 362 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
AnnaBridge 189:f392fc9709a3 363 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
AnnaBridge 189:f392fc9709a3 364 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
AnnaBridge 189:f392fc9709a3 365 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
AnnaBridge 189:f392fc9709a3 366 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
AnnaBridge 189:f392fc9709a3 367 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
AnnaBridge 189:f392fc9709a3 368 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
AnnaBridge 189:f392fc9709a3 369 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
AnnaBridge 189:f392fc9709a3 370 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
AnnaBridge 189:f392fc9709a3 371 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
AnnaBridge 189:f392fc9709a3 372 kDmaRequestMux0SPI2Rx = 58|0x100U, /**< SPI2 Receive. */
AnnaBridge 189:f392fc9709a3 373 kDmaRequestMux0SPI2Tx = 59|0x100U, /**< SPI2 Transmit. */
AnnaBridge 189:f392fc9709a3 374 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 375 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 376 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 377 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 378 kDmaRequestMux0Group1Disable = 0|0x200U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 189:f392fc9709a3 379 kDmaRequestMux0Group1FlexIO0Channel0 = 1|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 380 kDmaRequestMux0Group1FlexIO0Channel1 = 2|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 381 kDmaRequestMux0Group1FlexIO0Channel2 = 3|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 382 kDmaRequestMux0Group1FlexIO0Channel3 = 4|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 383 kDmaRequestMux0Group1FlexIO0Channel4 = 5|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 384 kDmaRequestMux0Group1FlexIO0Channel5 = 6|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 385 kDmaRequestMux0Group1FlexIO0Channel6 = 7|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 386 kDmaRequestMux0Group1FlexIO0Channel7 = 8|0x200U, /**< FLEXIO0. */
AnnaBridge 189:f392fc9709a3 387 kDmaRequestMux0Group1Reserved9 = 9|0x200U, /**< Reserved9 */
AnnaBridge 189:f392fc9709a3 388 kDmaRequestMux0Group1Reserved10 = 10|0x200U, /**< Reserved10 */
AnnaBridge 189:f392fc9709a3 389 kDmaRequestMux0Group1Reserved11 = 11|0x200U, /**< Reserved11 */
AnnaBridge 189:f392fc9709a3 390 kDmaRequestMux0Group1Reserved12 = 12|0x200U, /**< Reserved12 */
AnnaBridge 189:f392fc9709a3 391 kDmaRequestMux0Group1Reserved13 = 13|0x200U, /**< Reserved13 */
AnnaBridge 189:f392fc9709a3 392 kDmaRequestMux0Group1Reserved14 = 14|0x200U, /**< Reserved14 */
AnnaBridge 189:f392fc9709a3 393 kDmaRequestMux0Group1Reserved15 = 15|0x200U, /**< Reserved15 */
AnnaBridge 189:f392fc9709a3 394 kDmaRequestMux0Group1Reserved16 = 16|0x200U, /**< Reserved16 */
AnnaBridge 189:f392fc9709a3 395 kDmaRequestMux0Group1LTC0InputFIFO = 17|0x200U, /**< LTC0 Input FIFO. */
AnnaBridge 189:f392fc9709a3 396 kDmaRequestMux0Group1LTC0OutputFIFO = 18|0x200U, /**< LTC0 Output FIFO. */
AnnaBridge 189:f392fc9709a3 397 kDmaRequestMux0Group1LTC0PKHA = 19|0x200U, /**< LTC0 PKHA. */
AnnaBridge 189:f392fc9709a3 398 kDmaRequestMux0Group1EMVSIM0Rx = 20|0x200U, /**< EMVSIM0 Receive. */
AnnaBridge 189:f392fc9709a3 399 kDmaRequestMux0Group1EMVSIM0Tx = 21|0x200U, /**< EMVSIM0 Transmit. */
AnnaBridge 189:f392fc9709a3 400 kDmaRequestMux0Group1EMVSIM1Rx = 22|0x200U, /**< EMVSIM1 Receive. */
AnnaBridge 189:f392fc9709a3 401 kDmaRequestMux0Group1EMVSIM1Tx = 23|0x200U, /**< EMVSIM1 Transmit. */
AnnaBridge 189:f392fc9709a3 402 kDmaRequestMux0Group1QSPI0Rx = 24|0x200U, /**< QuadSPI0 Receive. */
AnnaBridge 189:f392fc9709a3 403 kDmaRequestMux0Group1QSPI0Tx = 25|0x200U, /**< QuadSPI0 Transmit. */
AnnaBridge 189:f392fc9709a3 404 kDmaRequestMux0Group1Reserved26 = 26|0x200U, /**< Reserved26 */
AnnaBridge 189:f392fc9709a3 405 kDmaRequestMux0Group1Reserved27 = 27|0x200U, /**< Reserved27 */
AnnaBridge 189:f392fc9709a3 406 kDmaRequestMux0Group1SPI0Rx = 28|0x200U, /**< SPI0 Receive. */
AnnaBridge 189:f392fc9709a3 407 kDmaRequestMux0Group1SPI0Tx = 29|0x200U, /**< SPI0 Transmit. */
AnnaBridge 189:f392fc9709a3 408 kDmaRequestMux0Group1SPI1Rx = 30|0x200U, /**< SPI1 Receive. */
AnnaBridge 189:f392fc9709a3 409 kDmaRequestMux0Group1SPI1Tx = 31|0x200U, /**< SPI1 Transmit. */
AnnaBridge 189:f392fc9709a3 410 kDmaRequestMux0Group1Reserved32 = 32|0x200U, /**< Reserved32 */
AnnaBridge 189:f392fc9709a3 411 kDmaRequestMux0Group1Reserved33 = 33|0x200U, /**< Reserved33 */
AnnaBridge 189:f392fc9709a3 412 kDmaRequestMux0Group1Reserved34 = 34|0x200U, /**< Reserved34 */
AnnaBridge 189:f392fc9709a3 413 kDmaRequestMux0Group1Reserved35 = 35|0x200U, /**< Reserved35 */
AnnaBridge 189:f392fc9709a3 414 kDmaRequestMux0Group1Reserved36 = 36|0x200U, /**< Reserved36 */
AnnaBridge 189:f392fc9709a3 415 kDmaRequestMux0Group1Reserved37 = 37|0x200U, /**< Reserved37 */
AnnaBridge 189:f392fc9709a3 416 kDmaRequestMux0Group1Reserved38 = 38|0x200U, /**< Reserved38 */
AnnaBridge 189:f392fc9709a3 417 kDmaRequestMux0Group1Reserved39 = 39|0x200U, /**< Reserved39 */
AnnaBridge 189:f392fc9709a3 418 kDmaRequestMux0Group1Reserved40 = 40|0x200U, /**< Reserved40 */
AnnaBridge 189:f392fc9709a3 419 kDmaRequestMux0Group1Reserved41 = 41|0x200U, /**< Reserved41 */
AnnaBridge 189:f392fc9709a3 420 kDmaRequestMux0Group1TPM1Channel0 = 42|0x200U, /**< TPM1 C0V. */
AnnaBridge 189:f392fc9709a3 421 kDmaRequestMux0Group1TPM1Channel1 = 43|0x200U, /**< TPM1 C1V. */
AnnaBridge 189:f392fc9709a3 422 kDmaRequestMux0Group1TPM2Channel0 = 44|0x200U, /**< TPM2 C0V. */
AnnaBridge 189:f392fc9709a3 423 kDmaRequestMux0Group1TPM2Channel1 = 45|0x200U, /**< TPM2 C1V. */
AnnaBridge 189:f392fc9709a3 424 kDmaRequestMux0Group1Reserved46 = 46|0x200U, /**< Reserved46 */
AnnaBridge 189:f392fc9709a3 425 kDmaRequestMux0Group1Reserved47 = 47|0x200U, /**< Reserved47 */
AnnaBridge 189:f392fc9709a3 426 kDmaRequestMux0Group1Reserved48 = 48|0x200U, /**< Reserved48 */
AnnaBridge 189:f392fc9709a3 427 kDmaRequestMux0Group1Reserved49 = 49|0x200U, /**< Reserved49 */
AnnaBridge 189:f392fc9709a3 428 kDmaRequestMux0Group1Reserved50 = 50|0x200U, /**< Reserved50 */
AnnaBridge 189:f392fc9709a3 429 kDmaRequestMux0Group1Reserved51 = 51|0x200U, /**< Reserved51 */
AnnaBridge 189:f392fc9709a3 430 kDmaRequestMux0Group1Reserved52 = 52|0x200U, /**< Reserved52 */
AnnaBridge 189:f392fc9709a3 431 kDmaRequestMux0Group1Reserved53 = 53|0x200U, /**< Reserved53 */
AnnaBridge 189:f392fc9709a3 432 kDmaRequestMux0Group1Reserved54 = 54|0x200U, /**< Reserved54 */
AnnaBridge 189:f392fc9709a3 433 kDmaRequestMux0Group1TPM1Overflow = 55|0x200U, /**< TPM1. */
AnnaBridge 189:f392fc9709a3 434 kDmaRequestMux0Group1TPM2Overflow = 56|0x200U, /**< TPM2. */
AnnaBridge 189:f392fc9709a3 435 kDmaRequestMux0Group1Reserved57 = 57|0x200U, /**< Reserved57 */
AnnaBridge 189:f392fc9709a3 436 kDmaRequestMux0Group1Reserved58 = 58|0x200U, /**< Reserved58 */
AnnaBridge 189:f392fc9709a3 437 kDmaRequestMux0Group1Reserved59 = 59|0x200U, /**< Reserved59 */
AnnaBridge 189:f392fc9709a3 438 kDmaRequestMux0Group1AlwaysOn60 = 60|0x200U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 439 kDmaRequestMux0Group1AlwaysOn61 = 61|0x200U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 440 kDmaRequestMux0Group1AlwaysOn62 = 62|0x200U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 441 kDmaRequestMux0Group1AlwaysOn63 = 63|0x200U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 189:f392fc9709a3 442 } dma_request_source_t;
AnnaBridge 189:f392fc9709a3 443
AnnaBridge 189:f392fc9709a3 444 /* @} */
AnnaBridge 189:f392fc9709a3 445
AnnaBridge 189:f392fc9709a3 446
AnnaBridge 189:f392fc9709a3 447 /*!
AnnaBridge 189:f392fc9709a3 448 * @}
AnnaBridge 189:f392fc9709a3 449 */ /* end of group Mapping_Information */
AnnaBridge 189:f392fc9709a3 450
AnnaBridge 189:f392fc9709a3 451
AnnaBridge 189:f392fc9709a3 452 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 453 -- Device Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 454 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 455
AnnaBridge 189:f392fc9709a3 456 /*!
AnnaBridge 189:f392fc9709a3 457 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 458 * @{
AnnaBridge 189:f392fc9709a3 459 */
AnnaBridge 189:f392fc9709a3 460
AnnaBridge 189:f392fc9709a3 461
AnnaBridge 189:f392fc9709a3 462 /*
AnnaBridge 189:f392fc9709a3 463 ** Start of section using anonymous unions
AnnaBridge 189:f392fc9709a3 464 */
AnnaBridge 189:f392fc9709a3 465
AnnaBridge 189:f392fc9709a3 466 #if defined(__ARMCC_VERSION)
AnnaBridge 189:f392fc9709a3 467 #pragma push
AnnaBridge 189:f392fc9709a3 468 #pragma anon_unions
AnnaBridge 189:f392fc9709a3 469 #elif defined(__CWCC__)
AnnaBridge 189:f392fc9709a3 470 #pragma push
AnnaBridge 189:f392fc9709a3 471 #pragma cpp_extensions on
AnnaBridge 189:f392fc9709a3 472 #elif defined(__GNUC__)
AnnaBridge 189:f392fc9709a3 473 /* anonymous unions are enabled by default */
AnnaBridge 189:f392fc9709a3 474 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 189:f392fc9709a3 475 #pragma language=extended
AnnaBridge 189:f392fc9709a3 476 #else
AnnaBridge 189:f392fc9709a3 477 #error Not supported compiler type
AnnaBridge 189:f392fc9709a3 478 #endif
AnnaBridge 189:f392fc9709a3 479
AnnaBridge 189:f392fc9709a3 480 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 481 -- ADC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 482 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 483
AnnaBridge 189:f392fc9709a3 484 /*!
AnnaBridge 189:f392fc9709a3 485 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 486 * @{
AnnaBridge 189:f392fc9709a3 487 */
AnnaBridge 189:f392fc9709a3 488
AnnaBridge 189:f392fc9709a3 489 /** ADC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 490 typedef struct {
AnnaBridge 189:f392fc9709a3 491 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 492 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 493 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 189:f392fc9709a3 494 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 495 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 496 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 497 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 498 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 499 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 500 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 501 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 502 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 503 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 189:f392fc9709a3 504 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 189:f392fc9709a3 505 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 506 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 189:f392fc9709a3 507 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 189:f392fc9709a3 508 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 189:f392fc9709a3 509 uint8_t RESERVED_0[4];
AnnaBridge 189:f392fc9709a3 510 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 189:f392fc9709a3 511 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 189:f392fc9709a3 512 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 189:f392fc9709a3 513 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 189:f392fc9709a3 514 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 189:f392fc9709a3 515 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 189:f392fc9709a3 516 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 189:f392fc9709a3 517 } ADC_Type;
AnnaBridge 189:f392fc9709a3 518
AnnaBridge 189:f392fc9709a3 519 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 520 -- ADC Register Masks
AnnaBridge 189:f392fc9709a3 521 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 522
AnnaBridge 189:f392fc9709a3 523 /*!
AnnaBridge 189:f392fc9709a3 524 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 189:f392fc9709a3 525 * @{
AnnaBridge 189:f392fc9709a3 526 */
AnnaBridge 189:f392fc9709a3 527
AnnaBridge 189:f392fc9709a3 528 /*! @name SC1 - ADC Status and Control Registers 1 */
AnnaBridge 189:f392fc9709a3 529 #define ADC_SC1_ADCH_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 530 #define ADC_SC1_ADCH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 531 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
AnnaBridge 189:f392fc9709a3 532 #define ADC_SC1_DIFF_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 533 #define ADC_SC1_DIFF_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 534 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
AnnaBridge 189:f392fc9709a3 535 #define ADC_SC1_AIEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 536 #define ADC_SC1_AIEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 537 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
AnnaBridge 189:f392fc9709a3 538 #define ADC_SC1_COCO_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 539 #define ADC_SC1_COCO_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 540 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
AnnaBridge 189:f392fc9709a3 541
AnnaBridge 189:f392fc9709a3 542 /* The count of ADC_SC1 */
AnnaBridge 189:f392fc9709a3 543 #define ADC_SC1_COUNT (2U)
AnnaBridge 189:f392fc9709a3 544
AnnaBridge 189:f392fc9709a3 545 /*! @name CFG1 - ADC Configuration Register 1 */
AnnaBridge 189:f392fc9709a3 546 #define ADC_CFG1_ADICLK_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 547 #define ADC_CFG1_ADICLK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 548 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
AnnaBridge 189:f392fc9709a3 549 #define ADC_CFG1_MODE_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 550 #define ADC_CFG1_MODE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 551 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
AnnaBridge 189:f392fc9709a3 552 #define ADC_CFG1_ADLSMP_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 553 #define ADC_CFG1_ADLSMP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 554 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
AnnaBridge 189:f392fc9709a3 555 #define ADC_CFG1_ADIV_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 556 #define ADC_CFG1_ADIV_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 557 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
AnnaBridge 189:f392fc9709a3 558 #define ADC_CFG1_ADLPC_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 559 #define ADC_CFG1_ADLPC_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 560 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
AnnaBridge 189:f392fc9709a3 561
AnnaBridge 189:f392fc9709a3 562 /*! @name CFG2 - ADC Configuration Register 2 */
AnnaBridge 189:f392fc9709a3 563 #define ADC_CFG2_ADLSTS_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 564 #define ADC_CFG2_ADLSTS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 565 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
AnnaBridge 189:f392fc9709a3 566 #define ADC_CFG2_ADHSC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 567 #define ADC_CFG2_ADHSC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 568 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
AnnaBridge 189:f392fc9709a3 569 #define ADC_CFG2_ADACKEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 570 #define ADC_CFG2_ADACKEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 571 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
AnnaBridge 189:f392fc9709a3 572 #define ADC_CFG2_MUXSEL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 573 #define ADC_CFG2_MUXSEL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 574 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
AnnaBridge 189:f392fc9709a3 575
AnnaBridge 189:f392fc9709a3 576 /*! @name R - ADC Data Result Register */
AnnaBridge 189:f392fc9709a3 577 #define ADC_R_D_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 578 #define ADC_R_D_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 579 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
AnnaBridge 189:f392fc9709a3 580
AnnaBridge 189:f392fc9709a3 581 /* The count of ADC_R */
AnnaBridge 189:f392fc9709a3 582 #define ADC_R_COUNT (2U)
AnnaBridge 189:f392fc9709a3 583
AnnaBridge 189:f392fc9709a3 584 /*! @name CV1 - Compare Value Registers */
AnnaBridge 189:f392fc9709a3 585 #define ADC_CV1_CV_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 586 #define ADC_CV1_CV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 587 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
AnnaBridge 189:f392fc9709a3 588
AnnaBridge 189:f392fc9709a3 589 /*! @name CV2 - Compare Value Registers */
AnnaBridge 189:f392fc9709a3 590 #define ADC_CV2_CV_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 591 #define ADC_CV2_CV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 592 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
AnnaBridge 189:f392fc9709a3 593
AnnaBridge 189:f392fc9709a3 594 /*! @name SC2 - Status and Control Register 2 */
AnnaBridge 189:f392fc9709a3 595 #define ADC_SC2_REFSEL_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 596 #define ADC_SC2_REFSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 597 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
AnnaBridge 189:f392fc9709a3 598 #define ADC_SC2_DMAEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 599 #define ADC_SC2_DMAEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 600 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
AnnaBridge 189:f392fc9709a3 601 #define ADC_SC2_ACREN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 602 #define ADC_SC2_ACREN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 603 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
AnnaBridge 189:f392fc9709a3 604 #define ADC_SC2_ACFGT_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 605 #define ADC_SC2_ACFGT_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 606 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
AnnaBridge 189:f392fc9709a3 607 #define ADC_SC2_ACFE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 608 #define ADC_SC2_ACFE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 609 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
AnnaBridge 189:f392fc9709a3 610 #define ADC_SC2_ADTRG_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 611 #define ADC_SC2_ADTRG_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 612 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
AnnaBridge 189:f392fc9709a3 613 #define ADC_SC2_ADACT_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 614 #define ADC_SC2_ADACT_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 615 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
AnnaBridge 189:f392fc9709a3 616
AnnaBridge 189:f392fc9709a3 617 /*! @name SC3 - Status and Control Register 3 */
AnnaBridge 189:f392fc9709a3 618 #define ADC_SC3_AVGS_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 619 #define ADC_SC3_AVGS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 620 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
AnnaBridge 189:f392fc9709a3 621 #define ADC_SC3_AVGE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 622 #define ADC_SC3_AVGE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 623 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
AnnaBridge 189:f392fc9709a3 624 #define ADC_SC3_ADCO_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 625 #define ADC_SC3_ADCO_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 626 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
AnnaBridge 189:f392fc9709a3 627 #define ADC_SC3_CALF_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 628 #define ADC_SC3_CALF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 629 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
AnnaBridge 189:f392fc9709a3 630 #define ADC_SC3_CAL_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 631 #define ADC_SC3_CAL_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 632 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
AnnaBridge 189:f392fc9709a3 633
AnnaBridge 189:f392fc9709a3 634 /*! @name OFS - ADC Offset Correction Register */
AnnaBridge 189:f392fc9709a3 635 #define ADC_OFS_OFS_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 636 #define ADC_OFS_OFS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 637 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
AnnaBridge 189:f392fc9709a3 638
AnnaBridge 189:f392fc9709a3 639 /*! @name PG - ADC Plus-Side Gain Register */
AnnaBridge 189:f392fc9709a3 640 #define ADC_PG_PG_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 641 #define ADC_PG_PG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 642 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
AnnaBridge 189:f392fc9709a3 643
AnnaBridge 189:f392fc9709a3 644 /*! @name MG - ADC Minus-Side Gain Register */
AnnaBridge 189:f392fc9709a3 645 #define ADC_MG_MG_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 646 #define ADC_MG_MG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 647 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
AnnaBridge 189:f392fc9709a3 648
AnnaBridge 189:f392fc9709a3 649 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 650 #define ADC_CLPD_CLPD_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 651 #define ADC_CLPD_CLPD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 652 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
AnnaBridge 189:f392fc9709a3 653
AnnaBridge 189:f392fc9709a3 654 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 655 #define ADC_CLPS_CLPS_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 656 #define ADC_CLPS_CLPS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 657 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
AnnaBridge 189:f392fc9709a3 658
AnnaBridge 189:f392fc9709a3 659 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 660 #define ADC_CLP4_CLP4_MASK (0x3FFU)
AnnaBridge 189:f392fc9709a3 661 #define ADC_CLP4_CLP4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 662 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
AnnaBridge 189:f392fc9709a3 663
AnnaBridge 189:f392fc9709a3 664 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 665 #define ADC_CLP3_CLP3_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 666 #define ADC_CLP3_CLP3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 667 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
AnnaBridge 189:f392fc9709a3 668
AnnaBridge 189:f392fc9709a3 669 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 670 #define ADC_CLP2_CLP2_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 671 #define ADC_CLP2_CLP2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 672 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
AnnaBridge 189:f392fc9709a3 673
AnnaBridge 189:f392fc9709a3 674 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 675 #define ADC_CLP1_CLP1_MASK (0x7FU)
AnnaBridge 189:f392fc9709a3 676 #define ADC_CLP1_CLP1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 677 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
AnnaBridge 189:f392fc9709a3 678
AnnaBridge 189:f392fc9709a3 679 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 680 #define ADC_CLP0_CLP0_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 681 #define ADC_CLP0_CLP0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 682 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
AnnaBridge 189:f392fc9709a3 683
AnnaBridge 189:f392fc9709a3 684 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 685 #define ADC_CLMD_CLMD_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 686 #define ADC_CLMD_CLMD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 687 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
AnnaBridge 189:f392fc9709a3 688
AnnaBridge 189:f392fc9709a3 689 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 690 #define ADC_CLMS_CLMS_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 691 #define ADC_CLMS_CLMS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 692 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
AnnaBridge 189:f392fc9709a3 693
AnnaBridge 189:f392fc9709a3 694 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 695 #define ADC_CLM4_CLM4_MASK (0x3FFU)
AnnaBridge 189:f392fc9709a3 696 #define ADC_CLM4_CLM4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 697 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
AnnaBridge 189:f392fc9709a3 698
AnnaBridge 189:f392fc9709a3 699 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 700 #define ADC_CLM3_CLM3_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 701 #define ADC_CLM3_CLM3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 702 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
AnnaBridge 189:f392fc9709a3 703
AnnaBridge 189:f392fc9709a3 704 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 705 #define ADC_CLM2_CLM2_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 706 #define ADC_CLM2_CLM2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 707 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
AnnaBridge 189:f392fc9709a3 708
AnnaBridge 189:f392fc9709a3 709 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 710 #define ADC_CLM1_CLM1_MASK (0x7FU)
AnnaBridge 189:f392fc9709a3 711 #define ADC_CLM1_CLM1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 712 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
AnnaBridge 189:f392fc9709a3 713
AnnaBridge 189:f392fc9709a3 714 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 189:f392fc9709a3 715 #define ADC_CLM0_CLM0_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 716 #define ADC_CLM0_CLM0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 717 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
AnnaBridge 189:f392fc9709a3 718
AnnaBridge 189:f392fc9709a3 719
AnnaBridge 189:f392fc9709a3 720 /*!
AnnaBridge 189:f392fc9709a3 721 * @}
AnnaBridge 189:f392fc9709a3 722 */ /* end of group ADC_Register_Masks */
AnnaBridge 189:f392fc9709a3 723
AnnaBridge 189:f392fc9709a3 724
AnnaBridge 189:f392fc9709a3 725 /* ADC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 726 /** Peripheral ADC0 base address */
AnnaBridge 189:f392fc9709a3 727 #define ADC0_BASE (0x4003B000u)
AnnaBridge 189:f392fc9709a3 728 /** Peripheral ADC0 base pointer */
AnnaBridge 189:f392fc9709a3 729 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 189:f392fc9709a3 730 /** Array initializer of ADC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 731 #define ADC_BASE_ADDRS { ADC0_BASE }
AnnaBridge 189:f392fc9709a3 732 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 733 #define ADC_BASE_PTRS { ADC0 }
AnnaBridge 189:f392fc9709a3 734 /** Interrupt vectors for the ADC peripheral type */
AnnaBridge 189:f392fc9709a3 735 #define ADC_IRQS { ADC0_IRQn }
AnnaBridge 189:f392fc9709a3 736
AnnaBridge 189:f392fc9709a3 737 /*!
AnnaBridge 189:f392fc9709a3 738 * @}
AnnaBridge 189:f392fc9709a3 739 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 740
AnnaBridge 189:f392fc9709a3 741
AnnaBridge 189:f392fc9709a3 742 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 743 -- AIPS Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 744 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 745
AnnaBridge 189:f392fc9709a3 746 /*!
AnnaBridge 189:f392fc9709a3 747 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 748 * @{
AnnaBridge 189:f392fc9709a3 749 */
AnnaBridge 189:f392fc9709a3 750
AnnaBridge 189:f392fc9709a3 751 /** AIPS - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 752 typedef struct {
AnnaBridge 189:f392fc9709a3 753 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 754 uint8_t RESERVED_0[28];
AnnaBridge 189:f392fc9709a3 755 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 756 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 757 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 758 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 759 uint8_t RESERVED_1[16];
AnnaBridge 189:f392fc9709a3 760 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 761 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
AnnaBridge 189:f392fc9709a3 762 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
AnnaBridge 189:f392fc9709a3 763 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
AnnaBridge 189:f392fc9709a3 764 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
AnnaBridge 189:f392fc9709a3 765 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
AnnaBridge 189:f392fc9709a3 766 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
AnnaBridge 189:f392fc9709a3 767 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
AnnaBridge 189:f392fc9709a3 768 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
AnnaBridge 189:f392fc9709a3 769 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
AnnaBridge 189:f392fc9709a3 770 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
AnnaBridge 189:f392fc9709a3 771 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
AnnaBridge 189:f392fc9709a3 772 } AIPS_Type;
AnnaBridge 189:f392fc9709a3 773
AnnaBridge 189:f392fc9709a3 774 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 775 -- AIPS Register Masks
AnnaBridge 189:f392fc9709a3 776 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 777
AnnaBridge 189:f392fc9709a3 778 /*!
AnnaBridge 189:f392fc9709a3 779 * @addtogroup AIPS_Register_Masks AIPS Register Masks
AnnaBridge 189:f392fc9709a3 780 * @{
AnnaBridge 189:f392fc9709a3 781 */
AnnaBridge 189:f392fc9709a3 782
AnnaBridge 189:f392fc9709a3 783 /*! @name MPRA - Master Privilege Register A */
AnnaBridge 189:f392fc9709a3 784 #define AIPS_MPRA_MPL4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 785 #define AIPS_MPRA_MPL4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 786 #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
AnnaBridge 189:f392fc9709a3 787 #define AIPS_MPRA_MTW4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 788 #define AIPS_MPRA_MTW4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 789 #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
AnnaBridge 189:f392fc9709a3 790 #define AIPS_MPRA_MTR4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 791 #define AIPS_MPRA_MTR4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 792 #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
AnnaBridge 189:f392fc9709a3 793 #define AIPS_MPRA_MPL3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 794 #define AIPS_MPRA_MPL3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 795 #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
AnnaBridge 189:f392fc9709a3 796 #define AIPS_MPRA_MTW3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 797 #define AIPS_MPRA_MTW3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 798 #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
AnnaBridge 189:f392fc9709a3 799 #define AIPS_MPRA_MTR3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 800 #define AIPS_MPRA_MTR3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 801 #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
AnnaBridge 189:f392fc9709a3 802 #define AIPS_MPRA_MPL2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 803 #define AIPS_MPRA_MPL2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 804 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
AnnaBridge 189:f392fc9709a3 805 #define AIPS_MPRA_MTW2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 806 #define AIPS_MPRA_MTW2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 807 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
AnnaBridge 189:f392fc9709a3 808 #define AIPS_MPRA_MTR2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 809 #define AIPS_MPRA_MTR2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 810 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
AnnaBridge 189:f392fc9709a3 811 #define AIPS_MPRA_MPL1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 812 #define AIPS_MPRA_MPL1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 813 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
AnnaBridge 189:f392fc9709a3 814 #define AIPS_MPRA_MTW1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 815 #define AIPS_MPRA_MTW1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 816 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
AnnaBridge 189:f392fc9709a3 817 #define AIPS_MPRA_MTR1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 818 #define AIPS_MPRA_MTR1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 819 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
AnnaBridge 189:f392fc9709a3 820 #define AIPS_MPRA_MPL0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 821 #define AIPS_MPRA_MPL0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 822 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
AnnaBridge 189:f392fc9709a3 823 #define AIPS_MPRA_MTW0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 824 #define AIPS_MPRA_MTW0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 825 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
AnnaBridge 189:f392fc9709a3 826 #define AIPS_MPRA_MTR0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 827 #define AIPS_MPRA_MTR0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 828 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
AnnaBridge 189:f392fc9709a3 829
AnnaBridge 189:f392fc9709a3 830 /*! @name PACRA - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 831 #define AIPS_PACRA_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 832 #define AIPS_PACRA_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 833 #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
AnnaBridge 189:f392fc9709a3 834 #define AIPS_PACRA_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 835 #define AIPS_PACRA_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 836 #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
AnnaBridge 189:f392fc9709a3 837 #define AIPS_PACRA_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 838 #define AIPS_PACRA_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 839 #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
AnnaBridge 189:f392fc9709a3 840 #define AIPS_PACRA_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 841 #define AIPS_PACRA_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 842 #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
AnnaBridge 189:f392fc9709a3 843 #define AIPS_PACRA_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 844 #define AIPS_PACRA_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 845 #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
AnnaBridge 189:f392fc9709a3 846 #define AIPS_PACRA_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 847 #define AIPS_PACRA_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 848 #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
AnnaBridge 189:f392fc9709a3 849 #define AIPS_PACRA_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 850 #define AIPS_PACRA_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 851 #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
AnnaBridge 189:f392fc9709a3 852 #define AIPS_PACRA_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 853 #define AIPS_PACRA_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 854 #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
AnnaBridge 189:f392fc9709a3 855 #define AIPS_PACRA_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 856 #define AIPS_PACRA_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 857 #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
AnnaBridge 189:f392fc9709a3 858 #define AIPS_PACRA_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 859 #define AIPS_PACRA_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 860 #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
AnnaBridge 189:f392fc9709a3 861 #define AIPS_PACRA_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 862 #define AIPS_PACRA_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 863 #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
AnnaBridge 189:f392fc9709a3 864 #define AIPS_PACRA_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 865 #define AIPS_PACRA_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 866 #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
AnnaBridge 189:f392fc9709a3 867 #define AIPS_PACRA_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 868 #define AIPS_PACRA_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 869 #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
AnnaBridge 189:f392fc9709a3 870 #define AIPS_PACRA_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 871 #define AIPS_PACRA_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 872 #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
AnnaBridge 189:f392fc9709a3 873 #define AIPS_PACRA_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 874 #define AIPS_PACRA_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 875 #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
AnnaBridge 189:f392fc9709a3 876 #define AIPS_PACRA_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 877 #define AIPS_PACRA_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 878 #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
AnnaBridge 189:f392fc9709a3 879 #define AIPS_PACRA_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 880 #define AIPS_PACRA_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 881 #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
AnnaBridge 189:f392fc9709a3 882 #define AIPS_PACRA_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 883 #define AIPS_PACRA_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 884 #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
AnnaBridge 189:f392fc9709a3 885 #define AIPS_PACRA_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 886 #define AIPS_PACRA_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 887 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
AnnaBridge 189:f392fc9709a3 888 #define AIPS_PACRA_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 889 #define AIPS_PACRA_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 890 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
AnnaBridge 189:f392fc9709a3 891 #define AIPS_PACRA_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 892 #define AIPS_PACRA_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 893 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
AnnaBridge 189:f392fc9709a3 894 #define AIPS_PACRA_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 895 #define AIPS_PACRA_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 896 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
AnnaBridge 189:f392fc9709a3 897 #define AIPS_PACRA_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 898 #define AIPS_PACRA_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 899 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
AnnaBridge 189:f392fc9709a3 900 #define AIPS_PACRA_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 901 #define AIPS_PACRA_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 902 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
AnnaBridge 189:f392fc9709a3 903
AnnaBridge 189:f392fc9709a3 904 /*! @name PACRB - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 905 #define AIPS_PACRB_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 906 #define AIPS_PACRB_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 907 #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
AnnaBridge 189:f392fc9709a3 908 #define AIPS_PACRB_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 909 #define AIPS_PACRB_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 910 #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
AnnaBridge 189:f392fc9709a3 911 #define AIPS_PACRB_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 912 #define AIPS_PACRB_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 913 #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
AnnaBridge 189:f392fc9709a3 914 #define AIPS_PACRB_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 915 #define AIPS_PACRB_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 916 #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
AnnaBridge 189:f392fc9709a3 917 #define AIPS_PACRB_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 918 #define AIPS_PACRB_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 919 #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
AnnaBridge 189:f392fc9709a3 920 #define AIPS_PACRB_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 921 #define AIPS_PACRB_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 922 #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
AnnaBridge 189:f392fc9709a3 923 #define AIPS_PACRB_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 924 #define AIPS_PACRB_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 925 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
AnnaBridge 189:f392fc9709a3 926 #define AIPS_PACRB_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 927 #define AIPS_PACRB_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 928 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
AnnaBridge 189:f392fc9709a3 929 #define AIPS_PACRB_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 930 #define AIPS_PACRB_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 931 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
AnnaBridge 189:f392fc9709a3 932 #define AIPS_PACRB_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 933 #define AIPS_PACRB_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 934 #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
AnnaBridge 189:f392fc9709a3 935 #define AIPS_PACRB_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 936 #define AIPS_PACRB_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 937 #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
AnnaBridge 189:f392fc9709a3 938 #define AIPS_PACRB_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 939 #define AIPS_PACRB_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 940 #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
AnnaBridge 189:f392fc9709a3 941 #define AIPS_PACRB_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 942 #define AIPS_PACRB_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 943 #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
AnnaBridge 189:f392fc9709a3 944 #define AIPS_PACRB_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 945 #define AIPS_PACRB_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 946 #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
AnnaBridge 189:f392fc9709a3 947 #define AIPS_PACRB_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 948 #define AIPS_PACRB_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 949 #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
AnnaBridge 189:f392fc9709a3 950 #define AIPS_PACRB_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 951 #define AIPS_PACRB_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 952 #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
AnnaBridge 189:f392fc9709a3 953 #define AIPS_PACRB_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 954 #define AIPS_PACRB_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 955 #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
AnnaBridge 189:f392fc9709a3 956 #define AIPS_PACRB_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 957 #define AIPS_PACRB_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 958 #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
AnnaBridge 189:f392fc9709a3 959 #define AIPS_PACRB_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 960 #define AIPS_PACRB_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 961 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
AnnaBridge 189:f392fc9709a3 962 #define AIPS_PACRB_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 963 #define AIPS_PACRB_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 964 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
AnnaBridge 189:f392fc9709a3 965 #define AIPS_PACRB_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 966 #define AIPS_PACRB_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 967 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
AnnaBridge 189:f392fc9709a3 968 #define AIPS_PACRB_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 969 #define AIPS_PACRB_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 970 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
AnnaBridge 189:f392fc9709a3 971 #define AIPS_PACRB_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 972 #define AIPS_PACRB_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 973 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
AnnaBridge 189:f392fc9709a3 974 #define AIPS_PACRB_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 975 #define AIPS_PACRB_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 976 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
AnnaBridge 189:f392fc9709a3 977
AnnaBridge 189:f392fc9709a3 978 /*! @name PACRC - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 979 #define AIPS_PACRC_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 980 #define AIPS_PACRC_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 981 #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
AnnaBridge 189:f392fc9709a3 982 #define AIPS_PACRC_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 983 #define AIPS_PACRC_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 984 #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
AnnaBridge 189:f392fc9709a3 985 #define AIPS_PACRC_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 986 #define AIPS_PACRC_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 987 #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
AnnaBridge 189:f392fc9709a3 988 #define AIPS_PACRC_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 989 #define AIPS_PACRC_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 990 #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
AnnaBridge 189:f392fc9709a3 991 #define AIPS_PACRC_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 992 #define AIPS_PACRC_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 993 #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
AnnaBridge 189:f392fc9709a3 994 #define AIPS_PACRC_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 995 #define AIPS_PACRC_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 996 #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
AnnaBridge 189:f392fc9709a3 997 #define AIPS_PACRC_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 998 #define AIPS_PACRC_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 999 #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1000 #define AIPS_PACRC_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1001 #define AIPS_PACRC_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1002 #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1003 #define AIPS_PACRC_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1004 #define AIPS_PACRC_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1005 #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1006 #define AIPS_PACRC_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1007 #define AIPS_PACRC_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1008 #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1009 #define AIPS_PACRC_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1010 #define AIPS_PACRC_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1011 #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1012 #define AIPS_PACRC_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1013 #define AIPS_PACRC_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1014 #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1015 #define AIPS_PACRC_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1016 #define AIPS_PACRC_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1017 #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1018 #define AIPS_PACRC_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1019 #define AIPS_PACRC_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1020 #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1021 #define AIPS_PACRC_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1022 #define AIPS_PACRC_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1023 #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1024 #define AIPS_PACRC_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1025 #define AIPS_PACRC_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1026 #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1027 #define AIPS_PACRC_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1028 #define AIPS_PACRC_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1029 #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1030 #define AIPS_PACRC_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1031 #define AIPS_PACRC_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1032 #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1033 #define AIPS_PACRC_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1034 #define AIPS_PACRC_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1035 #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1036 #define AIPS_PACRC_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1037 #define AIPS_PACRC_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1038 #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1039 #define AIPS_PACRC_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1040 #define AIPS_PACRC_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1041 #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1042 #define AIPS_PACRC_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1043 #define AIPS_PACRC_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1044 #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1045 #define AIPS_PACRC_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1046 #define AIPS_PACRC_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1047 #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1048 #define AIPS_PACRC_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1049 #define AIPS_PACRC_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1050 #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1051
AnnaBridge 189:f392fc9709a3 1052 /*! @name PACRD - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1053 #define AIPS_PACRD_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1054 #define AIPS_PACRD_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1055 #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1056 #define AIPS_PACRD_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1057 #define AIPS_PACRD_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1058 #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1059 #define AIPS_PACRD_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1060 #define AIPS_PACRD_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1061 #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1062 #define AIPS_PACRD_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1063 #define AIPS_PACRD_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1064 #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1065 #define AIPS_PACRD_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1066 #define AIPS_PACRD_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1067 #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1068 #define AIPS_PACRD_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1069 #define AIPS_PACRD_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1070 #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1071 #define AIPS_PACRD_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1072 #define AIPS_PACRD_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1073 #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1074 #define AIPS_PACRD_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1075 #define AIPS_PACRD_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1076 #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1077 #define AIPS_PACRD_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1078 #define AIPS_PACRD_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1079 #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1080 #define AIPS_PACRD_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1081 #define AIPS_PACRD_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1082 #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1083 #define AIPS_PACRD_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1084 #define AIPS_PACRD_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1085 #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1086 #define AIPS_PACRD_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1087 #define AIPS_PACRD_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1088 #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1089 #define AIPS_PACRD_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1090 #define AIPS_PACRD_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1091 #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1092 #define AIPS_PACRD_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1093 #define AIPS_PACRD_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1094 #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1095 #define AIPS_PACRD_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1096 #define AIPS_PACRD_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1097 #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1098 #define AIPS_PACRD_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1099 #define AIPS_PACRD_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1100 #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1101 #define AIPS_PACRD_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1102 #define AIPS_PACRD_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1103 #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1104 #define AIPS_PACRD_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1105 #define AIPS_PACRD_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1106 #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1107 #define AIPS_PACRD_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1108 #define AIPS_PACRD_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1109 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1110 #define AIPS_PACRD_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1111 #define AIPS_PACRD_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1112 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1113 #define AIPS_PACRD_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1114 #define AIPS_PACRD_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1115 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1116 #define AIPS_PACRD_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1117 #define AIPS_PACRD_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1118 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1119 #define AIPS_PACRD_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1120 #define AIPS_PACRD_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1121 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1122 #define AIPS_PACRD_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1123 #define AIPS_PACRD_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1124 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1125
AnnaBridge 189:f392fc9709a3 1126 /*! @name PACRE - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1127 #define AIPS_PACRE_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1128 #define AIPS_PACRE_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1129 #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1130 #define AIPS_PACRE_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1131 #define AIPS_PACRE_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1132 #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1133 #define AIPS_PACRE_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1134 #define AIPS_PACRE_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1135 #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1136 #define AIPS_PACRE_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1137 #define AIPS_PACRE_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1138 #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1139 #define AIPS_PACRE_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1140 #define AIPS_PACRE_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1141 #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1142 #define AIPS_PACRE_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1143 #define AIPS_PACRE_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1144 #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1145 #define AIPS_PACRE_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1146 #define AIPS_PACRE_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1147 #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1148 #define AIPS_PACRE_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1149 #define AIPS_PACRE_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1150 #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1151 #define AIPS_PACRE_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1152 #define AIPS_PACRE_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1153 #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1154 #define AIPS_PACRE_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1155 #define AIPS_PACRE_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1156 #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1157 #define AIPS_PACRE_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1158 #define AIPS_PACRE_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1159 #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1160 #define AIPS_PACRE_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1161 #define AIPS_PACRE_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1162 #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1163 #define AIPS_PACRE_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1164 #define AIPS_PACRE_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1165 #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1166 #define AIPS_PACRE_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1167 #define AIPS_PACRE_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1168 #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1169 #define AIPS_PACRE_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1170 #define AIPS_PACRE_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1171 #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1172 #define AIPS_PACRE_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1173 #define AIPS_PACRE_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1174 #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1175 #define AIPS_PACRE_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1176 #define AIPS_PACRE_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1177 #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1178 #define AIPS_PACRE_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1179 #define AIPS_PACRE_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1180 #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1181 #define AIPS_PACRE_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1182 #define AIPS_PACRE_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1183 #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1184 #define AIPS_PACRE_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1185 #define AIPS_PACRE_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1186 #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1187 #define AIPS_PACRE_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1188 #define AIPS_PACRE_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1189 #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1190 #define AIPS_PACRE_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1191 #define AIPS_PACRE_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1192 #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1193 #define AIPS_PACRE_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1194 #define AIPS_PACRE_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1195 #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1196 #define AIPS_PACRE_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1197 #define AIPS_PACRE_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1198 #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1199
AnnaBridge 189:f392fc9709a3 1200 /*! @name PACRF - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1201 #define AIPS_PACRF_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1202 #define AIPS_PACRF_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1203 #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1204 #define AIPS_PACRF_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1205 #define AIPS_PACRF_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1206 #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1207 #define AIPS_PACRF_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1208 #define AIPS_PACRF_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1209 #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1210 #define AIPS_PACRF_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1211 #define AIPS_PACRF_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1212 #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1213 #define AIPS_PACRF_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1214 #define AIPS_PACRF_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1215 #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1216 #define AIPS_PACRF_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1217 #define AIPS_PACRF_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1218 #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1219 #define AIPS_PACRF_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1220 #define AIPS_PACRF_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1221 #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1222 #define AIPS_PACRF_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1223 #define AIPS_PACRF_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1224 #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1225 #define AIPS_PACRF_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1226 #define AIPS_PACRF_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1227 #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1228 #define AIPS_PACRF_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1229 #define AIPS_PACRF_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1230 #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1231 #define AIPS_PACRF_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1232 #define AIPS_PACRF_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1233 #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1234 #define AIPS_PACRF_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1235 #define AIPS_PACRF_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1236 #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1237 #define AIPS_PACRF_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1238 #define AIPS_PACRF_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1239 #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1240 #define AIPS_PACRF_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1241 #define AIPS_PACRF_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1242 #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1243 #define AIPS_PACRF_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1244 #define AIPS_PACRF_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1245 #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1246 #define AIPS_PACRF_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1247 #define AIPS_PACRF_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1248 #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1249 #define AIPS_PACRF_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1250 #define AIPS_PACRF_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1251 #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1252 #define AIPS_PACRF_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1253 #define AIPS_PACRF_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1254 #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1255 #define AIPS_PACRF_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1256 #define AIPS_PACRF_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1257 #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1258 #define AIPS_PACRF_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1259 #define AIPS_PACRF_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1260 #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1261 #define AIPS_PACRF_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1262 #define AIPS_PACRF_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1263 #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1264 #define AIPS_PACRF_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1265 #define AIPS_PACRF_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1266 #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1267 #define AIPS_PACRF_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1268 #define AIPS_PACRF_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1269 #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1270 #define AIPS_PACRF_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1271 #define AIPS_PACRF_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1272 #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1273
AnnaBridge 189:f392fc9709a3 1274 /*! @name PACRG - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1275 #define AIPS_PACRG_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1276 #define AIPS_PACRG_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1277 #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1278 #define AIPS_PACRG_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1279 #define AIPS_PACRG_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1280 #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1281 #define AIPS_PACRG_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1282 #define AIPS_PACRG_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1283 #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1284 #define AIPS_PACRG_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1285 #define AIPS_PACRG_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1286 #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1287 #define AIPS_PACRG_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1288 #define AIPS_PACRG_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1289 #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1290 #define AIPS_PACRG_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1291 #define AIPS_PACRG_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1292 #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1293 #define AIPS_PACRG_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1294 #define AIPS_PACRG_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1295 #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1296 #define AIPS_PACRG_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1297 #define AIPS_PACRG_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1298 #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1299 #define AIPS_PACRG_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1300 #define AIPS_PACRG_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1301 #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1302 #define AIPS_PACRG_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1303 #define AIPS_PACRG_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1304 #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1305 #define AIPS_PACRG_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1306 #define AIPS_PACRG_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1307 #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1308 #define AIPS_PACRG_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1309 #define AIPS_PACRG_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1310 #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1311 #define AIPS_PACRG_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1312 #define AIPS_PACRG_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1313 #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1314 #define AIPS_PACRG_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1315 #define AIPS_PACRG_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1316 #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1317 #define AIPS_PACRG_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1318 #define AIPS_PACRG_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1319 #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1320 #define AIPS_PACRG_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1321 #define AIPS_PACRG_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1322 #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1323 #define AIPS_PACRG_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1324 #define AIPS_PACRG_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1325 #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1326 #define AIPS_PACRG_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1327 #define AIPS_PACRG_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1328 #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1329 #define AIPS_PACRG_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1330 #define AIPS_PACRG_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1331 #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1332 #define AIPS_PACRG_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1333 #define AIPS_PACRG_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1334 #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1335 #define AIPS_PACRG_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1336 #define AIPS_PACRG_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1337 #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1338 #define AIPS_PACRG_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1339 #define AIPS_PACRG_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1340 #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1341 #define AIPS_PACRG_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1342 #define AIPS_PACRG_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1343 #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1344 #define AIPS_PACRG_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1345 #define AIPS_PACRG_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1346 #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1347
AnnaBridge 189:f392fc9709a3 1348 /*! @name PACRH - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1349 #define AIPS_PACRH_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1350 #define AIPS_PACRH_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1351 #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1352 #define AIPS_PACRH_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1353 #define AIPS_PACRH_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1354 #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1355 #define AIPS_PACRH_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1356 #define AIPS_PACRH_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1357 #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1358 #define AIPS_PACRH_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1359 #define AIPS_PACRH_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1360 #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1361 #define AIPS_PACRH_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1362 #define AIPS_PACRH_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1363 #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1364 #define AIPS_PACRH_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1365 #define AIPS_PACRH_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1366 #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1367 #define AIPS_PACRH_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1368 #define AIPS_PACRH_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1369 #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1370 #define AIPS_PACRH_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1371 #define AIPS_PACRH_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1372 #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1373 #define AIPS_PACRH_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1374 #define AIPS_PACRH_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1375 #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1376 #define AIPS_PACRH_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1377 #define AIPS_PACRH_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1378 #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1379 #define AIPS_PACRH_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1380 #define AIPS_PACRH_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1381 #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1382 #define AIPS_PACRH_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1383 #define AIPS_PACRH_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1384 #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1385 #define AIPS_PACRH_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1386 #define AIPS_PACRH_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1387 #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1388 #define AIPS_PACRH_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1389 #define AIPS_PACRH_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1390 #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1391 #define AIPS_PACRH_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1392 #define AIPS_PACRH_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1393 #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1394 #define AIPS_PACRH_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1395 #define AIPS_PACRH_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1396 #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1397 #define AIPS_PACRH_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1398 #define AIPS_PACRH_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1399 #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1400 #define AIPS_PACRH_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1401 #define AIPS_PACRH_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1402 #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1403 #define AIPS_PACRH_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1404 #define AIPS_PACRH_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1405 #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1406 #define AIPS_PACRH_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1407 #define AIPS_PACRH_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1408 #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1409 #define AIPS_PACRH_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1410 #define AIPS_PACRH_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1411 #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1412 #define AIPS_PACRH_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1413 #define AIPS_PACRH_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1414 #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1415 #define AIPS_PACRH_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1416 #define AIPS_PACRH_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1417 #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1418 #define AIPS_PACRH_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1419 #define AIPS_PACRH_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1420 #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1421
AnnaBridge 189:f392fc9709a3 1422 /*! @name PACRI - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1423 #define AIPS_PACRI_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1424 #define AIPS_PACRI_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1425 #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1426 #define AIPS_PACRI_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1427 #define AIPS_PACRI_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1428 #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1429 #define AIPS_PACRI_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1430 #define AIPS_PACRI_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1431 #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1432 #define AIPS_PACRI_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1433 #define AIPS_PACRI_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1434 #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1435 #define AIPS_PACRI_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1436 #define AIPS_PACRI_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1437 #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1438 #define AIPS_PACRI_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1439 #define AIPS_PACRI_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1440 #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1441 #define AIPS_PACRI_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1442 #define AIPS_PACRI_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1443 #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1444 #define AIPS_PACRI_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1445 #define AIPS_PACRI_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1446 #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1447 #define AIPS_PACRI_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1448 #define AIPS_PACRI_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1449 #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1450 #define AIPS_PACRI_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1451 #define AIPS_PACRI_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1452 #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1453 #define AIPS_PACRI_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1454 #define AIPS_PACRI_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1455 #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1456 #define AIPS_PACRI_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1457 #define AIPS_PACRI_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1458 #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1459 #define AIPS_PACRI_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1460 #define AIPS_PACRI_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1461 #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1462 #define AIPS_PACRI_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1463 #define AIPS_PACRI_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1464 #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1465 #define AIPS_PACRI_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1466 #define AIPS_PACRI_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1467 #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1468 #define AIPS_PACRI_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1469 #define AIPS_PACRI_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1470 #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1471 #define AIPS_PACRI_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1472 #define AIPS_PACRI_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1473 #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1474 #define AIPS_PACRI_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1475 #define AIPS_PACRI_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1476 #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1477 #define AIPS_PACRI_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1478 #define AIPS_PACRI_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1479 #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1480 #define AIPS_PACRI_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1481 #define AIPS_PACRI_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1482 #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1483 #define AIPS_PACRI_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1484 #define AIPS_PACRI_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1485 #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1486 #define AIPS_PACRI_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1487 #define AIPS_PACRI_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1488 #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1489 #define AIPS_PACRI_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1490 #define AIPS_PACRI_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1491 #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1492 #define AIPS_PACRI_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1493 #define AIPS_PACRI_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1494 #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1495
AnnaBridge 189:f392fc9709a3 1496 /*! @name PACRJ - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1497 #define AIPS_PACRJ_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1498 #define AIPS_PACRJ_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1499 #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1500 #define AIPS_PACRJ_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1501 #define AIPS_PACRJ_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1502 #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1503 #define AIPS_PACRJ_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1504 #define AIPS_PACRJ_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1505 #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1506 #define AIPS_PACRJ_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1507 #define AIPS_PACRJ_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1508 #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1509 #define AIPS_PACRJ_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1510 #define AIPS_PACRJ_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1511 #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1512 #define AIPS_PACRJ_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1513 #define AIPS_PACRJ_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1514 #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1515 #define AIPS_PACRJ_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1516 #define AIPS_PACRJ_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1517 #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1518 #define AIPS_PACRJ_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1519 #define AIPS_PACRJ_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1520 #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1521 #define AIPS_PACRJ_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1522 #define AIPS_PACRJ_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1523 #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1524 #define AIPS_PACRJ_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1525 #define AIPS_PACRJ_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1526 #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1527 #define AIPS_PACRJ_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1528 #define AIPS_PACRJ_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1529 #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1530 #define AIPS_PACRJ_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1531 #define AIPS_PACRJ_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1532 #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1533 #define AIPS_PACRJ_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1534 #define AIPS_PACRJ_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1535 #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1536 #define AIPS_PACRJ_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1537 #define AIPS_PACRJ_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1538 #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1539 #define AIPS_PACRJ_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1540 #define AIPS_PACRJ_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1541 #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1542 #define AIPS_PACRJ_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1543 #define AIPS_PACRJ_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1544 #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1545 #define AIPS_PACRJ_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1546 #define AIPS_PACRJ_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1547 #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1548 #define AIPS_PACRJ_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1549 #define AIPS_PACRJ_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1550 #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1551 #define AIPS_PACRJ_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1552 #define AIPS_PACRJ_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1553 #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1554 #define AIPS_PACRJ_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1555 #define AIPS_PACRJ_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1556 #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1557 #define AIPS_PACRJ_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1558 #define AIPS_PACRJ_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1559 #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1560 #define AIPS_PACRJ_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1561 #define AIPS_PACRJ_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1562 #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1563 #define AIPS_PACRJ_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1564 #define AIPS_PACRJ_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1565 #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1566 #define AIPS_PACRJ_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1567 #define AIPS_PACRJ_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1568 #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1569
AnnaBridge 189:f392fc9709a3 1570 /*! @name PACRK - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1571 #define AIPS_PACRK_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1572 #define AIPS_PACRK_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1573 #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1574 #define AIPS_PACRK_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1575 #define AIPS_PACRK_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1576 #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1577 #define AIPS_PACRK_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1578 #define AIPS_PACRK_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1579 #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1580 #define AIPS_PACRK_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1581 #define AIPS_PACRK_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1582 #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1583 #define AIPS_PACRK_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1584 #define AIPS_PACRK_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1585 #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1586 #define AIPS_PACRK_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1587 #define AIPS_PACRK_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1588 #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1589 #define AIPS_PACRK_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1590 #define AIPS_PACRK_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1591 #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1592 #define AIPS_PACRK_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1593 #define AIPS_PACRK_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1594 #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1595 #define AIPS_PACRK_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1596 #define AIPS_PACRK_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1597 #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1598 #define AIPS_PACRK_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1599 #define AIPS_PACRK_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1600 #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1601 #define AIPS_PACRK_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1602 #define AIPS_PACRK_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1603 #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1604 #define AIPS_PACRK_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1605 #define AIPS_PACRK_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1606 #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1607 #define AIPS_PACRK_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1608 #define AIPS_PACRK_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1609 #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1610 #define AIPS_PACRK_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1611 #define AIPS_PACRK_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1612 #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1613 #define AIPS_PACRK_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1614 #define AIPS_PACRK_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1615 #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1616 #define AIPS_PACRK_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1617 #define AIPS_PACRK_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1618 #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1619 #define AIPS_PACRK_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1620 #define AIPS_PACRK_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1621 #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1622 #define AIPS_PACRK_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1623 #define AIPS_PACRK_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1624 #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1625 #define AIPS_PACRK_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1626 #define AIPS_PACRK_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1627 #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1628 #define AIPS_PACRK_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1629 #define AIPS_PACRK_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1630 #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1631 #define AIPS_PACRK_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1632 #define AIPS_PACRK_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1633 #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1634 #define AIPS_PACRK_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1635 #define AIPS_PACRK_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1636 #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1637 #define AIPS_PACRK_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1638 #define AIPS_PACRK_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1639 #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1640 #define AIPS_PACRK_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1641 #define AIPS_PACRK_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1642 #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1643
AnnaBridge 189:f392fc9709a3 1644 /*! @name PACRL - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1645 #define AIPS_PACRL_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1646 #define AIPS_PACRL_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1647 #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1648 #define AIPS_PACRL_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1649 #define AIPS_PACRL_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1650 #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1651 #define AIPS_PACRL_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1652 #define AIPS_PACRL_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1653 #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1654 #define AIPS_PACRL_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1655 #define AIPS_PACRL_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1656 #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1657 #define AIPS_PACRL_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1658 #define AIPS_PACRL_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1659 #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1660 #define AIPS_PACRL_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1661 #define AIPS_PACRL_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1662 #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1663 #define AIPS_PACRL_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1664 #define AIPS_PACRL_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1665 #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1666 #define AIPS_PACRL_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1667 #define AIPS_PACRL_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1668 #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1669 #define AIPS_PACRL_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1670 #define AIPS_PACRL_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1671 #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1672 #define AIPS_PACRL_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1673 #define AIPS_PACRL_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1674 #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1675 #define AIPS_PACRL_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1676 #define AIPS_PACRL_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1677 #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1678 #define AIPS_PACRL_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1679 #define AIPS_PACRL_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1680 #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1681 #define AIPS_PACRL_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1682 #define AIPS_PACRL_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1683 #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1684 #define AIPS_PACRL_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1685 #define AIPS_PACRL_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1686 #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1687 #define AIPS_PACRL_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1688 #define AIPS_PACRL_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1689 #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1690 #define AIPS_PACRL_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1691 #define AIPS_PACRL_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1692 #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1693 #define AIPS_PACRL_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1694 #define AIPS_PACRL_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1695 #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1696 #define AIPS_PACRL_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1697 #define AIPS_PACRL_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1698 #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1699 #define AIPS_PACRL_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1700 #define AIPS_PACRL_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1701 #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1702 #define AIPS_PACRL_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1703 #define AIPS_PACRL_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1704 #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1705 #define AIPS_PACRL_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1706 #define AIPS_PACRL_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1707 #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1708 #define AIPS_PACRL_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1709 #define AIPS_PACRL_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1710 #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1711 #define AIPS_PACRL_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1712 #define AIPS_PACRL_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1713 #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1714 #define AIPS_PACRL_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1715 #define AIPS_PACRL_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1716 #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1717
AnnaBridge 189:f392fc9709a3 1718 /*! @name PACRM - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1719 #define AIPS_PACRM_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1720 #define AIPS_PACRM_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1721 #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1722 #define AIPS_PACRM_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1723 #define AIPS_PACRM_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1724 #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1725 #define AIPS_PACRM_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1726 #define AIPS_PACRM_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1727 #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1728 #define AIPS_PACRM_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1729 #define AIPS_PACRM_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1730 #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1731 #define AIPS_PACRM_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1732 #define AIPS_PACRM_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1733 #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1734 #define AIPS_PACRM_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1735 #define AIPS_PACRM_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1736 #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1737 #define AIPS_PACRM_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1738 #define AIPS_PACRM_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1739 #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1740 #define AIPS_PACRM_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1741 #define AIPS_PACRM_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1742 #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1743 #define AIPS_PACRM_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1744 #define AIPS_PACRM_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1745 #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1746 #define AIPS_PACRM_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1747 #define AIPS_PACRM_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1748 #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1749 #define AIPS_PACRM_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1750 #define AIPS_PACRM_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1751 #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1752 #define AIPS_PACRM_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1753 #define AIPS_PACRM_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1754 #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1755 #define AIPS_PACRM_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1756 #define AIPS_PACRM_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1757 #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1758 #define AIPS_PACRM_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1759 #define AIPS_PACRM_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1760 #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1761 #define AIPS_PACRM_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1762 #define AIPS_PACRM_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1763 #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1764 #define AIPS_PACRM_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1765 #define AIPS_PACRM_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1766 #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1767 #define AIPS_PACRM_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1768 #define AIPS_PACRM_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1769 #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1770 #define AIPS_PACRM_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1771 #define AIPS_PACRM_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1772 #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1773 #define AIPS_PACRM_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1774 #define AIPS_PACRM_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1775 #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1776 #define AIPS_PACRM_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1777 #define AIPS_PACRM_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1778 #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1779 #define AIPS_PACRM_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1780 #define AIPS_PACRM_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1781 #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1782 #define AIPS_PACRM_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1783 #define AIPS_PACRM_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1784 #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1785 #define AIPS_PACRM_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1786 #define AIPS_PACRM_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1787 #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1788 #define AIPS_PACRM_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1789 #define AIPS_PACRM_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1790 #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1791
AnnaBridge 189:f392fc9709a3 1792 /*! @name PACRN - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1793 #define AIPS_PACRN_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1794 #define AIPS_PACRN_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1795 #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1796 #define AIPS_PACRN_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1797 #define AIPS_PACRN_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1798 #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1799 #define AIPS_PACRN_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1800 #define AIPS_PACRN_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1801 #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1802 #define AIPS_PACRN_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1803 #define AIPS_PACRN_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1804 #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1805 #define AIPS_PACRN_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1806 #define AIPS_PACRN_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1807 #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1808 #define AIPS_PACRN_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1809 #define AIPS_PACRN_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1810 #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1811 #define AIPS_PACRN_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1812 #define AIPS_PACRN_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1813 #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1814 #define AIPS_PACRN_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1815 #define AIPS_PACRN_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1816 #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1817 #define AIPS_PACRN_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1818 #define AIPS_PACRN_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1819 #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1820 #define AIPS_PACRN_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1821 #define AIPS_PACRN_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1822 #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1823 #define AIPS_PACRN_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1824 #define AIPS_PACRN_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1825 #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1826 #define AIPS_PACRN_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1827 #define AIPS_PACRN_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1828 #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1829 #define AIPS_PACRN_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1830 #define AIPS_PACRN_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1831 #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1832 #define AIPS_PACRN_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1833 #define AIPS_PACRN_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1834 #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1835 #define AIPS_PACRN_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1836 #define AIPS_PACRN_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1837 #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1838 #define AIPS_PACRN_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1839 #define AIPS_PACRN_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1840 #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1841 #define AIPS_PACRN_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1842 #define AIPS_PACRN_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1843 #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1844 #define AIPS_PACRN_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1845 #define AIPS_PACRN_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1846 #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1847 #define AIPS_PACRN_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1848 #define AIPS_PACRN_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1849 #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1850 #define AIPS_PACRN_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1851 #define AIPS_PACRN_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1852 #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1853 #define AIPS_PACRN_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1854 #define AIPS_PACRN_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1855 #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1856 #define AIPS_PACRN_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1857 #define AIPS_PACRN_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1858 #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1859 #define AIPS_PACRN_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1860 #define AIPS_PACRN_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1861 #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1862 #define AIPS_PACRN_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1863 #define AIPS_PACRN_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1864 #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1865
AnnaBridge 189:f392fc9709a3 1866 /*! @name PACRO - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1867 #define AIPS_PACRO_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1868 #define AIPS_PACRO_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1869 #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1870 #define AIPS_PACRO_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1871 #define AIPS_PACRO_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1872 #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1873 #define AIPS_PACRO_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1874 #define AIPS_PACRO_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1875 #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1876 #define AIPS_PACRO_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1877 #define AIPS_PACRO_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1878 #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1879 #define AIPS_PACRO_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1880 #define AIPS_PACRO_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1881 #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1882 #define AIPS_PACRO_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1883 #define AIPS_PACRO_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1884 #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1885 #define AIPS_PACRO_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1886 #define AIPS_PACRO_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1887 #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1888 #define AIPS_PACRO_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1889 #define AIPS_PACRO_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1890 #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1891 #define AIPS_PACRO_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1892 #define AIPS_PACRO_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1893 #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1894 #define AIPS_PACRO_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1895 #define AIPS_PACRO_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1896 #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1897 #define AIPS_PACRO_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1898 #define AIPS_PACRO_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1899 #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1900 #define AIPS_PACRO_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1901 #define AIPS_PACRO_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1902 #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1903 #define AIPS_PACRO_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1904 #define AIPS_PACRO_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1905 #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1906 #define AIPS_PACRO_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1907 #define AIPS_PACRO_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1908 #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1909 #define AIPS_PACRO_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1910 #define AIPS_PACRO_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1911 #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1912 #define AIPS_PACRO_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1913 #define AIPS_PACRO_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1914 #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1915 #define AIPS_PACRO_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1916 #define AIPS_PACRO_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1917 #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1918 #define AIPS_PACRO_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1919 #define AIPS_PACRO_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1920 #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1921 #define AIPS_PACRO_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1922 #define AIPS_PACRO_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1923 #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1924 #define AIPS_PACRO_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1925 #define AIPS_PACRO_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 1926 #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
AnnaBridge 189:f392fc9709a3 1927 #define AIPS_PACRO_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 1928 #define AIPS_PACRO_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 1929 #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
AnnaBridge 189:f392fc9709a3 1930 #define AIPS_PACRO_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 1931 #define AIPS_PACRO_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 1932 #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
AnnaBridge 189:f392fc9709a3 1933 #define AIPS_PACRO_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 1934 #define AIPS_PACRO_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 1935 #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
AnnaBridge 189:f392fc9709a3 1936 #define AIPS_PACRO_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 1937 #define AIPS_PACRO_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 1938 #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
AnnaBridge 189:f392fc9709a3 1939
AnnaBridge 189:f392fc9709a3 1940 /*! @name PACRP - Peripheral Access Control Register */
AnnaBridge 189:f392fc9709a3 1941 #define AIPS_PACRP_TP7_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 1942 #define AIPS_PACRP_TP7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 1943 #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
AnnaBridge 189:f392fc9709a3 1944 #define AIPS_PACRP_WP7_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 1945 #define AIPS_PACRP_WP7_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 1946 #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
AnnaBridge 189:f392fc9709a3 1947 #define AIPS_PACRP_SP7_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 1948 #define AIPS_PACRP_SP7_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 1949 #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
AnnaBridge 189:f392fc9709a3 1950 #define AIPS_PACRP_TP6_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 1951 #define AIPS_PACRP_TP6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 1952 #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
AnnaBridge 189:f392fc9709a3 1953 #define AIPS_PACRP_WP6_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 1954 #define AIPS_PACRP_WP6_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 1955 #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
AnnaBridge 189:f392fc9709a3 1956 #define AIPS_PACRP_SP6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 1957 #define AIPS_PACRP_SP6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 1958 #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
AnnaBridge 189:f392fc9709a3 1959 #define AIPS_PACRP_TP5_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 1960 #define AIPS_PACRP_TP5_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 1961 #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
AnnaBridge 189:f392fc9709a3 1962 #define AIPS_PACRP_WP5_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 1963 #define AIPS_PACRP_WP5_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 1964 #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
AnnaBridge 189:f392fc9709a3 1965 #define AIPS_PACRP_SP5_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 1966 #define AIPS_PACRP_SP5_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 1967 #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
AnnaBridge 189:f392fc9709a3 1968 #define AIPS_PACRP_TP4_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 1969 #define AIPS_PACRP_TP4_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 1970 #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
AnnaBridge 189:f392fc9709a3 1971 #define AIPS_PACRP_WP4_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 1972 #define AIPS_PACRP_WP4_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 1973 #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
AnnaBridge 189:f392fc9709a3 1974 #define AIPS_PACRP_SP4_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 1975 #define AIPS_PACRP_SP4_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 1976 #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
AnnaBridge 189:f392fc9709a3 1977 #define AIPS_PACRP_TP3_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 1978 #define AIPS_PACRP_TP3_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 1979 #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
AnnaBridge 189:f392fc9709a3 1980 #define AIPS_PACRP_WP3_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 1981 #define AIPS_PACRP_WP3_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 1982 #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
AnnaBridge 189:f392fc9709a3 1983 #define AIPS_PACRP_SP3_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 1984 #define AIPS_PACRP_SP3_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 1985 #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
AnnaBridge 189:f392fc9709a3 1986 #define AIPS_PACRP_TP2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 1987 #define AIPS_PACRP_TP2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 1988 #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
AnnaBridge 189:f392fc9709a3 1989 #define AIPS_PACRP_WP2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 1990 #define AIPS_PACRP_WP2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 1991 #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
AnnaBridge 189:f392fc9709a3 1992 #define AIPS_PACRP_SP2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 1993 #define AIPS_PACRP_SP2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 1994 #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
AnnaBridge 189:f392fc9709a3 1995 #define AIPS_PACRP_TP1_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 1996 #define AIPS_PACRP_TP1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 1997 #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
AnnaBridge 189:f392fc9709a3 1998 #define AIPS_PACRP_WP1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 1999 #define AIPS_PACRP_WP1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 2000 #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
AnnaBridge 189:f392fc9709a3 2001 #define AIPS_PACRP_SP1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 2002 #define AIPS_PACRP_SP1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 2003 #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
AnnaBridge 189:f392fc9709a3 2004 #define AIPS_PACRP_TP0_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 2005 #define AIPS_PACRP_TP0_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2006 #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
AnnaBridge 189:f392fc9709a3 2007 #define AIPS_PACRP_WP0_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 2008 #define AIPS_PACRP_WP0_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 2009 #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
AnnaBridge 189:f392fc9709a3 2010 #define AIPS_PACRP_SP0_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 2011 #define AIPS_PACRP_SP0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 2012 #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
AnnaBridge 189:f392fc9709a3 2013
AnnaBridge 189:f392fc9709a3 2014
AnnaBridge 189:f392fc9709a3 2015 /*!
AnnaBridge 189:f392fc9709a3 2016 * @}
AnnaBridge 189:f392fc9709a3 2017 */ /* end of group AIPS_Register_Masks */
AnnaBridge 189:f392fc9709a3 2018
AnnaBridge 189:f392fc9709a3 2019
AnnaBridge 189:f392fc9709a3 2020 /* AIPS - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 2021 /** Peripheral AIPS0 base address */
AnnaBridge 189:f392fc9709a3 2022 #define AIPS0_BASE (0x40000000u)
AnnaBridge 189:f392fc9709a3 2023 /** Peripheral AIPS0 base pointer */
AnnaBridge 189:f392fc9709a3 2024 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
AnnaBridge 189:f392fc9709a3 2025 /** Peripheral AIPS1 base address */
AnnaBridge 189:f392fc9709a3 2026 #define AIPS1_BASE (0x40080000u)
AnnaBridge 189:f392fc9709a3 2027 /** Peripheral AIPS1 base pointer */
AnnaBridge 189:f392fc9709a3 2028 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
AnnaBridge 189:f392fc9709a3 2029 /** Array initializer of AIPS peripheral base addresses */
AnnaBridge 189:f392fc9709a3 2030 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
AnnaBridge 189:f392fc9709a3 2031 /** Array initializer of AIPS peripheral base pointers */
AnnaBridge 189:f392fc9709a3 2032 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
AnnaBridge 189:f392fc9709a3 2033
AnnaBridge 189:f392fc9709a3 2034 /*!
AnnaBridge 189:f392fc9709a3 2035 * @}
AnnaBridge 189:f392fc9709a3 2036 */ /* end of group AIPS_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 2037
AnnaBridge 189:f392fc9709a3 2038
AnnaBridge 189:f392fc9709a3 2039 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2040 -- AXBS Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2041 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2042
AnnaBridge 189:f392fc9709a3 2043 /*!
AnnaBridge 189:f392fc9709a3 2044 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2045 * @{
AnnaBridge 189:f392fc9709a3 2046 */
AnnaBridge 189:f392fc9709a3 2047
AnnaBridge 189:f392fc9709a3 2048 /** AXBS - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 2049 typedef struct {
AnnaBridge 189:f392fc9709a3 2050 struct { /* offset: 0x0, array step: 0x100 */
AnnaBridge 189:f392fc9709a3 2051 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
AnnaBridge 189:f392fc9709a3 2052 uint8_t RESERVED_0[12];
AnnaBridge 189:f392fc9709a3 2053 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
AnnaBridge 189:f392fc9709a3 2054 uint8_t RESERVED_1[236];
AnnaBridge 189:f392fc9709a3 2055 } SLAVE[6];
AnnaBridge 189:f392fc9709a3 2056 uint8_t RESERVED_0[512];
AnnaBridge 189:f392fc9709a3 2057 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
AnnaBridge 189:f392fc9709a3 2058 uint8_t RESERVED_1[252];
AnnaBridge 189:f392fc9709a3 2059 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
AnnaBridge 189:f392fc9709a3 2060 uint8_t RESERVED_2[252];
AnnaBridge 189:f392fc9709a3 2061 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
AnnaBridge 189:f392fc9709a3 2062 uint8_t RESERVED_3[252];
AnnaBridge 189:f392fc9709a3 2063 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
AnnaBridge 189:f392fc9709a3 2064 uint8_t RESERVED_4[252];
AnnaBridge 189:f392fc9709a3 2065 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
AnnaBridge 189:f392fc9709a3 2066 } AXBS_Type;
AnnaBridge 189:f392fc9709a3 2067
AnnaBridge 189:f392fc9709a3 2068 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2069 -- AXBS Register Masks
AnnaBridge 189:f392fc9709a3 2070 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2071
AnnaBridge 189:f392fc9709a3 2072 /*!
AnnaBridge 189:f392fc9709a3 2073 * @addtogroup AXBS_Register_Masks AXBS Register Masks
AnnaBridge 189:f392fc9709a3 2074 * @{
AnnaBridge 189:f392fc9709a3 2075 */
AnnaBridge 189:f392fc9709a3 2076
AnnaBridge 189:f392fc9709a3 2077 /*! @name PRS - Priority Registers Slave */
AnnaBridge 189:f392fc9709a3 2078 #define AXBS_PRS_M0_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2079 #define AXBS_PRS_M0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2080 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
AnnaBridge 189:f392fc9709a3 2081 #define AXBS_PRS_M1_MASK (0x70U)
AnnaBridge 189:f392fc9709a3 2082 #define AXBS_PRS_M1_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 2083 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
AnnaBridge 189:f392fc9709a3 2084 #define AXBS_PRS_M2_MASK (0x700U)
AnnaBridge 189:f392fc9709a3 2085 #define AXBS_PRS_M2_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 2086 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
AnnaBridge 189:f392fc9709a3 2087 #define AXBS_PRS_M3_MASK (0x7000U)
AnnaBridge 189:f392fc9709a3 2088 #define AXBS_PRS_M3_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 2089 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
AnnaBridge 189:f392fc9709a3 2090 #define AXBS_PRS_M4_MASK (0x70000U)
AnnaBridge 189:f392fc9709a3 2091 #define AXBS_PRS_M4_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 2092 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
AnnaBridge 189:f392fc9709a3 2093
AnnaBridge 189:f392fc9709a3 2094 /* The count of AXBS_PRS */
AnnaBridge 189:f392fc9709a3 2095 #define AXBS_PRS_COUNT (6U)
AnnaBridge 189:f392fc9709a3 2096
AnnaBridge 189:f392fc9709a3 2097 /*! @name CRS - Control Register */
AnnaBridge 189:f392fc9709a3 2098 #define AXBS_CRS_PARK_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2099 #define AXBS_CRS_PARK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2100 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
AnnaBridge 189:f392fc9709a3 2101 #define AXBS_CRS_PCTL_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 2102 #define AXBS_CRS_PCTL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 2103 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
AnnaBridge 189:f392fc9709a3 2104 #define AXBS_CRS_ARB_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 2105 #define AXBS_CRS_ARB_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 2106 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
AnnaBridge 189:f392fc9709a3 2107 #define AXBS_CRS_HLP_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 2108 #define AXBS_CRS_HLP_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 2109 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
AnnaBridge 189:f392fc9709a3 2110 #define AXBS_CRS_RO_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 2111 #define AXBS_CRS_RO_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 2112 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
AnnaBridge 189:f392fc9709a3 2113
AnnaBridge 189:f392fc9709a3 2114 /* The count of AXBS_CRS */
AnnaBridge 189:f392fc9709a3 2115 #define AXBS_CRS_COUNT (6U)
AnnaBridge 189:f392fc9709a3 2116
AnnaBridge 189:f392fc9709a3 2117 /*! @name MGPCR0 - Master General Purpose Control Register */
AnnaBridge 189:f392fc9709a3 2118 #define AXBS_MGPCR0_AULB_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2119 #define AXBS_MGPCR0_AULB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2120 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
AnnaBridge 189:f392fc9709a3 2121
AnnaBridge 189:f392fc9709a3 2122 /*! @name MGPCR1 - Master General Purpose Control Register */
AnnaBridge 189:f392fc9709a3 2123 #define AXBS_MGPCR1_AULB_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2124 #define AXBS_MGPCR1_AULB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2125 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
AnnaBridge 189:f392fc9709a3 2126
AnnaBridge 189:f392fc9709a3 2127 /*! @name MGPCR2 - Master General Purpose Control Register */
AnnaBridge 189:f392fc9709a3 2128 #define AXBS_MGPCR2_AULB_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2129 #define AXBS_MGPCR2_AULB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2130 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
AnnaBridge 189:f392fc9709a3 2131
AnnaBridge 189:f392fc9709a3 2132 /*! @name MGPCR3 - Master General Purpose Control Register */
AnnaBridge 189:f392fc9709a3 2133 #define AXBS_MGPCR3_AULB_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2134 #define AXBS_MGPCR3_AULB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2135 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
AnnaBridge 189:f392fc9709a3 2136
AnnaBridge 189:f392fc9709a3 2137 /*! @name MGPCR4 - Master General Purpose Control Register */
AnnaBridge 189:f392fc9709a3 2138 #define AXBS_MGPCR4_AULB_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2139 #define AXBS_MGPCR4_AULB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2140 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
AnnaBridge 189:f392fc9709a3 2141
AnnaBridge 189:f392fc9709a3 2142
AnnaBridge 189:f392fc9709a3 2143 /*!
AnnaBridge 189:f392fc9709a3 2144 * @}
AnnaBridge 189:f392fc9709a3 2145 */ /* end of group AXBS_Register_Masks */
AnnaBridge 189:f392fc9709a3 2146
AnnaBridge 189:f392fc9709a3 2147
AnnaBridge 189:f392fc9709a3 2148 /* AXBS - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 2149 /** Peripheral AXBS base address */
AnnaBridge 189:f392fc9709a3 2150 #define AXBS_BASE (0x40004000u)
AnnaBridge 189:f392fc9709a3 2151 /** Peripheral AXBS base pointer */
AnnaBridge 189:f392fc9709a3 2152 #define AXBS ((AXBS_Type *)AXBS_BASE)
AnnaBridge 189:f392fc9709a3 2153 /** Array initializer of AXBS peripheral base addresses */
AnnaBridge 189:f392fc9709a3 2154 #define AXBS_BASE_ADDRS { AXBS_BASE }
AnnaBridge 189:f392fc9709a3 2155 /** Array initializer of AXBS peripheral base pointers */
AnnaBridge 189:f392fc9709a3 2156 #define AXBS_BASE_PTRS { AXBS }
AnnaBridge 189:f392fc9709a3 2157
AnnaBridge 189:f392fc9709a3 2158 /*!
AnnaBridge 189:f392fc9709a3 2159 * @}
AnnaBridge 189:f392fc9709a3 2160 */ /* end of group AXBS_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 2161
AnnaBridge 189:f392fc9709a3 2162
AnnaBridge 189:f392fc9709a3 2163 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2164 -- CAU Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2165 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2166
AnnaBridge 189:f392fc9709a3 2167 /*!
AnnaBridge 189:f392fc9709a3 2168 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2169 * @{
AnnaBridge 189:f392fc9709a3 2170 */
AnnaBridge 189:f392fc9709a3 2171
AnnaBridge 189:f392fc9709a3 2172 /** CAU - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 2173 typedef struct {
AnnaBridge 189:f392fc9709a3 2174 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2175 uint8_t RESERVED_0[2048];
AnnaBridge 189:f392fc9709a3 2176 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
AnnaBridge 189:f392fc9709a3 2177 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
AnnaBridge 189:f392fc9709a3 2178 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2179 uint8_t RESERVED_1[20];
AnnaBridge 189:f392fc9709a3 2180 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
AnnaBridge 189:f392fc9709a3 2181 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
AnnaBridge 189:f392fc9709a3 2182 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2183 uint8_t RESERVED_2[20];
AnnaBridge 189:f392fc9709a3 2184 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
AnnaBridge 189:f392fc9709a3 2185 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
AnnaBridge 189:f392fc9709a3 2186 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2187 uint8_t RESERVED_3[20];
AnnaBridge 189:f392fc9709a3 2188 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
AnnaBridge 189:f392fc9709a3 2189 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
AnnaBridge 189:f392fc9709a3 2190 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2191 uint8_t RESERVED_4[84];
AnnaBridge 189:f392fc9709a3 2192 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
AnnaBridge 189:f392fc9709a3 2193 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
AnnaBridge 189:f392fc9709a3 2194 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2195 uint8_t RESERVED_5[20];
AnnaBridge 189:f392fc9709a3 2196 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
AnnaBridge 189:f392fc9709a3 2197 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
AnnaBridge 189:f392fc9709a3 2198 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2199 uint8_t RESERVED_6[276];
AnnaBridge 189:f392fc9709a3 2200 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
AnnaBridge 189:f392fc9709a3 2201 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
AnnaBridge 189:f392fc9709a3 2202 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2203 uint8_t RESERVED_7[20];
AnnaBridge 189:f392fc9709a3 2204 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
AnnaBridge 189:f392fc9709a3 2205 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
AnnaBridge 189:f392fc9709a3 2206 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 2207 } CAU_Type;
AnnaBridge 189:f392fc9709a3 2208
AnnaBridge 189:f392fc9709a3 2209 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2210 -- CAU Register Masks
AnnaBridge 189:f392fc9709a3 2211 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2212
AnnaBridge 189:f392fc9709a3 2213 /*!
AnnaBridge 189:f392fc9709a3 2214 * @addtogroup CAU_Register_Masks CAU Register Masks
AnnaBridge 189:f392fc9709a3 2215 * @{
AnnaBridge 189:f392fc9709a3 2216 */
AnnaBridge 189:f392fc9709a3 2217
AnnaBridge 189:f392fc9709a3 2218 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
AnnaBridge 189:f392fc9709a3 2219 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2220 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2221 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
AnnaBridge 189:f392fc9709a3 2222 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2223 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2224 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
AnnaBridge 189:f392fc9709a3 2225 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2226 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2227 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
AnnaBridge 189:f392fc9709a3 2228 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2229 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2230 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
AnnaBridge 189:f392fc9709a3 2231 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2232 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2233 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
AnnaBridge 189:f392fc9709a3 2234 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2235 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2236 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
AnnaBridge 189:f392fc9709a3 2237 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2238 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2239 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
AnnaBridge 189:f392fc9709a3 2240 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2241 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2242 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
AnnaBridge 189:f392fc9709a3 2243 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2244 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2245 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
AnnaBridge 189:f392fc9709a3 2246 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2247 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2248 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
AnnaBridge 189:f392fc9709a3 2249 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2250 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2251 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
AnnaBridge 189:f392fc9709a3 2252 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2253 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2254 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
AnnaBridge 189:f392fc9709a3 2255 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2256 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2257 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
AnnaBridge 189:f392fc9709a3 2258 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2259 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2260 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
AnnaBridge 189:f392fc9709a3 2261 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2262 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2263 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
AnnaBridge 189:f392fc9709a3 2264 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2265 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2266 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
AnnaBridge 189:f392fc9709a3 2267
AnnaBridge 189:f392fc9709a3 2268 /* The count of CAU_DIRECT */
AnnaBridge 189:f392fc9709a3 2269 #define CAU_DIRECT_COUNT (16U)
AnnaBridge 189:f392fc9709a3 2270
AnnaBridge 189:f392fc9709a3 2271 /*! @name LDR_CASR - Status register - Load Register command */
AnnaBridge 189:f392fc9709a3 2272 #define CAU_LDR_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2273 #define CAU_LDR_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2274 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2275 #define CAU_LDR_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2276 #define CAU_LDR_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2277 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2278 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2279 #define CAU_LDR_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2280 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2281
AnnaBridge 189:f392fc9709a3 2282 /*! @name LDR_CAA - Accumulator register - Load Register command */
AnnaBridge 189:f392fc9709a3 2283 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2284 #define CAU_LDR_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2285 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2286
AnnaBridge 189:f392fc9709a3 2287 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
AnnaBridge 189:f392fc9709a3 2288 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2289 #define CAU_LDR_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2290 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2291 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2292 #define CAU_LDR_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2293 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2294 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2295 #define CAU_LDR_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2296 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2297 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2298 #define CAU_LDR_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2299 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2300 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2301 #define CAU_LDR_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2302 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2303 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2304 #define CAU_LDR_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2305 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2306 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2307 #define CAU_LDR_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2308 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2309 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2310 #define CAU_LDR_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2311 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2312 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2313 #define CAU_LDR_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2314 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2315
AnnaBridge 189:f392fc9709a3 2316 /* The count of CAU_LDR_CA */
AnnaBridge 189:f392fc9709a3 2317 #define CAU_LDR_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2318
AnnaBridge 189:f392fc9709a3 2319 /*! @name STR_CASR - Status register - Store Register command */
AnnaBridge 189:f392fc9709a3 2320 #define CAU_STR_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2321 #define CAU_STR_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2322 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2323 #define CAU_STR_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2324 #define CAU_STR_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2325 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2326 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2327 #define CAU_STR_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2328 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2329
AnnaBridge 189:f392fc9709a3 2330 /*! @name STR_CAA - Accumulator register - Store Register command */
AnnaBridge 189:f392fc9709a3 2331 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2332 #define CAU_STR_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2333 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2334
AnnaBridge 189:f392fc9709a3 2335 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
AnnaBridge 189:f392fc9709a3 2336 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2337 #define CAU_STR_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2338 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2339 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2340 #define CAU_STR_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2341 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2342 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2343 #define CAU_STR_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2344 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2345 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2346 #define CAU_STR_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2347 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2348 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2349 #define CAU_STR_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2350 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2351 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2352 #define CAU_STR_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2353 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2354 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2355 #define CAU_STR_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2356 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2357 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2358 #define CAU_STR_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2359 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2360 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2361 #define CAU_STR_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2362 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2363
AnnaBridge 189:f392fc9709a3 2364 /* The count of CAU_STR_CA */
AnnaBridge 189:f392fc9709a3 2365 #define CAU_STR_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2366
AnnaBridge 189:f392fc9709a3 2367 /*! @name ADR_CASR - Status register - Add Register command */
AnnaBridge 189:f392fc9709a3 2368 #define CAU_ADR_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2369 #define CAU_ADR_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2370 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2371 #define CAU_ADR_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2372 #define CAU_ADR_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2373 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2374 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2375 #define CAU_ADR_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2376 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2377
AnnaBridge 189:f392fc9709a3 2378 /*! @name ADR_CAA - Accumulator register - Add to register command */
AnnaBridge 189:f392fc9709a3 2379 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2380 #define CAU_ADR_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2381 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2382
AnnaBridge 189:f392fc9709a3 2383 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
AnnaBridge 189:f392fc9709a3 2384 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2385 #define CAU_ADR_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2386 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2387 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2388 #define CAU_ADR_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2389 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2390 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2391 #define CAU_ADR_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2392 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2393 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2394 #define CAU_ADR_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2395 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2396 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2397 #define CAU_ADR_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2398 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2399 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2400 #define CAU_ADR_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2401 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2402 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2403 #define CAU_ADR_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2404 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2405 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2406 #define CAU_ADR_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2407 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2408 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2409 #define CAU_ADR_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2410 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2411
AnnaBridge 189:f392fc9709a3 2412 /* The count of CAU_ADR_CA */
AnnaBridge 189:f392fc9709a3 2413 #define CAU_ADR_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2414
AnnaBridge 189:f392fc9709a3 2415 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
AnnaBridge 189:f392fc9709a3 2416 #define CAU_RADR_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2417 #define CAU_RADR_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2418 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2419 #define CAU_RADR_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2420 #define CAU_RADR_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2421 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2422 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2423 #define CAU_RADR_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2424 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2425
AnnaBridge 189:f392fc9709a3 2426 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
AnnaBridge 189:f392fc9709a3 2427 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2428 #define CAU_RADR_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2429 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2430
AnnaBridge 189:f392fc9709a3 2431 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
AnnaBridge 189:f392fc9709a3 2432 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2433 #define CAU_RADR_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2434 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2435 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2436 #define CAU_RADR_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2437 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2438 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2439 #define CAU_RADR_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2440 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2441 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2442 #define CAU_RADR_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2443 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2444 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2445 #define CAU_RADR_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2446 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2447 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2448 #define CAU_RADR_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2449 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2450 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2451 #define CAU_RADR_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2452 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2453 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2454 #define CAU_RADR_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2455 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2456 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2457 #define CAU_RADR_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2458 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2459
AnnaBridge 189:f392fc9709a3 2460 /* The count of CAU_RADR_CA */
AnnaBridge 189:f392fc9709a3 2461 #define CAU_RADR_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2462
AnnaBridge 189:f392fc9709a3 2463 /*! @name XOR_CASR - Status register - Exclusive Or command */
AnnaBridge 189:f392fc9709a3 2464 #define CAU_XOR_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2465 #define CAU_XOR_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2466 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2467 #define CAU_XOR_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2468 #define CAU_XOR_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2469 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2470 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2471 #define CAU_XOR_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2472 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2473
AnnaBridge 189:f392fc9709a3 2474 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
AnnaBridge 189:f392fc9709a3 2475 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2476 #define CAU_XOR_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2477 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2478
AnnaBridge 189:f392fc9709a3 2479 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
AnnaBridge 189:f392fc9709a3 2480 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2481 #define CAU_XOR_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2482 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2483 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2484 #define CAU_XOR_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2485 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2486 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2487 #define CAU_XOR_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2488 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2489 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2490 #define CAU_XOR_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2491 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2492 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2493 #define CAU_XOR_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2494 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2495 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2496 #define CAU_XOR_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2497 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2498 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2499 #define CAU_XOR_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2500 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2501 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2502 #define CAU_XOR_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2503 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2504 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2505 #define CAU_XOR_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2506 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2507
AnnaBridge 189:f392fc9709a3 2508 /* The count of CAU_XOR_CA */
AnnaBridge 189:f392fc9709a3 2509 #define CAU_XOR_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2510
AnnaBridge 189:f392fc9709a3 2511 /*! @name ROTL_CASR - Status register - Rotate Left command */
AnnaBridge 189:f392fc9709a3 2512 #define CAU_ROTL_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2513 #define CAU_ROTL_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2514 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2515 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2516 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2517 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2518 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2519 #define CAU_ROTL_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2520 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2521
AnnaBridge 189:f392fc9709a3 2522 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
AnnaBridge 189:f392fc9709a3 2523 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2524 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2525 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2526
AnnaBridge 189:f392fc9709a3 2527 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
AnnaBridge 189:f392fc9709a3 2528 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2529 #define CAU_ROTL_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2530 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2531 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2532 #define CAU_ROTL_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2533 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2534 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2535 #define CAU_ROTL_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2536 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2537 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2538 #define CAU_ROTL_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2539 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2540 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2541 #define CAU_ROTL_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2542 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2543 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2544 #define CAU_ROTL_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2545 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2546 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2547 #define CAU_ROTL_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2548 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2549 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2550 #define CAU_ROTL_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2551 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2552 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2553 #define CAU_ROTL_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2554 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2555
AnnaBridge 189:f392fc9709a3 2556 /* The count of CAU_ROTL_CA */
AnnaBridge 189:f392fc9709a3 2557 #define CAU_ROTL_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2558
AnnaBridge 189:f392fc9709a3 2559 /*! @name AESC_CASR - Status register - AES Column Operation command */
AnnaBridge 189:f392fc9709a3 2560 #define CAU_AESC_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2561 #define CAU_AESC_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2562 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2563 #define CAU_AESC_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2564 #define CAU_AESC_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2565 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2566 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2567 #define CAU_AESC_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2568 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2569
AnnaBridge 189:f392fc9709a3 2570 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
AnnaBridge 189:f392fc9709a3 2571 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2572 #define CAU_AESC_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2573 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2574
AnnaBridge 189:f392fc9709a3 2575 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
AnnaBridge 189:f392fc9709a3 2576 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2577 #define CAU_AESC_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2578 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2579 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2580 #define CAU_AESC_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2581 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2582 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2583 #define CAU_AESC_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2584 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2585 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2586 #define CAU_AESC_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2587 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2588 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2589 #define CAU_AESC_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2590 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2591 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2592 #define CAU_AESC_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2593 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2594 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2595 #define CAU_AESC_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2596 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2597 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2598 #define CAU_AESC_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2599 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2600 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2601 #define CAU_AESC_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2602 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2603
AnnaBridge 189:f392fc9709a3 2604 /* The count of CAU_AESC_CA */
AnnaBridge 189:f392fc9709a3 2605 #define CAU_AESC_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2606
AnnaBridge 189:f392fc9709a3 2607 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
AnnaBridge 189:f392fc9709a3 2608 #define CAU_AESIC_CASR_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2609 #define CAU_AESIC_CASR_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2610 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
AnnaBridge 189:f392fc9709a3 2611 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2612 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2613 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
AnnaBridge 189:f392fc9709a3 2614 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 2615 #define CAU_AESIC_CASR_VER_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 2616 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
AnnaBridge 189:f392fc9709a3 2617
AnnaBridge 189:f392fc9709a3 2618 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
AnnaBridge 189:f392fc9709a3 2619 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2620 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2621 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
AnnaBridge 189:f392fc9709a3 2622
AnnaBridge 189:f392fc9709a3 2623 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
AnnaBridge 189:f392fc9709a3 2624 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2625 #define CAU_AESIC_CA_CA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2626 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
AnnaBridge 189:f392fc9709a3 2627 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2628 #define CAU_AESIC_CA_CA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2629 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
AnnaBridge 189:f392fc9709a3 2630 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2631 #define CAU_AESIC_CA_CA2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2632 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
AnnaBridge 189:f392fc9709a3 2633 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2634 #define CAU_AESIC_CA_CA3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2635 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
AnnaBridge 189:f392fc9709a3 2636 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2637 #define CAU_AESIC_CA_CA4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2638 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
AnnaBridge 189:f392fc9709a3 2639 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2640 #define CAU_AESIC_CA_CA5_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2641 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
AnnaBridge 189:f392fc9709a3 2642 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2643 #define CAU_AESIC_CA_CA6_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2644 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
AnnaBridge 189:f392fc9709a3 2645 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2646 #define CAU_AESIC_CA_CA7_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2647 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
AnnaBridge 189:f392fc9709a3 2648 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 2649 #define CAU_AESIC_CA_CA8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2650 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
AnnaBridge 189:f392fc9709a3 2651
AnnaBridge 189:f392fc9709a3 2652 /* The count of CAU_AESIC_CA */
AnnaBridge 189:f392fc9709a3 2653 #define CAU_AESIC_CA_COUNT (9U)
AnnaBridge 189:f392fc9709a3 2654
AnnaBridge 189:f392fc9709a3 2655
AnnaBridge 189:f392fc9709a3 2656 /*!
AnnaBridge 189:f392fc9709a3 2657 * @}
AnnaBridge 189:f392fc9709a3 2658 */ /* end of group CAU_Register_Masks */
AnnaBridge 189:f392fc9709a3 2659
AnnaBridge 189:f392fc9709a3 2660
AnnaBridge 189:f392fc9709a3 2661 /* CAU - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 2662 /** Peripheral CAU base address */
AnnaBridge 189:f392fc9709a3 2663 #define CAU_BASE (0xE0081000u)
AnnaBridge 189:f392fc9709a3 2664 /** Peripheral CAU base pointer */
AnnaBridge 189:f392fc9709a3 2665 #define CAU ((CAU_Type *)CAU_BASE)
AnnaBridge 189:f392fc9709a3 2666 /** Array initializer of CAU peripheral base addresses */
AnnaBridge 189:f392fc9709a3 2667 #define CAU_BASE_ADDRS { CAU_BASE }
AnnaBridge 189:f392fc9709a3 2668 /** Array initializer of CAU peripheral base pointers */
AnnaBridge 189:f392fc9709a3 2669 #define CAU_BASE_PTRS { CAU }
AnnaBridge 189:f392fc9709a3 2670
AnnaBridge 189:f392fc9709a3 2671 /*!
AnnaBridge 189:f392fc9709a3 2672 * @}
AnnaBridge 189:f392fc9709a3 2673 */ /* end of group CAU_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 2674
AnnaBridge 189:f392fc9709a3 2675
AnnaBridge 189:f392fc9709a3 2676 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2677 -- CMP Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2678 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2679
AnnaBridge 189:f392fc9709a3 2680 /*!
AnnaBridge 189:f392fc9709a3 2681 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2682 * @{
AnnaBridge 189:f392fc9709a3 2683 */
AnnaBridge 189:f392fc9709a3 2684
AnnaBridge 189:f392fc9709a3 2685 /** CMP - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 2686 typedef struct {
AnnaBridge 189:f392fc9709a3 2687 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2688 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 2689 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 2690 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 2691 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2692 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 2693 } CMP_Type;
AnnaBridge 189:f392fc9709a3 2694
AnnaBridge 189:f392fc9709a3 2695 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2696 -- CMP Register Masks
AnnaBridge 189:f392fc9709a3 2697 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2698
AnnaBridge 189:f392fc9709a3 2699 /*!
AnnaBridge 189:f392fc9709a3 2700 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 189:f392fc9709a3 2701 * @{
AnnaBridge 189:f392fc9709a3 2702 */
AnnaBridge 189:f392fc9709a3 2703
AnnaBridge 189:f392fc9709a3 2704 /*! @name CR0 - CMP Control Register 0 */
AnnaBridge 189:f392fc9709a3 2705 #define CMP_CR0_HYSTCTR_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 2706 #define CMP_CR0_HYSTCTR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2707 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
AnnaBridge 189:f392fc9709a3 2708 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
AnnaBridge 189:f392fc9709a3 2709 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 2710 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 189:f392fc9709a3 2711
AnnaBridge 189:f392fc9709a3 2712 /*! @name CR1 - CMP Control Register 1 */
AnnaBridge 189:f392fc9709a3 2713 #define CMP_CR1_EN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2714 #define CMP_CR1_EN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2715 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
AnnaBridge 189:f392fc9709a3 2716 #define CMP_CR1_OPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2717 #define CMP_CR1_OPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2718 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
AnnaBridge 189:f392fc9709a3 2719 #define CMP_CR1_COS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 2720 #define CMP_CR1_COS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 2721 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
AnnaBridge 189:f392fc9709a3 2722 #define CMP_CR1_INV_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 2723 #define CMP_CR1_INV_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 2724 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
AnnaBridge 189:f392fc9709a3 2725 #define CMP_CR1_PMODE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 2726 #define CMP_CR1_PMODE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 2727 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
AnnaBridge 189:f392fc9709a3 2728 #define CMP_CR1_TRIGM_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 2729 #define CMP_CR1_TRIGM_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 2730 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
AnnaBridge 189:f392fc9709a3 2731 #define CMP_CR1_WE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 2732 #define CMP_CR1_WE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 2733 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
AnnaBridge 189:f392fc9709a3 2734 #define CMP_CR1_SE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 2735 #define CMP_CR1_SE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 2736 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
AnnaBridge 189:f392fc9709a3 2737
AnnaBridge 189:f392fc9709a3 2738 /*! @name FPR - CMP Filter Period Register */
AnnaBridge 189:f392fc9709a3 2739 #define CMP_FPR_FILT_PER_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2740 #define CMP_FPR_FILT_PER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2741 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
AnnaBridge 189:f392fc9709a3 2742
AnnaBridge 189:f392fc9709a3 2743 /*! @name SCR - CMP Status and Control Register */
AnnaBridge 189:f392fc9709a3 2744 #define CMP_SCR_COUT_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2745 #define CMP_SCR_COUT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2746 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
AnnaBridge 189:f392fc9709a3 2747 #define CMP_SCR_CFF_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2748 #define CMP_SCR_CFF_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2749 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
AnnaBridge 189:f392fc9709a3 2750 #define CMP_SCR_CFR_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 2751 #define CMP_SCR_CFR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 2752 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
AnnaBridge 189:f392fc9709a3 2753 #define CMP_SCR_IEF_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 2754 #define CMP_SCR_IEF_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 2755 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
AnnaBridge 189:f392fc9709a3 2756 #define CMP_SCR_IER_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 2757 #define CMP_SCR_IER_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 2758 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
AnnaBridge 189:f392fc9709a3 2759 #define CMP_SCR_DMAEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 2760 #define CMP_SCR_DMAEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 2761 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
AnnaBridge 189:f392fc9709a3 2762
AnnaBridge 189:f392fc9709a3 2763 /*! @name DACCR - DAC Control Register */
AnnaBridge 189:f392fc9709a3 2764 #define CMP_DACCR_VOSEL_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 2765 #define CMP_DACCR_VOSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2766 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
AnnaBridge 189:f392fc9709a3 2767 #define CMP_DACCR_VRSEL_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 2768 #define CMP_DACCR_VRSEL_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 2769 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
AnnaBridge 189:f392fc9709a3 2770 #define CMP_DACCR_DACEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 2771 #define CMP_DACCR_DACEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 2772 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
AnnaBridge 189:f392fc9709a3 2773
AnnaBridge 189:f392fc9709a3 2774 /*! @name MUXCR - MUX Control Register */
AnnaBridge 189:f392fc9709a3 2775 #define CMP_MUXCR_MSEL_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 2776 #define CMP_MUXCR_MSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2777 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
AnnaBridge 189:f392fc9709a3 2778 #define CMP_MUXCR_PSEL_MASK (0x38U)
AnnaBridge 189:f392fc9709a3 2779 #define CMP_MUXCR_PSEL_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 2780 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
AnnaBridge 189:f392fc9709a3 2781
AnnaBridge 189:f392fc9709a3 2782
AnnaBridge 189:f392fc9709a3 2783 /*!
AnnaBridge 189:f392fc9709a3 2784 * @}
AnnaBridge 189:f392fc9709a3 2785 */ /* end of group CMP_Register_Masks */
AnnaBridge 189:f392fc9709a3 2786
AnnaBridge 189:f392fc9709a3 2787
AnnaBridge 189:f392fc9709a3 2788 /* CMP - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 2789 /** Peripheral CMP0 base address */
AnnaBridge 189:f392fc9709a3 2790 #define CMP0_BASE (0x40073000u)
AnnaBridge 189:f392fc9709a3 2791 /** Peripheral CMP0 base pointer */
AnnaBridge 189:f392fc9709a3 2792 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 189:f392fc9709a3 2793 /** Peripheral CMP1 base address */
AnnaBridge 189:f392fc9709a3 2794 #define CMP1_BASE (0x40073008u)
AnnaBridge 189:f392fc9709a3 2795 /** Peripheral CMP1 base pointer */
AnnaBridge 189:f392fc9709a3 2796 #define CMP1 ((CMP_Type *)CMP1_BASE)
AnnaBridge 189:f392fc9709a3 2797 /** Array initializer of CMP peripheral base addresses */
AnnaBridge 189:f392fc9709a3 2798 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
AnnaBridge 189:f392fc9709a3 2799 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 189:f392fc9709a3 2800 #define CMP_BASE_PTRS { CMP0, CMP1 }
AnnaBridge 189:f392fc9709a3 2801 /** Interrupt vectors for the CMP peripheral type */
AnnaBridge 189:f392fc9709a3 2802 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
AnnaBridge 189:f392fc9709a3 2803
AnnaBridge 189:f392fc9709a3 2804 /*!
AnnaBridge 189:f392fc9709a3 2805 * @}
AnnaBridge 189:f392fc9709a3 2806 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 2807
AnnaBridge 189:f392fc9709a3 2808
AnnaBridge 189:f392fc9709a3 2809 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2810 -- CMT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2811 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2812
AnnaBridge 189:f392fc9709a3 2813 /*!
AnnaBridge 189:f392fc9709a3 2814 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2815 * @{
AnnaBridge 189:f392fc9709a3 2816 */
AnnaBridge 189:f392fc9709a3 2817
AnnaBridge 189:f392fc9709a3 2818 /** CMT - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 2819 typedef struct {
AnnaBridge 189:f392fc9709a3 2820 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2821 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 2822 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 2823 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 2824 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2825 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 2826 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
AnnaBridge 189:f392fc9709a3 2827 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
AnnaBridge 189:f392fc9709a3 2828 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 2829 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
AnnaBridge 189:f392fc9709a3 2830 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
AnnaBridge 189:f392fc9709a3 2831 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
AnnaBridge 189:f392fc9709a3 2832 } CMT_Type;
AnnaBridge 189:f392fc9709a3 2833
AnnaBridge 189:f392fc9709a3 2834 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2835 -- CMT Register Masks
AnnaBridge 189:f392fc9709a3 2836 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2837
AnnaBridge 189:f392fc9709a3 2838 /*!
AnnaBridge 189:f392fc9709a3 2839 * @addtogroup CMT_Register_Masks CMT Register Masks
AnnaBridge 189:f392fc9709a3 2840 * @{
AnnaBridge 189:f392fc9709a3 2841 */
AnnaBridge 189:f392fc9709a3 2842
AnnaBridge 189:f392fc9709a3 2843 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
AnnaBridge 189:f392fc9709a3 2844 #define CMT_CGH1_PH_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2845 #define CMT_CGH1_PH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2846 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
AnnaBridge 189:f392fc9709a3 2847
AnnaBridge 189:f392fc9709a3 2848 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
AnnaBridge 189:f392fc9709a3 2849 #define CMT_CGL1_PL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2850 #define CMT_CGL1_PL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2851 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
AnnaBridge 189:f392fc9709a3 2852
AnnaBridge 189:f392fc9709a3 2853 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
AnnaBridge 189:f392fc9709a3 2854 #define CMT_CGH2_SH_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2855 #define CMT_CGH2_SH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2856 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
AnnaBridge 189:f392fc9709a3 2857
AnnaBridge 189:f392fc9709a3 2858 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
AnnaBridge 189:f392fc9709a3 2859 #define CMT_CGL2_SL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2860 #define CMT_CGL2_SL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2861 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
AnnaBridge 189:f392fc9709a3 2862
AnnaBridge 189:f392fc9709a3 2863 /*! @name OC - CMT Output Control Register */
AnnaBridge 189:f392fc9709a3 2864 #define CMT_OC_IROPEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 2865 #define CMT_OC_IROPEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 2866 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
AnnaBridge 189:f392fc9709a3 2867 #define CMT_OC_CMTPOL_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 2868 #define CMT_OC_CMTPOL_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 2869 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
AnnaBridge 189:f392fc9709a3 2870 #define CMT_OC_IROL_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 2871 #define CMT_OC_IROL_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 2872 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
AnnaBridge 189:f392fc9709a3 2873
AnnaBridge 189:f392fc9709a3 2874 /*! @name MSC - CMT Modulator Status and Control Register */
AnnaBridge 189:f392fc9709a3 2875 #define CMT_MSC_MCGEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2876 #define CMT_MSC_MCGEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2877 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
AnnaBridge 189:f392fc9709a3 2878 #define CMT_MSC_EOCIE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 2879 #define CMT_MSC_EOCIE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 2880 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
AnnaBridge 189:f392fc9709a3 2881 #define CMT_MSC_FSK_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 2882 #define CMT_MSC_FSK_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 2883 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
AnnaBridge 189:f392fc9709a3 2884 #define CMT_MSC_BASE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 2885 #define CMT_MSC_BASE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 2886 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
AnnaBridge 189:f392fc9709a3 2887 #define CMT_MSC_EXSPC_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 2888 #define CMT_MSC_EXSPC_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 2889 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
AnnaBridge 189:f392fc9709a3 2890 #define CMT_MSC_CMTDIV_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 2891 #define CMT_MSC_CMTDIV_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 2892 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
AnnaBridge 189:f392fc9709a3 2893 #define CMT_MSC_EOCF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 2894 #define CMT_MSC_EOCF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 2895 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
AnnaBridge 189:f392fc9709a3 2896
AnnaBridge 189:f392fc9709a3 2897 /*! @name CMD1 - CMT Modulator Data Register Mark High */
AnnaBridge 189:f392fc9709a3 2898 #define CMT_CMD1_MB_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2899 #define CMT_CMD1_MB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2900 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
AnnaBridge 189:f392fc9709a3 2901
AnnaBridge 189:f392fc9709a3 2902 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
AnnaBridge 189:f392fc9709a3 2903 #define CMT_CMD2_MB_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2904 #define CMT_CMD2_MB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2905 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
AnnaBridge 189:f392fc9709a3 2906
AnnaBridge 189:f392fc9709a3 2907 /*! @name CMD3 - CMT Modulator Data Register Space High */
AnnaBridge 189:f392fc9709a3 2908 #define CMT_CMD3_SB_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2909 #define CMT_CMD3_SB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2910 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
AnnaBridge 189:f392fc9709a3 2911
AnnaBridge 189:f392fc9709a3 2912 /*! @name CMD4 - CMT Modulator Data Register Space Low */
AnnaBridge 189:f392fc9709a3 2913 #define CMT_CMD4_SB_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 2914 #define CMT_CMD4_SB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2915 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
AnnaBridge 189:f392fc9709a3 2916
AnnaBridge 189:f392fc9709a3 2917 /*! @name PPS - CMT Primary Prescaler Register */
AnnaBridge 189:f392fc9709a3 2918 #define CMT_PPS_PPSDIV_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 2919 #define CMT_PPS_PPSDIV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2920 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
AnnaBridge 189:f392fc9709a3 2921
AnnaBridge 189:f392fc9709a3 2922 /*! @name DMA - CMT Direct Memory Access Register */
AnnaBridge 189:f392fc9709a3 2923 #define CMT_DMA_DMA_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 2924 #define CMT_DMA_DMA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 2925 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
AnnaBridge 189:f392fc9709a3 2926
AnnaBridge 189:f392fc9709a3 2927
AnnaBridge 189:f392fc9709a3 2928 /*!
AnnaBridge 189:f392fc9709a3 2929 * @}
AnnaBridge 189:f392fc9709a3 2930 */ /* end of group CMT_Register_Masks */
AnnaBridge 189:f392fc9709a3 2931
AnnaBridge 189:f392fc9709a3 2932
AnnaBridge 189:f392fc9709a3 2933 /* CMT - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 2934 /** Peripheral CMT base address */
AnnaBridge 189:f392fc9709a3 2935 #define CMT_BASE (0x40062000u)
AnnaBridge 189:f392fc9709a3 2936 /** Peripheral CMT base pointer */
AnnaBridge 189:f392fc9709a3 2937 #define CMT ((CMT_Type *)CMT_BASE)
AnnaBridge 189:f392fc9709a3 2938 /** Array initializer of CMT peripheral base addresses */
AnnaBridge 189:f392fc9709a3 2939 #define CMT_BASE_ADDRS { CMT_BASE }
AnnaBridge 189:f392fc9709a3 2940 /** Array initializer of CMT peripheral base pointers */
AnnaBridge 189:f392fc9709a3 2941 #define CMT_BASE_PTRS { CMT }
AnnaBridge 189:f392fc9709a3 2942 /** Interrupt vectors for the CMT peripheral type */
AnnaBridge 189:f392fc9709a3 2943 #define CMT_IRQS { CMT_IRQn }
AnnaBridge 189:f392fc9709a3 2944
AnnaBridge 189:f392fc9709a3 2945 /*!
AnnaBridge 189:f392fc9709a3 2946 * @}
AnnaBridge 189:f392fc9709a3 2947 */ /* end of group CMT_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 2948
AnnaBridge 189:f392fc9709a3 2949
AnnaBridge 189:f392fc9709a3 2950 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2951 -- CRC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2952 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2953
AnnaBridge 189:f392fc9709a3 2954 /*!
AnnaBridge 189:f392fc9709a3 2955 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 2956 * @{
AnnaBridge 189:f392fc9709a3 2957 */
AnnaBridge 189:f392fc9709a3 2958
AnnaBridge 189:f392fc9709a3 2959 /** CRC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 2960 typedef struct {
AnnaBridge 189:f392fc9709a3 2961 union { /* offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2962 struct { /* offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2963 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2964 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
AnnaBridge 189:f392fc9709a3 2965 } ACCESS16BIT;
AnnaBridge 189:f392fc9709a3 2966 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2967 struct { /* offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2968 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
AnnaBridge 189:f392fc9709a3 2969 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
AnnaBridge 189:f392fc9709a3 2970 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
AnnaBridge 189:f392fc9709a3 2971 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
AnnaBridge 189:f392fc9709a3 2972 } ACCESS8BIT;
AnnaBridge 189:f392fc9709a3 2973 };
AnnaBridge 189:f392fc9709a3 2974 union { /* offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2975 struct { /* offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2976 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2977 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
AnnaBridge 189:f392fc9709a3 2978 } GPOLY_ACCESS16BIT;
AnnaBridge 189:f392fc9709a3 2979 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2980 struct { /* offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2981 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
AnnaBridge 189:f392fc9709a3 2982 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
AnnaBridge 189:f392fc9709a3 2983 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
AnnaBridge 189:f392fc9709a3 2984 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
AnnaBridge 189:f392fc9709a3 2985 } GPOLY_ACCESS8BIT;
AnnaBridge 189:f392fc9709a3 2986 };
AnnaBridge 189:f392fc9709a3 2987 union { /* offset: 0x8 */
AnnaBridge 189:f392fc9709a3 2988 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 2989 struct { /* offset: 0x8 */
AnnaBridge 189:f392fc9709a3 2990 uint8_t RESERVED_0[3];
AnnaBridge 189:f392fc9709a3 2991 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
AnnaBridge 189:f392fc9709a3 2992 } CTRL_ACCESS8BIT;
AnnaBridge 189:f392fc9709a3 2993 };
AnnaBridge 189:f392fc9709a3 2994 } CRC_Type;
AnnaBridge 189:f392fc9709a3 2995
AnnaBridge 189:f392fc9709a3 2996 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 2997 -- CRC Register Masks
AnnaBridge 189:f392fc9709a3 2998 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 2999
AnnaBridge 189:f392fc9709a3 3000 /*!
AnnaBridge 189:f392fc9709a3 3001 * @addtogroup CRC_Register_Masks CRC Register Masks
AnnaBridge 189:f392fc9709a3 3002 * @{
AnnaBridge 189:f392fc9709a3 3003 */
AnnaBridge 189:f392fc9709a3 3004
AnnaBridge 189:f392fc9709a3 3005 /*! @name DATAL - CRC_DATAL register. */
AnnaBridge 189:f392fc9709a3 3006 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 3007 #define CRC_DATAL_DATAL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3008 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
AnnaBridge 189:f392fc9709a3 3009
AnnaBridge 189:f392fc9709a3 3010 /*! @name DATAH - CRC_DATAH register. */
AnnaBridge 189:f392fc9709a3 3011 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 3012 #define CRC_DATAH_DATAH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3013 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
AnnaBridge 189:f392fc9709a3 3014
AnnaBridge 189:f392fc9709a3 3015 /*! @name DATA - CRC Data register */
AnnaBridge 189:f392fc9709a3 3016 #define CRC_DATA_LL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3017 #define CRC_DATA_LL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3018 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
AnnaBridge 189:f392fc9709a3 3019 #define CRC_DATA_LU_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 3020 #define CRC_DATA_LU_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3021 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
AnnaBridge 189:f392fc9709a3 3022 #define CRC_DATA_HL_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 3023 #define CRC_DATA_HL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3024 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
AnnaBridge 189:f392fc9709a3 3025 #define CRC_DATA_HU_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 3026 #define CRC_DATA_HU_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 3027 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
AnnaBridge 189:f392fc9709a3 3028
AnnaBridge 189:f392fc9709a3 3029 /*! @name DATALL - CRC_DATALL register. */
AnnaBridge 189:f392fc9709a3 3030 #define CRC_DATALL_DATALL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3031 #define CRC_DATALL_DATALL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3032 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
AnnaBridge 189:f392fc9709a3 3033
AnnaBridge 189:f392fc9709a3 3034 /*! @name DATALU - CRC_DATALU register. */
AnnaBridge 189:f392fc9709a3 3035 #define CRC_DATALU_DATALU_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3036 #define CRC_DATALU_DATALU_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3037 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
AnnaBridge 189:f392fc9709a3 3038
AnnaBridge 189:f392fc9709a3 3039 /*! @name DATAHL - CRC_DATAHL register. */
AnnaBridge 189:f392fc9709a3 3040 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3041 #define CRC_DATAHL_DATAHL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3042 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
AnnaBridge 189:f392fc9709a3 3043
AnnaBridge 189:f392fc9709a3 3044 /*! @name DATAHU - CRC_DATAHU register. */
AnnaBridge 189:f392fc9709a3 3045 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3046 #define CRC_DATAHU_DATAHU_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3047 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
AnnaBridge 189:f392fc9709a3 3048
AnnaBridge 189:f392fc9709a3 3049 /*! @name GPOLYL - CRC_GPOLYL register. */
AnnaBridge 189:f392fc9709a3 3050 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 3051 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3052 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
AnnaBridge 189:f392fc9709a3 3053
AnnaBridge 189:f392fc9709a3 3054 /*! @name GPOLYH - CRC_GPOLYH register. */
AnnaBridge 189:f392fc9709a3 3055 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 3056 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3057 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
AnnaBridge 189:f392fc9709a3 3058
AnnaBridge 189:f392fc9709a3 3059 /*! @name GPOLY - CRC Polynomial register */
AnnaBridge 189:f392fc9709a3 3060 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 3061 #define CRC_GPOLY_LOW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3062 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
AnnaBridge 189:f392fc9709a3 3063 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 3064 #define CRC_GPOLY_HIGH_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3065 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
AnnaBridge 189:f392fc9709a3 3066
AnnaBridge 189:f392fc9709a3 3067 /*! @name GPOLYLL - CRC_GPOLYLL register. */
AnnaBridge 189:f392fc9709a3 3068 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3069 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3070 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
AnnaBridge 189:f392fc9709a3 3071
AnnaBridge 189:f392fc9709a3 3072 /*! @name GPOLYLU - CRC_GPOLYLU register. */
AnnaBridge 189:f392fc9709a3 3073 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3074 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3075 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
AnnaBridge 189:f392fc9709a3 3076
AnnaBridge 189:f392fc9709a3 3077 /*! @name GPOLYHL - CRC_GPOLYHL register. */
AnnaBridge 189:f392fc9709a3 3078 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3079 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3080 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
AnnaBridge 189:f392fc9709a3 3081
AnnaBridge 189:f392fc9709a3 3082 /*! @name GPOLYHU - CRC_GPOLYHU register. */
AnnaBridge 189:f392fc9709a3 3083 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3084 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3085 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
AnnaBridge 189:f392fc9709a3 3086
AnnaBridge 189:f392fc9709a3 3087 /*! @name CTRL - CRC Control register */
AnnaBridge 189:f392fc9709a3 3088 #define CRC_CTRL_TCRC_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 3089 #define CRC_CTRL_TCRC_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 3090 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
AnnaBridge 189:f392fc9709a3 3091 #define CRC_CTRL_WAS_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 3092 #define CRC_CTRL_WAS_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 3093 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
AnnaBridge 189:f392fc9709a3 3094 #define CRC_CTRL_FXOR_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 3095 #define CRC_CTRL_FXOR_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 3096 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
AnnaBridge 189:f392fc9709a3 3097 #define CRC_CTRL_TOTR_MASK (0x30000000U)
AnnaBridge 189:f392fc9709a3 3098 #define CRC_CTRL_TOTR_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 3099 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
AnnaBridge 189:f392fc9709a3 3100 #define CRC_CTRL_TOT_MASK (0xC0000000U)
AnnaBridge 189:f392fc9709a3 3101 #define CRC_CTRL_TOT_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 3102 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
AnnaBridge 189:f392fc9709a3 3103
AnnaBridge 189:f392fc9709a3 3104 /*! @name CTRLHU - CRC_CTRLHU register. */
AnnaBridge 189:f392fc9709a3 3105 #define CRC_CTRLHU_TCRC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3106 #define CRC_CTRLHU_TCRC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3107 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
AnnaBridge 189:f392fc9709a3 3108 #define CRC_CTRLHU_WAS_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3109 #define CRC_CTRLHU_WAS_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3110 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
AnnaBridge 189:f392fc9709a3 3111 #define CRC_CTRLHU_FXOR_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3112 #define CRC_CTRLHU_FXOR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3113 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
AnnaBridge 189:f392fc9709a3 3114 #define CRC_CTRLHU_TOTR_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 3115 #define CRC_CTRLHU_TOTR_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3116 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
AnnaBridge 189:f392fc9709a3 3117 #define CRC_CTRLHU_TOT_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 3118 #define CRC_CTRLHU_TOT_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3119 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
AnnaBridge 189:f392fc9709a3 3120
AnnaBridge 189:f392fc9709a3 3121
AnnaBridge 189:f392fc9709a3 3122 /*!
AnnaBridge 189:f392fc9709a3 3123 * @}
AnnaBridge 189:f392fc9709a3 3124 */ /* end of group CRC_Register_Masks */
AnnaBridge 189:f392fc9709a3 3125
AnnaBridge 189:f392fc9709a3 3126
AnnaBridge 189:f392fc9709a3 3127 /* CRC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 3128 /** Peripheral CRC base address */
AnnaBridge 189:f392fc9709a3 3129 #define CRC_BASE (0x40032000u)
AnnaBridge 189:f392fc9709a3 3130 /** Peripheral CRC base pointer */
AnnaBridge 189:f392fc9709a3 3131 #define CRC0 ((CRC_Type *)CRC_BASE)
AnnaBridge 189:f392fc9709a3 3132 /** Array initializer of CRC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 3133 #define CRC_BASE_ADDRS { CRC_BASE }
AnnaBridge 189:f392fc9709a3 3134 /** Array initializer of CRC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 3135 #define CRC_BASE_PTRS { CRC0 }
AnnaBridge 189:f392fc9709a3 3136
AnnaBridge 189:f392fc9709a3 3137 /*!
AnnaBridge 189:f392fc9709a3 3138 * @}
AnnaBridge 189:f392fc9709a3 3139 */ /* end of group CRC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 3140
AnnaBridge 189:f392fc9709a3 3141
AnnaBridge 189:f392fc9709a3 3142 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 3143 -- DAC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 3144 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 3145
AnnaBridge 189:f392fc9709a3 3146 /*!
AnnaBridge 189:f392fc9709a3 3147 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 3148 * @{
AnnaBridge 189:f392fc9709a3 3149 */
AnnaBridge 189:f392fc9709a3 3150
AnnaBridge 189:f392fc9709a3 3151 /** DAC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 3152 typedef struct {
AnnaBridge 189:f392fc9709a3 3153 struct { /* offset: 0x0, array step: 0x2 */
AnnaBridge 189:f392fc9709a3 3154 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
AnnaBridge 189:f392fc9709a3 3155 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
AnnaBridge 189:f392fc9709a3 3156 } DAT[16];
AnnaBridge 189:f392fc9709a3 3157 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 3158 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
AnnaBridge 189:f392fc9709a3 3159 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
AnnaBridge 189:f392fc9709a3 3160 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
AnnaBridge 189:f392fc9709a3 3161 } DAC_Type;
AnnaBridge 189:f392fc9709a3 3162
AnnaBridge 189:f392fc9709a3 3163 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 3164 -- DAC Register Masks
AnnaBridge 189:f392fc9709a3 3165 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 3166
AnnaBridge 189:f392fc9709a3 3167 /*!
AnnaBridge 189:f392fc9709a3 3168 * @addtogroup DAC_Register_Masks DAC Register Masks
AnnaBridge 189:f392fc9709a3 3169 * @{
AnnaBridge 189:f392fc9709a3 3170 */
AnnaBridge 189:f392fc9709a3 3171
AnnaBridge 189:f392fc9709a3 3172 /*! @name DATL - DAC Data Low Register */
AnnaBridge 189:f392fc9709a3 3173 #define DAC_DATL_DATA0_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 3174 #define DAC_DATL_DATA0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3175 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
AnnaBridge 189:f392fc9709a3 3176
AnnaBridge 189:f392fc9709a3 3177 /* The count of DAC_DATL */
AnnaBridge 189:f392fc9709a3 3178 #define DAC_DATL_COUNT (16U)
AnnaBridge 189:f392fc9709a3 3179
AnnaBridge 189:f392fc9709a3 3180 /*! @name DATH - DAC Data High Register */
AnnaBridge 189:f392fc9709a3 3181 #define DAC_DATH_DATA1_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 3182 #define DAC_DATH_DATA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3183 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
AnnaBridge 189:f392fc9709a3 3184
AnnaBridge 189:f392fc9709a3 3185 /* The count of DAC_DATH */
AnnaBridge 189:f392fc9709a3 3186 #define DAC_DATH_COUNT (16U)
AnnaBridge 189:f392fc9709a3 3187
AnnaBridge 189:f392fc9709a3 3188 /*! @name SR - DAC Status Register */
AnnaBridge 189:f392fc9709a3 3189 #define DAC_SR_DACBFRPBF_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3190 #define DAC_SR_DACBFRPBF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3191 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
AnnaBridge 189:f392fc9709a3 3192 #define DAC_SR_DACBFRPTF_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3193 #define DAC_SR_DACBFRPTF_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3194 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
AnnaBridge 189:f392fc9709a3 3195 #define DAC_SR_DACBFWMF_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3196 #define DAC_SR_DACBFWMF_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3197 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
AnnaBridge 189:f392fc9709a3 3198
AnnaBridge 189:f392fc9709a3 3199 /*! @name C0 - DAC Control Register */
AnnaBridge 189:f392fc9709a3 3200 #define DAC_C0_DACBBIEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3201 #define DAC_C0_DACBBIEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3202 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
AnnaBridge 189:f392fc9709a3 3203 #define DAC_C0_DACBTIEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3204 #define DAC_C0_DACBTIEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3205 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
AnnaBridge 189:f392fc9709a3 3206 #define DAC_C0_DACBWIEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3207 #define DAC_C0_DACBWIEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3208 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
AnnaBridge 189:f392fc9709a3 3209 #define DAC_C0_LPEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3210 #define DAC_C0_LPEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3211 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
AnnaBridge 189:f392fc9709a3 3212 #define DAC_C0_DACSWTRG_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3213 #define DAC_C0_DACSWTRG_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3214 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
AnnaBridge 189:f392fc9709a3 3215 #define DAC_C0_DACTRGSEL_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3216 #define DAC_C0_DACTRGSEL_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3217 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
AnnaBridge 189:f392fc9709a3 3218 #define DAC_C0_DACRFS_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3219 #define DAC_C0_DACRFS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3220 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
AnnaBridge 189:f392fc9709a3 3221 #define DAC_C0_DACEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3222 #define DAC_C0_DACEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3223 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
AnnaBridge 189:f392fc9709a3 3224
AnnaBridge 189:f392fc9709a3 3225 /*! @name C1 - DAC Control Register 1 */
AnnaBridge 189:f392fc9709a3 3226 #define DAC_C1_DACBFEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3227 #define DAC_C1_DACBFEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3228 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
AnnaBridge 189:f392fc9709a3 3229 #define DAC_C1_DACBFMD_MASK (0x6U)
AnnaBridge 189:f392fc9709a3 3230 #define DAC_C1_DACBFMD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3231 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
AnnaBridge 189:f392fc9709a3 3232 #define DAC_C1_DACBFWM_MASK (0x18U)
AnnaBridge 189:f392fc9709a3 3233 #define DAC_C1_DACBFWM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3234 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
AnnaBridge 189:f392fc9709a3 3235 #define DAC_C1_DMAEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3236 #define DAC_C1_DMAEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3237 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
AnnaBridge 189:f392fc9709a3 3238
AnnaBridge 189:f392fc9709a3 3239 /*! @name C2 - DAC Control Register 2 */
AnnaBridge 189:f392fc9709a3 3240 #define DAC_C2_DACBFUP_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 3241 #define DAC_C2_DACBFUP_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3242 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
AnnaBridge 189:f392fc9709a3 3243 #define DAC_C2_DACBFRP_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 3244 #define DAC_C2_DACBFRP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3245 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
AnnaBridge 189:f392fc9709a3 3246
AnnaBridge 189:f392fc9709a3 3247
AnnaBridge 189:f392fc9709a3 3248 /*!
AnnaBridge 189:f392fc9709a3 3249 * @}
AnnaBridge 189:f392fc9709a3 3250 */ /* end of group DAC_Register_Masks */
AnnaBridge 189:f392fc9709a3 3251
AnnaBridge 189:f392fc9709a3 3252
AnnaBridge 189:f392fc9709a3 3253 /* DAC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 3254 /** Peripheral DAC0 base address */
AnnaBridge 189:f392fc9709a3 3255 #define DAC0_BASE (0x400CC000u)
AnnaBridge 189:f392fc9709a3 3256 /** Peripheral DAC0 base pointer */
AnnaBridge 189:f392fc9709a3 3257 #define DAC0 ((DAC_Type *)DAC0_BASE)
AnnaBridge 189:f392fc9709a3 3258 /** Array initializer of DAC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 3259 #define DAC_BASE_ADDRS { DAC0_BASE }
AnnaBridge 189:f392fc9709a3 3260 /** Array initializer of DAC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 3261 #define DAC_BASE_PTRS { DAC0 }
AnnaBridge 189:f392fc9709a3 3262 /** Interrupt vectors for the DAC peripheral type */
AnnaBridge 189:f392fc9709a3 3263 #define DAC_IRQS { DAC0_IRQn }
AnnaBridge 189:f392fc9709a3 3264
AnnaBridge 189:f392fc9709a3 3265 /*!
AnnaBridge 189:f392fc9709a3 3266 * @}
AnnaBridge 189:f392fc9709a3 3267 */ /* end of group DAC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 3268
AnnaBridge 189:f392fc9709a3 3269
AnnaBridge 189:f392fc9709a3 3270 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 3271 -- DMA Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 3272 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 3273
AnnaBridge 189:f392fc9709a3 3274 /*!
AnnaBridge 189:f392fc9709a3 3275 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 3276 * @{
AnnaBridge 189:f392fc9709a3 3277 */
AnnaBridge 189:f392fc9709a3 3278
AnnaBridge 189:f392fc9709a3 3279 /** DMA - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 3280 typedef struct {
AnnaBridge 189:f392fc9709a3 3281 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 3282 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 3283 uint8_t RESERVED_0[4];
AnnaBridge 189:f392fc9709a3 3284 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 3285 uint8_t RESERVED_1[4];
AnnaBridge 189:f392fc9709a3 3286 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 3287 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 3288 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
AnnaBridge 189:f392fc9709a3 3289 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
AnnaBridge 189:f392fc9709a3 3290 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
AnnaBridge 189:f392fc9709a3 3291 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 3292 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
AnnaBridge 189:f392fc9709a3 3293 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
AnnaBridge 189:f392fc9709a3 3294 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
AnnaBridge 189:f392fc9709a3 3295 uint8_t RESERVED_2[4];
AnnaBridge 189:f392fc9709a3 3296 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 3297 uint8_t RESERVED_3[4];
AnnaBridge 189:f392fc9709a3 3298 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 3299 uint8_t RESERVED_4[4];
AnnaBridge 189:f392fc9709a3 3300 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 3301 uint8_t RESERVED_5[12];
AnnaBridge 189:f392fc9709a3 3302 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
AnnaBridge 189:f392fc9709a3 3303 uint8_t RESERVED_6[184];
AnnaBridge 189:f392fc9709a3 3304 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
AnnaBridge 189:f392fc9709a3 3305 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
AnnaBridge 189:f392fc9709a3 3306 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
AnnaBridge 189:f392fc9709a3 3307 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
AnnaBridge 189:f392fc9709a3 3308 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
AnnaBridge 189:f392fc9709a3 3309 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
AnnaBridge 189:f392fc9709a3 3310 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
AnnaBridge 189:f392fc9709a3 3311 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
AnnaBridge 189:f392fc9709a3 3312 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
AnnaBridge 189:f392fc9709a3 3313 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
AnnaBridge 189:f392fc9709a3 3314 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
AnnaBridge 189:f392fc9709a3 3315 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
AnnaBridge 189:f392fc9709a3 3316 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
AnnaBridge 189:f392fc9709a3 3317 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
AnnaBridge 189:f392fc9709a3 3318 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
AnnaBridge 189:f392fc9709a3 3319 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
AnnaBridge 189:f392fc9709a3 3320 __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
AnnaBridge 189:f392fc9709a3 3321 __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
AnnaBridge 189:f392fc9709a3 3322 __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
AnnaBridge 189:f392fc9709a3 3323 __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
AnnaBridge 189:f392fc9709a3 3324 __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
AnnaBridge 189:f392fc9709a3 3325 __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
AnnaBridge 189:f392fc9709a3 3326 __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
AnnaBridge 189:f392fc9709a3 3327 __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
AnnaBridge 189:f392fc9709a3 3328 __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
AnnaBridge 189:f392fc9709a3 3329 __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
AnnaBridge 189:f392fc9709a3 3330 __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
AnnaBridge 189:f392fc9709a3 3331 __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
AnnaBridge 189:f392fc9709a3 3332 __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
AnnaBridge 189:f392fc9709a3 3333 __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
AnnaBridge 189:f392fc9709a3 3334 __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
AnnaBridge 189:f392fc9709a3 3335 __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
AnnaBridge 189:f392fc9709a3 3336 uint8_t RESERVED_7[3808];
AnnaBridge 189:f392fc9709a3 3337 struct { /* offset: 0x1000, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3338 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3339 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3340 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3341 union { /* offset: 0x1008, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3342 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3343 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3344 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3345 };
AnnaBridge 189:f392fc9709a3 3346 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3347 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3348 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3349 union { /* offset: 0x1016, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3350 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3351 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3352 };
AnnaBridge 189:f392fc9709a3 3353 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3354 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3355 union { /* offset: 0x101E, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3356 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3357 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 189:f392fc9709a3 3358 };
AnnaBridge 189:f392fc9709a3 3359 } TCD[32];
AnnaBridge 189:f392fc9709a3 3360 } DMA_Type;
AnnaBridge 189:f392fc9709a3 3361
AnnaBridge 189:f392fc9709a3 3362 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 3363 -- DMA Register Masks
AnnaBridge 189:f392fc9709a3 3364 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 3365
AnnaBridge 189:f392fc9709a3 3366 /*!
AnnaBridge 189:f392fc9709a3 3367 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 189:f392fc9709a3 3368 * @{
AnnaBridge 189:f392fc9709a3 3369 */
AnnaBridge 189:f392fc9709a3 3370
AnnaBridge 189:f392fc9709a3 3371 /*! @name CR - Control Register */
AnnaBridge 189:f392fc9709a3 3372 #define DMA_CR_EDBG_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3373 #define DMA_CR_EDBG_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3374 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
AnnaBridge 189:f392fc9709a3 3375 #define DMA_CR_ERCA_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3376 #define DMA_CR_ERCA_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3377 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
AnnaBridge 189:f392fc9709a3 3378 #define DMA_CR_ERGA_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3379 #define DMA_CR_ERGA_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3380 #define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
AnnaBridge 189:f392fc9709a3 3381 #define DMA_CR_HOE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3382 #define DMA_CR_HOE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3383 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
AnnaBridge 189:f392fc9709a3 3384 #define DMA_CR_HALT_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3385 #define DMA_CR_HALT_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3386 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
AnnaBridge 189:f392fc9709a3 3387 #define DMA_CR_CLM_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3388 #define DMA_CR_CLM_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3389 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
AnnaBridge 189:f392fc9709a3 3390 #define DMA_CR_EMLM_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3391 #define DMA_CR_EMLM_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3392 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
AnnaBridge 189:f392fc9709a3 3393 #define DMA_CR_GRP0PRI_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 3394 #define DMA_CR_GRP0PRI_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3395 #define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
AnnaBridge 189:f392fc9709a3 3396 #define DMA_CR_GRP1PRI_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 3397 #define DMA_CR_GRP1PRI_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 3398 #define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
AnnaBridge 189:f392fc9709a3 3399 #define DMA_CR_ECX_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 3400 #define DMA_CR_ECX_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3401 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
AnnaBridge 189:f392fc9709a3 3402 #define DMA_CR_CX_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 3403 #define DMA_CR_CX_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 3404 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
AnnaBridge 189:f392fc9709a3 3405
AnnaBridge 189:f392fc9709a3 3406 /*! @name ES - Error Status Register */
AnnaBridge 189:f392fc9709a3 3407 #define DMA_ES_DBE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3408 #define DMA_ES_DBE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3409 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
AnnaBridge 189:f392fc9709a3 3410 #define DMA_ES_SBE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3411 #define DMA_ES_SBE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3412 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
AnnaBridge 189:f392fc9709a3 3413 #define DMA_ES_SGE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3414 #define DMA_ES_SGE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3415 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
AnnaBridge 189:f392fc9709a3 3416 #define DMA_ES_NCE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3417 #define DMA_ES_NCE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3418 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
AnnaBridge 189:f392fc9709a3 3419 #define DMA_ES_DOE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3420 #define DMA_ES_DOE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3421 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
AnnaBridge 189:f392fc9709a3 3422 #define DMA_ES_DAE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3423 #define DMA_ES_DAE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3424 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
AnnaBridge 189:f392fc9709a3 3425 #define DMA_ES_SOE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3426 #define DMA_ES_SOE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3427 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
AnnaBridge 189:f392fc9709a3 3428 #define DMA_ES_SAE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3429 #define DMA_ES_SAE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3430 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
AnnaBridge 189:f392fc9709a3 3431 #define DMA_ES_ERRCHN_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 3432 #define DMA_ES_ERRCHN_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3433 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
AnnaBridge 189:f392fc9709a3 3434 #define DMA_ES_CPE_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 3435 #define DMA_ES_CPE_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 3436 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
AnnaBridge 189:f392fc9709a3 3437 #define DMA_ES_GPE_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 3438 #define DMA_ES_GPE_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 3439 #define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
AnnaBridge 189:f392fc9709a3 3440 #define DMA_ES_ECX_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 3441 #define DMA_ES_ECX_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3442 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
AnnaBridge 189:f392fc9709a3 3443 #define DMA_ES_VLD_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 3444 #define DMA_ES_VLD_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 3445 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
AnnaBridge 189:f392fc9709a3 3446
AnnaBridge 189:f392fc9709a3 3447 /*! @name ERQ - Enable Request Register */
AnnaBridge 189:f392fc9709a3 3448 #define DMA_ERQ_ERQ0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3449 #define DMA_ERQ_ERQ0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3450 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
AnnaBridge 189:f392fc9709a3 3451 #define DMA_ERQ_ERQ1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3452 #define DMA_ERQ_ERQ1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3453 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
AnnaBridge 189:f392fc9709a3 3454 #define DMA_ERQ_ERQ2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3455 #define DMA_ERQ_ERQ2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3456 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
AnnaBridge 189:f392fc9709a3 3457 #define DMA_ERQ_ERQ3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3458 #define DMA_ERQ_ERQ3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3459 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
AnnaBridge 189:f392fc9709a3 3460 #define DMA_ERQ_ERQ4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3461 #define DMA_ERQ_ERQ4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3462 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
AnnaBridge 189:f392fc9709a3 3463 #define DMA_ERQ_ERQ5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3464 #define DMA_ERQ_ERQ5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3465 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
AnnaBridge 189:f392fc9709a3 3466 #define DMA_ERQ_ERQ6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3467 #define DMA_ERQ_ERQ6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3468 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
AnnaBridge 189:f392fc9709a3 3469 #define DMA_ERQ_ERQ7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3470 #define DMA_ERQ_ERQ7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3471 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
AnnaBridge 189:f392fc9709a3 3472 #define DMA_ERQ_ERQ8_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 3473 #define DMA_ERQ_ERQ8_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3474 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
AnnaBridge 189:f392fc9709a3 3475 #define DMA_ERQ_ERQ9_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 3476 #define DMA_ERQ_ERQ9_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 3477 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
AnnaBridge 189:f392fc9709a3 3478 #define DMA_ERQ_ERQ10_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 3479 #define DMA_ERQ_ERQ10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 3480 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
AnnaBridge 189:f392fc9709a3 3481 #define DMA_ERQ_ERQ11_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 3482 #define DMA_ERQ_ERQ11_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 3483 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
AnnaBridge 189:f392fc9709a3 3484 #define DMA_ERQ_ERQ12_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 3485 #define DMA_ERQ_ERQ12_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 3486 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
AnnaBridge 189:f392fc9709a3 3487 #define DMA_ERQ_ERQ13_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 3488 #define DMA_ERQ_ERQ13_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 3489 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
AnnaBridge 189:f392fc9709a3 3490 #define DMA_ERQ_ERQ14_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 3491 #define DMA_ERQ_ERQ14_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 3492 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
AnnaBridge 189:f392fc9709a3 3493 #define DMA_ERQ_ERQ15_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 3494 #define DMA_ERQ_ERQ15_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 3495 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
AnnaBridge 189:f392fc9709a3 3496 #define DMA_ERQ_ERQ16_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 3497 #define DMA_ERQ_ERQ16_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3498 #define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
AnnaBridge 189:f392fc9709a3 3499 #define DMA_ERQ_ERQ17_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 3500 #define DMA_ERQ_ERQ17_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 3501 #define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
AnnaBridge 189:f392fc9709a3 3502 #define DMA_ERQ_ERQ18_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 3503 #define DMA_ERQ_ERQ18_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 3504 #define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
AnnaBridge 189:f392fc9709a3 3505 #define DMA_ERQ_ERQ19_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 3506 #define DMA_ERQ_ERQ19_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 3507 #define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
AnnaBridge 189:f392fc9709a3 3508 #define DMA_ERQ_ERQ20_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 3509 #define DMA_ERQ_ERQ20_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 3510 #define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
AnnaBridge 189:f392fc9709a3 3511 #define DMA_ERQ_ERQ21_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 3512 #define DMA_ERQ_ERQ21_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 3513 #define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
AnnaBridge 189:f392fc9709a3 3514 #define DMA_ERQ_ERQ22_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 3515 #define DMA_ERQ_ERQ22_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 3516 #define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
AnnaBridge 189:f392fc9709a3 3517 #define DMA_ERQ_ERQ23_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 3518 #define DMA_ERQ_ERQ23_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 3519 #define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
AnnaBridge 189:f392fc9709a3 3520 #define DMA_ERQ_ERQ24_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 3521 #define DMA_ERQ_ERQ24_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 3522 #define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
AnnaBridge 189:f392fc9709a3 3523 #define DMA_ERQ_ERQ25_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 3524 #define DMA_ERQ_ERQ25_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 3525 #define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
AnnaBridge 189:f392fc9709a3 3526 #define DMA_ERQ_ERQ26_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 3527 #define DMA_ERQ_ERQ26_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 3528 #define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
AnnaBridge 189:f392fc9709a3 3529 #define DMA_ERQ_ERQ27_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 3530 #define DMA_ERQ_ERQ27_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 3531 #define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
AnnaBridge 189:f392fc9709a3 3532 #define DMA_ERQ_ERQ28_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 3533 #define DMA_ERQ_ERQ28_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 3534 #define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
AnnaBridge 189:f392fc9709a3 3535 #define DMA_ERQ_ERQ29_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 3536 #define DMA_ERQ_ERQ29_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 3537 #define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
AnnaBridge 189:f392fc9709a3 3538 #define DMA_ERQ_ERQ30_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 3539 #define DMA_ERQ_ERQ30_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 3540 #define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
AnnaBridge 189:f392fc9709a3 3541 #define DMA_ERQ_ERQ31_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 3542 #define DMA_ERQ_ERQ31_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 3543 #define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
AnnaBridge 189:f392fc9709a3 3544
AnnaBridge 189:f392fc9709a3 3545 /*! @name EEI - Enable Error Interrupt Register */
AnnaBridge 189:f392fc9709a3 3546 #define DMA_EEI_EEI0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3547 #define DMA_EEI_EEI0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3548 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
AnnaBridge 189:f392fc9709a3 3549 #define DMA_EEI_EEI1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3550 #define DMA_EEI_EEI1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3551 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
AnnaBridge 189:f392fc9709a3 3552 #define DMA_EEI_EEI2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3553 #define DMA_EEI_EEI2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3554 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
AnnaBridge 189:f392fc9709a3 3555 #define DMA_EEI_EEI3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3556 #define DMA_EEI_EEI3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3557 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
AnnaBridge 189:f392fc9709a3 3558 #define DMA_EEI_EEI4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3559 #define DMA_EEI_EEI4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3560 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
AnnaBridge 189:f392fc9709a3 3561 #define DMA_EEI_EEI5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3562 #define DMA_EEI_EEI5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3563 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
AnnaBridge 189:f392fc9709a3 3564 #define DMA_EEI_EEI6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3565 #define DMA_EEI_EEI6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3566 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
AnnaBridge 189:f392fc9709a3 3567 #define DMA_EEI_EEI7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3568 #define DMA_EEI_EEI7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3569 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
AnnaBridge 189:f392fc9709a3 3570 #define DMA_EEI_EEI8_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 3571 #define DMA_EEI_EEI8_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3572 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
AnnaBridge 189:f392fc9709a3 3573 #define DMA_EEI_EEI9_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 3574 #define DMA_EEI_EEI9_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 3575 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
AnnaBridge 189:f392fc9709a3 3576 #define DMA_EEI_EEI10_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 3577 #define DMA_EEI_EEI10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 3578 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
AnnaBridge 189:f392fc9709a3 3579 #define DMA_EEI_EEI11_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 3580 #define DMA_EEI_EEI11_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 3581 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
AnnaBridge 189:f392fc9709a3 3582 #define DMA_EEI_EEI12_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 3583 #define DMA_EEI_EEI12_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 3584 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
AnnaBridge 189:f392fc9709a3 3585 #define DMA_EEI_EEI13_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 3586 #define DMA_EEI_EEI13_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 3587 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
AnnaBridge 189:f392fc9709a3 3588 #define DMA_EEI_EEI14_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 3589 #define DMA_EEI_EEI14_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 3590 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
AnnaBridge 189:f392fc9709a3 3591 #define DMA_EEI_EEI15_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 3592 #define DMA_EEI_EEI15_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 3593 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
AnnaBridge 189:f392fc9709a3 3594 #define DMA_EEI_EEI16_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 3595 #define DMA_EEI_EEI16_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3596 #define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
AnnaBridge 189:f392fc9709a3 3597 #define DMA_EEI_EEI17_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 3598 #define DMA_EEI_EEI17_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 3599 #define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
AnnaBridge 189:f392fc9709a3 3600 #define DMA_EEI_EEI18_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 3601 #define DMA_EEI_EEI18_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 3602 #define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
AnnaBridge 189:f392fc9709a3 3603 #define DMA_EEI_EEI19_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 3604 #define DMA_EEI_EEI19_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 3605 #define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
AnnaBridge 189:f392fc9709a3 3606 #define DMA_EEI_EEI20_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 3607 #define DMA_EEI_EEI20_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 3608 #define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
AnnaBridge 189:f392fc9709a3 3609 #define DMA_EEI_EEI21_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 3610 #define DMA_EEI_EEI21_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 3611 #define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
AnnaBridge 189:f392fc9709a3 3612 #define DMA_EEI_EEI22_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 3613 #define DMA_EEI_EEI22_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 3614 #define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
AnnaBridge 189:f392fc9709a3 3615 #define DMA_EEI_EEI23_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 3616 #define DMA_EEI_EEI23_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 3617 #define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
AnnaBridge 189:f392fc9709a3 3618 #define DMA_EEI_EEI24_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 3619 #define DMA_EEI_EEI24_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 3620 #define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
AnnaBridge 189:f392fc9709a3 3621 #define DMA_EEI_EEI25_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 3622 #define DMA_EEI_EEI25_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 3623 #define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
AnnaBridge 189:f392fc9709a3 3624 #define DMA_EEI_EEI26_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 3625 #define DMA_EEI_EEI26_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 3626 #define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
AnnaBridge 189:f392fc9709a3 3627 #define DMA_EEI_EEI27_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 3628 #define DMA_EEI_EEI27_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 3629 #define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
AnnaBridge 189:f392fc9709a3 3630 #define DMA_EEI_EEI28_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 3631 #define DMA_EEI_EEI28_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 3632 #define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
AnnaBridge 189:f392fc9709a3 3633 #define DMA_EEI_EEI29_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 3634 #define DMA_EEI_EEI29_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 3635 #define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
AnnaBridge 189:f392fc9709a3 3636 #define DMA_EEI_EEI30_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 3637 #define DMA_EEI_EEI30_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 3638 #define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
AnnaBridge 189:f392fc9709a3 3639 #define DMA_EEI_EEI31_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 3640 #define DMA_EEI_EEI31_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 3641 #define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
AnnaBridge 189:f392fc9709a3 3642
AnnaBridge 189:f392fc9709a3 3643 /*! @name CEEI - Clear Enable Error Interrupt Register */
AnnaBridge 189:f392fc9709a3 3644 #define DMA_CEEI_CEEI_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3645 #define DMA_CEEI_CEEI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3646 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
AnnaBridge 189:f392fc9709a3 3647 #define DMA_CEEI_CAEE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3648 #define DMA_CEEI_CAEE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3649 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
AnnaBridge 189:f392fc9709a3 3650 #define DMA_CEEI_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3651 #define DMA_CEEI_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3652 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3653
AnnaBridge 189:f392fc9709a3 3654 /*! @name SEEI - Set Enable Error Interrupt Register */
AnnaBridge 189:f392fc9709a3 3655 #define DMA_SEEI_SEEI_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3656 #define DMA_SEEI_SEEI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3657 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
AnnaBridge 189:f392fc9709a3 3658 #define DMA_SEEI_SAEE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3659 #define DMA_SEEI_SAEE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3660 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
AnnaBridge 189:f392fc9709a3 3661 #define DMA_SEEI_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3662 #define DMA_SEEI_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3663 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3664
AnnaBridge 189:f392fc9709a3 3665 /*! @name CERQ - Clear Enable Request Register */
AnnaBridge 189:f392fc9709a3 3666 #define DMA_CERQ_CERQ_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3667 #define DMA_CERQ_CERQ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3668 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
AnnaBridge 189:f392fc9709a3 3669 #define DMA_CERQ_CAER_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3670 #define DMA_CERQ_CAER_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3671 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
AnnaBridge 189:f392fc9709a3 3672 #define DMA_CERQ_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3673 #define DMA_CERQ_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3674 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3675
AnnaBridge 189:f392fc9709a3 3676 /*! @name SERQ - Set Enable Request Register */
AnnaBridge 189:f392fc9709a3 3677 #define DMA_SERQ_SERQ_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3678 #define DMA_SERQ_SERQ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3679 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
AnnaBridge 189:f392fc9709a3 3680 #define DMA_SERQ_SAER_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3681 #define DMA_SERQ_SAER_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3682 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
AnnaBridge 189:f392fc9709a3 3683 #define DMA_SERQ_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3684 #define DMA_SERQ_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3685 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3686
AnnaBridge 189:f392fc9709a3 3687 /*! @name CDNE - Clear DONE Status Bit Register */
AnnaBridge 189:f392fc9709a3 3688 #define DMA_CDNE_CDNE_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3689 #define DMA_CDNE_CDNE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3690 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
AnnaBridge 189:f392fc9709a3 3691 #define DMA_CDNE_CADN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3692 #define DMA_CDNE_CADN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3693 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
AnnaBridge 189:f392fc9709a3 3694 #define DMA_CDNE_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3695 #define DMA_CDNE_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3696 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3697
AnnaBridge 189:f392fc9709a3 3698 /*! @name SSRT - Set START Bit Register */
AnnaBridge 189:f392fc9709a3 3699 #define DMA_SSRT_SSRT_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3700 #define DMA_SSRT_SSRT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3701 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
AnnaBridge 189:f392fc9709a3 3702 #define DMA_SSRT_SAST_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3703 #define DMA_SSRT_SAST_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3704 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
AnnaBridge 189:f392fc9709a3 3705 #define DMA_SSRT_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3706 #define DMA_SSRT_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3707 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3708
AnnaBridge 189:f392fc9709a3 3709 /*! @name CERR - Clear Error Register */
AnnaBridge 189:f392fc9709a3 3710 #define DMA_CERR_CERR_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3711 #define DMA_CERR_CERR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3712 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
AnnaBridge 189:f392fc9709a3 3713 #define DMA_CERR_CAEI_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3714 #define DMA_CERR_CAEI_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3715 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
AnnaBridge 189:f392fc9709a3 3716 #define DMA_CERR_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3717 #define DMA_CERR_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3718 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3719
AnnaBridge 189:f392fc9709a3 3720 /*! @name CINT - Clear Interrupt Request Register */
AnnaBridge 189:f392fc9709a3 3721 #define DMA_CINT_CINT_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 3722 #define DMA_CINT_CINT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3723 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
AnnaBridge 189:f392fc9709a3 3724 #define DMA_CINT_CAIR_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3725 #define DMA_CINT_CAIR_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3726 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
AnnaBridge 189:f392fc9709a3 3727 #define DMA_CINT_NOP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3728 #define DMA_CINT_NOP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3729 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
AnnaBridge 189:f392fc9709a3 3730
AnnaBridge 189:f392fc9709a3 3731 /*! @name INT - Interrupt Request Register */
AnnaBridge 189:f392fc9709a3 3732 #define DMA_INT_INT0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3733 #define DMA_INT_INT0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3734 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
AnnaBridge 189:f392fc9709a3 3735 #define DMA_INT_INT1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3736 #define DMA_INT_INT1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3737 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
AnnaBridge 189:f392fc9709a3 3738 #define DMA_INT_INT2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3739 #define DMA_INT_INT2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3740 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
AnnaBridge 189:f392fc9709a3 3741 #define DMA_INT_INT3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3742 #define DMA_INT_INT3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3743 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
AnnaBridge 189:f392fc9709a3 3744 #define DMA_INT_INT4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3745 #define DMA_INT_INT4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3746 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
AnnaBridge 189:f392fc9709a3 3747 #define DMA_INT_INT5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3748 #define DMA_INT_INT5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3749 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
AnnaBridge 189:f392fc9709a3 3750 #define DMA_INT_INT6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3751 #define DMA_INT_INT6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3752 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
AnnaBridge 189:f392fc9709a3 3753 #define DMA_INT_INT7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3754 #define DMA_INT_INT7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3755 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
AnnaBridge 189:f392fc9709a3 3756 #define DMA_INT_INT8_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 3757 #define DMA_INT_INT8_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3758 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
AnnaBridge 189:f392fc9709a3 3759 #define DMA_INT_INT9_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 3760 #define DMA_INT_INT9_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 3761 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
AnnaBridge 189:f392fc9709a3 3762 #define DMA_INT_INT10_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 3763 #define DMA_INT_INT10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 3764 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
AnnaBridge 189:f392fc9709a3 3765 #define DMA_INT_INT11_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 3766 #define DMA_INT_INT11_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 3767 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
AnnaBridge 189:f392fc9709a3 3768 #define DMA_INT_INT12_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 3769 #define DMA_INT_INT12_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 3770 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
AnnaBridge 189:f392fc9709a3 3771 #define DMA_INT_INT13_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 3772 #define DMA_INT_INT13_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 3773 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
AnnaBridge 189:f392fc9709a3 3774 #define DMA_INT_INT14_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 3775 #define DMA_INT_INT14_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 3776 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
AnnaBridge 189:f392fc9709a3 3777 #define DMA_INT_INT15_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 3778 #define DMA_INT_INT15_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 3779 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
AnnaBridge 189:f392fc9709a3 3780 #define DMA_INT_INT16_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 3781 #define DMA_INT_INT16_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3782 #define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
AnnaBridge 189:f392fc9709a3 3783 #define DMA_INT_INT17_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 3784 #define DMA_INT_INT17_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 3785 #define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
AnnaBridge 189:f392fc9709a3 3786 #define DMA_INT_INT18_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 3787 #define DMA_INT_INT18_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 3788 #define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
AnnaBridge 189:f392fc9709a3 3789 #define DMA_INT_INT19_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 3790 #define DMA_INT_INT19_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 3791 #define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
AnnaBridge 189:f392fc9709a3 3792 #define DMA_INT_INT20_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 3793 #define DMA_INT_INT20_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 3794 #define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
AnnaBridge 189:f392fc9709a3 3795 #define DMA_INT_INT21_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 3796 #define DMA_INT_INT21_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 3797 #define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
AnnaBridge 189:f392fc9709a3 3798 #define DMA_INT_INT22_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 3799 #define DMA_INT_INT22_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 3800 #define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
AnnaBridge 189:f392fc9709a3 3801 #define DMA_INT_INT23_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 3802 #define DMA_INT_INT23_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 3803 #define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
AnnaBridge 189:f392fc9709a3 3804 #define DMA_INT_INT24_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 3805 #define DMA_INT_INT24_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 3806 #define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
AnnaBridge 189:f392fc9709a3 3807 #define DMA_INT_INT25_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 3808 #define DMA_INT_INT25_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 3809 #define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
AnnaBridge 189:f392fc9709a3 3810 #define DMA_INT_INT26_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 3811 #define DMA_INT_INT26_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 3812 #define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
AnnaBridge 189:f392fc9709a3 3813 #define DMA_INT_INT27_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 3814 #define DMA_INT_INT27_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 3815 #define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
AnnaBridge 189:f392fc9709a3 3816 #define DMA_INT_INT28_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 3817 #define DMA_INT_INT28_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 3818 #define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
AnnaBridge 189:f392fc9709a3 3819 #define DMA_INT_INT29_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 3820 #define DMA_INT_INT29_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 3821 #define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
AnnaBridge 189:f392fc9709a3 3822 #define DMA_INT_INT30_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 3823 #define DMA_INT_INT30_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 3824 #define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
AnnaBridge 189:f392fc9709a3 3825 #define DMA_INT_INT31_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 3826 #define DMA_INT_INT31_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 3827 #define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
AnnaBridge 189:f392fc9709a3 3828
AnnaBridge 189:f392fc9709a3 3829 /*! @name ERR - Error Register */
AnnaBridge 189:f392fc9709a3 3830 #define DMA_ERR_ERR0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3831 #define DMA_ERR_ERR0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3832 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
AnnaBridge 189:f392fc9709a3 3833 #define DMA_ERR_ERR1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3834 #define DMA_ERR_ERR1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3835 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
AnnaBridge 189:f392fc9709a3 3836 #define DMA_ERR_ERR2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3837 #define DMA_ERR_ERR2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3838 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
AnnaBridge 189:f392fc9709a3 3839 #define DMA_ERR_ERR3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3840 #define DMA_ERR_ERR3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3841 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
AnnaBridge 189:f392fc9709a3 3842 #define DMA_ERR_ERR4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3843 #define DMA_ERR_ERR4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3844 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
AnnaBridge 189:f392fc9709a3 3845 #define DMA_ERR_ERR5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3846 #define DMA_ERR_ERR5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3847 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
AnnaBridge 189:f392fc9709a3 3848 #define DMA_ERR_ERR6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3849 #define DMA_ERR_ERR6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3850 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
AnnaBridge 189:f392fc9709a3 3851 #define DMA_ERR_ERR7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3852 #define DMA_ERR_ERR7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3853 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
AnnaBridge 189:f392fc9709a3 3854 #define DMA_ERR_ERR8_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 3855 #define DMA_ERR_ERR8_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3856 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
AnnaBridge 189:f392fc9709a3 3857 #define DMA_ERR_ERR9_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 3858 #define DMA_ERR_ERR9_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 3859 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
AnnaBridge 189:f392fc9709a3 3860 #define DMA_ERR_ERR10_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 3861 #define DMA_ERR_ERR10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 3862 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
AnnaBridge 189:f392fc9709a3 3863 #define DMA_ERR_ERR11_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 3864 #define DMA_ERR_ERR11_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 3865 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
AnnaBridge 189:f392fc9709a3 3866 #define DMA_ERR_ERR12_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 3867 #define DMA_ERR_ERR12_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 3868 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
AnnaBridge 189:f392fc9709a3 3869 #define DMA_ERR_ERR13_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 3870 #define DMA_ERR_ERR13_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 3871 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
AnnaBridge 189:f392fc9709a3 3872 #define DMA_ERR_ERR14_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 3873 #define DMA_ERR_ERR14_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 3874 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
AnnaBridge 189:f392fc9709a3 3875 #define DMA_ERR_ERR15_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 3876 #define DMA_ERR_ERR15_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 3877 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
AnnaBridge 189:f392fc9709a3 3878 #define DMA_ERR_ERR16_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 3879 #define DMA_ERR_ERR16_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3880 #define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
AnnaBridge 189:f392fc9709a3 3881 #define DMA_ERR_ERR17_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 3882 #define DMA_ERR_ERR17_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 3883 #define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
AnnaBridge 189:f392fc9709a3 3884 #define DMA_ERR_ERR18_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 3885 #define DMA_ERR_ERR18_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 3886 #define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
AnnaBridge 189:f392fc9709a3 3887 #define DMA_ERR_ERR19_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 3888 #define DMA_ERR_ERR19_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 3889 #define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
AnnaBridge 189:f392fc9709a3 3890 #define DMA_ERR_ERR20_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 3891 #define DMA_ERR_ERR20_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 3892 #define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
AnnaBridge 189:f392fc9709a3 3893 #define DMA_ERR_ERR21_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 3894 #define DMA_ERR_ERR21_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 3895 #define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
AnnaBridge 189:f392fc9709a3 3896 #define DMA_ERR_ERR22_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 3897 #define DMA_ERR_ERR22_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 3898 #define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
AnnaBridge 189:f392fc9709a3 3899 #define DMA_ERR_ERR23_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 3900 #define DMA_ERR_ERR23_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 3901 #define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
AnnaBridge 189:f392fc9709a3 3902 #define DMA_ERR_ERR24_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 3903 #define DMA_ERR_ERR24_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 3904 #define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
AnnaBridge 189:f392fc9709a3 3905 #define DMA_ERR_ERR25_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 3906 #define DMA_ERR_ERR25_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 3907 #define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
AnnaBridge 189:f392fc9709a3 3908 #define DMA_ERR_ERR26_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 3909 #define DMA_ERR_ERR26_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 3910 #define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
AnnaBridge 189:f392fc9709a3 3911 #define DMA_ERR_ERR27_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 3912 #define DMA_ERR_ERR27_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 3913 #define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
AnnaBridge 189:f392fc9709a3 3914 #define DMA_ERR_ERR28_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 3915 #define DMA_ERR_ERR28_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 3916 #define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
AnnaBridge 189:f392fc9709a3 3917 #define DMA_ERR_ERR29_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 3918 #define DMA_ERR_ERR29_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 3919 #define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
AnnaBridge 189:f392fc9709a3 3920 #define DMA_ERR_ERR30_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 3921 #define DMA_ERR_ERR30_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 3922 #define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
AnnaBridge 189:f392fc9709a3 3923 #define DMA_ERR_ERR31_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 3924 #define DMA_ERR_ERR31_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 3925 #define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
AnnaBridge 189:f392fc9709a3 3926
AnnaBridge 189:f392fc9709a3 3927 /*! @name HRS - Hardware Request Status Register */
AnnaBridge 189:f392fc9709a3 3928 #define DMA_HRS_HRS0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 3929 #define DMA_HRS_HRS0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 3930 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
AnnaBridge 189:f392fc9709a3 3931 #define DMA_HRS_HRS1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 3932 #define DMA_HRS_HRS1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 3933 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
AnnaBridge 189:f392fc9709a3 3934 #define DMA_HRS_HRS2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 3935 #define DMA_HRS_HRS2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 3936 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
AnnaBridge 189:f392fc9709a3 3937 #define DMA_HRS_HRS3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 3938 #define DMA_HRS_HRS3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 3939 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
AnnaBridge 189:f392fc9709a3 3940 #define DMA_HRS_HRS4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 3941 #define DMA_HRS_HRS4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 3942 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
AnnaBridge 189:f392fc9709a3 3943 #define DMA_HRS_HRS5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 3944 #define DMA_HRS_HRS5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 3945 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
AnnaBridge 189:f392fc9709a3 3946 #define DMA_HRS_HRS6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 3947 #define DMA_HRS_HRS6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 3948 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
AnnaBridge 189:f392fc9709a3 3949 #define DMA_HRS_HRS7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 3950 #define DMA_HRS_HRS7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 3951 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
AnnaBridge 189:f392fc9709a3 3952 #define DMA_HRS_HRS8_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 3953 #define DMA_HRS_HRS8_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 3954 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
AnnaBridge 189:f392fc9709a3 3955 #define DMA_HRS_HRS9_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 3956 #define DMA_HRS_HRS9_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 3957 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
AnnaBridge 189:f392fc9709a3 3958 #define DMA_HRS_HRS10_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 3959 #define DMA_HRS_HRS10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 3960 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
AnnaBridge 189:f392fc9709a3 3961 #define DMA_HRS_HRS11_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 3962 #define DMA_HRS_HRS11_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 3963 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
AnnaBridge 189:f392fc9709a3 3964 #define DMA_HRS_HRS12_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 3965 #define DMA_HRS_HRS12_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 3966 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
AnnaBridge 189:f392fc9709a3 3967 #define DMA_HRS_HRS13_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 3968 #define DMA_HRS_HRS13_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 3969 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
AnnaBridge 189:f392fc9709a3 3970 #define DMA_HRS_HRS14_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 3971 #define DMA_HRS_HRS14_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 3972 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
AnnaBridge 189:f392fc9709a3 3973 #define DMA_HRS_HRS15_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 3974 #define DMA_HRS_HRS15_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 3975 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
AnnaBridge 189:f392fc9709a3 3976 #define DMA_HRS_HRS16_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 3977 #define DMA_HRS_HRS16_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 3978 #define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
AnnaBridge 189:f392fc9709a3 3979 #define DMA_HRS_HRS17_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 3980 #define DMA_HRS_HRS17_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 3981 #define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
AnnaBridge 189:f392fc9709a3 3982 #define DMA_HRS_HRS18_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 3983 #define DMA_HRS_HRS18_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 3984 #define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
AnnaBridge 189:f392fc9709a3 3985 #define DMA_HRS_HRS19_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 3986 #define DMA_HRS_HRS19_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 3987 #define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
AnnaBridge 189:f392fc9709a3 3988 #define DMA_HRS_HRS20_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 3989 #define DMA_HRS_HRS20_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 3990 #define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
AnnaBridge 189:f392fc9709a3 3991 #define DMA_HRS_HRS21_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 3992 #define DMA_HRS_HRS21_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 3993 #define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
AnnaBridge 189:f392fc9709a3 3994 #define DMA_HRS_HRS22_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 3995 #define DMA_HRS_HRS22_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 3996 #define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
AnnaBridge 189:f392fc9709a3 3997 #define DMA_HRS_HRS23_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 3998 #define DMA_HRS_HRS23_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 3999 #define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
AnnaBridge 189:f392fc9709a3 4000 #define DMA_HRS_HRS24_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 4001 #define DMA_HRS_HRS24_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 4002 #define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
AnnaBridge 189:f392fc9709a3 4003 #define DMA_HRS_HRS25_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 4004 #define DMA_HRS_HRS25_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 4005 #define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
AnnaBridge 189:f392fc9709a3 4006 #define DMA_HRS_HRS26_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 4007 #define DMA_HRS_HRS26_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 4008 #define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
AnnaBridge 189:f392fc9709a3 4009 #define DMA_HRS_HRS27_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 4010 #define DMA_HRS_HRS27_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 4011 #define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
AnnaBridge 189:f392fc9709a3 4012 #define DMA_HRS_HRS28_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 4013 #define DMA_HRS_HRS28_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 4014 #define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
AnnaBridge 189:f392fc9709a3 4015 #define DMA_HRS_HRS29_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 4016 #define DMA_HRS_HRS29_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 4017 #define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
AnnaBridge 189:f392fc9709a3 4018 #define DMA_HRS_HRS30_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 4019 #define DMA_HRS_HRS30_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 4020 #define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
AnnaBridge 189:f392fc9709a3 4021 #define DMA_HRS_HRS31_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 4022 #define DMA_HRS_HRS31_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 4023 #define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
AnnaBridge 189:f392fc9709a3 4024
AnnaBridge 189:f392fc9709a3 4025 /*! @name EARS - Enable Asynchronous Request in Stop Register */
AnnaBridge 189:f392fc9709a3 4026 #define DMA_EARS_EDREQ_0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 4027 #define DMA_EARS_EDREQ_0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4028 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
AnnaBridge 189:f392fc9709a3 4029 #define DMA_EARS_EDREQ_1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 4030 #define DMA_EARS_EDREQ_1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 4031 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
AnnaBridge 189:f392fc9709a3 4032 #define DMA_EARS_EDREQ_2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 4033 #define DMA_EARS_EDREQ_2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 4034 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
AnnaBridge 189:f392fc9709a3 4035 #define DMA_EARS_EDREQ_3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 4036 #define DMA_EARS_EDREQ_3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 4037 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
AnnaBridge 189:f392fc9709a3 4038 #define DMA_EARS_EDREQ_4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 4039 #define DMA_EARS_EDREQ_4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4040 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
AnnaBridge 189:f392fc9709a3 4041 #define DMA_EARS_EDREQ_5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 4042 #define DMA_EARS_EDREQ_5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 4043 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
AnnaBridge 189:f392fc9709a3 4044 #define DMA_EARS_EDREQ_6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4045 #define DMA_EARS_EDREQ_6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4046 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
AnnaBridge 189:f392fc9709a3 4047 #define DMA_EARS_EDREQ_7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4048 #define DMA_EARS_EDREQ_7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4049 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
AnnaBridge 189:f392fc9709a3 4050 #define DMA_EARS_EDREQ_8_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 4051 #define DMA_EARS_EDREQ_8_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 4052 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
AnnaBridge 189:f392fc9709a3 4053 #define DMA_EARS_EDREQ_9_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 4054 #define DMA_EARS_EDREQ_9_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 4055 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
AnnaBridge 189:f392fc9709a3 4056 #define DMA_EARS_EDREQ_10_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 4057 #define DMA_EARS_EDREQ_10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 4058 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
AnnaBridge 189:f392fc9709a3 4059 #define DMA_EARS_EDREQ_11_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 4060 #define DMA_EARS_EDREQ_11_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 4061 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
AnnaBridge 189:f392fc9709a3 4062 #define DMA_EARS_EDREQ_12_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 4063 #define DMA_EARS_EDREQ_12_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 4064 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
AnnaBridge 189:f392fc9709a3 4065 #define DMA_EARS_EDREQ_13_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 4066 #define DMA_EARS_EDREQ_13_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 4067 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
AnnaBridge 189:f392fc9709a3 4068 #define DMA_EARS_EDREQ_14_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 4069 #define DMA_EARS_EDREQ_14_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 4070 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
AnnaBridge 189:f392fc9709a3 4071 #define DMA_EARS_EDREQ_15_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 4072 #define DMA_EARS_EDREQ_15_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 4073 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
AnnaBridge 189:f392fc9709a3 4074 #define DMA_EARS_EDREQ_16_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 4075 #define DMA_EARS_EDREQ_16_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 4076 #define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
AnnaBridge 189:f392fc9709a3 4077 #define DMA_EARS_EDREQ_17_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 4078 #define DMA_EARS_EDREQ_17_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 4079 #define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
AnnaBridge 189:f392fc9709a3 4080 #define DMA_EARS_EDREQ_18_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 4081 #define DMA_EARS_EDREQ_18_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 4082 #define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
AnnaBridge 189:f392fc9709a3 4083 #define DMA_EARS_EDREQ_19_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 4084 #define DMA_EARS_EDREQ_19_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 4085 #define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
AnnaBridge 189:f392fc9709a3 4086 #define DMA_EARS_EDREQ_20_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 4087 #define DMA_EARS_EDREQ_20_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 4088 #define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
AnnaBridge 189:f392fc9709a3 4089 #define DMA_EARS_EDREQ_21_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 4090 #define DMA_EARS_EDREQ_21_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 4091 #define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
AnnaBridge 189:f392fc9709a3 4092 #define DMA_EARS_EDREQ_22_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 4093 #define DMA_EARS_EDREQ_22_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 4094 #define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
AnnaBridge 189:f392fc9709a3 4095 #define DMA_EARS_EDREQ_23_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 4096 #define DMA_EARS_EDREQ_23_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 4097 #define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
AnnaBridge 189:f392fc9709a3 4098 #define DMA_EARS_EDREQ_24_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 4099 #define DMA_EARS_EDREQ_24_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 4100 #define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
AnnaBridge 189:f392fc9709a3 4101 #define DMA_EARS_EDREQ_25_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 4102 #define DMA_EARS_EDREQ_25_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 4103 #define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
AnnaBridge 189:f392fc9709a3 4104 #define DMA_EARS_EDREQ_26_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 4105 #define DMA_EARS_EDREQ_26_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 4106 #define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
AnnaBridge 189:f392fc9709a3 4107 #define DMA_EARS_EDREQ_27_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 4108 #define DMA_EARS_EDREQ_27_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 4109 #define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
AnnaBridge 189:f392fc9709a3 4110 #define DMA_EARS_EDREQ_28_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 4111 #define DMA_EARS_EDREQ_28_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 4112 #define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
AnnaBridge 189:f392fc9709a3 4113 #define DMA_EARS_EDREQ_29_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 4114 #define DMA_EARS_EDREQ_29_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 4115 #define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
AnnaBridge 189:f392fc9709a3 4116 #define DMA_EARS_EDREQ_30_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 4117 #define DMA_EARS_EDREQ_30_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 4118 #define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
AnnaBridge 189:f392fc9709a3 4119 #define DMA_EARS_EDREQ_31_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 4120 #define DMA_EARS_EDREQ_31_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 4121 #define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
AnnaBridge 189:f392fc9709a3 4122
AnnaBridge 189:f392fc9709a3 4123 /*! @name DCHPRI3 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4124 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4125 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4126 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4127 #define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4128 #define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4129 #define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4130 #define DMA_DCHPRI3_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4131 #define DMA_DCHPRI3_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4132 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4133 #define DMA_DCHPRI3_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4134 #define DMA_DCHPRI3_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4135 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4136
AnnaBridge 189:f392fc9709a3 4137 /*! @name DCHPRI2 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4138 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4139 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4140 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4141 #define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4142 #define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4143 #define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4144 #define DMA_DCHPRI2_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4145 #define DMA_DCHPRI2_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4146 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4147 #define DMA_DCHPRI2_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4148 #define DMA_DCHPRI2_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4149 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4150
AnnaBridge 189:f392fc9709a3 4151 /*! @name DCHPRI1 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4152 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4153 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4154 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4155 #define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4156 #define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4157 #define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4158 #define DMA_DCHPRI1_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4159 #define DMA_DCHPRI1_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4160 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4161 #define DMA_DCHPRI1_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4162 #define DMA_DCHPRI1_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4163 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4164
AnnaBridge 189:f392fc9709a3 4165 /*! @name DCHPRI0 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4166 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4167 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4168 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4169 #define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4170 #define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4171 #define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4172 #define DMA_DCHPRI0_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4173 #define DMA_DCHPRI0_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4174 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4175 #define DMA_DCHPRI0_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4176 #define DMA_DCHPRI0_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4177 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4178
AnnaBridge 189:f392fc9709a3 4179 /*! @name DCHPRI7 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4180 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4181 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4182 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4183 #define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4184 #define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4185 #define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4186 #define DMA_DCHPRI7_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4187 #define DMA_DCHPRI7_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4188 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4189 #define DMA_DCHPRI7_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4190 #define DMA_DCHPRI7_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4191 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4192
AnnaBridge 189:f392fc9709a3 4193 /*! @name DCHPRI6 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4194 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4195 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4196 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4197 #define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4198 #define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4199 #define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4200 #define DMA_DCHPRI6_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4201 #define DMA_DCHPRI6_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4202 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4203 #define DMA_DCHPRI6_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4204 #define DMA_DCHPRI6_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4205 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4206
AnnaBridge 189:f392fc9709a3 4207 /*! @name DCHPRI5 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4208 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4209 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4210 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4211 #define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4212 #define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4213 #define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4214 #define DMA_DCHPRI5_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4215 #define DMA_DCHPRI5_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4216 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4217 #define DMA_DCHPRI5_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4218 #define DMA_DCHPRI5_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4219 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4220
AnnaBridge 189:f392fc9709a3 4221 /*! @name DCHPRI4 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4222 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4223 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4224 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4225 #define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4226 #define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4227 #define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4228 #define DMA_DCHPRI4_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4229 #define DMA_DCHPRI4_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4230 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4231 #define DMA_DCHPRI4_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4232 #define DMA_DCHPRI4_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4233 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4234
AnnaBridge 189:f392fc9709a3 4235 /*! @name DCHPRI11 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4236 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4237 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4238 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4239 #define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4240 #define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4241 #define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4242 #define DMA_DCHPRI11_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4243 #define DMA_DCHPRI11_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4244 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4245 #define DMA_DCHPRI11_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4246 #define DMA_DCHPRI11_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4247 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4248
AnnaBridge 189:f392fc9709a3 4249 /*! @name DCHPRI10 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4250 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4251 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4252 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4253 #define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4254 #define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4255 #define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4256 #define DMA_DCHPRI10_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4257 #define DMA_DCHPRI10_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4258 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4259 #define DMA_DCHPRI10_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4260 #define DMA_DCHPRI10_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4261 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4262
AnnaBridge 189:f392fc9709a3 4263 /*! @name DCHPRI9 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4264 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4265 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4266 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4267 #define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4268 #define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4269 #define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4270 #define DMA_DCHPRI9_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4271 #define DMA_DCHPRI9_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4272 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4273 #define DMA_DCHPRI9_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4274 #define DMA_DCHPRI9_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4275 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4276
AnnaBridge 189:f392fc9709a3 4277 /*! @name DCHPRI8 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4278 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4279 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4281 #define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4282 #define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4283 #define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4284 #define DMA_DCHPRI8_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4285 #define DMA_DCHPRI8_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4286 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4287 #define DMA_DCHPRI8_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4288 #define DMA_DCHPRI8_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4289 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4290
AnnaBridge 189:f392fc9709a3 4291 /*! @name DCHPRI15 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4292 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4293 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4294 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4295 #define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4296 #define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4297 #define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4298 #define DMA_DCHPRI15_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4299 #define DMA_DCHPRI15_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4300 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4301 #define DMA_DCHPRI15_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4302 #define DMA_DCHPRI15_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4303 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4304
AnnaBridge 189:f392fc9709a3 4305 /*! @name DCHPRI14 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4306 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4307 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4308 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4309 #define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4310 #define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4311 #define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4312 #define DMA_DCHPRI14_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4313 #define DMA_DCHPRI14_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4314 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4315 #define DMA_DCHPRI14_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4316 #define DMA_DCHPRI14_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4317 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4318
AnnaBridge 189:f392fc9709a3 4319 /*! @name DCHPRI13 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4320 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4321 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4322 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4323 #define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4324 #define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4325 #define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4326 #define DMA_DCHPRI13_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4327 #define DMA_DCHPRI13_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4328 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4329 #define DMA_DCHPRI13_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4330 #define DMA_DCHPRI13_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4331 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4332
AnnaBridge 189:f392fc9709a3 4333 /*! @name DCHPRI12 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4334 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4335 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4336 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4337 #define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4338 #define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4339 #define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4340 #define DMA_DCHPRI12_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4341 #define DMA_DCHPRI12_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4342 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4343 #define DMA_DCHPRI12_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4344 #define DMA_DCHPRI12_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4345 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4346
AnnaBridge 189:f392fc9709a3 4347 /*! @name DCHPRI19 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4348 #define DMA_DCHPRI19_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4349 #define DMA_DCHPRI19_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4350 #define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4351 #define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4352 #define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4353 #define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4354 #define DMA_DCHPRI19_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4355 #define DMA_DCHPRI19_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4356 #define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4357 #define DMA_DCHPRI19_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4358 #define DMA_DCHPRI19_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4359 #define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4360
AnnaBridge 189:f392fc9709a3 4361 /*! @name DCHPRI18 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4362 #define DMA_DCHPRI18_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4363 #define DMA_DCHPRI18_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4364 #define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4365 #define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4366 #define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4367 #define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4368 #define DMA_DCHPRI18_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4369 #define DMA_DCHPRI18_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4370 #define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4371 #define DMA_DCHPRI18_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4372 #define DMA_DCHPRI18_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4373 #define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4374
AnnaBridge 189:f392fc9709a3 4375 /*! @name DCHPRI17 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4376 #define DMA_DCHPRI17_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4377 #define DMA_DCHPRI17_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4378 #define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4379 #define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4380 #define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4381 #define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4382 #define DMA_DCHPRI17_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4383 #define DMA_DCHPRI17_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4384 #define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4385 #define DMA_DCHPRI17_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4386 #define DMA_DCHPRI17_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4387 #define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4388
AnnaBridge 189:f392fc9709a3 4389 /*! @name DCHPRI16 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4390 #define DMA_DCHPRI16_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4391 #define DMA_DCHPRI16_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4392 #define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4393 #define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4394 #define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4395 #define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4396 #define DMA_DCHPRI16_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4397 #define DMA_DCHPRI16_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4398 #define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4399 #define DMA_DCHPRI16_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4400 #define DMA_DCHPRI16_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4401 #define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4402
AnnaBridge 189:f392fc9709a3 4403 /*! @name DCHPRI23 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4404 #define DMA_DCHPRI23_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4405 #define DMA_DCHPRI23_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4406 #define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4407 #define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4408 #define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4409 #define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4410 #define DMA_DCHPRI23_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4411 #define DMA_DCHPRI23_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4412 #define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4413 #define DMA_DCHPRI23_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4414 #define DMA_DCHPRI23_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4415 #define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4416
AnnaBridge 189:f392fc9709a3 4417 /*! @name DCHPRI22 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4418 #define DMA_DCHPRI22_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4419 #define DMA_DCHPRI22_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4420 #define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4421 #define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4422 #define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4423 #define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4424 #define DMA_DCHPRI22_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4425 #define DMA_DCHPRI22_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4426 #define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4427 #define DMA_DCHPRI22_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4428 #define DMA_DCHPRI22_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4429 #define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4430
AnnaBridge 189:f392fc9709a3 4431 /*! @name DCHPRI21 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4432 #define DMA_DCHPRI21_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4433 #define DMA_DCHPRI21_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4434 #define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4435 #define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4436 #define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4437 #define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4438 #define DMA_DCHPRI21_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4439 #define DMA_DCHPRI21_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4440 #define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4441 #define DMA_DCHPRI21_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4442 #define DMA_DCHPRI21_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4443 #define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4444
AnnaBridge 189:f392fc9709a3 4445 /*! @name DCHPRI20 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4446 #define DMA_DCHPRI20_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4447 #define DMA_DCHPRI20_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4448 #define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4449 #define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4450 #define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4451 #define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4452 #define DMA_DCHPRI20_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4453 #define DMA_DCHPRI20_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4454 #define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4455 #define DMA_DCHPRI20_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4456 #define DMA_DCHPRI20_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4457 #define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4458
AnnaBridge 189:f392fc9709a3 4459 /*! @name DCHPRI27 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4460 #define DMA_DCHPRI27_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4461 #define DMA_DCHPRI27_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4462 #define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4463 #define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4464 #define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4465 #define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4466 #define DMA_DCHPRI27_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4467 #define DMA_DCHPRI27_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4468 #define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4469 #define DMA_DCHPRI27_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4470 #define DMA_DCHPRI27_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4471 #define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4472
AnnaBridge 189:f392fc9709a3 4473 /*! @name DCHPRI26 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4474 #define DMA_DCHPRI26_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4475 #define DMA_DCHPRI26_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4476 #define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4477 #define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4478 #define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4479 #define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4480 #define DMA_DCHPRI26_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4481 #define DMA_DCHPRI26_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4482 #define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4483 #define DMA_DCHPRI26_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4484 #define DMA_DCHPRI26_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4485 #define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4486
AnnaBridge 189:f392fc9709a3 4487 /*! @name DCHPRI25 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4488 #define DMA_DCHPRI25_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4489 #define DMA_DCHPRI25_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4490 #define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4491 #define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4492 #define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4493 #define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4494 #define DMA_DCHPRI25_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4495 #define DMA_DCHPRI25_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4496 #define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4497 #define DMA_DCHPRI25_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4498 #define DMA_DCHPRI25_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4499 #define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4500
AnnaBridge 189:f392fc9709a3 4501 /*! @name DCHPRI24 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4502 #define DMA_DCHPRI24_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4503 #define DMA_DCHPRI24_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4504 #define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4505 #define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4506 #define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4507 #define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4508 #define DMA_DCHPRI24_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4509 #define DMA_DCHPRI24_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4510 #define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4511 #define DMA_DCHPRI24_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4512 #define DMA_DCHPRI24_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4513 #define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4514
AnnaBridge 189:f392fc9709a3 4515 /*! @name DCHPRI31 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4516 #define DMA_DCHPRI31_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4517 #define DMA_DCHPRI31_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4518 #define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4519 #define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4520 #define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4521 #define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4522 #define DMA_DCHPRI31_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4523 #define DMA_DCHPRI31_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4524 #define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4525 #define DMA_DCHPRI31_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4526 #define DMA_DCHPRI31_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4527 #define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4528
AnnaBridge 189:f392fc9709a3 4529 /*! @name DCHPRI30 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4530 #define DMA_DCHPRI30_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4531 #define DMA_DCHPRI30_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4532 #define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4533 #define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4534 #define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4535 #define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4536 #define DMA_DCHPRI30_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4537 #define DMA_DCHPRI30_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4538 #define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4539 #define DMA_DCHPRI30_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4540 #define DMA_DCHPRI30_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4541 #define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4542
AnnaBridge 189:f392fc9709a3 4543 /*! @name DCHPRI29 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4544 #define DMA_DCHPRI29_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4545 #define DMA_DCHPRI29_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4546 #define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4547 #define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4548 #define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4549 #define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4550 #define DMA_DCHPRI29_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4551 #define DMA_DCHPRI29_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4552 #define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4553 #define DMA_DCHPRI29_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4554 #define DMA_DCHPRI29_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4555 #define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4556
AnnaBridge 189:f392fc9709a3 4557 /*! @name DCHPRI28 - Channel n Priority Register */
AnnaBridge 189:f392fc9709a3 4558 #define DMA_DCHPRI28_CHPRI_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 4559 #define DMA_DCHPRI28_CHPRI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4560 #define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
AnnaBridge 189:f392fc9709a3 4561 #define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 4562 #define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4563 #define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
AnnaBridge 189:f392fc9709a3 4564 #define DMA_DCHPRI28_DPA_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4565 #define DMA_DCHPRI28_DPA_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4566 #define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
AnnaBridge 189:f392fc9709a3 4567 #define DMA_DCHPRI28_ECP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4568 #define DMA_DCHPRI28_ECP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4569 #define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
AnnaBridge 189:f392fc9709a3 4570
AnnaBridge 189:f392fc9709a3 4571 /*! @name SADDR - TCD Source Address */
AnnaBridge 189:f392fc9709a3 4572 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 4573 #define DMA_SADDR_SADDR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4574 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
AnnaBridge 189:f392fc9709a3 4575
AnnaBridge 189:f392fc9709a3 4576 /* The count of DMA_SADDR */
AnnaBridge 189:f392fc9709a3 4577 #define DMA_SADDR_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4578
AnnaBridge 189:f392fc9709a3 4579 /*! @name SOFF - TCD Signed Source Address Offset */
AnnaBridge 189:f392fc9709a3 4580 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 4581 #define DMA_SOFF_SOFF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4582 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
AnnaBridge 189:f392fc9709a3 4583
AnnaBridge 189:f392fc9709a3 4584 /* The count of DMA_SOFF */
AnnaBridge 189:f392fc9709a3 4585 #define DMA_SOFF_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4586
AnnaBridge 189:f392fc9709a3 4587 /*! @name ATTR - TCD Transfer Attributes */
AnnaBridge 189:f392fc9709a3 4588 #define DMA_ATTR_DSIZE_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 4589 #define DMA_ATTR_DSIZE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4590 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
AnnaBridge 189:f392fc9709a3 4591 #define DMA_ATTR_DMOD_MASK (0xF8U)
AnnaBridge 189:f392fc9709a3 4592 #define DMA_ATTR_DMOD_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 4593 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
AnnaBridge 189:f392fc9709a3 4594 #define DMA_ATTR_SSIZE_MASK (0x700U)
AnnaBridge 189:f392fc9709a3 4595 #define DMA_ATTR_SSIZE_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 4596 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
AnnaBridge 189:f392fc9709a3 4597 #define DMA_ATTR_SMOD_MASK (0xF800U)
AnnaBridge 189:f392fc9709a3 4598 #define DMA_ATTR_SMOD_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 4599 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
AnnaBridge 189:f392fc9709a3 4600
AnnaBridge 189:f392fc9709a3 4601 /* The count of DMA_ATTR */
AnnaBridge 189:f392fc9709a3 4602 #define DMA_ATTR_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4603
AnnaBridge 189:f392fc9709a3 4604 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
AnnaBridge 189:f392fc9709a3 4605 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 4606 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4607 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
AnnaBridge 189:f392fc9709a3 4608
AnnaBridge 189:f392fc9709a3 4609 /* The count of DMA_NBYTES_MLNO */
AnnaBridge 189:f392fc9709a3 4610 #define DMA_NBYTES_MLNO_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4611
AnnaBridge 189:f392fc9709a3 4612 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
AnnaBridge 189:f392fc9709a3 4613 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
AnnaBridge 189:f392fc9709a3 4614 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4615 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
AnnaBridge 189:f392fc9709a3 4616 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 4617 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 4618 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
AnnaBridge 189:f392fc9709a3 4619 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 4620 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 4621 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
AnnaBridge 189:f392fc9709a3 4622
AnnaBridge 189:f392fc9709a3 4623 /* The count of DMA_NBYTES_MLOFFNO */
AnnaBridge 189:f392fc9709a3 4624 #define DMA_NBYTES_MLOFFNO_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4625
AnnaBridge 189:f392fc9709a3 4626 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
AnnaBridge 189:f392fc9709a3 4627 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
AnnaBridge 189:f392fc9709a3 4628 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4629 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
AnnaBridge 189:f392fc9709a3 4630 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
AnnaBridge 189:f392fc9709a3 4631 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 4632 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
AnnaBridge 189:f392fc9709a3 4633 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 4634 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 4635 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
AnnaBridge 189:f392fc9709a3 4636 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 4637 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 4638 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
AnnaBridge 189:f392fc9709a3 4639
AnnaBridge 189:f392fc9709a3 4640 /* The count of DMA_NBYTES_MLOFFYES */
AnnaBridge 189:f392fc9709a3 4641 #define DMA_NBYTES_MLOFFYES_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4642
AnnaBridge 189:f392fc9709a3 4643 /*! @name SLAST - TCD Last Source Address Adjustment */
AnnaBridge 189:f392fc9709a3 4644 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 4645 #define DMA_SLAST_SLAST_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4646 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
AnnaBridge 189:f392fc9709a3 4647
AnnaBridge 189:f392fc9709a3 4648 /* The count of DMA_SLAST */
AnnaBridge 189:f392fc9709a3 4649 #define DMA_SLAST_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4650
AnnaBridge 189:f392fc9709a3 4651 /*! @name DADDR - TCD Destination Address */
AnnaBridge 189:f392fc9709a3 4652 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 4653 #define DMA_DADDR_DADDR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4654 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
AnnaBridge 189:f392fc9709a3 4655
AnnaBridge 189:f392fc9709a3 4656 /* The count of DMA_DADDR */
AnnaBridge 189:f392fc9709a3 4657 #define DMA_DADDR_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4658
AnnaBridge 189:f392fc9709a3 4659 /*! @name DOFF - TCD Signed Destination Address Offset */
AnnaBridge 189:f392fc9709a3 4660 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 4661 #define DMA_DOFF_DOFF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4662 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
AnnaBridge 189:f392fc9709a3 4663
AnnaBridge 189:f392fc9709a3 4664 /* The count of DMA_DOFF */
AnnaBridge 189:f392fc9709a3 4665 #define DMA_DOFF_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4666
AnnaBridge 189:f392fc9709a3 4667 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 189:f392fc9709a3 4668 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
AnnaBridge 189:f392fc9709a3 4669 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4670 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
AnnaBridge 189:f392fc9709a3 4671 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 4672 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 4673 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
AnnaBridge 189:f392fc9709a3 4674
AnnaBridge 189:f392fc9709a3 4675 /* The count of DMA_CITER_ELINKNO */
AnnaBridge 189:f392fc9709a3 4676 #define DMA_CITER_ELINKNO_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4677
AnnaBridge 189:f392fc9709a3 4678 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 189:f392fc9709a3 4679 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 4680 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4681 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
AnnaBridge 189:f392fc9709a3 4682 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
AnnaBridge 189:f392fc9709a3 4683 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 4684 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
AnnaBridge 189:f392fc9709a3 4685 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 4686 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 4687 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
AnnaBridge 189:f392fc9709a3 4688
AnnaBridge 189:f392fc9709a3 4689 /* The count of DMA_CITER_ELINKYES */
AnnaBridge 189:f392fc9709a3 4690 #define DMA_CITER_ELINKYES_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4691
AnnaBridge 189:f392fc9709a3 4692 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
AnnaBridge 189:f392fc9709a3 4693 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 4694 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4695 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
AnnaBridge 189:f392fc9709a3 4696
AnnaBridge 189:f392fc9709a3 4697 /* The count of DMA_DLAST_SGA */
AnnaBridge 189:f392fc9709a3 4698 #define DMA_DLAST_SGA_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4699
AnnaBridge 189:f392fc9709a3 4700 /*! @name CSR - TCD Control and Status */
AnnaBridge 189:f392fc9709a3 4701 #define DMA_CSR_START_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 4702 #define DMA_CSR_START_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4703 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
AnnaBridge 189:f392fc9709a3 4704 #define DMA_CSR_INTMAJOR_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 4705 #define DMA_CSR_INTMAJOR_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 4706 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
AnnaBridge 189:f392fc9709a3 4707 #define DMA_CSR_INTHALF_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 4708 #define DMA_CSR_INTHALF_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 4709 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
AnnaBridge 189:f392fc9709a3 4710 #define DMA_CSR_DREQ_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 4711 #define DMA_CSR_DREQ_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 4712 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
AnnaBridge 189:f392fc9709a3 4713 #define DMA_CSR_ESG_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 4714 #define DMA_CSR_ESG_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4715 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
AnnaBridge 189:f392fc9709a3 4716 #define DMA_CSR_MAJORELINK_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 4717 #define DMA_CSR_MAJORELINK_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 4718 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
AnnaBridge 189:f392fc9709a3 4719 #define DMA_CSR_ACTIVE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4720 #define DMA_CSR_ACTIVE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4721 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
AnnaBridge 189:f392fc9709a3 4722 #define DMA_CSR_DONE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4723 #define DMA_CSR_DONE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4724 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
AnnaBridge 189:f392fc9709a3 4725 #define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 4726 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 4727 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
AnnaBridge 189:f392fc9709a3 4728 #define DMA_CSR_BWC_MASK (0xC000U)
AnnaBridge 189:f392fc9709a3 4729 #define DMA_CSR_BWC_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 4730 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
AnnaBridge 189:f392fc9709a3 4731
AnnaBridge 189:f392fc9709a3 4732 /* The count of DMA_CSR */
AnnaBridge 189:f392fc9709a3 4733 #define DMA_CSR_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4734
AnnaBridge 189:f392fc9709a3 4735 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 189:f392fc9709a3 4736 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
AnnaBridge 189:f392fc9709a3 4737 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4738 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
AnnaBridge 189:f392fc9709a3 4739 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 4740 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 4741 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
AnnaBridge 189:f392fc9709a3 4742
AnnaBridge 189:f392fc9709a3 4743 /* The count of DMA_BITER_ELINKNO */
AnnaBridge 189:f392fc9709a3 4744 #define DMA_BITER_ELINKNO_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4745
AnnaBridge 189:f392fc9709a3 4746 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 189:f392fc9709a3 4747 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 4748 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4749 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
AnnaBridge 189:f392fc9709a3 4750 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
AnnaBridge 189:f392fc9709a3 4751 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 4752 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
AnnaBridge 189:f392fc9709a3 4753 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 4754 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 4755 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
AnnaBridge 189:f392fc9709a3 4756
AnnaBridge 189:f392fc9709a3 4757 /* The count of DMA_BITER_ELINKYES */
AnnaBridge 189:f392fc9709a3 4758 #define DMA_BITER_ELINKYES_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4759
AnnaBridge 189:f392fc9709a3 4760
AnnaBridge 189:f392fc9709a3 4761 /*!
AnnaBridge 189:f392fc9709a3 4762 * @}
AnnaBridge 189:f392fc9709a3 4763 */ /* end of group DMA_Register_Masks */
AnnaBridge 189:f392fc9709a3 4764
AnnaBridge 189:f392fc9709a3 4765
AnnaBridge 189:f392fc9709a3 4766 /* DMA - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 4767 /** Peripheral DMA base address */
AnnaBridge 189:f392fc9709a3 4768 #define DMA_BASE (0x40008000u)
AnnaBridge 189:f392fc9709a3 4769 /** Peripheral DMA base pointer */
AnnaBridge 189:f392fc9709a3 4770 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 189:f392fc9709a3 4771 /** Array initializer of DMA peripheral base addresses */
AnnaBridge 189:f392fc9709a3 4772 #define DMA_BASE_ADDRS { DMA_BASE }
AnnaBridge 189:f392fc9709a3 4773 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 189:f392fc9709a3 4774 #define DMA_BASE_PTRS { DMA0 }
AnnaBridge 189:f392fc9709a3 4775 /** Interrupt vectors for the DMA peripheral type */
AnnaBridge 189:f392fc9709a3 4776 #define DMA_CHN_IRQS { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn }
AnnaBridge 189:f392fc9709a3 4777 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
AnnaBridge 189:f392fc9709a3 4778
AnnaBridge 189:f392fc9709a3 4779 /*!
AnnaBridge 189:f392fc9709a3 4780 * @}
AnnaBridge 189:f392fc9709a3 4781 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 4782
AnnaBridge 189:f392fc9709a3 4783
AnnaBridge 189:f392fc9709a3 4784 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 4785 -- DMAMUX Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 4786 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 4787
AnnaBridge 189:f392fc9709a3 4788 /*!
AnnaBridge 189:f392fc9709a3 4789 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 4790 * @{
AnnaBridge 189:f392fc9709a3 4791 */
AnnaBridge 189:f392fc9709a3 4792
AnnaBridge 189:f392fc9709a3 4793 /** DMAMUX - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 4794 typedef struct {
AnnaBridge 189:f392fc9709a3 4795 __IO uint8_t CHCFG[32]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 189:f392fc9709a3 4796 } DMAMUX_Type;
AnnaBridge 189:f392fc9709a3 4797
AnnaBridge 189:f392fc9709a3 4798 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 4799 -- DMAMUX Register Masks
AnnaBridge 189:f392fc9709a3 4800 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 4801
AnnaBridge 189:f392fc9709a3 4802 /*!
AnnaBridge 189:f392fc9709a3 4803 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 189:f392fc9709a3 4804 * @{
AnnaBridge 189:f392fc9709a3 4805 */
AnnaBridge 189:f392fc9709a3 4806
AnnaBridge 189:f392fc9709a3 4807 /*! @name CHCFG - Channel Configuration register */
AnnaBridge 189:f392fc9709a3 4808 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 4809 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4810 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 189:f392fc9709a3 4811 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 4812 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 4813 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
AnnaBridge 189:f392fc9709a3 4814 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 4815 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 4816 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
AnnaBridge 189:f392fc9709a3 4817
AnnaBridge 189:f392fc9709a3 4818 /* The count of DMAMUX_CHCFG */
AnnaBridge 189:f392fc9709a3 4819 #define DMAMUX_CHCFG_COUNT (32U)
AnnaBridge 189:f392fc9709a3 4820
AnnaBridge 189:f392fc9709a3 4821
AnnaBridge 189:f392fc9709a3 4822 /*!
AnnaBridge 189:f392fc9709a3 4823 * @}
AnnaBridge 189:f392fc9709a3 4824 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 189:f392fc9709a3 4825
AnnaBridge 189:f392fc9709a3 4826
AnnaBridge 189:f392fc9709a3 4827 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 4828 /** Peripheral DMAMUX base address */
AnnaBridge 189:f392fc9709a3 4829 #define DMAMUX_BASE (0x40021000u)
AnnaBridge 189:f392fc9709a3 4830 /** Peripheral DMAMUX base pointer */
AnnaBridge 189:f392fc9709a3 4831 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
AnnaBridge 189:f392fc9709a3 4832 /** Array initializer of DMAMUX peripheral base addresses */
AnnaBridge 189:f392fc9709a3 4833 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
AnnaBridge 189:f392fc9709a3 4834 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 189:f392fc9709a3 4835 #define DMAMUX_BASE_PTRS { DMAMUX }
AnnaBridge 189:f392fc9709a3 4836
AnnaBridge 189:f392fc9709a3 4837 /*!
AnnaBridge 189:f392fc9709a3 4838 * @}
AnnaBridge 189:f392fc9709a3 4839 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 4840
AnnaBridge 189:f392fc9709a3 4841
AnnaBridge 189:f392fc9709a3 4842 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 4843 -- EMVSIM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 4844 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 4845
AnnaBridge 189:f392fc9709a3 4846 /*!
AnnaBridge 189:f392fc9709a3 4847 * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 4848 * @{
AnnaBridge 189:f392fc9709a3 4849 */
AnnaBridge 189:f392fc9709a3 4850
AnnaBridge 189:f392fc9709a3 4851 /** EMVSIM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 4852 typedef struct {
AnnaBridge 189:f392fc9709a3 4853 __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 4854 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 4855 __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 4856 __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 4857 __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 4858 __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 4859 __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 4860 __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 4861 __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 4862 __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 4863 __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 4864 __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 4865 __IO uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 4866 __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 4867 __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */
AnnaBridge 189:f392fc9709a3 4868 __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */
AnnaBridge 189:f392fc9709a3 4869 __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 4870 __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
AnnaBridge 189:f392fc9709a3 4871 __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
AnnaBridge 189:f392fc9709a3 4872 } EMVSIM_Type;
AnnaBridge 189:f392fc9709a3 4873
AnnaBridge 189:f392fc9709a3 4874 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 4875 -- EMVSIM Register Masks
AnnaBridge 189:f392fc9709a3 4876 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 4877
AnnaBridge 189:f392fc9709a3 4878 /*!
AnnaBridge 189:f392fc9709a3 4879 * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
AnnaBridge 189:f392fc9709a3 4880 * @{
AnnaBridge 189:f392fc9709a3 4881 */
AnnaBridge 189:f392fc9709a3 4882
AnnaBridge 189:f392fc9709a3 4883 /*! @name VER_ID - Version ID Register */
AnnaBridge 189:f392fc9709a3 4884 #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 4885 #define EMVSIM_VER_ID_VER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4886 #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
AnnaBridge 189:f392fc9709a3 4887
AnnaBridge 189:f392fc9709a3 4888 /*! @name PARAM - Parameter Register */
AnnaBridge 189:f392fc9709a3 4889 #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 4890 #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4891 #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
AnnaBridge 189:f392fc9709a3 4892 #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 4893 #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 4894 #define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
AnnaBridge 189:f392fc9709a3 4895
AnnaBridge 189:f392fc9709a3 4896 /*! @name CLKCFG - Clock Configuration Register */
AnnaBridge 189:f392fc9709a3 4897 #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 4898 #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4899 #define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
AnnaBridge 189:f392fc9709a3 4900 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 4901 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 4902 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
AnnaBridge 189:f392fc9709a3 4903 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
AnnaBridge 189:f392fc9709a3 4904 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 4905 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
AnnaBridge 189:f392fc9709a3 4906
AnnaBridge 189:f392fc9709a3 4907 /*! @name DIVISOR - Baud Rate Divisor Register */
AnnaBridge 189:f392fc9709a3 4908 #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 4909 #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4910 #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
AnnaBridge 189:f392fc9709a3 4911
AnnaBridge 189:f392fc9709a3 4912 /*! @name CTRL - Control Register */
AnnaBridge 189:f392fc9709a3 4913 #define EMVSIM_CTRL_IC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 4914 #define EMVSIM_CTRL_IC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4915 #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
AnnaBridge 189:f392fc9709a3 4916 #define EMVSIM_CTRL_ICM_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 4917 #define EMVSIM_CTRL_ICM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 4918 #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
AnnaBridge 189:f392fc9709a3 4919 #define EMVSIM_CTRL_ANACK_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 4920 #define EMVSIM_CTRL_ANACK_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 4921 #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
AnnaBridge 189:f392fc9709a3 4922 #define EMVSIM_CTRL_ONACK_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 4923 #define EMVSIM_CTRL_ONACK_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 4924 #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
AnnaBridge 189:f392fc9709a3 4925 #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 4926 #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 4927 #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
AnnaBridge 189:f392fc9709a3 4928 #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 4929 #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 4930 #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
AnnaBridge 189:f392fc9709a3 4931 #define EMVSIM_CTRL_SW_RST_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 4932 #define EMVSIM_CTRL_SW_RST_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 4933 #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
AnnaBridge 189:f392fc9709a3 4934 #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 4935 #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 4936 #define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
AnnaBridge 189:f392fc9709a3 4937 #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 4938 #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 4939 #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
AnnaBridge 189:f392fc9709a3 4940 #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 4941 #define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 4942 #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
AnnaBridge 189:f392fc9709a3 4943 #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 4944 #define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 4945 #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
AnnaBridge 189:f392fc9709a3 4946 #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 4947 #define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 4948 #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
AnnaBridge 189:f392fc9709a3 4949 #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 4950 #define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 4951 #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
AnnaBridge 189:f392fc9709a3 4952 #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 4953 #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 4954 #define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
AnnaBridge 189:f392fc9709a3 4955 #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 4956 #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 4957 #define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
AnnaBridge 189:f392fc9709a3 4958 #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 4959 #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 4960 #define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
AnnaBridge 189:f392fc9709a3 4961 #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 4962 #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 4963 #define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
AnnaBridge 189:f392fc9709a3 4964 #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 4965 #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 4966 #define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
AnnaBridge 189:f392fc9709a3 4967 #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 4968 #define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 4969 #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
AnnaBridge 189:f392fc9709a3 4970 #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 4971 #define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 4972 #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
AnnaBridge 189:f392fc9709a3 4973 #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 4974 #define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 4975 #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
AnnaBridge 189:f392fc9709a3 4976 #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 4977 #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 4978 #define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
AnnaBridge 189:f392fc9709a3 4979 #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 4980 #define EMVSIM_CTRL_BWT_EN_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 4981 #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
AnnaBridge 189:f392fc9709a3 4982
AnnaBridge 189:f392fc9709a3 4983 /*! @name INT_MASK - Interrupt Mask Register */
AnnaBridge 189:f392fc9709a3 4984 #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 4985 #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 4986 #define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
AnnaBridge 189:f392fc9709a3 4987 #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 4988 #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 4989 #define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
AnnaBridge 189:f392fc9709a3 4990 #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 4991 #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 4992 #define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
AnnaBridge 189:f392fc9709a3 4993 #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 4994 #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 4995 #define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
AnnaBridge 189:f392fc9709a3 4996 #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 4997 #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 4998 #define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
AnnaBridge 189:f392fc9709a3 4999 #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 5000 #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 5001 #define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
AnnaBridge 189:f392fc9709a3 5002 #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 5003 #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5004 #define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
AnnaBridge 189:f392fc9709a3 5005 #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 5006 #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 5007 #define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
AnnaBridge 189:f392fc9709a3 5008 #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 5009 #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5010 #define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
AnnaBridge 189:f392fc9709a3 5011 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 5012 #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 5013 #define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
AnnaBridge 189:f392fc9709a3 5014 #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 5015 #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 5016 #define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
AnnaBridge 189:f392fc9709a3 5017 #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 5018 #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 5019 #define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
AnnaBridge 189:f392fc9709a3 5020 #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 5021 #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 5022 #define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
AnnaBridge 189:f392fc9709a3 5023 #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 5024 #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 5025 #define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
AnnaBridge 189:f392fc9709a3 5026 #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 5027 #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 5028 #define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
AnnaBridge 189:f392fc9709a3 5029 #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 5030 #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 5031 #define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
AnnaBridge 189:f392fc9709a3 5032
AnnaBridge 189:f392fc9709a3 5033 /*! @name RX_THD - Receiver Threshold Register */
AnnaBridge 189:f392fc9709a3 5034 #define EMVSIM_RX_THD_RDT_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 5035 #define EMVSIM_RX_THD_RDT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5036 #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
AnnaBridge 189:f392fc9709a3 5037 #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 5038 #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5039 #define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
AnnaBridge 189:f392fc9709a3 5040
AnnaBridge 189:f392fc9709a3 5041 /*! @name TX_THD - Transmitter Threshold Register */
AnnaBridge 189:f392fc9709a3 5042 #define EMVSIM_TX_THD_TDT_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 5043 #define EMVSIM_TX_THD_TDT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5044 #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
AnnaBridge 189:f392fc9709a3 5045 #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 5046 #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5047 #define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
AnnaBridge 189:f392fc9709a3 5048
AnnaBridge 189:f392fc9709a3 5049 /*! @name RX_STATUS - Receive Status Register */
AnnaBridge 189:f392fc9709a3 5050 #define EMVSIM_RX_STATUS_RFO_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5051 #define EMVSIM_RX_STATUS_RFO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5052 #define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
AnnaBridge 189:f392fc9709a3 5053 #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 5054 #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5055 #define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
AnnaBridge 189:f392fc9709a3 5056 #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 5057 #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 5058 #define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
AnnaBridge 189:f392fc9709a3 5059 #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 5060 #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5061 #define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
AnnaBridge 189:f392fc9709a3 5062 #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 5063 #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 5064 #define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
AnnaBridge 189:f392fc9709a3 5065 #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 5066 #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5067 #define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
AnnaBridge 189:f392fc9709a3 5068 #define EMVSIM_RX_STATUS_RTE_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 5069 #define EMVSIM_RX_STATUS_RTE_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 5070 #define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
AnnaBridge 189:f392fc9709a3 5071 #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 5072 #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 5073 #define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
AnnaBridge 189:f392fc9709a3 5074 #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 5075 #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 5076 #define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
AnnaBridge 189:f392fc9709a3 5077 #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 5078 #define EMVSIM_RX_STATUS_PEF_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 5079 #define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
AnnaBridge 189:f392fc9709a3 5080 #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 5081 #define EMVSIM_RX_STATUS_FEF_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 5082 #define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
AnnaBridge 189:f392fc9709a3 5083 #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 5084 #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5085 #define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
AnnaBridge 189:f392fc9709a3 5086 #define EMVSIM_RX_STATUS_RX_CNT_MASK (0x1F000000U)
AnnaBridge 189:f392fc9709a3 5087 #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5088 #define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
AnnaBridge 189:f392fc9709a3 5089
AnnaBridge 189:f392fc9709a3 5090 /*! @name TX_STATUS - Transmitter Status Register */
AnnaBridge 189:f392fc9709a3 5091 #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5092 #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5093 #define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
AnnaBridge 189:f392fc9709a3 5094 #define EMVSIM_TX_STATUS_TFE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 5095 #define EMVSIM_TX_STATUS_TFE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 5096 #define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
AnnaBridge 189:f392fc9709a3 5097 #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 5098 #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5099 #define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
AnnaBridge 189:f392fc9709a3 5100 #define EMVSIM_TX_STATUS_TCF_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 5101 #define EMVSIM_TX_STATUS_TCF_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 5102 #define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
AnnaBridge 189:f392fc9709a3 5103 #define EMVSIM_TX_STATUS_TFF_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 5104 #define EMVSIM_TX_STATUS_TFF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5105 #define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
AnnaBridge 189:f392fc9709a3 5106 #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 5107 #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 5108 #define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
AnnaBridge 189:f392fc9709a3 5109 #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 5110 #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5111 #define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
AnnaBridge 189:f392fc9709a3 5112 #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 5113 #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 5114 #define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
AnnaBridge 189:f392fc9709a3 5115 #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 5116 #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5117 #define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
AnnaBridge 189:f392fc9709a3 5118 #define EMVSIM_TX_STATUS_TX_CNT_MASK (0x1F000000U)
AnnaBridge 189:f392fc9709a3 5119 #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5120 #define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
AnnaBridge 189:f392fc9709a3 5121
AnnaBridge 189:f392fc9709a3 5122 /*! @name PCSR - Port Control and Status Register */
AnnaBridge 189:f392fc9709a3 5123 #define EMVSIM_PCSR_SAPD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5124 #define EMVSIM_PCSR_SAPD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5125 #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
AnnaBridge 189:f392fc9709a3 5126 #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 5127 #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 5128 #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
AnnaBridge 189:f392fc9709a3 5129 #define EMVSIM_PCSR_VCCENP_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 5130 #define EMVSIM_PCSR_VCCENP_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 5131 #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
AnnaBridge 189:f392fc9709a3 5132 #define EMVSIM_PCSR_SRST_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 5133 #define EMVSIM_PCSR_SRST_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 5134 #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
AnnaBridge 189:f392fc9709a3 5135 #define EMVSIM_PCSR_SCEN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 5136 #define EMVSIM_PCSR_SCEN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5137 #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
AnnaBridge 189:f392fc9709a3 5138 #define EMVSIM_PCSR_SCSP_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 5139 #define EMVSIM_PCSR_SCSP_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 5140 #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
AnnaBridge 189:f392fc9709a3 5141 #define EMVSIM_PCSR_SPD_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 5142 #define EMVSIM_PCSR_SPD_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 5143 #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
AnnaBridge 189:f392fc9709a3 5144 #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 5145 #define EMVSIM_PCSR_SPDIM_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5146 #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
AnnaBridge 189:f392fc9709a3 5147 #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 5148 #define EMVSIM_PCSR_SPDIF_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 5149 #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
AnnaBridge 189:f392fc9709a3 5150 #define EMVSIM_PCSR_SPDP_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 5151 #define EMVSIM_PCSR_SPDP_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 5152 #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
AnnaBridge 189:f392fc9709a3 5153 #define EMVSIM_PCSR_SPDES_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 5154 #define EMVSIM_PCSR_SPDES_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 5155 #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
AnnaBridge 189:f392fc9709a3 5156
AnnaBridge 189:f392fc9709a3 5157 /*! @name RX_BUF - Receive Data Read Buffer */
AnnaBridge 189:f392fc9709a3 5158 #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5159 #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5160 #define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
AnnaBridge 189:f392fc9709a3 5161
AnnaBridge 189:f392fc9709a3 5162 /*! @name TX_BUF - Transmit Data Buffer */
AnnaBridge 189:f392fc9709a3 5163 #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5164 #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5165 #define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
AnnaBridge 189:f392fc9709a3 5166
AnnaBridge 189:f392fc9709a3 5167 /*! @name TX_GETU - Transmitter Guard ETU Value Register */
AnnaBridge 189:f392fc9709a3 5168 #define EMVSIM_TX_GETU_GETU_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5169 #define EMVSIM_TX_GETU_GETU_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5170 #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
AnnaBridge 189:f392fc9709a3 5171
AnnaBridge 189:f392fc9709a3 5172 /*! @name CWT_VAL - Character Wait Time Value Register */
AnnaBridge 189:f392fc9709a3 5173 #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 5174 #define EMVSIM_CWT_VAL_CWT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5175 #define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
AnnaBridge 189:f392fc9709a3 5176
AnnaBridge 189:f392fc9709a3 5177 /*! @name BWT_VAL - Block Wait Time Value Register */
AnnaBridge 189:f392fc9709a3 5178 #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5179 #define EMVSIM_BWT_VAL_BWT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5180 #define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
AnnaBridge 189:f392fc9709a3 5181
AnnaBridge 189:f392fc9709a3 5182 /*! @name BGT_VAL - Block Guard Time Value Register */
AnnaBridge 189:f392fc9709a3 5183 #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 5184 #define EMVSIM_BGT_VAL_BGT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5185 #define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
AnnaBridge 189:f392fc9709a3 5186
AnnaBridge 189:f392fc9709a3 5187 /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
AnnaBridge 189:f392fc9709a3 5188 #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 5189 #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5190 #define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
AnnaBridge 189:f392fc9709a3 5191
AnnaBridge 189:f392fc9709a3 5192 /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
AnnaBridge 189:f392fc9709a3 5193 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 5194 #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5195 #define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
AnnaBridge 189:f392fc9709a3 5196
AnnaBridge 189:f392fc9709a3 5197
AnnaBridge 189:f392fc9709a3 5198 /*!
AnnaBridge 189:f392fc9709a3 5199 * @}
AnnaBridge 189:f392fc9709a3 5200 */ /* end of group EMVSIM_Register_Masks */
AnnaBridge 189:f392fc9709a3 5201
AnnaBridge 189:f392fc9709a3 5202
AnnaBridge 189:f392fc9709a3 5203 /* EMVSIM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 5204 /** Peripheral EMVSIM0 base address */
AnnaBridge 189:f392fc9709a3 5205 #define EMVSIM0_BASE (0x400D4000u)
AnnaBridge 189:f392fc9709a3 5206 /** Peripheral EMVSIM0 base pointer */
AnnaBridge 189:f392fc9709a3 5207 #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE)
AnnaBridge 189:f392fc9709a3 5208 /** Peripheral EMVSIM1 base address */
AnnaBridge 189:f392fc9709a3 5209 #define EMVSIM1_BASE (0x400D5000u)
AnnaBridge 189:f392fc9709a3 5210 /** Peripheral EMVSIM1 base pointer */
AnnaBridge 189:f392fc9709a3 5211 #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE)
AnnaBridge 189:f392fc9709a3 5212 /** Array initializer of EMVSIM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 5213 #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE }
AnnaBridge 189:f392fc9709a3 5214 /** Array initializer of EMVSIM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 5215 #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 }
AnnaBridge 189:f392fc9709a3 5216 /** Interrupt vectors for the EMVSIM peripheral type */
AnnaBridge 189:f392fc9709a3 5217 #define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn }
AnnaBridge 189:f392fc9709a3 5218
AnnaBridge 189:f392fc9709a3 5219 /*!
AnnaBridge 189:f392fc9709a3 5220 * @}
AnnaBridge 189:f392fc9709a3 5221 */ /* end of group EMVSIM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 5222
AnnaBridge 189:f392fc9709a3 5223
AnnaBridge 189:f392fc9709a3 5224 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5225 -- EWM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5226 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5227
AnnaBridge 189:f392fc9709a3 5228 /*!
AnnaBridge 189:f392fc9709a3 5229 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5230 * @{
AnnaBridge 189:f392fc9709a3 5231 */
AnnaBridge 189:f392fc9709a3 5232
AnnaBridge 189:f392fc9709a3 5233 /** EWM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 5234 typedef struct {
AnnaBridge 189:f392fc9709a3 5235 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 5236 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 5237 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 5238 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 5239 __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 5240 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 5241 } EWM_Type;
AnnaBridge 189:f392fc9709a3 5242
AnnaBridge 189:f392fc9709a3 5243 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5244 -- EWM Register Masks
AnnaBridge 189:f392fc9709a3 5245 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5246
AnnaBridge 189:f392fc9709a3 5247 /*!
AnnaBridge 189:f392fc9709a3 5248 * @addtogroup EWM_Register_Masks EWM Register Masks
AnnaBridge 189:f392fc9709a3 5249 * @{
AnnaBridge 189:f392fc9709a3 5250 */
AnnaBridge 189:f392fc9709a3 5251
AnnaBridge 189:f392fc9709a3 5252 /*! @name CTRL - Control Register */
AnnaBridge 189:f392fc9709a3 5253 #define EWM_CTRL_EWMEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5254 #define EWM_CTRL_EWMEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5255 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
AnnaBridge 189:f392fc9709a3 5256 #define EWM_CTRL_ASSIN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 5257 #define EWM_CTRL_ASSIN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 5258 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
AnnaBridge 189:f392fc9709a3 5259 #define EWM_CTRL_INEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 5260 #define EWM_CTRL_INEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 5261 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
AnnaBridge 189:f392fc9709a3 5262 #define EWM_CTRL_INTEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 5263 #define EWM_CTRL_INTEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 5264 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
AnnaBridge 189:f392fc9709a3 5265
AnnaBridge 189:f392fc9709a3 5266 /*! @name SERV - Service Register */
AnnaBridge 189:f392fc9709a3 5267 #define EWM_SERV_SERVICE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5268 #define EWM_SERV_SERVICE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5269 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
AnnaBridge 189:f392fc9709a3 5270
AnnaBridge 189:f392fc9709a3 5271 /*! @name CMPL - Compare Low Register */
AnnaBridge 189:f392fc9709a3 5272 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5273 #define EWM_CMPL_COMPAREL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5274 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
AnnaBridge 189:f392fc9709a3 5275
AnnaBridge 189:f392fc9709a3 5276 /*! @name CMPH - Compare High Register */
AnnaBridge 189:f392fc9709a3 5277 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5278 #define EWM_CMPH_COMPAREH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5279 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
AnnaBridge 189:f392fc9709a3 5280
AnnaBridge 189:f392fc9709a3 5281 /*! @name CLKCTRL - Clock Control Register */
AnnaBridge 189:f392fc9709a3 5282 #define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 5283 #define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5284 #define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 5285
AnnaBridge 189:f392fc9709a3 5286 /*! @name CLKPRESCALER - Clock Prescaler Register */
AnnaBridge 189:f392fc9709a3 5287 #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5288 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5289 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
AnnaBridge 189:f392fc9709a3 5290
AnnaBridge 189:f392fc9709a3 5291
AnnaBridge 189:f392fc9709a3 5292 /*!
AnnaBridge 189:f392fc9709a3 5293 * @}
AnnaBridge 189:f392fc9709a3 5294 */ /* end of group EWM_Register_Masks */
AnnaBridge 189:f392fc9709a3 5295
AnnaBridge 189:f392fc9709a3 5296
AnnaBridge 189:f392fc9709a3 5297 /* EWM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 5298 /** Peripheral EWM base address */
AnnaBridge 189:f392fc9709a3 5299 #define EWM_BASE (0x40061000u)
AnnaBridge 189:f392fc9709a3 5300 /** Peripheral EWM base pointer */
AnnaBridge 189:f392fc9709a3 5301 #define EWM ((EWM_Type *)EWM_BASE)
AnnaBridge 189:f392fc9709a3 5302 /** Array initializer of EWM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 5303 #define EWM_BASE_ADDRS { EWM_BASE }
AnnaBridge 189:f392fc9709a3 5304 /** Array initializer of EWM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 5305 #define EWM_BASE_PTRS { EWM }
AnnaBridge 189:f392fc9709a3 5306 /** Interrupt vectors for the EWM peripheral type */
AnnaBridge 189:f392fc9709a3 5307 #define EWM_IRQS { WDOG_EWM_IRQn }
AnnaBridge 189:f392fc9709a3 5308
AnnaBridge 189:f392fc9709a3 5309 /*!
AnnaBridge 189:f392fc9709a3 5310 * @}
AnnaBridge 189:f392fc9709a3 5311 */ /* end of group EWM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 5312
AnnaBridge 189:f392fc9709a3 5313
AnnaBridge 189:f392fc9709a3 5314 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5315 -- FB Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5316 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5317
AnnaBridge 189:f392fc9709a3 5318 /*!
AnnaBridge 189:f392fc9709a3 5319 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5320 * @{
AnnaBridge 189:f392fc9709a3 5321 */
AnnaBridge 189:f392fc9709a3 5322
AnnaBridge 189:f392fc9709a3 5323 /** FB - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 5324 typedef struct {
AnnaBridge 189:f392fc9709a3 5325 struct { /* offset: 0x0, array step: 0xC */
AnnaBridge 189:f392fc9709a3 5326 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
AnnaBridge 189:f392fc9709a3 5327 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
AnnaBridge 189:f392fc9709a3 5328 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
AnnaBridge 189:f392fc9709a3 5329 } CS[6];
AnnaBridge 189:f392fc9709a3 5330 uint8_t RESERVED_0[24];
AnnaBridge 189:f392fc9709a3 5331 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
AnnaBridge 189:f392fc9709a3 5332 } FB_Type;
AnnaBridge 189:f392fc9709a3 5333
AnnaBridge 189:f392fc9709a3 5334 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5335 -- FB Register Masks
AnnaBridge 189:f392fc9709a3 5336 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5337
AnnaBridge 189:f392fc9709a3 5338 /*!
AnnaBridge 189:f392fc9709a3 5339 * @addtogroup FB_Register_Masks FB Register Masks
AnnaBridge 189:f392fc9709a3 5340 * @{
AnnaBridge 189:f392fc9709a3 5341 */
AnnaBridge 189:f392fc9709a3 5342
AnnaBridge 189:f392fc9709a3 5343 /*! @name CSAR - Chip Select Address Register */
AnnaBridge 189:f392fc9709a3 5344 #define FB_CSAR_BA_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 5345 #define FB_CSAR_BA_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5346 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
AnnaBridge 189:f392fc9709a3 5347
AnnaBridge 189:f392fc9709a3 5348 /* The count of FB_CSAR */
AnnaBridge 189:f392fc9709a3 5349 #define FB_CSAR_COUNT (6U)
AnnaBridge 189:f392fc9709a3 5350
AnnaBridge 189:f392fc9709a3 5351 /*! @name CSMR - Chip Select Mask Register */
AnnaBridge 189:f392fc9709a3 5352 #define FB_CSMR_V_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5353 #define FB_CSMR_V_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5354 #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
AnnaBridge 189:f392fc9709a3 5355 #define FB_CSMR_WP_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 5356 #define FB_CSMR_WP_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5357 #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
AnnaBridge 189:f392fc9709a3 5358 #define FB_CSMR_BAM_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 5359 #define FB_CSMR_BAM_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5360 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
AnnaBridge 189:f392fc9709a3 5361
AnnaBridge 189:f392fc9709a3 5362 /* The count of FB_CSMR */
AnnaBridge 189:f392fc9709a3 5363 #define FB_CSMR_COUNT (6U)
AnnaBridge 189:f392fc9709a3 5364
AnnaBridge 189:f392fc9709a3 5365 /*! @name CSCR - Chip Select Control Register */
AnnaBridge 189:f392fc9709a3 5366 #define FB_CSCR_BSTW_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 5367 #define FB_CSCR_BSTW_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 5368 #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
AnnaBridge 189:f392fc9709a3 5369 #define FB_CSCR_BSTR_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 5370 #define FB_CSCR_BSTR_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5371 #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
AnnaBridge 189:f392fc9709a3 5372 #define FB_CSCR_BEM_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 5373 #define FB_CSCR_BEM_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 5374 #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
AnnaBridge 189:f392fc9709a3 5375 #define FB_CSCR_PS_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 5376 #define FB_CSCR_PS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5377 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
AnnaBridge 189:f392fc9709a3 5378 #define FB_CSCR_AA_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 5379 #define FB_CSCR_AA_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5380 #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
AnnaBridge 189:f392fc9709a3 5381 #define FB_CSCR_BLS_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 5382 #define FB_CSCR_BLS_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 5383 #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
AnnaBridge 189:f392fc9709a3 5384 #define FB_CSCR_WS_MASK (0xFC00U)
AnnaBridge 189:f392fc9709a3 5385 #define FB_CSCR_WS_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 5386 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
AnnaBridge 189:f392fc9709a3 5387 #define FB_CSCR_WRAH_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 5388 #define FB_CSCR_WRAH_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5389 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
AnnaBridge 189:f392fc9709a3 5390 #define FB_CSCR_RDAH_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 5391 #define FB_CSCR_RDAH_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 5392 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
AnnaBridge 189:f392fc9709a3 5393 #define FB_CSCR_ASET_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 5394 #define FB_CSCR_ASET_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 5395 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
AnnaBridge 189:f392fc9709a3 5396 #define FB_CSCR_EXTS_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 5397 #define FB_CSCR_EXTS_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 5398 #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
AnnaBridge 189:f392fc9709a3 5399 #define FB_CSCR_SWSEN_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 5400 #define FB_CSCR_SWSEN_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 5401 #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
AnnaBridge 189:f392fc9709a3 5402 #define FB_CSCR_SWS_MASK (0xFC000000U)
AnnaBridge 189:f392fc9709a3 5403 #define FB_CSCR_SWS_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 5404 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
AnnaBridge 189:f392fc9709a3 5405
AnnaBridge 189:f392fc9709a3 5406 /* The count of FB_CSCR */
AnnaBridge 189:f392fc9709a3 5407 #define FB_CSCR_COUNT (6U)
AnnaBridge 189:f392fc9709a3 5408
AnnaBridge 189:f392fc9709a3 5409 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
AnnaBridge 189:f392fc9709a3 5410 #define FB_CSPMCR_GROUP5_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 5411 #define FB_CSPMCR_GROUP5_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 5412 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
AnnaBridge 189:f392fc9709a3 5413 #define FB_CSPMCR_GROUP4_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 5414 #define FB_CSPMCR_GROUP4_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5415 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
AnnaBridge 189:f392fc9709a3 5416 #define FB_CSPMCR_GROUP3_MASK (0xF00000U)
AnnaBridge 189:f392fc9709a3 5417 #define FB_CSPMCR_GROUP3_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 5418 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
AnnaBridge 189:f392fc9709a3 5419 #define FB_CSPMCR_GROUP2_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 5420 #define FB_CSPMCR_GROUP2_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5421 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
AnnaBridge 189:f392fc9709a3 5422 #define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 5423 #define FB_CSPMCR_GROUP1_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 5424 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
AnnaBridge 189:f392fc9709a3 5425
AnnaBridge 189:f392fc9709a3 5426
AnnaBridge 189:f392fc9709a3 5427 /*!
AnnaBridge 189:f392fc9709a3 5428 * @}
AnnaBridge 189:f392fc9709a3 5429 */ /* end of group FB_Register_Masks */
AnnaBridge 189:f392fc9709a3 5430
AnnaBridge 189:f392fc9709a3 5431
AnnaBridge 189:f392fc9709a3 5432 /* FB - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 5433 /** Peripheral FB base address */
AnnaBridge 189:f392fc9709a3 5434 #define FB_BASE (0x4000C000u)
AnnaBridge 189:f392fc9709a3 5435 /** Peripheral FB base pointer */
AnnaBridge 189:f392fc9709a3 5436 #define FB ((FB_Type *)FB_BASE)
AnnaBridge 189:f392fc9709a3 5437 /** Array initializer of FB peripheral base addresses */
AnnaBridge 189:f392fc9709a3 5438 #define FB_BASE_ADDRS { FB_BASE }
AnnaBridge 189:f392fc9709a3 5439 /** Array initializer of FB peripheral base pointers */
AnnaBridge 189:f392fc9709a3 5440 #define FB_BASE_PTRS { FB }
AnnaBridge 189:f392fc9709a3 5441
AnnaBridge 189:f392fc9709a3 5442 /*!
AnnaBridge 189:f392fc9709a3 5443 * @}
AnnaBridge 189:f392fc9709a3 5444 */ /* end of group FB_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 5445
AnnaBridge 189:f392fc9709a3 5446
AnnaBridge 189:f392fc9709a3 5447 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5448 -- FLEXIO Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5449 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5450
AnnaBridge 189:f392fc9709a3 5451 /*!
AnnaBridge 189:f392fc9709a3 5452 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5453 * @{
AnnaBridge 189:f392fc9709a3 5454 */
AnnaBridge 189:f392fc9709a3 5455
AnnaBridge 189:f392fc9709a3 5456 /** FLEXIO - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 5457 typedef struct {
AnnaBridge 189:f392fc9709a3 5458 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 5459 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 5460 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 5461 __I uint32_t PIN; /**< Pin State Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 5462 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 5463 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 5464 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 5465 uint8_t RESERVED_0[4];
AnnaBridge 189:f392fc9709a3 5466 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 5467 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 5468 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 5469 uint8_t RESERVED_1[4];
AnnaBridge 189:f392fc9709a3 5470 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 5471 uint8_t RESERVED_2[12];
AnnaBridge 189:f392fc9709a3 5472 __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 5473 uint8_t RESERVED_3[60];
AnnaBridge 189:f392fc9709a3 5474 __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5475 uint8_t RESERVED_4[96];
AnnaBridge 189:f392fc9709a3 5476 __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5477 uint8_t RESERVED_5[224];
AnnaBridge 189:f392fc9709a3 5478 __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5479 uint8_t RESERVED_6[96];
AnnaBridge 189:f392fc9709a3 5480 __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5481 uint8_t RESERVED_7[96];
AnnaBridge 189:f392fc9709a3 5482 __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5483 uint8_t RESERVED_8[96];
AnnaBridge 189:f392fc9709a3 5484 __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5485 uint8_t RESERVED_9[96];
AnnaBridge 189:f392fc9709a3 5486 __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5487 uint8_t RESERVED_10[96];
AnnaBridge 189:f392fc9709a3 5488 __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5489 uint8_t RESERVED_11[96];
AnnaBridge 189:f392fc9709a3 5490 __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5491 uint8_t RESERVED_12[352];
AnnaBridge 189:f392fc9709a3 5492 __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5493 uint8_t RESERVED_13[96];
AnnaBridge 189:f392fc9709a3 5494 __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5495 uint8_t RESERVED_14[96];
AnnaBridge 189:f392fc9709a3 5496 __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5497 } FLEXIO_Type;
AnnaBridge 189:f392fc9709a3 5498
AnnaBridge 189:f392fc9709a3 5499 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5500 -- FLEXIO Register Masks
AnnaBridge 189:f392fc9709a3 5501 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5502
AnnaBridge 189:f392fc9709a3 5503 /*!
AnnaBridge 189:f392fc9709a3 5504 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
AnnaBridge 189:f392fc9709a3 5505 * @{
AnnaBridge 189:f392fc9709a3 5506 */
AnnaBridge 189:f392fc9709a3 5507
AnnaBridge 189:f392fc9709a3 5508 /*! @name VERID - Version ID Register */
AnnaBridge 189:f392fc9709a3 5509 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 5510 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5511 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
AnnaBridge 189:f392fc9709a3 5512 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 5513 #define FLEXIO_VERID_MINOR_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5514 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
AnnaBridge 189:f392fc9709a3 5515 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 5516 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5517 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
AnnaBridge 189:f392fc9709a3 5518
AnnaBridge 189:f392fc9709a3 5519 /*! @name PARAM - Parameter Register */
AnnaBridge 189:f392fc9709a3 5520 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5521 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5522 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
AnnaBridge 189:f392fc9709a3 5523 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 5524 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5525 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
AnnaBridge 189:f392fc9709a3 5526 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 5527 #define FLEXIO_PARAM_PIN_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5528 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
AnnaBridge 189:f392fc9709a3 5529 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 5530 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5531 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
AnnaBridge 189:f392fc9709a3 5532
AnnaBridge 189:f392fc9709a3 5533 /*! @name CTRL - FlexIO Control Register */
AnnaBridge 189:f392fc9709a3 5534 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5535 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5536 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
AnnaBridge 189:f392fc9709a3 5537 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 5538 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 5539 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
AnnaBridge 189:f392fc9709a3 5540 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 5541 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 5542 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
AnnaBridge 189:f392fc9709a3 5543 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 5544 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 5545 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
AnnaBridge 189:f392fc9709a3 5546 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 5547 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 5548 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
AnnaBridge 189:f392fc9709a3 5549
AnnaBridge 189:f392fc9709a3 5550 /*! @name PIN - Pin State Register */
AnnaBridge 189:f392fc9709a3 5551 #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5552 #define FLEXIO_PIN_PDI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5553 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
AnnaBridge 189:f392fc9709a3 5554
AnnaBridge 189:f392fc9709a3 5555 /*! @name SHIFTSTAT - Shifter Status Register */
AnnaBridge 189:f392fc9709a3 5556 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5557 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5558 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
AnnaBridge 189:f392fc9709a3 5559
AnnaBridge 189:f392fc9709a3 5560 /*! @name SHIFTERR - Shifter Error Register */
AnnaBridge 189:f392fc9709a3 5561 #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5562 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5563 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
AnnaBridge 189:f392fc9709a3 5564
AnnaBridge 189:f392fc9709a3 5565 /*! @name TIMSTAT - Timer Status Register */
AnnaBridge 189:f392fc9709a3 5566 #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5567 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5568 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
AnnaBridge 189:f392fc9709a3 5569
AnnaBridge 189:f392fc9709a3 5570 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
AnnaBridge 189:f392fc9709a3 5571 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5572 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5573 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
AnnaBridge 189:f392fc9709a3 5574
AnnaBridge 189:f392fc9709a3 5575 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
AnnaBridge 189:f392fc9709a3 5576 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5577 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5578 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
AnnaBridge 189:f392fc9709a3 5579
AnnaBridge 189:f392fc9709a3 5580 /*! @name TIMIEN - Timer Interrupt Enable Register */
AnnaBridge 189:f392fc9709a3 5581 #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5582 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5583 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
AnnaBridge 189:f392fc9709a3 5584
AnnaBridge 189:f392fc9709a3 5585 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
AnnaBridge 189:f392fc9709a3 5586 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 5587 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5588 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
AnnaBridge 189:f392fc9709a3 5589
AnnaBridge 189:f392fc9709a3 5590 /*! @name SHIFTSTATE - Shifter State Register */
AnnaBridge 189:f392fc9709a3 5591 #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 5592 #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5593 #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
AnnaBridge 189:f392fc9709a3 5594
AnnaBridge 189:f392fc9709a3 5595 /*! @name SHIFTCTL - Shifter Control N Register */
AnnaBridge 189:f392fc9709a3 5596 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 5597 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5598 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
AnnaBridge 189:f392fc9709a3 5599 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 5600 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 5601 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
AnnaBridge 189:f392fc9709a3 5602 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 5603 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5604 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
AnnaBridge 189:f392fc9709a3 5605 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 5606 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5607 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
AnnaBridge 189:f392fc9709a3 5608 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 5609 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 5610 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
AnnaBridge 189:f392fc9709a3 5611 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
AnnaBridge 189:f392fc9709a3 5612 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5613 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
AnnaBridge 189:f392fc9709a3 5614
AnnaBridge 189:f392fc9709a3 5615 /* The count of FLEXIO_SHIFTCTL */
AnnaBridge 189:f392fc9709a3 5616 #define FLEXIO_SHIFTCTL_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5617
AnnaBridge 189:f392fc9709a3 5618 /*! @name SHIFTCFG - Shifter Configuration N Register */
AnnaBridge 189:f392fc9709a3 5619 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 5620 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5621 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
AnnaBridge 189:f392fc9709a3 5622 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 5623 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5624 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
AnnaBridge 189:f392fc9709a3 5625 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 5626 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5627 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
AnnaBridge 189:f392fc9709a3 5628 #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
AnnaBridge 189:f392fc9709a3 5629 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5630 #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
AnnaBridge 189:f392fc9709a3 5631
AnnaBridge 189:f392fc9709a3 5632 /* The count of FLEXIO_SHIFTCFG */
AnnaBridge 189:f392fc9709a3 5633 #define FLEXIO_SHIFTCFG_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5634
AnnaBridge 189:f392fc9709a3 5635 /*! @name SHIFTBUF - Shifter Buffer N Register */
AnnaBridge 189:f392fc9709a3 5636 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5637 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5638 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
AnnaBridge 189:f392fc9709a3 5639
AnnaBridge 189:f392fc9709a3 5640 /* The count of FLEXIO_SHIFTBUF */
AnnaBridge 189:f392fc9709a3 5641 #define FLEXIO_SHIFTBUF_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5642
AnnaBridge 189:f392fc9709a3 5643 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
AnnaBridge 189:f392fc9709a3 5644 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5645 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5646 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
AnnaBridge 189:f392fc9709a3 5647
AnnaBridge 189:f392fc9709a3 5648 /* The count of FLEXIO_SHIFTBUFBIS */
AnnaBridge 189:f392fc9709a3 5649 #define FLEXIO_SHIFTBUFBIS_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5650
AnnaBridge 189:f392fc9709a3 5651 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
AnnaBridge 189:f392fc9709a3 5652 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5653 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5654 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
AnnaBridge 189:f392fc9709a3 5655
AnnaBridge 189:f392fc9709a3 5656 /* The count of FLEXIO_SHIFTBUFBYS */
AnnaBridge 189:f392fc9709a3 5657 #define FLEXIO_SHIFTBUFBYS_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5658
AnnaBridge 189:f392fc9709a3 5659 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
AnnaBridge 189:f392fc9709a3 5660 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5661 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5662 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
AnnaBridge 189:f392fc9709a3 5663
AnnaBridge 189:f392fc9709a3 5664 /* The count of FLEXIO_SHIFTBUFBBS */
AnnaBridge 189:f392fc9709a3 5665 #define FLEXIO_SHIFTBUFBBS_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5666
AnnaBridge 189:f392fc9709a3 5667 /*! @name TIMCTL - Timer Control N Register */
AnnaBridge 189:f392fc9709a3 5668 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 5669 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5670 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
AnnaBridge 189:f392fc9709a3 5671 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 5672 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 5673 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
AnnaBridge 189:f392fc9709a3 5674 #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 5675 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5676 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
AnnaBridge 189:f392fc9709a3 5677 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 5678 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5679 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
AnnaBridge 189:f392fc9709a3 5680 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 5681 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 5682 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
AnnaBridge 189:f392fc9709a3 5683 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 5684 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 5685 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
AnnaBridge 189:f392fc9709a3 5686 #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
AnnaBridge 189:f392fc9709a3 5687 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5688 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
AnnaBridge 189:f392fc9709a3 5689
AnnaBridge 189:f392fc9709a3 5690 /* The count of FLEXIO_TIMCTL */
AnnaBridge 189:f392fc9709a3 5691 #define FLEXIO_TIMCTL_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5692
AnnaBridge 189:f392fc9709a3 5693 /*! @name TIMCFG - Timer Configuration N Register */
AnnaBridge 189:f392fc9709a3 5694 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 5695 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 5696 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
AnnaBridge 189:f392fc9709a3 5697 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 5698 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5699 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
AnnaBridge 189:f392fc9709a3 5700 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
AnnaBridge 189:f392fc9709a3 5701 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5702 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
AnnaBridge 189:f392fc9709a3 5703 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
AnnaBridge 189:f392fc9709a3 5704 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 5705 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
AnnaBridge 189:f392fc9709a3 5706 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
AnnaBridge 189:f392fc9709a3 5707 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5708 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
AnnaBridge 189:f392fc9709a3 5709 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 5710 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 5711 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
AnnaBridge 189:f392fc9709a3 5712 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 5713 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5714 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
AnnaBridge 189:f392fc9709a3 5715
AnnaBridge 189:f392fc9709a3 5716 /* The count of FLEXIO_TIMCFG */
AnnaBridge 189:f392fc9709a3 5717 #define FLEXIO_TIMCFG_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5718
AnnaBridge 189:f392fc9709a3 5719 /*! @name TIMCMP - Timer Compare N Register */
AnnaBridge 189:f392fc9709a3 5720 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 5721 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5722 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
AnnaBridge 189:f392fc9709a3 5723
AnnaBridge 189:f392fc9709a3 5724 /* The count of FLEXIO_TIMCMP */
AnnaBridge 189:f392fc9709a3 5725 #define FLEXIO_TIMCMP_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5726
AnnaBridge 189:f392fc9709a3 5727 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
AnnaBridge 189:f392fc9709a3 5728 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5729 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5730 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
AnnaBridge 189:f392fc9709a3 5731
AnnaBridge 189:f392fc9709a3 5732 /* The count of FLEXIO_SHIFTBUFNBS */
AnnaBridge 189:f392fc9709a3 5733 #define FLEXIO_SHIFTBUFNBS_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5734
AnnaBridge 189:f392fc9709a3 5735 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
AnnaBridge 189:f392fc9709a3 5736 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5737 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5738 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
AnnaBridge 189:f392fc9709a3 5739
AnnaBridge 189:f392fc9709a3 5740 /* The count of FLEXIO_SHIFTBUFHWS */
AnnaBridge 189:f392fc9709a3 5741 #define FLEXIO_SHIFTBUFHWS_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5742
AnnaBridge 189:f392fc9709a3 5743 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
AnnaBridge 189:f392fc9709a3 5744 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5745 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5746 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
AnnaBridge 189:f392fc9709a3 5747
AnnaBridge 189:f392fc9709a3 5748 /* The count of FLEXIO_SHIFTBUFNIS */
AnnaBridge 189:f392fc9709a3 5749 #define FLEXIO_SHIFTBUFNIS_COUNT (8U)
AnnaBridge 189:f392fc9709a3 5750
AnnaBridge 189:f392fc9709a3 5751
AnnaBridge 189:f392fc9709a3 5752 /*!
AnnaBridge 189:f392fc9709a3 5753 * @}
AnnaBridge 189:f392fc9709a3 5754 */ /* end of group FLEXIO_Register_Masks */
AnnaBridge 189:f392fc9709a3 5755
AnnaBridge 189:f392fc9709a3 5756
AnnaBridge 189:f392fc9709a3 5757 /* FLEXIO - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 5758 /** Peripheral FLEXIO0 base address */
AnnaBridge 189:f392fc9709a3 5759 #define FLEXIO0_BASE (0x400DF000u)
AnnaBridge 189:f392fc9709a3 5760 /** Peripheral FLEXIO0 base pointer */
AnnaBridge 189:f392fc9709a3 5761 #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE)
AnnaBridge 189:f392fc9709a3 5762 /** Array initializer of FLEXIO peripheral base addresses */
AnnaBridge 189:f392fc9709a3 5763 #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE }
AnnaBridge 189:f392fc9709a3 5764 /** Array initializer of FLEXIO peripheral base pointers */
AnnaBridge 189:f392fc9709a3 5765 #define FLEXIO_BASE_PTRS { FLEXIO0 }
AnnaBridge 189:f392fc9709a3 5766 /** Interrupt vectors for the FLEXIO peripheral type */
AnnaBridge 189:f392fc9709a3 5767 #define FLEXIO_IRQS { FLEXIO0_IRQn }
AnnaBridge 189:f392fc9709a3 5768
AnnaBridge 189:f392fc9709a3 5769 /*!
AnnaBridge 189:f392fc9709a3 5770 * @}
AnnaBridge 189:f392fc9709a3 5771 */ /* end of group FLEXIO_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 5772
AnnaBridge 189:f392fc9709a3 5773
AnnaBridge 189:f392fc9709a3 5774 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5775 -- FMC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5776 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5777
AnnaBridge 189:f392fc9709a3 5778 /*!
AnnaBridge 189:f392fc9709a3 5779 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5780 * @{
AnnaBridge 189:f392fc9709a3 5781 */
AnnaBridge 189:f392fc9709a3 5782
AnnaBridge 189:f392fc9709a3 5783 /** FMC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 5784 typedef struct {
AnnaBridge 189:f392fc9709a3 5785 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 5786 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 5787 __I uint32_t RESERVED; /**< Reserved, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 5788 uint8_t RESERVED_0[244];
AnnaBridge 189:f392fc9709a3 5789 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5790 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5791 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5792 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 5793 uint8_t RESERVED_1[192];
AnnaBridge 189:f392fc9709a3 5794 struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */
AnnaBridge 189:f392fc9709a3 5795 __IO uint32_t DATA_UM; /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */
AnnaBridge 189:f392fc9709a3 5796 __IO uint32_t DATA_MU; /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */
AnnaBridge 189:f392fc9709a3 5797 __IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
AnnaBridge 189:f392fc9709a3 5798 __IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
AnnaBridge 189:f392fc9709a3 5799 } SET[4][4];
AnnaBridge 189:f392fc9709a3 5800 } FMC_Type;
AnnaBridge 189:f392fc9709a3 5801
AnnaBridge 189:f392fc9709a3 5802 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5803 -- FMC Register Masks
AnnaBridge 189:f392fc9709a3 5804 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5805
AnnaBridge 189:f392fc9709a3 5806 /*!
AnnaBridge 189:f392fc9709a3 5807 * @addtogroup FMC_Register_Masks FMC Register Masks
AnnaBridge 189:f392fc9709a3 5808 * @{
AnnaBridge 189:f392fc9709a3 5809 */
AnnaBridge 189:f392fc9709a3 5810
AnnaBridge 189:f392fc9709a3 5811 /*! @name PFAPR - Flash Access Protection Register */
AnnaBridge 189:f392fc9709a3 5812 #define FMC_PFAPR_M0AP_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 5813 #define FMC_PFAPR_M0AP_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5814 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
AnnaBridge 189:f392fc9709a3 5815 #define FMC_PFAPR_M1AP_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 5816 #define FMC_PFAPR_M1AP_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 5817 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
AnnaBridge 189:f392fc9709a3 5818 #define FMC_PFAPR_M2AP_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 5819 #define FMC_PFAPR_M2AP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5820 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
AnnaBridge 189:f392fc9709a3 5821 #define FMC_PFAPR_M3AP_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 5822 #define FMC_PFAPR_M3AP_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5823 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
AnnaBridge 189:f392fc9709a3 5824 #define FMC_PFAPR_M4AP_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 5825 #define FMC_PFAPR_M4AP_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 5826 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
AnnaBridge 189:f392fc9709a3 5827 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 5828 #define FMC_PFAPR_M0PFD_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 5829 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
AnnaBridge 189:f392fc9709a3 5830 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 5831 #define FMC_PFAPR_M1PFD_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 5832 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
AnnaBridge 189:f392fc9709a3 5833 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 5834 #define FMC_PFAPR_M2PFD_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 5835 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
AnnaBridge 189:f392fc9709a3 5836 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 5837 #define FMC_PFAPR_M3PFD_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 5838 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
AnnaBridge 189:f392fc9709a3 5839 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 5840 #define FMC_PFAPR_M4PFD_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 5841 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
AnnaBridge 189:f392fc9709a3 5842
AnnaBridge 189:f392fc9709a3 5843 /*! @name PFB0CR - Flash Bank 0 Control Register */
AnnaBridge 189:f392fc9709a3 5844 #define FMC_PFB0CR_B0SEBE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5845 #define FMC_PFB0CR_B0SEBE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5846 #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
AnnaBridge 189:f392fc9709a3 5847 #define FMC_PFB0CR_B0IPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 5848 #define FMC_PFB0CR_B0IPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 5849 #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
AnnaBridge 189:f392fc9709a3 5850 #define FMC_PFB0CR_B0DPE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 5851 #define FMC_PFB0CR_B0DPE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 5852 #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
AnnaBridge 189:f392fc9709a3 5853 #define FMC_PFB0CR_B0ICE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 5854 #define FMC_PFB0CR_B0ICE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 5855 #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
AnnaBridge 189:f392fc9709a3 5856 #define FMC_PFB0CR_B0DCE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 5857 #define FMC_PFB0CR_B0DCE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 5858 #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
AnnaBridge 189:f392fc9709a3 5859 #define FMC_PFB0CR_CRC_MASK (0xE0U)
AnnaBridge 189:f392fc9709a3 5860 #define FMC_PFB0CR_CRC_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 5861 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
AnnaBridge 189:f392fc9709a3 5862 #define FMC_PFB0CR_B0MW_MASK (0x60000U)
AnnaBridge 189:f392fc9709a3 5863 #define FMC_PFB0CR_B0MW_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 5864 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
AnnaBridge 189:f392fc9709a3 5865 #define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 5866 #define FMC_PFB0CR_S_B_INV_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 5867 #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
AnnaBridge 189:f392fc9709a3 5868 #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
AnnaBridge 189:f392fc9709a3 5869 #define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 5870 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
AnnaBridge 189:f392fc9709a3 5871 #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 5872 #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 5873 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
AnnaBridge 189:f392fc9709a3 5874 #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 5875 #define FMC_PFB0CR_B0RWSC_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 5876 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
AnnaBridge 189:f392fc9709a3 5877
AnnaBridge 189:f392fc9709a3 5878 /*! @name TAGVDW0S - Cache Tag Storage */
AnnaBridge 189:f392fc9709a3 5879 #define FMC_TAGVDW0S_valid_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5880 #define FMC_TAGVDW0S_valid_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5881 #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
AnnaBridge 189:f392fc9709a3 5882 #define FMC_TAGVDW0S_cache_tag_MASK (0xFFFC0U)
AnnaBridge 189:f392fc9709a3 5883 #define FMC_TAGVDW0S_cache_tag_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5884 #define FMC_TAGVDW0S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_cache_tag_SHIFT)) & FMC_TAGVDW0S_cache_tag_MASK)
AnnaBridge 189:f392fc9709a3 5885
AnnaBridge 189:f392fc9709a3 5886 /* The count of FMC_TAGVDW0S */
AnnaBridge 189:f392fc9709a3 5887 #define FMC_TAGVDW0S_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5888
AnnaBridge 189:f392fc9709a3 5889 /*! @name TAGVDW1S - Cache Tag Storage */
AnnaBridge 189:f392fc9709a3 5890 #define FMC_TAGVDW1S_valid_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5891 #define FMC_TAGVDW1S_valid_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5892 #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
AnnaBridge 189:f392fc9709a3 5893 #define FMC_TAGVDW1S_cache_tag_MASK (0xFFFC0U)
AnnaBridge 189:f392fc9709a3 5894 #define FMC_TAGVDW1S_cache_tag_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5895 #define FMC_TAGVDW1S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_cache_tag_SHIFT)) & FMC_TAGVDW1S_cache_tag_MASK)
AnnaBridge 189:f392fc9709a3 5896
AnnaBridge 189:f392fc9709a3 5897 /* The count of FMC_TAGVDW1S */
AnnaBridge 189:f392fc9709a3 5898 #define FMC_TAGVDW1S_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5899
AnnaBridge 189:f392fc9709a3 5900 /*! @name TAGVDW2S - Cache Tag Storage */
AnnaBridge 189:f392fc9709a3 5901 #define FMC_TAGVDW2S_valid_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5902 #define FMC_TAGVDW2S_valid_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5903 #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
AnnaBridge 189:f392fc9709a3 5904 #define FMC_TAGVDW2S_cache_tag_MASK (0xFFFC0U)
AnnaBridge 189:f392fc9709a3 5905 #define FMC_TAGVDW2S_cache_tag_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5906 #define FMC_TAGVDW2S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_cache_tag_SHIFT)) & FMC_TAGVDW2S_cache_tag_MASK)
AnnaBridge 189:f392fc9709a3 5907
AnnaBridge 189:f392fc9709a3 5908 /* The count of FMC_TAGVDW2S */
AnnaBridge 189:f392fc9709a3 5909 #define FMC_TAGVDW2S_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5910
AnnaBridge 189:f392fc9709a3 5911 /*! @name TAGVDW3S - Cache Tag Storage */
AnnaBridge 189:f392fc9709a3 5912 #define FMC_TAGVDW3S_valid_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 5913 #define FMC_TAGVDW3S_valid_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5914 #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
AnnaBridge 189:f392fc9709a3 5915 #define FMC_TAGVDW3S_cache_tag_MASK (0xFFFC0U)
AnnaBridge 189:f392fc9709a3 5916 #define FMC_TAGVDW3S_cache_tag_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 5917 #define FMC_TAGVDW3S_cache_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_cache_tag_SHIFT)) & FMC_TAGVDW3S_cache_tag_MASK)
AnnaBridge 189:f392fc9709a3 5918
AnnaBridge 189:f392fc9709a3 5919 /* The count of FMC_TAGVDW3S */
AnnaBridge 189:f392fc9709a3 5920 #define FMC_TAGVDW3S_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5921
AnnaBridge 189:f392fc9709a3 5922 /*! @name DATA_UM - Cache Data Storage (uppermost word) */
AnnaBridge 189:f392fc9709a3 5923 #define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5924 #define FMC_DATA_UM_data_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5925 #define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
AnnaBridge 189:f392fc9709a3 5926
AnnaBridge 189:f392fc9709a3 5927 /* The count of FMC_DATA_UM */
AnnaBridge 189:f392fc9709a3 5928 #define FMC_DATA_UM_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5929
AnnaBridge 189:f392fc9709a3 5930 /* The count of FMC_DATA_UM */
AnnaBridge 189:f392fc9709a3 5931 #define FMC_DATA_UM_COUNT2 (4U)
AnnaBridge 189:f392fc9709a3 5932
AnnaBridge 189:f392fc9709a3 5933 /*! @name DATA_MU - Cache Data Storage (mid-upper word) */
AnnaBridge 189:f392fc9709a3 5934 #define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5935 #define FMC_DATA_MU_data_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5936 #define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
AnnaBridge 189:f392fc9709a3 5937
AnnaBridge 189:f392fc9709a3 5938 /* The count of FMC_DATA_MU */
AnnaBridge 189:f392fc9709a3 5939 #define FMC_DATA_MU_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5940
AnnaBridge 189:f392fc9709a3 5941 /* The count of FMC_DATA_MU */
AnnaBridge 189:f392fc9709a3 5942 #define FMC_DATA_MU_COUNT2 (4U)
AnnaBridge 189:f392fc9709a3 5943
AnnaBridge 189:f392fc9709a3 5944 /*! @name DATA_ML - Cache Data Storage (mid-lower word) */
AnnaBridge 189:f392fc9709a3 5945 #define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5946 #define FMC_DATA_ML_data_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5947 #define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
AnnaBridge 189:f392fc9709a3 5948
AnnaBridge 189:f392fc9709a3 5949 /* The count of FMC_DATA_ML */
AnnaBridge 189:f392fc9709a3 5950 #define FMC_DATA_ML_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5951
AnnaBridge 189:f392fc9709a3 5952 /* The count of FMC_DATA_ML */
AnnaBridge 189:f392fc9709a3 5953 #define FMC_DATA_ML_COUNT2 (4U)
AnnaBridge 189:f392fc9709a3 5954
AnnaBridge 189:f392fc9709a3 5955 /*! @name DATA_LM - Cache Data Storage (lowermost word) */
AnnaBridge 189:f392fc9709a3 5956 #define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 5957 #define FMC_DATA_LM_data_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 5958 #define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
AnnaBridge 189:f392fc9709a3 5959
AnnaBridge 189:f392fc9709a3 5960 /* The count of FMC_DATA_LM */
AnnaBridge 189:f392fc9709a3 5961 #define FMC_DATA_LM_COUNT (4U)
AnnaBridge 189:f392fc9709a3 5962
AnnaBridge 189:f392fc9709a3 5963 /* The count of FMC_DATA_LM */
AnnaBridge 189:f392fc9709a3 5964 #define FMC_DATA_LM_COUNT2 (4U)
AnnaBridge 189:f392fc9709a3 5965
AnnaBridge 189:f392fc9709a3 5966
AnnaBridge 189:f392fc9709a3 5967 /*!
AnnaBridge 189:f392fc9709a3 5968 * @}
AnnaBridge 189:f392fc9709a3 5969 */ /* end of group FMC_Register_Masks */
AnnaBridge 189:f392fc9709a3 5970
AnnaBridge 189:f392fc9709a3 5971
AnnaBridge 189:f392fc9709a3 5972 /* FMC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 5973 /** Peripheral FMC base address */
AnnaBridge 189:f392fc9709a3 5974 #define FMC_BASE (0x4001F000u)
AnnaBridge 189:f392fc9709a3 5975 /** Peripheral FMC base pointer */
AnnaBridge 189:f392fc9709a3 5976 #define FMC ((FMC_Type *)FMC_BASE)
AnnaBridge 189:f392fc9709a3 5977 /** Array initializer of FMC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 5978 #define FMC_BASE_ADDRS { FMC_BASE }
AnnaBridge 189:f392fc9709a3 5979 /** Array initializer of FMC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 5980 #define FMC_BASE_PTRS { FMC }
AnnaBridge 189:f392fc9709a3 5981
AnnaBridge 189:f392fc9709a3 5982 /*!
AnnaBridge 189:f392fc9709a3 5983 * @}
AnnaBridge 189:f392fc9709a3 5984 */ /* end of group FMC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 5985
AnnaBridge 189:f392fc9709a3 5986
AnnaBridge 189:f392fc9709a3 5987 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 5988 -- FTFA Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5989 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 5990
AnnaBridge 189:f392fc9709a3 5991 /*!
AnnaBridge 189:f392fc9709a3 5992 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 5993 * @{
AnnaBridge 189:f392fc9709a3 5994 */
AnnaBridge 189:f392fc9709a3 5995
AnnaBridge 189:f392fc9709a3 5996 /** FTFA - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 5997 typedef struct {
AnnaBridge 189:f392fc9709a3 5998 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 5999 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 6000 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 6001 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 6002 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 6003 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 6004 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 189:f392fc9709a3 6005 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 189:f392fc9709a3 6006 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 6007 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 189:f392fc9709a3 6008 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 189:f392fc9709a3 6009 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 189:f392fc9709a3 6010 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 189:f392fc9709a3 6011 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 189:f392fc9709a3 6012 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 189:f392fc9709a3 6013 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 189:f392fc9709a3 6014 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 6015 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 189:f392fc9709a3 6016 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 189:f392fc9709a3 6017 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 189:f392fc9709a3 6018 uint8_t RESERVED_0[4];
AnnaBridge 189:f392fc9709a3 6019 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 6020 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
AnnaBridge 189:f392fc9709a3 6021 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
AnnaBridge 189:f392fc9709a3 6022 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
AnnaBridge 189:f392fc9709a3 6023 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 6024 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
AnnaBridge 189:f392fc9709a3 6025 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
AnnaBridge 189:f392fc9709a3 6026 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
AnnaBridge 189:f392fc9709a3 6027 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 6028 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
AnnaBridge 189:f392fc9709a3 6029 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
AnnaBridge 189:f392fc9709a3 6030 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
AnnaBridge 189:f392fc9709a3 6031 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 6032 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
AnnaBridge 189:f392fc9709a3 6033 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
AnnaBridge 189:f392fc9709a3 6034 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
AnnaBridge 189:f392fc9709a3 6035 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 6036 uint8_t RESERVED_1[2];
AnnaBridge 189:f392fc9709a3 6037 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
AnnaBridge 189:f392fc9709a3 6038 } FTFA_Type;
AnnaBridge 189:f392fc9709a3 6039
AnnaBridge 189:f392fc9709a3 6040 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 6041 -- FTFA Register Masks
AnnaBridge 189:f392fc9709a3 6042 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 6043
AnnaBridge 189:f392fc9709a3 6044 /*!
AnnaBridge 189:f392fc9709a3 6045 * @addtogroup FTFA_Register_Masks FTFA Register Masks
AnnaBridge 189:f392fc9709a3 6046 * @{
AnnaBridge 189:f392fc9709a3 6047 */
AnnaBridge 189:f392fc9709a3 6048
AnnaBridge 189:f392fc9709a3 6049 /*! @name FSTAT - Flash Status Register */
AnnaBridge 189:f392fc9709a3 6050 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6051 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6052 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
AnnaBridge 189:f392fc9709a3 6053 #define FTFA_FSTAT_FPVIOL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6054 #define FTFA_FSTAT_FPVIOL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6055 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
AnnaBridge 189:f392fc9709a3 6056 #define FTFA_FSTAT_ACCERR_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6057 #define FTFA_FSTAT_ACCERR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6058 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
AnnaBridge 189:f392fc9709a3 6059 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6060 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6061 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
AnnaBridge 189:f392fc9709a3 6062 #define FTFA_FSTAT_CCIF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6063 #define FTFA_FSTAT_CCIF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6064 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
AnnaBridge 189:f392fc9709a3 6065
AnnaBridge 189:f392fc9709a3 6066 /*! @name FCNFG - Flash Configuration Register */
AnnaBridge 189:f392fc9709a3 6067 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6068 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6069 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
AnnaBridge 189:f392fc9709a3 6070 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6071 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6072 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
AnnaBridge 189:f392fc9709a3 6073 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6074 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6075 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
AnnaBridge 189:f392fc9709a3 6076 #define FTFA_FCNFG_CCIE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6077 #define FTFA_FCNFG_CCIE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6078 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
AnnaBridge 189:f392fc9709a3 6079
AnnaBridge 189:f392fc9709a3 6080 /*! @name FSEC - Flash Security Register */
AnnaBridge 189:f392fc9709a3 6081 #define FTFA_FSEC_SEC_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 6082 #define FTFA_FSEC_SEC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6083 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
AnnaBridge 189:f392fc9709a3 6084 #define FTFA_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 6085 #define FTFA_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6086 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
AnnaBridge 189:f392fc9709a3 6087 #define FTFA_FSEC_MEEN_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 6088 #define FTFA_FSEC_MEEN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6089 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
AnnaBridge 189:f392fc9709a3 6090 #define FTFA_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 6091 #define FTFA_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6092 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
AnnaBridge 189:f392fc9709a3 6093
AnnaBridge 189:f392fc9709a3 6094 /*! @name FOPT - Flash Option Register */
AnnaBridge 189:f392fc9709a3 6095 #define FTFA_FOPT_OPT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6096 #define FTFA_FOPT_OPT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6097 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
AnnaBridge 189:f392fc9709a3 6098
AnnaBridge 189:f392fc9709a3 6099 /*! @name FCCOB3 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6100 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6101 #define FTFA_FCCOB3_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6102 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6103
AnnaBridge 189:f392fc9709a3 6104 /*! @name FCCOB2 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6105 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6106 #define FTFA_FCCOB2_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6107 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6108
AnnaBridge 189:f392fc9709a3 6109 /*! @name FCCOB1 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6110 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6111 #define FTFA_FCCOB1_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6112 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6113
AnnaBridge 189:f392fc9709a3 6114 /*! @name FCCOB0 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6115 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6116 #define FTFA_FCCOB0_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6117 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6118
AnnaBridge 189:f392fc9709a3 6119 /*! @name FCCOB7 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6120 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6121 #define FTFA_FCCOB7_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6122 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6123
AnnaBridge 189:f392fc9709a3 6124 /*! @name FCCOB6 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6125 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6126 #define FTFA_FCCOB6_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6127 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6128
AnnaBridge 189:f392fc9709a3 6129 /*! @name FCCOB5 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6130 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6131 #define FTFA_FCCOB5_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6132 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6133
AnnaBridge 189:f392fc9709a3 6134 /*! @name FCCOB4 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6135 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6136 #define FTFA_FCCOB4_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6137 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6138
AnnaBridge 189:f392fc9709a3 6139 /*! @name FCCOBB - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6140 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6141 #define FTFA_FCCOBB_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6142 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6143
AnnaBridge 189:f392fc9709a3 6144 /*! @name FCCOBA - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6145 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6146 #define FTFA_FCCOBA_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6147 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6148
AnnaBridge 189:f392fc9709a3 6149 /*! @name FCCOB9 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6150 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6151 #define FTFA_FCCOB9_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6152 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6153
AnnaBridge 189:f392fc9709a3 6154 /*! @name FCCOB8 - Flash Common Command Object Registers */
AnnaBridge 189:f392fc9709a3 6155 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6156 #define FTFA_FCCOB8_CCOBn_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6157 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
AnnaBridge 189:f392fc9709a3 6158
AnnaBridge 189:f392fc9709a3 6159 /*! @name FPROT3 - Program Flash Protection Registers */
AnnaBridge 189:f392fc9709a3 6160 #define FTFA_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6161 #define FTFA_FPROT3_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6162 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
AnnaBridge 189:f392fc9709a3 6163
AnnaBridge 189:f392fc9709a3 6164 /*! @name FPROT2 - Program Flash Protection Registers */
AnnaBridge 189:f392fc9709a3 6165 #define FTFA_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6166 #define FTFA_FPROT2_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6167 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
AnnaBridge 189:f392fc9709a3 6168
AnnaBridge 189:f392fc9709a3 6169 /*! @name FPROT1 - Program Flash Protection Registers */
AnnaBridge 189:f392fc9709a3 6170 #define FTFA_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6171 #define FTFA_FPROT1_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6172 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
AnnaBridge 189:f392fc9709a3 6173
AnnaBridge 189:f392fc9709a3 6174 /*! @name FPROT0 - Program Flash Protection Registers */
AnnaBridge 189:f392fc9709a3 6175 #define FTFA_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6176 #define FTFA_FPROT0_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6177 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
AnnaBridge 189:f392fc9709a3 6178
AnnaBridge 189:f392fc9709a3 6179 /*! @name XACCH3 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6180 #define FTFA_XACCH3_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6181 #define FTFA_XACCH3_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6182 #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
AnnaBridge 189:f392fc9709a3 6183
AnnaBridge 189:f392fc9709a3 6184 /*! @name XACCH2 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6185 #define FTFA_XACCH2_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6186 #define FTFA_XACCH2_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6187 #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
AnnaBridge 189:f392fc9709a3 6188
AnnaBridge 189:f392fc9709a3 6189 /*! @name XACCH1 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6190 #define FTFA_XACCH1_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6191 #define FTFA_XACCH1_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6192 #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
AnnaBridge 189:f392fc9709a3 6193
AnnaBridge 189:f392fc9709a3 6194 /*! @name XACCH0 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6195 #define FTFA_XACCH0_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6196 #define FTFA_XACCH0_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6197 #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
AnnaBridge 189:f392fc9709a3 6198
AnnaBridge 189:f392fc9709a3 6199 /*! @name XACCL3 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6200 #define FTFA_XACCL3_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6201 #define FTFA_XACCL3_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6202 #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
AnnaBridge 189:f392fc9709a3 6203
AnnaBridge 189:f392fc9709a3 6204 /*! @name XACCL2 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6205 #define FTFA_XACCL2_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6206 #define FTFA_XACCL2_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6207 #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
AnnaBridge 189:f392fc9709a3 6208
AnnaBridge 189:f392fc9709a3 6209 /*! @name XACCL1 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6210 #define FTFA_XACCL1_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6211 #define FTFA_XACCL1_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6212 #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
AnnaBridge 189:f392fc9709a3 6213
AnnaBridge 189:f392fc9709a3 6214 /*! @name XACCL0 - Execute-only Access Registers */
AnnaBridge 189:f392fc9709a3 6215 #define FTFA_XACCL0_XA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6216 #define FTFA_XACCL0_XA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6217 #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
AnnaBridge 189:f392fc9709a3 6218
AnnaBridge 189:f392fc9709a3 6219 /*! @name SACCH3 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6220 #define FTFA_SACCH3_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6221 #define FTFA_SACCH3_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6222 #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
AnnaBridge 189:f392fc9709a3 6223
AnnaBridge 189:f392fc9709a3 6224 /*! @name SACCH2 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6225 #define FTFA_SACCH2_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6226 #define FTFA_SACCH2_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6227 #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
AnnaBridge 189:f392fc9709a3 6228
AnnaBridge 189:f392fc9709a3 6229 /*! @name SACCH1 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6230 #define FTFA_SACCH1_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6231 #define FTFA_SACCH1_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6232 #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
AnnaBridge 189:f392fc9709a3 6233
AnnaBridge 189:f392fc9709a3 6234 /*! @name SACCH0 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6235 #define FTFA_SACCH0_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6236 #define FTFA_SACCH0_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6237 #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
AnnaBridge 189:f392fc9709a3 6238
AnnaBridge 189:f392fc9709a3 6239 /*! @name SACCL3 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6240 #define FTFA_SACCL3_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6241 #define FTFA_SACCL3_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6242 #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
AnnaBridge 189:f392fc9709a3 6243
AnnaBridge 189:f392fc9709a3 6244 /*! @name SACCL2 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6245 #define FTFA_SACCL2_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6246 #define FTFA_SACCL2_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6247 #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
AnnaBridge 189:f392fc9709a3 6248
AnnaBridge 189:f392fc9709a3 6249 /*! @name SACCL1 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6250 #define FTFA_SACCL1_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6251 #define FTFA_SACCL1_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6252 #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
AnnaBridge 189:f392fc9709a3 6253
AnnaBridge 189:f392fc9709a3 6254 /*! @name SACCL0 - Supervisor-only Access Registers */
AnnaBridge 189:f392fc9709a3 6255 #define FTFA_SACCL0_SA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6256 #define FTFA_SACCL0_SA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6257 #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
AnnaBridge 189:f392fc9709a3 6258
AnnaBridge 189:f392fc9709a3 6259 /*! @name FACSS - Flash Access Segment Size Register */
AnnaBridge 189:f392fc9709a3 6260 #define FTFA_FACSS_SGSIZE_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6261 #define FTFA_FACSS_SGSIZE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6262 #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
AnnaBridge 189:f392fc9709a3 6263
AnnaBridge 189:f392fc9709a3 6264 /*! @name FACSN - Flash Access Segment Number Register */
AnnaBridge 189:f392fc9709a3 6265 #define FTFA_FACSN_NUMSG_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 6266 #define FTFA_FACSN_NUMSG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6267 #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
AnnaBridge 189:f392fc9709a3 6268
AnnaBridge 189:f392fc9709a3 6269
AnnaBridge 189:f392fc9709a3 6270 /*!
AnnaBridge 189:f392fc9709a3 6271 * @}
AnnaBridge 189:f392fc9709a3 6272 */ /* end of group FTFA_Register_Masks */
AnnaBridge 189:f392fc9709a3 6273
AnnaBridge 189:f392fc9709a3 6274
AnnaBridge 189:f392fc9709a3 6275 /* FTFA - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 6276 /** Peripheral FTFA base address */
AnnaBridge 189:f392fc9709a3 6277 #define FTFA_BASE (0x40020000u)
AnnaBridge 189:f392fc9709a3 6278 /** Peripheral FTFA base pointer */
AnnaBridge 189:f392fc9709a3 6279 #define FTFA ((FTFA_Type *)FTFA_BASE)
AnnaBridge 189:f392fc9709a3 6280 /** Array initializer of FTFA peripheral base addresses */
AnnaBridge 189:f392fc9709a3 6281 #define FTFA_BASE_ADDRS { FTFA_BASE }
AnnaBridge 189:f392fc9709a3 6282 /** Array initializer of FTFA peripheral base pointers */
AnnaBridge 189:f392fc9709a3 6283 #define FTFA_BASE_PTRS { FTFA }
AnnaBridge 189:f392fc9709a3 6284 /** Interrupt vectors for the FTFA peripheral type */
AnnaBridge 189:f392fc9709a3 6285 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
AnnaBridge 189:f392fc9709a3 6286 #define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
AnnaBridge 189:f392fc9709a3 6287
AnnaBridge 189:f392fc9709a3 6288 /*!
AnnaBridge 189:f392fc9709a3 6289 * @}
AnnaBridge 189:f392fc9709a3 6290 */ /* end of group FTFA_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 6291
AnnaBridge 189:f392fc9709a3 6292
AnnaBridge 189:f392fc9709a3 6293 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 6294 -- FTM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 6295 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 6296
AnnaBridge 189:f392fc9709a3 6297 /*!
AnnaBridge 189:f392fc9709a3 6298 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 6299 * @{
AnnaBridge 189:f392fc9709a3 6300 */
AnnaBridge 189:f392fc9709a3 6301
AnnaBridge 189:f392fc9709a3 6302 /** FTM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 6303 typedef struct {
AnnaBridge 189:f392fc9709a3 6304 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 6305 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 6306 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 6307 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 6308 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 6309 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 6310 } CONTROLS[8];
AnnaBridge 189:f392fc9709a3 6311 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
AnnaBridge 189:f392fc9709a3 6312 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
AnnaBridge 189:f392fc9709a3 6313 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
AnnaBridge 189:f392fc9709a3 6314 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
AnnaBridge 189:f392fc9709a3 6315 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
AnnaBridge 189:f392fc9709a3 6316 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
AnnaBridge 189:f392fc9709a3 6317 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
AnnaBridge 189:f392fc9709a3 6318 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
AnnaBridge 189:f392fc9709a3 6319 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
AnnaBridge 189:f392fc9709a3 6320 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
AnnaBridge 189:f392fc9709a3 6321 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
AnnaBridge 189:f392fc9709a3 6322 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
AnnaBridge 189:f392fc9709a3 6323 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
AnnaBridge 189:f392fc9709a3 6324 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 6325 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 189:f392fc9709a3 6326 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
AnnaBridge 189:f392fc9709a3 6327 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
AnnaBridge 189:f392fc9709a3 6328 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
AnnaBridge 189:f392fc9709a3 6329 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
AnnaBridge 189:f392fc9709a3 6330 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
AnnaBridge 189:f392fc9709a3 6331 } FTM_Type;
AnnaBridge 189:f392fc9709a3 6332
AnnaBridge 189:f392fc9709a3 6333 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 6334 -- FTM Register Masks
AnnaBridge 189:f392fc9709a3 6335 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 6336
AnnaBridge 189:f392fc9709a3 6337 /*!
AnnaBridge 189:f392fc9709a3 6338 * @addtogroup FTM_Register_Masks FTM Register Masks
AnnaBridge 189:f392fc9709a3 6339 * @{
AnnaBridge 189:f392fc9709a3 6340 */
AnnaBridge 189:f392fc9709a3 6341
AnnaBridge 189:f392fc9709a3 6342 /*! @name SC - Status And Control */
AnnaBridge 189:f392fc9709a3 6343 #define FTM_SC_PS_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 6344 #define FTM_SC_PS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6345 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
AnnaBridge 189:f392fc9709a3 6346 #define FTM_SC_CLKS_MASK (0x18U)
AnnaBridge 189:f392fc9709a3 6347 #define FTM_SC_CLKS_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6348 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
AnnaBridge 189:f392fc9709a3 6349 #define FTM_SC_CPWMS_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6350 #define FTM_SC_CPWMS_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6351 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
AnnaBridge 189:f392fc9709a3 6352 #define FTM_SC_TOIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6353 #define FTM_SC_TOIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6354 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
AnnaBridge 189:f392fc9709a3 6355 #define FTM_SC_TOF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6356 #define FTM_SC_TOF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6357 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
AnnaBridge 189:f392fc9709a3 6358
AnnaBridge 189:f392fc9709a3 6359 /*! @name CNT - Counter */
AnnaBridge 189:f392fc9709a3 6360 #define FTM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 6361 #define FTM_CNT_COUNT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6362 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
AnnaBridge 189:f392fc9709a3 6363
AnnaBridge 189:f392fc9709a3 6364 /*! @name MOD - Modulo */
AnnaBridge 189:f392fc9709a3 6365 #define FTM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 6366 #define FTM_MOD_MOD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6367 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
AnnaBridge 189:f392fc9709a3 6368
AnnaBridge 189:f392fc9709a3 6369 /*! @name CnSC - Channel (n) Status And Control */
AnnaBridge 189:f392fc9709a3 6370 #define FTM_CnSC_DMA_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6371 #define FTM_CnSC_DMA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6372 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
AnnaBridge 189:f392fc9709a3 6373 #define FTM_CnSC_ICRST_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6374 #define FTM_CnSC_ICRST_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6375 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
AnnaBridge 189:f392fc9709a3 6376 #define FTM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6377 #define FTM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6378 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
AnnaBridge 189:f392fc9709a3 6379 #define FTM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6380 #define FTM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6381 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
AnnaBridge 189:f392fc9709a3 6382 #define FTM_CnSC_MSA_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6383 #define FTM_CnSC_MSA_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6384 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
AnnaBridge 189:f392fc9709a3 6385 #define FTM_CnSC_MSB_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6386 #define FTM_CnSC_MSB_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6387 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
AnnaBridge 189:f392fc9709a3 6388 #define FTM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6389 #define FTM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6390 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
AnnaBridge 189:f392fc9709a3 6391 #define FTM_CnSC_CHF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6392 #define FTM_CnSC_CHF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6393 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
AnnaBridge 189:f392fc9709a3 6394
AnnaBridge 189:f392fc9709a3 6395 /* The count of FTM_CnSC */
AnnaBridge 189:f392fc9709a3 6396 #define FTM_CnSC_COUNT (8U)
AnnaBridge 189:f392fc9709a3 6397
AnnaBridge 189:f392fc9709a3 6398 /*! @name CnV - Channel (n) Value */
AnnaBridge 189:f392fc9709a3 6399 #define FTM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 6400 #define FTM_CnV_VAL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6401 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
AnnaBridge 189:f392fc9709a3 6402
AnnaBridge 189:f392fc9709a3 6403 /* The count of FTM_CnV */
AnnaBridge 189:f392fc9709a3 6404 #define FTM_CnV_COUNT (8U)
AnnaBridge 189:f392fc9709a3 6405
AnnaBridge 189:f392fc9709a3 6406 /*! @name CNTIN - Counter Initial Value */
AnnaBridge 189:f392fc9709a3 6407 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 6408 #define FTM_CNTIN_INIT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6409 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
AnnaBridge 189:f392fc9709a3 6410
AnnaBridge 189:f392fc9709a3 6411 /*! @name STATUS - Capture And Compare Status */
AnnaBridge 189:f392fc9709a3 6412 #define FTM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6413 #define FTM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6414 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
AnnaBridge 189:f392fc9709a3 6415 #define FTM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6416 #define FTM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6417 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
AnnaBridge 189:f392fc9709a3 6418 #define FTM_STATUS_CH2F_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6419 #define FTM_STATUS_CH2F_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6420 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
AnnaBridge 189:f392fc9709a3 6421 #define FTM_STATUS_CH3F_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6422 #define FTM_STATUS_CH3F_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6423 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
AnnaBridge 189:f392fc9709a3 6424 #define FTM_STATUS_CH4F_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6425 #define FTM_STATUS_CH4F_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6426 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
AnnaBridge 189:f392fc9709a3 6427 #define FTM_STATUS_CH5F_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6428 #define FTM_STATUS_CH5F_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6429 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
AnnaBridge 189:f392fc9709a3 6430 #define FTM_STATUS_CH6F_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6431 #define FTM_STATUS_CH6F_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6432 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
AnnaBridge 189:f392fc9709a3 6433 #define FTM_STATUS_CH7F_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6434 #define FTM_STATUS_CH7F_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6435 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
AnnaBridge 189:f392fc9709a3 6436
AnnaBridge 189:f392fc9709a3 6437 /*! @name MODE - Features Mode Selection */
AnnaBridge 189:f392fc9709a3 6438 #define FTM_MODE_FTMEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6439 #define FTM_MODE_FTMEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6440 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
AnnaBridge 189:f392fc9709a3 6441 #define FTM_MODE_INIT_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6442 #define FTM_MODE_INIT_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6443 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
AnnaBridge 189:f392fc9709a3 6444 #define FTM_MODE_WPDIS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6445 #define FTM_MODE_WPDIS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6446 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
AnnaBridge 189:f392fc9709a3 6447 #define FTM_MODE_PWMSYNC_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6448 #define FTM_MODE_PWMSYNC_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6449 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
AnnaBridge 189:f392fc9709a3 6450 #define FTM_MODE_CAPTEST_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6451 #define FTM_MODE_CAPTEST_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6452 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
AnnaBridge 189:f392fc9709a3 6453 #define FTM_MODE_FAULTM_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 6454 #define FTM_MODE_FAULTM_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6455 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
AnnaBridge 189:f392fc9709a3 6456 #define FTM_MODE_FAULTIE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6457 #define FTM_MODE_FAULTIE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6458 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
AnnaBridge 189:f392fc9709a3 6459
AnnaBridge 189:f392fc9709a3 6460 /*! @name SYNC - Synchronization */
AnnaBridge 189:f392fc9709a3 6461 #define FTM_SYNC_CNTMIN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6462 #define FTM_SYNC_CNTMIN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6463 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
AnnaBridge 189:f392fc9709a3 6464 #define FTM_SYNC_CNTMAX_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6465 #define FTM_SYNC_CNTMAX_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6466 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
AnnaBridge 189:f392fc9709a3 6467 #define FTM_SYNC_REINIT_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6468 #define FTM_SYNC_REINIT_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6469 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
AnnaBridge 189:f392fc9709a3 6470 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6471 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6472 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
AnnaBridge 189:f392fc9709a3 6473 #define FTM_SYNC_TRIG0_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6474 #define FTM_SYNC_TRIG0_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6475 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
AnnaBridge 189:f392fc9709a3 6476 #define FTM_SYNC_TRIG1_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6477 #define FTM_SYNC_TRIG1_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6478 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
AnnaBridge 189:f392fc9709a3 6479 #define FTM_SYNC_TRIG2_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6480 #define FTM_SYNC_TRIG2_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6481 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
AnnaBridge 189:f392fc9709a3 6482 #define FTM_SYNC_SWSYNC_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6483 #define FTM_SYNC_SWSYNC_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6484 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
AnnaBridge 189:f392fc9709a3 6485
AnnaBridge 189:f392fc9709a3 6486 /*! @name OUTINIT - Initial State For Channels Output */
AnnaBridge 189:f392fc9709a3 6487 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6488 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6489 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
AnnaBridge 189:f392fc9709a3 6490 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6491 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6492 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
AnnaBridge 189:f392fc9709a3 6493 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6494 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6495 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
AnnaBridge 189:f392fc9709a3 6496 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6497 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6498 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
AnnaBridge 189:f392fc9709a3 6499 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6500 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6501 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
AnnaBridge 189:f392fc9709a3 6502 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6503 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6504 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
AnnaBridge 189:f392fc9709a3 6505 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6506 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6507 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
AnnaBridge 189:f392fc9709a3 6508 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6509 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6510 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
AnnaBridge 189:f392fc9709a3 6511
AnnaBridge 189:f392fc9709a3 6512 /*! @name OUTMASK - Output Mask */
AnnaBridge 189:f392fc9709a3 6513 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6514 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6515 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
AnnaBridge 189:f392fc9709a3 6516 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6517 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6518 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
AnnaBridge 189:f392fc9709a3 6519 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6520 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6521 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
AnnaBridge 189:f392fc9709a3 6522 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6523 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6524 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
AnnaBridge 189:f392fc9709a3 6525 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6526 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6527 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
AnnaBridge 189:f392fc9709a3 6528 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6529 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6530 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
AnnaBridge 189:f392fc9709a3 6531 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6532 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6533 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
AnnaBridge 189:f392fc9709a3 6534 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6535 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6536 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
AnnaBridge 189:f392fc9709a3 6537
AnnaBridge 189:f392fc9709a3 6538 /*! @name COMBINE - Function For Linked Channels */
AnnaBridge 189:f392fc9709a3 6539 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6540 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6541 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
AnnaBridge 189:f392fc9709a3 6542 #define FTM_COMBINE_COMP0_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6543 #define FTM_COMBINE_COMP0_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6544 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
AnnaBridge 189:f392fc9709a3 6545 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6546 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6547 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
AnnaBridge 189:f392fc9709a3 6548 #define FTM_COMBINE_DECAP0_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6549 #define FTM_COMBINE_DECAP0_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6550 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
AnnaBridge 189:f392fc9709a3 6551 #define FTM_COMBINE_DTEN0_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6552 #define FTM_COMBINE_DTEN0_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6553 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
AnnaBridge 189:f392fc9709a3 6554 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6555 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6556 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
AnnaBridge 189:f392fc9709a3 6557 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6558 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6559 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
AnnaBridge 189:f392fc9709a3 6560 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 6561 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 6562 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
AnnaBridge 189:f392fc9709a3 6563 #define FTM_COMBINE_COMP1_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 6564 #define FTM_COMBINE_COMP1_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 6565 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
AnnaBridge 189:f392fc9709a3 6566 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 6567 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 6568 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
AnnaBridge 189:f392fc9709a3 6569 #define FTM_COMBINE_DECAP1_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 6570 #define FTM_COMBINE_DECAP1_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 6571 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
AnnaBridge 189:f392fc9709a3 6572 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 6573 #define FTM_COMBINE_DTEN1_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 6574 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
AnnaBridge 189:f392fc9709a3 6575 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 6576 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 6577 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
AnnaBridge 189:f392fc9709a3 6578 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 6579 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 6580 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
AnnaBridge 189:f392fc9709a3 6581 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 6582 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 6583 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
AnnaBridge 189:f392fc9709a3 6584 #define FTM_COMBINE_COMP2_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 6585 #define FTM_COMBINE_COMP2_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 6586 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
AnnaBridge 189:f392fc9709a3 6587 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 6588 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 6589 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
AnnaBridge 189:f392fc9709a3 6590 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 6591 #define FTM_COMBINE_DECAP2_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 6592 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
AnnaBridge 189:f392fc9709a3 6593 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 6594 #define FTM_COMBINE_DTEN2_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 6595 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
AnnaBridge 189:f392fc9709a3 6596 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 6597 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 6598 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
AnnaBridge 189:f392fc9709a3 6599 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 6600 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 6601 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
AnnaBridge 189:f392fc9709a3 6602 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 6603 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 6604 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
AnnaBridge 189:f392fc9709a3 6605 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 6606 #define FTM_COMBINE_COMP3_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 6607 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
AnnaBridge 189:f392fc9709a3 6608 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 6609 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 6610 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
AnnaBridge 189:f392fc9709a3 6611 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 6612 #define FTM_COMBINE_DECAP3_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 6613 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
AnnaBridge 189:f392fc9709a3 6614 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 6615 #define FTM_COMBINE_DTEN3_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 6616 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
AnnaBridge 189:f392fc9709a3 6617 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 6618 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 6619 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
AnnaBridge 189:f392fc9709a3 6620 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 6621 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 6622 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
AnnaBridge 189:f392fc9709a3 6623
AnnaBridge 189:f392fc9709a3 6624 /*! @name DEADTIME - Deadtime Insertion Control */
AnnaBridge 189:f392fc9709a3 6625 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 6626 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6627 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
AnnaBridge 189:f392fc9709a3 6628 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 6629 #define FTM_DEADTIME_DTPS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6630 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
AnnaBridge 189:f392fc9709a3 6631
AnnaBridge 189:f392fc9709a3 6632 /*! @name EXTTRIG - FTM External Trigger */
AnnaBridge 189:f392fc9709a3 6633 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6634 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6635 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
AnnaBridge 189:f392fc9709a3 6636 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6637 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6638 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
AnnaBridge 189:f392fc9709a3 6639 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6640 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6641 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
AnnaBridge 189:f392fc9709a3 6642 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6643 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6644 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
AnnaBridge 189:f392fc9709a3 6645 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6646 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6647 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
AnnaBridge 189:f392fc9709a3 6648 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6649 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6650 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
AnnaBridge 189:f392fc9709a3 6651 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6652 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6653 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
AnnaBridge 189:f392fc9709a3 6654 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6655 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6656 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
AnnaBridge 189:f392fc9709a3 6657
AnnaBridge 189:f392fc9709a3 6658 /*! @name POL - Channels Polarity */
AnnaBridge 189:f392fc9709a3 6659 #define FTM_POL_POL0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6660 #define FTM_POL_POL0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6661 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
AnnaBridge 189:f392fc9709a3 6662 #define FTM_POL_POL1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6663 #define FTM_POL_POL1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6664 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
AnnaBridge 189:f392fc9709a3 6665 #define FTM_POL_POL2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6666 #define FTM_POL_POL2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6667 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
AnnaBridge 189:f392fc9709a3 6668 #define FTM_POL_POL3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6669 #define FTM_POL_POL3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6670 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
AnnaBridge 189:f392fc9709a3 6671 #define FTM_POL_POL4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6672 #define FTM_POL_POL4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6673 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
AnnaBridge 189:f392fc9709a3 6674 #define FTM_POL_POL5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6675 #define FTM_POL_POL5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6676 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
AnnaBridge 189:f392fc9709a3 6677 #define FTM_POL_POL6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6678 #define FTM_POL_POL6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6679 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
AnnaBridge 189:f392fc9709a3 6680 #define FTM_POL_POL7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6681 #define FTM_POL_POL7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6682 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
AnnaBridge 189:f392fc9709a3 6683
AnnaBridge 189:f392fc9709a3 6684 /*! @name FMS - Fault Mode Status */
AnnaBridge 189:f392fc9709a3 6685 #define FTM_FMS_FAULTF0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6686 #define FTM_FMS_FAULTF0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6687 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
AnnaBridge 189:f392fc9709a3 6688 #define FTM_FMS_FAULTF1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6689 #define FTM_FMS_FAULTF1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6690 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
AnnaBridge 189:f392fc9709a3 6691 #define FTM_FMS_FAULTF2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6692 #define FTM_FMS_FAULTF2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6693 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
AnnaBridge 189:f392fc9709a3 6694 #define FTM_FMS_FAULTF3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6695 #define FTM_FMS_FAULTF3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6696 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
AnnaBridge 189:f392fc9709a3 6697 #define FTM_FMS_FAULTIN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6698 #define FTM_FMS_FAULTIN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6699 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
AnnaBridge 189:f392fc9709a3 6700 #define FTM_FMS_WPEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6701 #define FTM_FMS_WPEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6702 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
AnnaBridge 189:f392fc9709a3 6703 #define FTM_FMS_FAULTF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6704 #define FTM_FMS_FAULTF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6705 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
AnnaBridge 189:f392fc9709a3 6706
AnnaBridge 189:f392fc9709a3 6707 /*! @name FILTER - Input Capture Filter Control */
AnnaBridge 189:f392fc9709a3 6708 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 6709 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6710 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
AnnaBridge 189:f392fc9709a3 6711 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 6712 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6713 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
AnnaBridge 189:f392fc9709a3 6714 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 6715 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 6716 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
AnnaBridge 189:f392fc9709a3 6717 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 6718 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 6719 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
AnnaBridge 189:f392fc9709a3 6720
AnnaBridge 189:f392fc9709a3 6721 /*! @name FLTCTRL - Fault Control */
AnnaBridge 189:f392fc9709a3 6722 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6723 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6724 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
AnnaBridge 189:f392fc9709a3 6725 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6726 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6727 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
AnnaBridge 189:f392fc9709a3 6728 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6729 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6730 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
AnnaBridge 189:f392fc9709a3 6731 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6732 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6733 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
AnnaBridge 189:f392fc9709a3 6734 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6735 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6736 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
AnnaBridge 189:f392fc9709a3 6737 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6738 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6739 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
AnnaBridge 189:f392fc9709a3 6740 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6741 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6742 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
AnnaBridge 189:f392fc9709a3 6743 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6744 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6745 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
AnnaBridge 189:f392fc9709a3 6746 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 6747 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 6748 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
AnnaBridge 189:f392fc9709a3 6749
AnnaBridge 189:f392fc9709a3 6750 /*! @name QDCTRL - Quadrature Decoder Control And Status */
AnnaBridge 189:f392fc9709a3 6751 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6752 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6753 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
AnnaBridge 189:f392fc9709a3 6754 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6755 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6756 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
AnnaBridge 189:f392fc9709a3 6757 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6758 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6759 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
AnnaBridge 189:f392fc9709a3 6760 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6761 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6762 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
AnnaBridge 189:f392fc9709a3 6763 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6764 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6765 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
AnnaBridge 189:f392fc9709a3 6766 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6767 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6768 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
AnnaBridge 189:f392fc9709a3 6769 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6770 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6771 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
AnnaBridge 189:f392fc9709a3 6772 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6773 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6774 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
AnnaBridge 189:f392fc9709a3 6775
AnnaBridge 189:f392fc9709a3 6776 /*! @name CONF - Configuration */
AnnaBridge 189:f392fc9709a3 6777 #define FTM_CONF_NUMTOF_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 6778 #define FTM_CONF_NUMTOF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6779 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
AnnaBridge 189:f392fc9709a3 6780 #define FTM_CONF_BDMMODE_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 6781 #define FTM_CONF_BDMMODE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6782 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
AnnaBridge 189:f392fc9709a3 6783 #define FTM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 6784 #define FTM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 6785 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
AnnaBridge 189:f392fc9709a3 6786 #define FTM_CONF_GTBEOUT_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 6787 #define FTM_CONF_GTBEOUT_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 6788 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
AnnaBridge 189:f392fc9709a3 6789
AnnaBridge 189:f392fc9709a3 6790 /*! @name FLTPOL - FTM Fault Input Polarity */
AnnaBridge 189:f392fc9709a3 6791 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6792 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6793 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
AnnaBridge 189:f392fc9709a3 6794 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6795 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6796 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
AnnaBridge 189:f392fc9709a3 6797 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6798 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6799 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
AnnaBridge 189:f392fc9709a3 6800 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6801 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6802 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
AnnaBridge 189:f392fc9709a3 6803
AnnaBridge 189:f392fc9709a3 6804 /*! @name SYNCONF - Synchronization Configuration */
AnnaBridge 189:f392fc9709a3 6805 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6806 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6807 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
AnnaBridge 189:f392fc9709a3 6808 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6809 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6810 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
AnnaBridge 189:f392fc9709a3 6811 #define FTM_SYNCONF_INVC_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6812 #define FTM_SYNCONF_INVC_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6813 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
AnnaBridge 189:f392fc9709a3 6814 #define FTM_SYNCONF_SWOC_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6815 #define FTM_SYNCONF_SWOC_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6816 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
AnnaBridge 189:f392fc9709a3 6817 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6818 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6819 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
AnnaBridge 189:f392fc9709a3 6820 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 6821 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 6822 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
AnnaBridge 189:f392fc9709a3 6823 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 6824 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 6825 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
AnnaBridge 189:f392fc9709a3 6826 #define FTM_SYNCONF_SWOM_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 6827 #define FTM_SYNCONF_SWOM_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 6828 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
AnnaBridge 189:f392fc9709a3 6829 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 6830 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 6831 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
AnnaBridge 189:f392fc9709a3 6832 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 6833 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 6834 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
AnnaBridge 189:f392fc9709a3 6835 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 6836 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 6837 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
AnnaBridge 189:f392fc9709a3 6838 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 6839 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 6840 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
AnnaBridge 189:f392fc9709a3 6841 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 6842 #define FTM_SYNCONF_HWOM_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 6843 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
AnnaBridge 189:f392fc9709a3 6844 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 6845 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 6846 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
AnnaBridge 189:f392fc9709a3 6847 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 6848 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 6849 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
AnnaBridge 189:f392fc9709a3 6850
AnnaBridge 189:f392fc9709a3 6851 /*! @name INVCTRL - FTM Inverting Control */
AnnaBridge 189:f392fc9709a3 6852 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6853 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6854 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
AnnaBridge 189:f392fc9709a3 6855 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6856 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6857 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
AnnaBridge 189:f392fc9709a3 6858 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6859 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6860 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
AnnaBridge 189:f392fc9709a3 6861 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6862 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6863 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
AnnaBridge 189:f392fc9709a3 6864
AnnaBridge 189:f392fc9709a3 6865 /*! @name SWOCTRL - FTM Software Output Control */
AnnaBridge 189:f392fc9709a3 6866 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6867 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6868 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
AnnaBridge 189:f392fc9709a3 6869 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6870 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6871 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
AnnaBridge 189:f392fc9709a3 6872 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6873 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6874 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
AnnaBridge 189:f392fc9709a3 6875 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6876 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6877 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
AnnaBridge 189:f392fc9709a3 6878 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6879 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6880 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
AnnaBridge 189:f392fc9709a3 6881 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6882 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6883 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
AnnaBridge 189:f392fc9709a3 6884 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6885 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6886 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
AnnaBridge 189:f392fc9709a3 6887 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6888 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6889 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
AnnaBridge 189:f392fc9709a3 6890 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 6891 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 6892 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
AnnaBridge 189:f392fc9709a3 6893 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 6894 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 6895 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
AnnaBridge 189:f392fc9709a3 6896 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 6897 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 6898 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
AnnaBridge 189:f392fc9709a3 6899 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 6900 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 6901 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
AnnaBridge 189:f392fc9709a3 6902 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 6903 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 6904 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
AnnaBridge 189:f392fc9709a3 6905 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 6906 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 6907 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
AnnaBridge 189:f392fc9709a3 6908 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 6909 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 6910 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
AnnaBridge 189:f392fc9709a3 6911 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 6912 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 6913 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
AnnaBridge 189:f392fc9709a3 6914
AnnaBridge 189:f392fc9709a3 6915 /*! @name PWMLOAD - FTM PWM Load */
AnnaBridge 189:f392fc9709a3 6916 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 6917 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 6918 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
AnnaBridge 189:f392fc9709a3 6919 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 6920 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 6921 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
AnnaBridge 189:f392fc9709a3 6922 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 6923 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 6924 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
AnnaBridge 189:f392fc9709a3 6925 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 6926 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 6927 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
AnnaBridge 189:f392fc9709a3 6928 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 6929 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 6930 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
AnnaBridge 189:f392fc9709a3 6931 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 6932 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 6933 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
AnnaBridge 189:f392fc9709a3 6934 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 6935 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 6936 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
AnnaBridge 189:f392fc9709a3 6937 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 6938 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 6939 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
AnnaBridge 189:f392fc9709a3 6940 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 6941 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 6942 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
AnnaBridge 189:f392fc9709a3 6943
AnnaBridge 189:f392fc9709a3 6944
AnnaBridge 189:f392fc9709a3 6945 /*!
AnnaBridge 189:f392fc9709a3 6946 * @}
AnnaBridge 189:f392fc9709a3 6947 */ /* end of group FTM_Register_Masks */
AnnaBridge 189:f392fc9709a3 6948
AnnaBridge 189:f392fc9709a3 6949
AnnaBridge 189:f392fc9709a3 6950 /* FTM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 6951 /** Peripheral FTM0 base address */
AnnaBridge 189:f392fc9709a3 6952 #define FTM0_BASE (0x40038000u)
AnnaBridge 189:f392fc9709a3 6953 /** Peripheral FTM0 base pointer */
AnnaBridge 189:f392fc9709a3 6954 #define FTM0 ((FTM_Type *)FTM0_BASE)
AnnaBridge 189:f392fc9709a3 6955 /** Peripheral FTM1 base address */
AnnaBridge 189:f392fc9709a3 6956 #define FTM1_BASE (0x40039000u)
AnnaBridge 189:f392fc9709a3 6957 /** Peripheral FTM1 base pointer */
AnnaBridge 189:f392fc9709a3 6958 #define FTM1 ((FTM_Type *)FTM1_BASE)
AnnaBridge 189:f392fc9709a3 6959 /** Peripheral FTM2 base address */
AnnaBridge 189:f392fc9709a3 6960 #define FTM2_BASE (0x4003A000u)
AnnaBridge 189:f392fc9709a3 6961 /** Peripheral FTM2 base pointer */
AnnaBridge 189:f392fc9709a3 6962 #define FTM2 ((FTM_Type *)FTM2_BASE)
AnnaBridge 189:f392fc9709a3 6963 /** Peripheral FTM3 base address */
AnnaBridge 189:f392fc9709a3 6964 #define FTM3_BASE (0x400B9000u)
AnnaBridge 189:f392fc9709a3 6965 /** Peripheral FTM3 base pointer */
AnnaBridge 189:f392fc9709a3 6966 #define FTM3 ((FTM_Type *)FTM3_BASE)
AnnaBridge 189:f392fc9709a3 6967 /** Array initializer of FTM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 6968 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
AnnaBridge 189:f392fc9709a3 6969 /** Array initializer of FTM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 6970 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
AnnaBridge 189:f392fc9709a3 6971 /** Interrupt vectors for the FTM peripheral type */
AnnaBridge 189:f392fc9709a3 6972 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
AnnaBridge 189:f392fc9709a3 6973
AnnaBridge 189:f392fc9709a3 6974 /*!
AnnaBridge 189:f392fc9709a3 6975 * @}
AnnaBridge 189:f392fc9709a3 6976 */ /* end of group FTM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 6977
AnnaBridge 189:f392fc9709a3 6978
AnnaBridge 189:f392fc9709a3 6979 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 6980 -- GPIO Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 6981 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 6982
AnnaBridge 189:f392fc9709a3 6983 /*!
AnnaBridge 189:f392fc9709a3 6984 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 6985 * @{
AnnaBridge 189:f392fc9709a3 6986 */
AnnaBridge 189:f392fc9709a3 6987
AnnaBridge 189:f392fc9709a3 6988 /** GPIO - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 6989 typedef struct {
AnnaBridge 189:f392fc9709a3 6990 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 6991 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 6992 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 6993 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 6994 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 6995 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 6996 } GPIO_Type;
AnnaBridge 189:f392fc9709a3 6997
AnnaBridge 189:f392fc9709a3 6998 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 6999 -- GPIO Register Masks
AnnaBridge 189:f392fc9709a3 7000 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 7001
AnnaBridge 189:f392fc9709a3 7002 /*!
AnnaBridge 189:f392fc9709a3 7003 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 189:f392fc9709a3 7004 * @{
AnnaBridge 189:f392fc9709a3 7005 */
AnnaBridge 189:f392fc9709a3 7006
AnnaBridge 189:f392fc9709a3 7007 /*! @name PDOR - Port Data Output Register */
AnnaBridge 189:f392fc9709a3 7008 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7009 #define GPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7010 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
AnnaBridge 189:f392fc9709a3 7011
AnnaBridge 189:f392fc9709a3 7012 /*! @name PSOR - Port Set Output Register */
AnnaBridge 189:f392fc9709a3 7013 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7014 #define GPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7015 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
AnnaBridge 189:f392fc9709a3 7016
AnnaBridge 189:f392fc9709a3 7017 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 189:f392fc9709a3 7018 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7019 #define GPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7020 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
AnnaBridge 189:f392fc9709a3 7021
AnnaBridge 189:f392fc9709a3 7022 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 189:f392fc9709a3 7023 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7024 #define GPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7025 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
AnnaBridge 189:f392fc9709a3 7026
AnnaBridge 189:f392fc9709a3 7027 /*! @name PDIR - Port Data Input Register */
AnnaBridge 189:f392fc9709a3 7028 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7029 #define GPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7030 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
AnnaBridge 189:f392fc9709a3 7031
AnnaBridge 189:f392fc9709a3 7032 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 189:f392fc9709a3 7033 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7034 #define GPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7035 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
AnnaBridge 189:f392fc9709a3 7036
AnnaBridge 189:f392fc9709a3 7037
AnnaBridge 189:f392fc9709a3 7038 /*!
AnnaBridge 189:f392fc9709a3 7039 * @}
AnnaBridge 189:f392fc9709a3 7040 */ /* end of group GPIO_Register_Masks */
AnnaBridge 189:f392fc9709a3 7041
AnnaBridge 189:f392fc9709a3 7042
AnnaBridge 189:f392fc9709a3 7043 /* GPIO - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 7044 /** Peripheral GPIOA base address */
AnnaBridge 189:f392fc9709a3 7045 #define GPIOA_BASE (0x400FF000u)
AnnaBridge 189:f392fc9709a3 7046 /** Peripheral GPIOA base pointer */
AnnaBridge 189:f392fc9709a3 7047 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
AnnaBridge 189:f392fc9709a3 7048 /** Peripheral GPIOB base address */
AnnaBridge 189:f392fc9709a3 7049 #define GPIOB_BASE (0x400FF040u)
AnnaBridge 189:f392fc9709a3 7050 /** Peripheral GPIOB base pointer */
AnnaBridge 189:f392fc9709a3 7051 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
AnnaBridge 189:f392fc9709a3 7052 /** Peripheral GPIOC base address */
AnnaBridge 189:f392fc9709a3 7053 #define GPIOC_BASE (0x400FF080u)
AnnaBridge 189:f392fc9709a3 7054 /** Peripheral GPIOC base pointer */
AnnaBridge 189:f392fc9709a3 7055 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
AnnaBridge 189:f392fc9709a3 7056 /** Peripheral GPIOD base address */
AnnaBridge 189:f392fc9709a3 7057 #define GPIOD_BASE (0x400FF0C0u)
AnnaBridge 189:f392fc9709a3 7058 /** Peripheral GPIOD base pointer */
AnnaBridge 189:f392fc9709a3 7059 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
AnnaBridge 189:f392fc9709a3 7060 /** Peripheral GPIOE base address */
AnnaBridge 189:f392fc9709a3 7061 #define GPIOE_BASE (0x400FF100u)
AnnaBridge 189:f392fc9709a3 7062 /** Peripheral GPIOE base pointer */
AnnaBridge 189:f392fc9709a3 7063 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
AnnaBridge 189:f392fc9709a3 7064 /** Array initializer of GPIO peripheral base addresses */
AnnaBridge 189:f392fc9709a3 7065 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
AnnaBridge 189:f392fc9709a3 7066 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 189:f392fc9709a3 7067 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
AnnaBridge 189:f392fc9709a3 7068
AnnaBridge 189:f392fc9709a3 7069 /*!
AnnaBridge 189:f392fc9709a3 7070 * @}
AnnaBridge 189:f392fc9709a3 7071 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 7072
AnnaBridge 189:f392fc9709a3 7073
AnnaBridge 189:f392fc9709a3 7074 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 7075 -- I2C Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 7076 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 7077
AnnaBridge 189:f392fc9709a3 7078 /*!
AnnaBridge 189:f392fc9709a3 7079 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 7080 * @{
AnnaBridge 189:f392fc9709a3 7081 */
AnnaBridge 189:f392fc9709a3 7082
AnnaBridge 189:f392fc9709a3 7083 /** I2C - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 7084 typedef struct {
AnnaBridge 189:f392fc9709a3 7085 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 7086 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 7087 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 7088 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 7089 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 7090 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 7091 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
AnnaBridge 189:f392fc9709a3 7092 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 189:f392fc9709a3 7093 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 7094 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 189:f392fc9709a3 7095 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 189:f392fc9709a3 7096 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 189:f392fc9709a3 7097 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
AnnaBridge 189:f392fc9709a3 7098 } I2C_Type;
AnnaBridge 189:f392fc9709a3 7099
AnnaBridge 189:f392fc9709a3 7100 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 7101 -- I2C Register Masks
AnnaBridge 189:f392fc9709a3 7102 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 7103
AnnaBridge 189:f392fc9709a3 7104 /*!
AnnaBridge 189:f392fc9709a3 7105 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 189:f392fc9709a3 7106 * @{
AnnaBridge 189:f392fc9709a3 7107 */
AnnaBridge 189:f392fc9709a3 7108
AnnaBridge 189:f392fc9709a3 7109 /*! @name A1 - I2C Address Register 1 */
AnnaBridge 189:f392fc9709a3 7110 #define I2C_A1_AD_MASK (0xFEU)
AnnaBridge 189:f392fc9709a3 7111 #define I2C_A1_AD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7112 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
AnnaBridge 189:f392fc9709a3 7113
AnnaBridge 189:f392fc9709a3 7114 /*! @name F - I2C Frequency Divider register */
AnnaBridge 189:f392fc9709a3 7115 #define I2C_F_ICR_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 7116 #define I2C_F_ICR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7117 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
AnnaBridge 189:f392fc9709a3 7118 #define I2C_F_MULT_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7119 #define I2C_F_MULT_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7120 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
AnnaBridge 189:f392fc9709a3 7121
AnnaBridge 189:f392fc9709a3 7122 /*! @name C1 - I2C Control Register 1 */
AnnaBridge 189:f392fc9709a3 7123 #define I2C_C1_DMAEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7124 #define I2C_C1_DMAEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7125 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
AnnaBridge 189:f392fc9709a3 7126 #define I2C_C1_WUEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7127 #define I2C_C1_WUEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7128 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
AnnaBridge 189:f392fc9709a3 7129 #define I2C_C1_RSTA_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7130 #define I2C_C1_RSTA_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7131 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
AnnaBridge 189:f392fc9709a3 7132 #define I2C_C1_TXAK_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7133 #define I2C_C1_TXAK_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7134 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
AnnaBridge 189:f392fc9709a3 7135 #define I2C_C1_TX_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7136 #define I2C_C1_TX_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7137 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
AnnaBridge 189:f392fc9709a3 7138 #define I2C_C1_MST_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7139 #define I2C_C1_MST_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7140 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
AnnaBridge 189:f392fc9709a3 7141 #define I2C_C1_IICIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7142 #define I2C_C1_IICIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7143 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
AnnaBridge 189:f392fc9709a3 7144 #define I2C_C1_IICEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7145 #define I2C_C1_IICEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7146 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
AnnaBridge 189:f392fc9709a3 7147
AnnaBridge 189:f392fc9709a3 7148 /*! @name S - I2C Status register */
AnnaBridge 189:f392fc9709a3 7149 #define I2C_S_RXAK_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7150 #define I2C_S_RXAK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7151 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
AnnaBridge 189:f392fc9709a3 7152 #define I2C_S_IICIF_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7153 #define I2C_S_IICIF_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7154 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
AnnaBridge 189:f392fc9709a3 7155 #define I2C_S_SRW_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7156 #define I2C_S_SRW_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7157 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
AnnaBridge 189:f392fc9709a3 7158 #define I2C_S_RAM_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7159 #define I2C_S_RAM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7160 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
AnnaBridge 189:f392fc9709a3 7161 #define I2C_S_ARBL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7162 #define I2C_S_ARBL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7163 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
AnnaBridge 189:f392fc9709a3 7164 #define I2C_S_BUSY_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7165 #define I2C_S_BUSY_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7166 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
AnnaBridge 189:f392fc9709a3 7167 #define I2C_S_IAAS_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7168 #define I2C_S_IAAS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7169 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
AnnaBridge 189:f392fc9709a3 7170 #define I2C_S_TCF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7171 #define I2C_S_TCF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7172 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
AnnaBridge 189:f392fc9709a3 7173
AnnaBridge 189:f392fc9709a3 7174 /*! @name D - I2C Data I/O register */
AnnaBridge 189:f392fc9709a3 7175 #define I2C_D_DATA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 7176 #define I2C_D_DATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7177 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
AnnaBridge 189:f392fc9709a3 7178
AnnaBridge 189:f392fc9709a3 7179 /*! @name C2 - I2C Control Register 2 */
AnnaBridge 189:f392fc9709a3 7180 #define I2C_C2_AD_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 7181 #define I2C_C2_AD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7182 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
AnnaBridge 189:f392fc9709a3 7183 #define I2C_C2_RMEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7184 #define I2C_C2_RMEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7185 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
AnnaBridge 189:f392fc9709a3 7186 #define I2C_C2_SBRC_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7187 #define I2C_C2_SBRC_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7188 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
AnnaBridge 189:f392fc9709a3 7189 #define I2C_C2_HDRS_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7190 #define I2C_C2_HDRS_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7191 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
AnnaBridge 189:f392fc9709a3 7192 #define I2C_C2_ADEXT_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7193 #define I2C_C2_ADEXT_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7194 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
AnnaBridge 189:f392fc9709a3 7195 #define I2C_C2_GCAEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7196 #define I2C_C2_GCAEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7197 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
AnnaBridge 189:f392fc9709a3 7198
AnnaBridge 189:f392fc9709a3 7199 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
AnnaBridge 189:f392fc9709a3 7200 #define I2C_FLT_FLT_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 7201 #define I2C_FLT_FLT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7202 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
AnnaBridge 189:f392fc9709a3 7203 #define I2C_FLT_STARTF_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7204 #define I2C_FLT_STARTF_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7205 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
AnnaBridge 189:f392fc9709a3 7206 #define I2C_FLT_SSIE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7207 #define I2C_FLT_SSIE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7208 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
AnnaBridge 189:f392fc9709a3 7209 #define I2C_FLT_STOPF_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7210 #define I2C_FLT_STOPF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7211 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
AnnaBridge 189:f392fc9709a3 7212 #define I2C_FLT_SHEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7213 #define I2C_FLT_SHEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7214 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
AnnaBridge 189:f392fc9709a3 7215
AnnaBridge 189:f392fc9709a3 7216 /*! @name RA - I2C Range Address register */
AnnaBridge 189:f392fc9709a3 7217 #define I2C_RA_RAD_MASK (0xFEU)
AnnaBridge 189:f392fc9709a3 7218 #define I2C_RA_RAD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7219 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
AnnaBridge 189:f392fc9709a3 7220
AnnaBridge 189:f392fc9709a3 7221 /*! @name SMB - I2C SMBus Control and Status register */
AnnaBridge 189:f392fc9709a3 7222 #define I2C_SMB_SHTF2IE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7223 #define I2C_SMB_SHTF2IE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7224 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
AnnaBridge 189:f392fc9709a3 7225 #define I2C_SMB_SHTF2_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7226 #define I2C_SMB_SHTF2_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7227 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
AnnaBridge 189:f392fc9709a3 7228 #define I2C_SMB_SHTF1_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7229 #define I2C_SMB_SHTF1_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7230 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
AnnaBridge 189:f392fc9709a3 7231 #define I2C_SMB_SLTF_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7232 #define I2C_SMB_SLTF_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7233 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
AnnaBridge 189:f392fc9709a3 7234 #define I2C_SMB_TCKSEL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7235 #define I2C_SMB_TCKSEL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7236 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
AnnaBridge 189:f392fc9709a3 7237 #define I2C_SMB_SIICAEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7238 #define I2C_SMB_SIICAEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7239 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
AnnaBridge 189:f392fc9709a3 7240 #define I2C_SMB_ALERTEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7241 #define I2C_SMB_ALERTEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7242 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
AnnaBridge 189:f392fc9709a3 7243 #define I2C_SMB_FACK_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7244 #define I2C_SMB_FACK_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7245 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
AnnaBridge 189:f392fc9709a3 7246
AnnaBridge 189:f392fc9709a3 7247 /*! @name A2 - I2C Address Register 2 */
AnnaBridge 189:f392fc9709a3 7248 #define I2C_A2_SAD_MASK (0xFEU)
AnnaBridge 189:f392fc9709a3 7249 #define I2C_A2_SAD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7250 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
AnnaBridge 189:f392fc9709a3 7251
AnnaBridge 189:f392fc9709a3 7252 /*! @name SLTH - I2C SCL Low Timeout Register High */
AnnaBridge 189:f392fc9709a3 7253 #define I2C_SLTH_SSLT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 7254 #define I2C_SLTH_SSLT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7255 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
AnnaBridge 189:f392fc9709a3 7256
AnnaBridge 189:f392fc9709a3 7257 /*! @name SLTL - I2C SCL Low Timeout Register Low */
AnnaBridge 189:f392fc9709a3 7258 #define I2C_SLTL_SSLT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 7259 #define I2C_SLTL_SSLT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7260 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
AnnaBridge 189:f392fc9709a3 7261
AnnaBridge 189:f392fc9709a3 7262 /*! @name S2 - I2C Status register 2 */
AnnaBridge 189:f392fc9709a3 7263 #define I2C_S2_EMPTY_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7264 #define I2C_S2_EMPTY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7265 #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
AnnaBridge 189:f392fc9709a3 7266 #define I2C_S2_ERROR_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7267 #define I2C_S2_ERROR_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7268 #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
AnnaBridge 189:f392fc9709a3 7269
AnnaBridge 189:f392fc9709a3 7270
AnnaBridge 189:f392fc9709a3 7271 /*!
AnnaBridge 189:f392fc9709a3 7272 * @}
AnnaBridge 189:f392fc9709a3 7273 */ /* end of group I2C_Register_Masks */
AnnaBridge 189:f392fc9709a3 7274
AnnaBridge 189:f392fc9709a3 7275
AnnaBridge 189:f392fc9709a3 7276 /* I2C - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 7277 /** Peripheral I2C0 base address */
AnnaBridge 189:f392fc9709a3 7278 #define I2C0_BASE (0x40066000u)
AnnaBridge 189:f392fc9709a3 7279 /** Peripheral I2C0 base pointer */
AnnaBridge 189:f392fc9709a3 7280 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 189:f392fc9709a3 7281 /** Peripheral I2C1 base address */
AnnaBridge 189:f392fc9709a3 7282 #define I2C1_BASE (0x40067000u)
AnnaBridge 189:f392fc9709a3 7283 /** Peripheral I2C1 base pointer */
AnnaBridge 189:f392fc9709a3 7284 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 189:f392fc9709a3 7285 /** Peripheral I2C2 base address */
AnnaBridge 189:f392fc9709a3 7286 #define I2C2_BASE (0x400E6000u)
AnnaBridge 189:f392fc9709a3 7287 /** Peripheral I2C2 base pointer */
AnnaBridge 189:f392fc9709a3 7288 #define I2C2 ((I2C_Type *)I2C2_BASE)
AnnaBridge 189:f392fc9709a3 7289 /** Peripheral I2C3 base address */
AnnaBridge 189:f392fc9709a3 7290 #define I2C3_BASE (0x400E7000u)
AnnaBridge 189:f392fc9709a3 7291 /** Peripheral I2C3 base pointer */
AnnaBridge 189:f392fc9709a3 7292 #define I2C3 ((I2C_Type *)I2C3_BASE)
AnnaBridge 189:f392fc9709a3 7293 /** Array initializer of I2C peripheral base addresses */
AnnaBridge 189:f392fc9709a3 7294 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
AnnaBridge 189:f392fc9709a3 7295 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 189:f392fc9709a3 7296 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
AnnaBridge 189:f392fc9709a3 7297 /** Interrupt vectors for the I2C peripheral type */
AnnaBridge 189:f392fc9709a3 7298 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
AnnaBridge 189:f392fc9709a3 7299
AnnaBridge 189:f392fc9709a3 7300 /*!
AnnaBridge 189:f392fc9709a3 7301 * @}
AnnaBridge 189:f392fc9709a3 7302 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 7303
AnnaBridge 189:f392fc9709a3 7304
AnnaBridge 189:f392fc9709a3 7305 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 7306 -- I2S Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 7307 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 7308
AnnaBridge 189:f392fc9709a3 7309 /*!
AnnaBridge 189:f392fc9709a3 7310 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 7311 * @{
AnnaBridge 189:f392fc9709a3 7312 */
AnnaBridge 189:f392fc9709a3 7313
AnnaBridge 189:f392fc9709a3 7314 /** I2S - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 7315 typedef struct {
AnnaBridge 189:f392fc9709a3 7316 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 7317 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 7318 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 7319 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 7320 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 7321 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 7322 uint8_t RESERVED_0[8];
AnnaBridge 189:f392fc9709a3 7323 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 7324 uint8_t RESERVED_1[24];
AnnaBridge 189:f392fc9709a3 7325 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 7326 uint8_t RESERVED_2[24];
AnnaBridge 189:f392fc9709a3 7327 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
AnnaBridge 189:f392fc9709a3 7328 uint8_t RESERVED_3[28];
AnnaBridge 189:f392fc9709a3 7329 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 7330 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
AnnaBridge 189:f392fc9709a3 7331 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
AnnaBridge 189:f392fc9709a3 7332 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
AnnaBridge 189:f392fc9709a3 7333 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
AnnaBridge 189:f392fc9709a3 7334 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
AnnaBridge 189:f392fc9709a3 7335 uint8_t RESERVED_4[8];
AnnaBridge 189:f392fc9709a3 7336 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 7337 uint8_t RESERVED_5[24];
AnnaBridge 189:f392fc9709a3 7338 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 7339 uint8_t RESERVED_6[24];
AnnaBridge 189:f392fc9709a3 7340 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
AnnaBridge 189:f392fc9709a3 7341 uint8_t RESERVED_7[28];
AnnaBridge 189:f392fc9709a3 7342 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
AnnaBridge 189:f392fc9709a3 7343 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
AnnaBridge 189:f392fc9709a3 7344 } I2S_Type;
AnnaBridge 189:f392fc9709a3 7345
AnnaBridge 189:f392fc9709a3 7346 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 7347 -- I2S Register Masks
AnnaBridge 189:f392fc9709a3 7348 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 7349
AnnaBridge 189:f392fc9709a3 7350 /*!
AnnaBridge 189:f392fc9709a3 7351 * @addtogroup I2S_Register_Masks I2S Register Masks
AnnaBridge 189:f392fc9709a3 7352 * @{
AnnaBridge 189:f392fc9709a3 7353 */
AnnaBridge 189:f392fc9709a3 7354
AnnaBridge 189:f392fc9709a3 7355 /*! @name TCSR - SAI Transmit Control Register */
AnnaBridge 189:f392fc9709a3 7356 #define I2S_TCSR_FRDE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7357 #define I2S_TCSR_FRDE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7358 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
AnnaBridge 189:f392fc9709a3 7359 #define I2S_TCSR_FWDE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7360 #define I2S_TCSR_FWDE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7361 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
AnnaBridge 189:f392fc9709a3 7362 #define I2S_TCSR_FRIE_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 7363 #define I2S_TCSR_FRIE_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 7364 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
AnnaBridge 189:f392fc9709a3 7365 #define I2S_TCSR_FWIE_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 7366 #define I2S_TCSR_FWIE_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 7367 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
AnnaBridge 189:f392fc9709a3 7368 #define I2S_TCSR_FEIE_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 7369 #define I2S_TCSR_FEIE_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 7370 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
AnnaBridge 189:f392fc9709a3 7371 #define I2S_TCSR_SEIE_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 7372 #define I2S_TCSR_SEIE_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 7373 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
AnnaBridge 189:f392fc9709a3 7374 #define I2S_TCSR_WSIE_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 7375 #define I2S_TCSR_WSIE_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 7376 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
AnnaBridge 189:f392fc9709a3 7377 #define I2S_TCSR_FRF_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 7378 #define I2S_TCSR_FRF_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7379 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
AnnaBridge 189:f392fc9709a3 7380 #define I2S_TCSR_FWF_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 7381 #define I2S_TCSR_FWF_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 7382 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
AnnaBridge 189:f392fc9709a3 7383 #define I2S_TCSR_FEF_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 7384 #define I2S_TCSR_FEF_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 7385 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
AnnaBridge 189:f392fc9709a3 7386 #define I2S_TCSR_SEF_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 7387 #define I2S_TCSR_SEF_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 7388 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
AnnaBridge 189:f392fc9709a3 7389 #define I2S_TCSR_WSF_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 7390 #define I2S_TCSR_WSF_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 7391 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
AnnaBridge 189:f392fc9709a3 7392 #define I2S_TCSR_SR_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 7393 #define I2S_TCSR_SR_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7394 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
AnnaBridge 189:f392fc9709a3 7395 #define I2S_TCSR_FR_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 7396 #define I2S_TCSR_FR_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 7397 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
AnnaBridge 189:f392fc9709a3 7398 #define I2S_TCSR_BCE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 7399 #define I2S_TCSR_BCE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 7400 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
AnnaBridge 189:f392fc9709a3 7401 #define I2S_TCSR_DBGE_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 7402 #define I2S_TCSR_DBGE_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 7403 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
AnnaBridge 189:f392fc9709a3 7404 #define I2S_TCSR_STOPE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 7405 #define I2S_TCSR_STOPE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 7406 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
AnnaBridge 189:f392fc9709a3 7407 #define I2S_TCSR_TE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 7408 #define I2S_TCSR_TE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 7409 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
AnnaBridge 189:f392fc9709a3 7410
AnnaBridge 189:f392fc9709a3 7411 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
AnnaBridge 189:f392fc9709a3 7412 #define I2S_TCR1_TFW_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 7413 #define I2S_TCR1_TFW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7414 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
AnnaBridge 189:f392fc9709a3 7415
AnnaBridge 189:f392fc9709a3 7416 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
AnnaBridge 189:f392fc9709a3 7417 #define I2S_TCR2_DIV_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 7418 #define I2S_TCR2_DIV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7419 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
AnnaBridge 189:f392fc9709a3 7420 #define I2S_TCR2_BCD_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 7421 #define I2S_TCR2_BCD_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7422 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
AnnaBridge 189:f392fc9709a3 7423 #define I2S_TCR2_BCP_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 7424 #define I2S_TCR2_BCP_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 7425 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
AnnaBridge 189:f392fc9709a3 7426 #define I2S_TCR2_MSEL_MASK (0xC000000U)
AnnaBridge 189:f392fc9709a3 7427 #define I2S_TCR2_MSEL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 7428 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
AnnaBridge 189:f392fc9709a3 7429 #define I2S_TCR2_BCI_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 7430 #define I2S_TCR2_BCI_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 7431 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
AnnaBridge 189:f392fc9709a3 7432 #define I2S_TCR2_BCS_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 7433 #define I2S_TCR2_BCS_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 7434 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
AnnaBridge 189:f392fc9709a3 7435 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 189:f392fc9709a3 7436 #define I2S_TCR2_SYNC_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 7437 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
AnnaBridge 189:f392fc9709a3 7438
AnnaBridge 189:f392fc9709a3 7439 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
AnnaBridge 189:f392fc9709a3 7440 #define I2S_TCR3_WDFL_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 7441 #define I2S_TCR3_WDFL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7442 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
AnnaBridge 189:f392fc9709a3 7443 #define I2S_TCR3_TCE_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 7444 #define I2S_TCR3_TCE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7445 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
AnnaBridge 189:f392fc9709a3 7446 #define I2S_TCR3_CFR_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 7447 #define I2S_TCR3_CFR_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7448 #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
AnnaBridge 189:f392fc9709a3 7449
AnnaBridge 189:f392fc9709a3 7450 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
AnnaBridge 189:f392fc9709a3 7451 #define I2S_TCR4_FSD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7452 #define I2S_TCR4_FSD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7453 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
AnnaBridge 189:f392fc9709a3 7454 #define I2S_TCR4_FSP_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7455 #define I2S_TCR4_FSP_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7456 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
AnnaBridge 189:f392fc9709a3 7457 #define I2S_TCR4_ONDEM_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7458 #define I2S_TCR4_ONDEM_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7459 #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
AnnaBridge 189:f392fc9709a3 7460 #define I2S_TCR4_FSE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7461 #define I2S_TCR4_FSE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7462 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
AnnaBridge 189:f392fc9709a3 7463 #define I2S_TCR4_MF_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7464 #define I2S_TCR4_MF_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7465 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
AnnaBridge 189:f392fc9709a3 7466 #define I2S_TCR4_SYWD_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 7467 #define I2S_TCR4_SYWD_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 7468 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
AnnaBridge 189:f392fc9709a3 7469 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 189:f392fc9709a3 7470 #define I2S_TCR4_FRSZ_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7471 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
AnnaBridge 189:f392fc9709a3 7472 #define I2S_TCR4_FPACK_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 7473 #define I2S_TCR4_FPACK_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7474 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
AnnaBridge 189:f392fc9709a3 7475 #define I2S_TCR4_FCOMB_MASK (0xC000000U)
AnnaBridge 189:f392fc9709a3 7476 #define I2S_TCR4_FCOMB_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 7477 #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
AnnaBridge 189:f392fc9709a3 7478 #define I2S_TCR4_FCONT_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 7479 #define I2S_TCR4_FCONT_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 7480 #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
AnnaBridge 189:f392fc9709a3 7481
AnnaBridge 189:f392fc9709a3 7482 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
AnnaBridge 189:f392fc9709a3 7483 #define I2S_TCR5_FBT_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 7484 #define I2S_TCR5_FBT_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 7485 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
AnnaBridge 189:f392fc9709a3 7486 #define I2S_TCR5_W0W_MASK (0x1F0000U)
AnnaBridge 189:f392fc9709a3 7487 #define I2S_TCR5_W0W_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7488 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
AnnaBridge 189:f392fc9709a3 7489 #define I2S_TCR5_WNW_MASK (0x1F000000U)
AnnaBridge 189:f392fc9709a3 7490 #define I2S_TCR5_WNW_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7491 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
AnnaBridge 189:f392fc9709a3 7492
AnnaBridge 189:f392fc9709a3 7493 /*! @name TDR - SAI Transmit Data Register */
AnnaBridge 189:f392fc9709a3 7494 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7495 #define I2S_TDR_TDR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7496 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
AnnaBridge 189:f392fc9709a3 7497
AnnaBridge 189:f392fc9709a3 7498 /* The count of I2S_TDR */
AnnaBridge 189:f392fc9709a3 7499 #define I2S_TDR_COUNT (2U)
AnnaBridge 189:f392fc9709a3 7500
AnnaBridge 189:f392fc9709a3 7501 /*! @name TFR - SAI Transmit FIFO Register */
AnnaBridge 189:f392fc9709a3 7502 #define I2S_TFR_RFP_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 7503 #define I2S_TFR_RFP_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7504 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
AnnaBridge 189:f392fc9709a3 7505 #define I2S_TFR_WFP_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 7506 #define I2S_TFR_WFP_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7507 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
AnnaBridge 189:f392fc9709a3 7508 #define I2S_TFR_WCP_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 7509 #define I2S_TFR_WCP_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 7510 #define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
AnnaBridge 189:f392fc9709a3 7511
AnnaBridge 189:f392fc9709a3 7512 /* The count of I2S_TFR */
AnnaBridge 189:f392fc9709a3 7513 #define I2S_TFR_COUNT (2U)
AnnaBridge 189:f392fc9709a3 7514
AnnaBridge 189:f392fc9709a3 7515 /*! @name TMR - SAI Transmit Mask Register */
AnnaBridge 189:f392fc9709a3 7516 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7517 #define I2S_TMR_TWM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7518 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
AnnaBridge 189:f392fc9709a3 7519
AnnaBridge 189:f392fc9709a3 7520 /*! @name RCSR - SAI Receive Control Register */
AnnaBridge 189:f392fc9709a3 7521 #define I2S_RCSR_FRDE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7522 #define I2S_RCSR_FRDE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7523 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
AnnaBridge 189:f392fc9709a3 7524 #define I2S_RCSR_FWDE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7525 #define I2S_RCSR_FWDE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7526 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
AnnaBridge 189:f392fc9709a3 7527 #define I2S_RCSR_FRIE_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 7528 #define I2S_RCSR_FRIE_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 7529 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
AnnaBridge 189:f392fc9709a3 7530 #define I2S_RCSR_FWIE_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 7531 #define I2S_RCSR_FWIE_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 7532 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
AnnaBridge 189:f392fc9709a3 7533 #define I2S_RCSR_FEIE_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 7534 #define I2S_RCSR_FEIE_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 7535 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
AnnaBridge 189:f392fc9709a3 7536 #define I2S_RCSR_SEIE_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 7537 #define I2S_RCSR_SEIE_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 7538 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
AnnaBridge 189:f392fc9709a3 7539 #define I2S_RCSR_WSIE_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 7540 #define I2S_RCSR_WSIE_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 7541 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
AnnaBridge 189:f392fc9709a3 7542 #define I2S_RCSR_FRF_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 7543 #define I2S_RCSR_FRF_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7544 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
AnnaBridge 189:f392fc9709a3 7545 #define I2S_RCSR_FWF_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 7546 #define I2S_RCSR_FWF_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 7547 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
AnnaBridge 189:f392fc9709a3 7548 #define I2S_RCSR_FEF_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 7549 #define I2S_RCSR_FEF_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 7550 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
AnnaBridge 189:f392fc9709a3 7551 #define I2S_RCSR_SEF_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 7552 #define I2S_RCSR_SEF_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 7553 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
AnnaBridge 189:f392fc9709a3 7554 #define I2S_RCSR_WSF_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 7555 #define I2S_RCSR_WSF_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 7556 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
AnnaBridge 189:f392fc9709a3 7557 #define I2S_RCSR_SR_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 7558 #define I2S_RCSR_SR_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7559 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
AnnaBridge 189:f392fc9709a3 7560 #define I2S_RCSR_FR_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 7561 #define I2S_RCSR_FR_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 7562 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
AnnaBridge 189:f392fc9709a3 7563 #define I2S_RCSR_BCE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 7564 #define I2S_RCSR_BCE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 7565 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
AnnaBridge 189:f392fc9709a3 7566 #define I2S_RCSR_DBGE_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 7567 #define I2S_RCSR_DBGE_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 7568 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
AnnaBridge 189:f392fc9709a3 7569 #define I2S_RCSR_STOPE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 7570 #define I2S_RCSR_STOPE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 7571 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
AnnaBridge 189:f392fc9709a3 7572 #define I2S_RCSR_RE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 7573 #define I2S_RCSR_RE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 7574 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
AnnaBridge 189:f392fc9709a3 7575
AnnaBridge 189:f392fc9709a3 7576 /*! @name RCR1 - SAI Receive Configuration 1 Register */
AnnaBridge 189:f392fc9709a3 7577 #define I2S_RCR1_RFW_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 7578 #define I2S_RCR1_RFW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7579 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
AnnaBridge 189:f392fc9709a3 7580
AnnaBridge 189:f392fc9709a3 7581 /*! @name RCR2 - SAI Receive Configuration 2 Register */
AnnaBridge 189:f392fc9709a3 7582 #define I2S_RCR2_DIV_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 7583 #define I2S_RCR2_DIV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7584 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
AnnaBridge 189:f392fc9709a3 7585 #define I2S_RCR2_BCD_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 7586 #define I2S_RCR2_BCD_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7587 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
AnnaBridge 189:f392fc9709a3 7588 #define I2S_RCR2_BCP_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 7589 #define I2S_RCR2_BCP_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 7590 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
AnnaBridge 189:f392fc9709a3 7591 #define I2S_RCR2_MSEL_MASK (0xC000000U)
AnnaBridge 189:f392fc9709a3 7592 #define I2S_RCR2_MSEL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 7593 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
AnnaBridge 189:f392fc9709a3 7594 #define I2S_RCR2_BCI_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 7595 #define I2S_RCR2_BCI_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 7596 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
AnnaBridge 189:f392fc9709a3 7597 #define I2S_RCR2_BCS_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 7598 #define I2S_RCR2_BCS_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 7599 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
AnnaBridge 189:f392fc9709a3 7600 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 189:f392fc9709a3 7601 #define I2S_RCR2_SYNC_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 7602 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
AnnaBridge 189:f392fc9709a3 7603
AnnaBridge 189:f392fc9709a3 7604 /*! @name RCR3 - SAI Receive Configuration 3 Register */
AnnaBridge 189:f392fc9709a3 7605 #define I2S_RCR3_WDFL_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 7606 #define I2S_RCR3_WDFL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7607 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
AnnaBridge 189:f392fc9709a3 7608 #define I2S_RCR3_RCE_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 7609 #define I2S_RCR3_RCE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7610 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
AnnaBridge 189:f392fc9709a3 7611 #define I2S_RCR3_CFR_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 7612 #define I2S_RCR3_CFR_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7613 #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
AnnaBridge 189:f392fc9709a3 7614
AnnaBridge 189:f392fc9709a3 7615 /*! @name RCR4 - SAI Receive Configuration 4 Register */
AnnaBridge 189:f392fc9709a3 7616 #define I2S_RCR4_FSD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7617 #define I2S_RCR4_FSD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7618 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
AnnaBridge 189:f392fc9709a3 7619 #define I2S_RCR4_FSP_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7620 #define I2S_RCR4_FSP_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7621 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
AnnaBridge 189:f392fc9709a3 7622 #define I2S_RCR4_ONDEM_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7623 #define I2S_RCR4_ONDEM_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7624 #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
AnnaBridge 189:f392fc9709a3 7625 #define I2S_RCR4_FSE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7626 #define I2S_RCR4_FSE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7627 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
AnnaBridge 189:f392fc9709a3 7628 #define I2S_RCR4_MF_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7629 #define I2S_RCR4_MF_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7630 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
AnnaBridge 189:f392fc9709a3 7631 #define I2S_RCR4_SYWD_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 7632 #define I2S_RCR4_SYWD_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 7633 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
AnnaBridge 189:f392fc9709a3 7634 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 189:f392fc9709a3 7635 #define I2S_RCR4_FRSZ_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7636 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
AnnaBridge 189:f392fc9709a3 7637 #define I2S_RCR4_FPACK_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 7638 #define I2S_RCR4_FPACK_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7639 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
AnnaBridge 189:f392fc9709a3 7640 #define I2S_RCR4_FCOMB_MASK (0xC000000U)
AnnaBridge 189:f392fc9709a3 7641 #define I2S_RCR4_FCOMB_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 7642 #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
AnnaBridge 189:f392fc9709a3 7643 #define I2S_RCR4_FCONT_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 7644 #define I2S_RCR4_FCONT_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 7645 #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
AnnaBridge 189:f392fc9709a3 7646
AnnaBridge 189:f392fc9709a3 7647 /*! @name RCR5 - SAI Receive Configuration 5 Register */
AnnaBridge 189:f392fc9709a3 7648 #define I2S_RCR5_FBT_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 7649 #define I2S_RCR5_FBT_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 7650 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
AnnaBridge 189:f392fc9709a3 7651 #define I2S_RCR5_W0W_MASK (0x1F0000U)
AnnaBridge 189:f392fc9709a3 7652 #define I2S_RCR5_W0W_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7653 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
AnnaBridge 189:f392fc9709a3 7654 #define I2S_RCR5_WNW_MASK (0x1F000000U)
AnnaBridge 189:f392fc9709a3 7655 #define I2S_RCR5_WNW_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7656 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
AnnaBridge 189:f392fc9709a3 7657
AnnaBridge 189:f392fc9709a3 7658 /*! @name RDR - SAI Receive Data Register */
AnnaBridge 189:f392fc9709a3 7659 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7660 #define I2S_RDR_RDR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7661 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
AnnaBridge 189:f392fc9709a3 7662
AnnaBridge 189:f392fc9709a3 7663 /* The count of I2S_RDR */
AnnaBridge 189:f392fc9709a3 7664 #define I2S_RDR_COUNT (2U)
AnnaBridge 189:f392fc9709a3 7665
AnnaBridge 189:f392fc9709a3 7666 /*! @name RFR - SAI Receive FIFO Register */
AnnaBridge 189:f392fc9709a3 7667 #define I2S_RFR_RFP_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 7668 #define I2S_RFR_RFP_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7669 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
AnnaBridge 189:f392fc9709a3 7670 #define I2S_RFR_RCP_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 7671 #define I2S_RFR_RCP_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 7672 #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
AnnaBridge 189:f392fc9709a3 7673 #define I2S_RFR_WFP_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 7674 #define I2S_RFR_WFP_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 7675 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
AnnaBridge 189:f392fc9709a3 7676
AnnaBridge 189:f392fc9709a3 7677 /* The count of I2S_RFR */
AnnaBridge 189:f392fc9709a3 7678 #define I2S_RFR_COUNT (2U)
AnnaBridge 189:f392fc9709a3 7679
AnnaBridge 189:f392fc9709a3 7680 /*! @name RMR - SAI Receive Mask Register */
AnnaBridge 189:f392fc9709a3 7681 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 7682 #define I2S_RMR_RWM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7683 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
AnnaBridge 189:f392fc9709a3 7684
AnnaBridge 189:f392fc9709a3 7685 /*! @name MCR - SAI MCLK Control Register */
AnnaBridge 189:f392fc9709a3 7686 #define I2S_MCR_MICS_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 7687 #define I2S_MCR_MICS_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 7688 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
AnnaBridge 189:f392fc9709a3 7689 #define I2S_MCR_MOE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 7690 #define I2S_MCR_MOE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 7691 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
AnnaBridge 189:f392fc9709a3 7692 #define I2S_MCR_DUF_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 7693 #define I2S_MCR_DUF_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 7694 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
AnnaBridge 189:f392fc9709a3 7695
AnnaBridge 189:f392fc9709a3 7696 /*! @name MDR - SAI MCLK Divide Register */
AnnaBridge 189:f392fc9709a3 7697 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
AnnaBridge 189:f392fc9709a3 7698 #define I2S_MDR_DIVIDE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7699 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
AnnaBridge 189:f392fc9709a3 7700 #define I2S_MDR_FRACT_MASK (0xFF000U)
AnnaBridge 189:f392fc9709a3 7701 #define I2S_MDR_FRACT_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 7702 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
AnnaBridge 189:f392fc9709a3 7703
AnnaBridge 189:f392fc9709a3 7704
AnnaBridge 189:f392fc9709a3 7705 /*!
AnnaBridge 189:f392fc9709a3 7706 * @}
AnnaBridge 189:f392fc9709a3 7707 */ /* end of group I2S_Register_Masks */
AnnaBridge 189:f392fc9709a3 7708
AnnaBridge 189:f392fc9709a3 7709
AnnaBridge 189:f392fc9709a3 7710 /* I2S - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 7711 /** Peripheral I2S0 base address */
AnnaBridge 189:f392fc9709a3 7712 #define I2S0_BASE (0x4002F000u)
AnnaBridge 189:f392fc9709a3 7713 /** Peripheral I2S0 base pointer */
AnnaBridge 189:f392fc9709a3 7714 #define I2S0 ((I2S_Type *)I2S0_BASE)
AnnaBridge 189:f392fc9709a3 7715 /** Array initializer of I2S peripheral base addresses */
AnnaBridge 189:f392fc9709a3 7716 #define I2S_BASE_ADDRS { I2S0_BASE }
AnnaBridge 189:f392fc9709a3 7717 /** Array initializer of I2S peripheral base pointers */
AnnaBridge 189:f392fc9709a3 7718 #define I2S_BASE_PTRS { I2S0 }
AnnaBridge 189:f392fc9709a3 7719 /** Interrupt vectors for the I2S peripheral type */
AnnaBridge 189:f392fc9709a3 7720 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
AnnaBridge 189:f392fc9709a3 7721 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
AnnaBridge 189:f392fc9709a3 7722
AnnaBridge 189:f392fc9709a3 7723 /*!
AnnaBridge 189:f392fc9709a3 7724 * @}
AnnaBridge 189:f392fc9709a3 7725 */ /* end of group I2S_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 7726
AnnaBridge 189:f392fc9709a3 7727
AnnaBridge 189:f392fc9709a3 7728 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 7729 -- LLWU Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 7730 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 7731
AnnaBridge 189:f392fc9709a3 7732 /*!
AnnaBridge 189:f392fc9709a3 7733 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 7734 * @{
AnnaBridge 189:f392fc9709a3 7735 */
AnnaBridge 189:f392fc9709a3 7736
AnnaBridge 189:f392fc9709a3 7737 /** LLWU - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 7738 typedef struct {
AnnaBridge 189:f392fc9709a3 7739 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 7740 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 7741 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 7742 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 7743 __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 7744 __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 7745 __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */
AnnaBridge 189:f392fc9709a3 7746 __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */
AnnaBridge 189:f392fc9709a3 7747 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 7748 __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */
AnnaBridge 189:f392fc9709a3 7749 __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */
AnnaBridge 189:f392fc9709a3 7750 __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */
AnnaBridge 189:f392fc9709a3 7751 __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 7752 __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */
AnnaBridge 189:f392fc9709a3 7753 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */
AnnaBridge 189:f392fc9709a3 7754 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */
AnnaBridge 189:f392fc9709a3 7755 __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 7756 __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */
AnnaBridge 189:f392fc9709a3 7757 } LLWU_Type;
AnnaBridge 189:f392fc9709a3 7758
AnnaBridge 189:f392fc9709a3 7759 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 7760 -- LLWU Register Masks
AnnaBridge 189:f392fc9709a3 7761 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 7762
AnnaBridge 189:f392fc9709a3 7763 /*!
AnnaBridge 189:f392fc9709a3 7764 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 189:f392fc9709a3 7765 * @{
AnnaBridge 189:f392fc9709a3 7766 */
AnnaBridge 189:f392fc9709a3 7767
AnnaBridge 189:f392fc9709a3 7768 /*! @name PE1 - LLWU Pin Enable 1 register */
AnnaBridge 189:f392fc9709a3 7769 #define LLWU_PE1_WUPE0_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7770 #define LLWU_PE1_WUPE0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7771 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
AnnaBridge 189:f392fc9709a3 7772 #define LLWU_PE1_WUPE1_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7773 #define LLWU_PE1_WUPE1_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7774 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
AnnaBridge 189:f392fc9709a3 7775 #define LLWU_PE1_WUPE2_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7776 #define LLWU_PE1_WUPE2_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7777 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
AnnaBridge 189:f392fc9709a3 7778 #define LLWU_PE1_WUPE3_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7779 #define LLWU_PE1_WUPE3_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7780 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
AnnaBridge 189:f392fc9709a3 7781
AnnaBridge 189:f392fc9709a3 7782 /*! @name PE2 - LLWU Pin Enable 2 register */
AnnaBridge 189:f392fc9709a3 7783 #define LLWU_PE2_WUPE4_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7784 #define LLWU_PE2_WUPE4_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7785 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
AnnaBridge 189:f392fc9709a3 7786 #define LLWU_PE2_WUPE5_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7787 #define LLWU_PE2_WUPE5_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7788 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
AnnaBridge 189:f392fc9709a3 7789 #define LLWU_PE2_WUPE6_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7790 #define LLWU_PE2_WUPE6_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7791 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
AnnaBridge 189:f392fc9709a3 7792 #define LLWU_PE2_WUPE7_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7793 #define LLWU_PE2_WUPE7_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7794 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
AnnaBridge 189:f392fc9709a3 7795
AnnaBridge 189:f392fc9709a3 7796 /*! @name PE3 - LLWU Pin Enable 3 register */
AnnaBridge 189:f392fc9709a3 7797 #define LLWU_PE3_WUPE8_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7798 #define LLWU_PE3_WUPE8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7799 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
AnnaBridge 189:f392fc9709a3 7800 #define LLWU_PE3_WUPE9_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7801 #define LLWU_PE3_WUPE9_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7802 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
AnnaBridge 189:f392fc9709a3 7803 #define LLWU_PE3_WUPE10_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7804 #define LLWU_PE3_WUPE10_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7805 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
AnnaBridge 189:f392fc9709a3 7806 #define LLWU_PE3_WUPE11_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7807 #define LLWU_PE3_WUPE11_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7808 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
AnnaBridge 189:f392fc9709a3 7809
AnnaBridge 189:f392fc9709a3 7810 /*! @name PE4 - LLWU Pin Enable 4 register */
AnnaBridge 189:f392fc9709a3 7811 #define LLWU_PE4_WUPE12_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7812 #define LLWU_PE4_WUPE12_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7813 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
AnnaBridge 189:f392fc9709a3 7814 #define LLWU_PE4_WUPE13_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7815 #define LLWU_PE4_WUPE13_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7816 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
AnnaBridge 189:f392fc9709a3 7817 #define LLWU_PE4_WUPE14_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7818 #define LLWU_PE4_WUPE14_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7819 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
AnnaBridge 189:f392fc9709a3 7820 #define LLWU_PE4_WUPE15_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7821 #define LLWU_PE4_WUPE15_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7822 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
AnnaBridge 189:f392fc9709a3 7823
AnnaBridge 189:f392fc9709a3 7824 /*! @name PE5 - LLWU Pin Enable 5 register */
AnnaBridge 189:f392fc9709a3 7825 #define LLWU_PE5_WUPE16_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7826 #define LLWU_PE5_WUPE16_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7827 #define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
AnnaBridge 189:f392fc9709a3 7828 #define LLWU_PE5_WUPE17_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7829 #define LLWU_PE5_WUPE17_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7830 #define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
AnnaBridge 189:f392fc9709a3 7831 #define LLWU_PE5_WUPE18_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7832 #define LLWU_PE5_WUPE18_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7833 #define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
AnnaBridge 189:f392fc9709a3 7834 #define LLWU_PE5_WUPE19_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7835 #define LLWU_PE5_WUPE19_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7836 #define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
AnnaBridge 189:f392fc9709a3 7837
AnnaBridge 189:f392fc9709a3 7838 /*! @name PE6 - LLWU Pin Enable 6 register */
AnnaBridge 189:f392fc9709a3 7839 #define LLWU_PE6_WUPE20_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7840 #define LLWU_PE6_WUPE20_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7841 #define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
AnnaBridge 189:f392fc9709a3 7842 #define LLWU_PE6_WUPE21_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7843 #define LLWU_PE6_WUPE21_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7844 #define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
AnnaBridge 189:f392fc9709a3 7845 #define LLWU_PE6_WUPE22_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7846 #define LLWU_PE6_WUPE22_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7847 #define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
AnnaBridge 189:f392fc9709a3 7848 #define LLWU_PE6_WUPE23_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7849 #define LLWU_PE6_WUPE23_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7850 #define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
AnnaBridge 189:f392fc9709a3 7851
AnnaBridge 189:f392fc9709a3 7852 /*! @name PE7 - LLWU Pin Enable 7 register */
AnnaBridge 189:f392fc9709a3 7853 #define LLWU_PE7_WUPE24_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7854 #define LLWU_PE7_WUPE24_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7855 #define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
AnnaBridge 189:f392fc9709a3 7856 #define LLWU_PE7_WUPE25_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7857 #define LLWU_PE7_WUPE25_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7858 #define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
AnnaBridge 189:f392fc9709a3 7859 #define LLWU_PE7_WUPE26_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7860 #define LLWU_PE7_WUPE26_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7861 #define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
AnnaBridge 189:f392fc9709a3 7862 #define LLWU_PE7_WUPE27_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7863 #define LLWU_PE7_WUPE27_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7864 #define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
AnnaBridge 189:f392fc9709a3 7865
AnnaBridge 189:f392fc9709a3 7866 /*! @name PE8 - LLWU Pin Enable 8 register */
AnnaBridge 189:f392fc9709a3 7867 #define LLWU_PE8_WUPE28_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 7868 #define LLWU_PE8_WUPE28_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7869 #define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
AnnaBridge 189:f392fc9709a3 7870 #define LLWU_PE8_WUPE29_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 7871 #define LLWU_PE8_WUPE29_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7872 #define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
AnnaBridge 189:f392fc9709a3 7873 #define LLWU_PE8_WUPE30_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 7874 #define LLWU_PE8_WUPE30_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7875 #define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
AnnaBridge 189:f392fc9709a3 7876 #define LLWU_PE8_WUPE31_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 7877 #define LLWU_PE8_WUPE31_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7878 #define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
AnnaBridge 189:f392fc9709a3 7879
AnnaBridge 189:f392fc9709a3 7880 /*! @name ME - LLWU Module Enable register */
AnnaBridge 189:f392fc9709a3 7881 #define LLWU_ME_WUME0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7882 #define LLWU_ME_WUME0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7883 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
AnnaBridge 189:f392fc9709a3 7884 #define LLWU_ME_WUME1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7885 #define LLWU_ME_WUME1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7886 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
AnnaBridge 189:f392fc9709a3 7887 #define LLWU_ME_WUME2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7888 #define LLWU_ME_WUME2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7889 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
AnnaBridge 189:f392fc9709a3 7890 #define LLWU_ME_WUME3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7891 #define LLWU_ME_WUME3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7892 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
AnnaBridge 189:f392fc9709a3 7893 #define LLWU_ME_WUME4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7894 #define LLWU_ME_WUME4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7895 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
AnnaBridge 189:f392fc9709a3 7896 #define LLWU_ME_WUME5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7897 #define LLWU_ME_WUME5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7898 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
AnnaBridge 189:f392fc9709a3 7899 #define LLWU_ME_WUME6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7900 #define LLWU_ME_WUME6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7901 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
AnnaBridge 189:f392fc9709a3 7902 #define LLWU_ME_WUME7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7903 #define LLWU_ME_WUME7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7904 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
AnnaBridge 189:f392fc9709a3 7905
AnnaBridge 189:f392fc9709a3 7906 /*! @name PF1 - LLWU Pin Flag 1 register */
AnnaBridge 189:f392fc9709a3 7907 #define LLWU_PF1_WUF0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7908 #define LLWU_PF1_WUF0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7909 #define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
AnnaBridge 189:f392fc9709a3 7910 #define LLWU_PF1_WUF1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7911 #define LLWU_PF1_WUF1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7912 #define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
AnnaBridge 189:f392fc9709a3 7913 #define LLWU_PF1_WUF2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7914 #define LLWU_PF1_WUF2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7915 #define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
AnnaBridge 189:f392fc9709a3 7916 #define LLWU_PF1_WUF3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7917 #define LLWU_PF1_WUF3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7918 #define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
AnnaBridge 189:f392fc9709a3 7919 #define LLWU_PF1_WUF4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7920 #define LLWU_PF1_WUF4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7921 #define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
AnnaBridge 189:f392fc9709a3 7922 #define LLWU_PF1_WUF5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7923 #define LLWU_PF1_WUF5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7924 #define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
AnnaBridge 189:f392fc9709a3 7925 #define LLWU_PF1_WUF6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7926 #define LLWU_PF1_WUF6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7927 #define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
AnnaBridge 189:f392fc9709a3 7928 #define LLWU_PF1_WUF7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7929 #define LLWU_PF1_WUF7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7930 #define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
AnnaBridge 189:f392fc9709a3 7931
AnnaBridge 189:f392fc9709a3 7932 /*! @name PF2 - LLWU Pin Flag 2 register */
AnnaBridge 189:f392fc9709a3 7933 #define LLWU_PF2_WUF8_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7934 #define LLWU_PF2_WUF8_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7935 #define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
AnnaBridge 189:f392fc9709a3 7936 #define LLWU_PF2_WUF9_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7937 #define LLWU_PF2_WUF9_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7938 #define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
AnnaBridge 189:f392fc9709a3 7939 #define LLWU_PF2_WUF10_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7940 #define LLWU_PF2_WUF10_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7941 #define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
AnnaBridge 189:f392fc9709a3 7942 #define LLWU_PF2_WUF11_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7943 #define LLWU_PF2_WUF11_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7944 #define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
AnnaBridge 189:f392fc9709a3 7945 #define LLWU_PF2_WUF12_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7946 #define LLWU_PF2_WUF12_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7947 #define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
AnnaBridge 189:f392fc9709a3 7948 #define LLWU_PF2_WUF13_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7949 #define LLWU_PF2_WUF13_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7950 #define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
AnnaBridge 189:f392fc9709a3 7951 #define LLWU_PF2_WUF14_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7952 #define LLWU_PF2_WUF14_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7953 #define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
AnnaBridge 189:f392fc9709a3 7954 #define LLWU_PF2_WUF15_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7955 #define LLWU_PF2_WUF15_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7956 #define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
AnnaBridge 189:f392fc9709a3 7957
AnnaBridge 189:f392fc9709a3 7958 /*! @name PF3 - LLWU Pin Flag 3 register */
AnnaBridge 189:f392fc9709a3 7959 #define LLWU_PF3_WUF16_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7960 #define LLWU_PF3_WUF16_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7961 #define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
AnnaBridge 189:f392fc9709a3 7962 #define LLWU_PF3_WUF17_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7963 #define LLWU_PF3_WUF17_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7964 #define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
AnnaBridge 189:f392fc9709a3 7965 #define LLWU_PF3_WUF18_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7966 #define LLWU_PF3_WUF18_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7967 #define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
AnnaBridge 189:f392fc9709a3 7968 #define LLWU_PF3_WUF19_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7969 #define LLWU_PF3_WUF19_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7970 #define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
AnnaBridge 189:f392fc9709a3 7971 #define LLWU_PF3_WUF20_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7972 #define LLWU_PF3_WUF20_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7973 #define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
AnnaBridge 189:f392fc9709a3 7974 #define LLWU_PF3_WUF21_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 7975 #define LLWU_PF3_WUF21_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 7976 #define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
AnnaBridge 189:f392fc9709a3 7977 #define LLWU_PF3_WUF22_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 7978 #define LLWU_PF3_WUF22_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 7979 #define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
AnnaBridge 189:f392fc9709a3 7980 #define LLWU_PF3_WUF23_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 7981 #define LLWU_PF3_WUF23_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 7982 #define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
AnnaBridge 189:f392fc9709a3 7983
AnnaBridge 189:f392fc9709a3 7984 /*! @name PF4 - LLWU Pin Flag 4 register */
AnnaBridge 189:f392fc9709a3 7985 #define LLWU_PF4_WUF24_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 7986 #define LLWU_PF4_WUF24_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 7987 #define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
AnnaBridge 189:f392fc9709a3 7988 #define LLWU_PF4_WUF25_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 7989 #define LLWU_PF4_WUF25_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 7990 #define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
AnnaBridge 189:f392fc9709a3 7991 #define LLWU_PF4_WUF26_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 7992 #define LLWU_PF4_WUF26_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 7993 #define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
AnnaBridge 189:f392fc9709a3 7994 #define LLWU_PF4_WUF27_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 7995 #define LLWU_PF4_WUF27_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 7996 #define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
AnnaBridge 189:f392fc9709a3 7997 #define LLWU_PF4_WUF28_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 7998 #define LLWU_PF4_WUF28_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 7999 #define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
AnnaBridge 189:f392fc9709a3 8000 #define LLWU_PF4_WUF29_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 8001 #define LLWU_PF4_WUF29_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8002 #define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
AnnaBridge 189:f392fc9709a3 8003 #define LLWU_PF4_WUF30_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 8004 #define LLWU_PF4_WUF30_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 8005 #define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
AnnaBridge 189:f392fc9709a3 8006 #define LLWU_PF4_WUF31_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8007 #define LLWU_PF4_WUF31_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8008 #define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
AnnaBridge 189:f392fc9709a3 8009
AnnaBridge 189:f392fc9709a3 8010 /*! @name MF5 - LLWU Module Flag 5 register */
AnnaBridge 189:f392fc9709a3 8011 #define LLWU_MF5_MWUF0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8012 #define LLWU_MF5_MWUF0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8013 #define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
AnnaBridge 189:f392fc9709a3 8014 #define LLWU_MF5_MWUF1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 8015 #define LLWU_MF5_MWUF1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 8016 #define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
AnnaBridge 189:f392fc9709a3 8017 #define LLWU_MF5_MWUF2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 8018 #define LLWU_MF5_MWUF2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8019 #define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
AnnaBridge 189:f392fc9709a3 8020 #define LLWU_MF5_MWUF3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 8021 #define LLWU_MF5_MWUF3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8022 #define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
AnnaBridge 189:f392fc9709a3 8023 #define LLWU_MF5_MWUF4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 8024 #define LLWU_MF5_MWUF4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8025 #define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
AnnaBridge 189:f392fc9709a3 8026 #define LLWU_MF5_MWUF5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 8027 #define LLWU_MF5_MWUF5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8028 #define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
AnnaBridge 189:f392fc9709a3 8029 #define LLWU_MF5_MWUF6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 8030 #define LLWU_MF5_MWUF6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 8031 #define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
AnnaBridge 189:f392fc9709a3 8032 #define LLWU_MF5_MWUF7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8033 #define LLWU_MF5_MWUF7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8034 #define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
AnnaBridge 189:f392fc9709a3 8035
AnnaBridge 189:f392fc9709a3 8036 /*! @name FILT1 - LLWU Pin Filter 1 register */
AnnaBridge 189:f392fc9709a3 8037 #define LLWU_FILT1_FILTSEL_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 8038 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8039 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 189:f392fc9709a3 8040 #define LLWU_FILT1_FILTE_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 8041 #define LLWU_FILT1_FILTE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8042 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
AnnaBridge 189:f392fc9709a3 8043 #define LLWU_FILT1_FILTF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8044 #define LLWU_FILT1_FILTF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8045 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
AnnaBridge 189:f392fc9709a3 8046
AnnaBridge 189:f392fc9709a3 8047 /*! @name FILT2 - LLWU Pin Filter 2 register */
AnnaBridge 189:f392fc9709a3 8048 #define LLWU_FILT2_FILTSEL_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 8049 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8050 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 189:f392fc9709a3 8051 #define LLWU_FILT2_FILTE_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 8052 #define LLWU_FILT2_FILTE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8053 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
AnnaBridge 189:f392fc9709a3 8054 #define LLWU_FILT2_FILTF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8055 #define LLWU_FILT2_FILTF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8056 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
AnnaBridge 189:f392fc9709a3 8057
AnnaBridge 189:f392fc9709a3 8058 /*! @name FILT3 - LLWU Pin Filter 3 register */
AnnaBridge 189:f392fc9709a3 8059 #define LLWU_FILT3_FILTSEL_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 8060 #define LLWU_FILT3_FILTSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8061 #define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
AnnaBridge 189:f392fc9709a3 8062 #define LLWU_FILT3_FILTE_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 8063 #define LLWU_FILT3_FILTE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8064 #define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
AnnaBridge 189:f392fc9709a3 8065 #define LLWU_FILT3_FILTF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8066 #define LLWU_FILT3_FILTF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8067 #define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
AnnaBridge 189:f392fc9709a3 8068
AnnaBridge 189:f392fc9709a3 8069 /*! @name FILT4 - LLWU Pin Filter 4 register */
AnnaBridge 189:f392fc9709a3 8070 #define LLWU_FILT4_FILTSEL_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 8071 #define LLWU_FILT4_FILTSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8072 #define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
AnnaBridge 189:f392fc9709a3 8073 #define LLWU_FILT4_FILTE_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 8074 #define LLWU_FILT4_FILTE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8075 #define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
AnnaBridge 189:f392fc9709a3 8076 #define LLWU_FILT4_FILTF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8077 #define LLWU_FILT4_FILTF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8078 #define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
AnnaBridge 189:f392fc9709a3 8079
AnnaBridge 189:f392fc9709a3 8080
AnnaBridge 189:f392fc9709a3 8081 /*!
AnnaBridge 189:f392fc9709a3 8082 * @}
AnnaBridge 189:f392fc9709a3 8083 */ /* end of group LLWU_Register_Masks */
AnnaBridge 189:f392fc9709a3 8084
AnnaBridge 189:f392fc9709a3 8085
AnnaBridge 189:f392fc9709a3 8086 /* LLWU - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 8087 /** Peripheral LLWU base address */
AnnaBridge 189:f392fc9709a3 8088 #define LLWU_BASE (0x4007C000u)
AnnaBridge 189:f392fc9709a3 8089 /** Peripheral LLWU base pointer */
AnnaBridge 189:f392fc9709a3 8090 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 189:f392fc9709a3 8091 /** Array initializer of LLWU peripheral base addresses */
AnnaBridge 189:f392fc9709a3 8092 #define LLWU_BASE_ADDRS { LLWU_BASE }
AnnaBridge 189:f392fc9709a3 8093 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 189:f392fc9709a3 8094 #define LLWU_BASE_PTRS { LLWU }
AnnaBridge 189:f392fc9709a3 8095 /** Interrupt vectors for the LLWU peripheral type */
AnnaBridge 189:f392fc9709a3 8096 #define LLWU_IRQS { LLWU_IRQn }
AnnaBridge 189:f392fc9709a3 8097
AnnaBridge 189:f392fc9709a3 8098 /*!
AnnaBridge 189:f392fc9709a3 8099 * @}
AnnaBridge 189:f392fc9709a3 8100 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 8101
AnnaBridge 189:f392fc9709a3 8102
AnnaBridge 189:f392fc9709a3 8103 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8104 -- LMEM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8105 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8106
AnnaBridge 189:f392fc9709a3 8107 /*!
AnnaBridge 189:f392fc9709a3 8108 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8109 * @{
AnnaBridge 189:f392fc9709a3 8110 */
AnnaBridge 189:f392fc9709a3 8111
AnnaBridge 189:f392fc9709a3 8112 /** LMEM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 8113 typedef struct {
AnnaBridge 189:f392fc9709a3 8114 __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 8115 __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 8116 __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 8117 __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 8118 uint8_t RESERVED_0[16];
AnnaBridge 189:f392fc9709a3 8119 __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 8120 uint8_t RESERVED_1[2012];
AnnaBridge 189:f392fc9709a3 8121 __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */
AnnaBridge 189:f392fc9709a3 8122 __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */
AnnaBridge 189:f392fc9709a3 8123 __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */
AnnaBridge 189:f392fc9709a3 8124 __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */
AnnaBridge 189:f392fc9709a3 8125 uint8_t RESERVED_2[16];
AnnaBridge 189:f392fc9709a3 8126 __IO uint32_t PSCRMR; /**< Cache regions mode register, offset: 0x820 */
AnnaBridge 189:f392fc9709a3 8127 } LMEM_Type;
AnnaBridge 189:f392fc9709a3 8128
AnnaBridge 189:f392fc9709a3 8129 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8130 -- LMEM Register Masks
AnnaBridge 189:f392fc9709a3 8131 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8132
AnnaBridge 189:f392fc9709a3 8133 /*!
AnnaBridge 189:f392fc9709a3 8134 * @addtogroup LMEM_Register_Masks LMEM Register Masks
AnnaBridge 189:f392fc9709a3 8135 * @{
AnnaBridge 189:f392fc9709a3 8136 */
AnnaBridge 189:f392fc9709a3 8137
AnnaBridge 189:f392fc9709a3 8138 /*! @name PCCCR - Cache control register */
AnnaBridge 189:f392fc9709a3 8139 #define LMEM_PCCCR_ENCACHE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8140 #define LMEM_PCCCR_ENCACHE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8141 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
AnnaBridge 189:f392fc9709a3 8142 #define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 8143 #define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 8144 #define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
AnnaBridge 189:f392fc9709a3 8145 #define LMEM_PCCCR_PCCR2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 8146 #define LMEM_PCCCR_PCCR2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8147 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
AnnaBridge 189:f392fc9709a3 8148 #define LMEM_PCCCR_PCCR3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 8149 #define LMEM_PCCCR_PCCR3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8150 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
AnnaBridge 189:f392fc9709a3 8151 #define LMEM_PCCCR_INVW0_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 8152 #define LMEM_PCCCR_INVW0_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8153 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
AnnaBridge 189:f392fc9709a3 8154 #define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 8155 #define LMEM_PCCCR_PUSHW0_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 8156 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
AnnaBridge 189:f392fc9709a3 8157 #define LMEM_PCCCR_INVW1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 8158 #define LMEM_PCCCR_INVW1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8159 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
AnnaBridge 189:f392fc9709a3 8160 #define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 8161 #define LMEM_PCCCR_PUSHW1_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 8162 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
AnnaBridge 189:f392fc9709a3 8163 #define LMEM_PCCCR_GO_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 8164 #define LMEM_PCCCR_GO_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 8165 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
AnnaBridge 189:f392fc9709a3 8166
AnnaBridge 189:f392fc9709a3 8167 /*! @name PCCLCR - Cache line control register */
AnnaBridge 189:f392fc9709a3 8168 #define LMEM_PCCLCR_LGO_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8169 #define LMEM_PCCLCR_LGO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8170 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
AnnaBridge 189:f392fc9709a3 8171 #define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)
AnnaBridge 189:f392fc9709a3 8172 #define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8173 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
AnnaBridge 189:f392fc9709a3 8174 #define LMEM_PCCLCR_WSEL_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 8175 #define LMEM_PCCLCR_WSEL_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8176 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
AnnaBridge 189:f392fc9709a3 8177 #define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 8178 #define LMEM_PCCLCR_TDSEL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8179 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
AnnaBridge 189:f392fc9709a3 8180 #define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 8181 #define LMEM_PCCLCR_LCIVB_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 8182 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
AnnaBridge 189:f392fc9709a3 8183 #define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 8184 #define LMEM_PCCLCR_LCIMB_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 8185 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
AnnaBridge 189:f392fc9709a3 8186 #define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 8187 #define LMEM_PCCLCR_LCWAY_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 8188 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
AnnaBridge 189:f392fc9709a3 8189 #define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 8190 #define LMEM_PCCLCR_LCMD_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8191 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
AnnaBridge 189:f392fc9709a3 8192 #define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 8193 #define LMEM_PCCLCR_LADSEL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8194 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
AnnaBridge 189:f392fc9709a3 8195 #define LMEM_PCCLCR_LACC_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 8196 #define LMEM_PCCLCR_LACC_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 8197 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
AnnaBridge 189:f392fc9709a3 8198
AnnaBridge 189:f392fc9709a3 8199 /*! @name PCCSAR - Cache search address register */
AnnaBridge 189:f392fc9709a3 8200 #define LMEM_PCCSAR_LGO_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8201 #define LMEM_PCCSAR_LGO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8202 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
AnnaBridge 189:f392fc9709a3 8203 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
AnnaBridge 189:f392fc9709a3 8204 #define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8205 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
AnnaBridge 189:f392fc9709a3 8206
AnnaBridge 189:f392fc9709a3 8207 /*! @name PCCCVR - Cache read/write value register */
AnnaBridge 189:f392fc9709a3 8208 #define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 8209 #define LMEM_PCCCVR_DATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8210 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
AnnaBridge 189:f392fc9709a3 8211
AnnaBridge 189:f392fc9709a3 8212 /*! @name PCCRMR - Cache regions mode register */
AnnaBridge 189:f392fc9709a3 8213 #define LMEM_PCCRMR_R15_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 8214 #define LMEM_PCCRMR_R15_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8215 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
AnnaBridge 189:f392fc9709a3 8216 #define LMEM_PCCRMR_R14_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 8217 #define LMEM_PCCRMR_R14_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8218 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
AnnaBridge 189:f392fc9709a3 8219 #define LMEM_PCCRMR_R13_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 8220 #define LMEM_PCCRMR_R13_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8221 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
AnnaBridge 189:f392fc9709a3 8222 #define LMEM_PCCRMR_R12_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 8223 #define LMEM_PCCRMR_R12_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 8224 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
AnnaBridge 189:f392fc9709a3 8225 #define LMEM_PCCRMR_R11_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 8226 #define LMEM_PCCRMR_R11_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 8227 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
AnnaBridge 189:f392fc9709a3 8228 #define LMEM_PCCRMR_R10_MASK (0xC00U)
AnnaBridge 189:f392fc9709a3 8229 #define LMEM_PCCRMR_R10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 8230 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
AnnaBridge 189:f392fc9709a3 8231 #define LMEM_PCCRMR_R9_MASK (0x3000U)
AnnaBridge 189:f392fc9709a3 8232 #define LMEM_PCCRMR_R9_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 8233 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
AnnaBridge 189:f392fc9709a3 8234 #define LMEM_PCCRMR_R8_MASK (0xC000U)
AnnaBridge 189:f392fc9709a3 8235 #define LMEM_PCCRMR_R8_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8236 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
AnnaBridge 189:f392fc9709a3 8237 #define LMEM_PCCRMR_R7_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 8238 #define LMEM_PCCRMR_R7_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8239 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
AnnaBridge 189:f392fc9709a3 8240 #define LMEM_PCCRMR_R6_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 8241 #define LMEM_PCCRMR_R6_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 8242 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
AnnaBridge 189:f392fc9709a3 8243 #define LMEM_PCCRMR_R5_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 8244 #define LMEM_PCCRMR_R5_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 8245 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
AnnaBridge 189:f392fc9709a3 8246 #define LMEM_PCCRMR_R4_MASK (0xC00000U)
AnnaBridge 189:f392fc9709a3 8247 #define LMEM_PCCRMR_R4_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 8248 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
AnnaBridge 189:f392fc9709a3 8249 #define LMEM_PCCRMR_R3_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 8250 #define LMEM_PCCRMR_R3_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8251 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
AnnaBridge 189:f392fc9709a3 8252 #define LMEM_PCCRMR_R2_MASK (0xC000000U)
AnnaBridge 189:f392fc9709a3 8253 #define LMEM_PCCRMR_R2_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8254 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
AnnaBridge 189:f392fc9709a3 8255 #define LMEM_PCCRMR_R1_MASK (0x30000000U)
AnnaBridge 189:f392fc9709a3 8256 #define LMEM_PCCRMR_R1_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 8257 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
AnnaBridge 189:f392fc9709a3 8258 #define LMEM_PCCRMR_R0_MASK (0xC0000000U)
AnnaBridge 189:f392fc9709a3 8259 #define LMEM_PCCRMR_R0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 8260 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
AnnaBridge 189:f392fc9709a3 8261
AnnaBridge 189:f392fc9709a3 8262 /*! @name PSCCR - Cache control register */
AnnaBridge 189:f392fc9709a3 8263 #define LMEM_PSCCR_ENCACHE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8264 #define LMEM_PSCCR_ENCACHE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8265 #define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK)
AnnaBridge 189:f392fc9709a3 8266 #define LMEM_PSCCR_ENWRBUF_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 8267 #define LMEM_PSCCR_ENWRBUF_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 8268 #define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK)
AnnaBridge 189:f392fc9709a3 8269 #define LMEM_PSCCR_INVW0_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 8270 #define LMEM_PSCCR_INVW0_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8271 #define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK)
AnnaBridge 189:f392fc9709a3 8272 #define LMEM_PSCCR_PUSHW0_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 8273 #define LMEM_PSCCR_PUSHW0_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 8274 #define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK)
AnnaBridge 189:f392fc9709a3 8275 #define LMEM_PSCCR_INVW1_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 8276 #define LMEM_PSCCR_INVW1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8277 #define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK)
AnnaBridge 189:f392fc9709a3 8278 #define LMEM_PSCCR_PUSHW1_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 8279 #define LMEM_PSCCR_PUSHW1_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 8280 #define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK)
AnnaBridge 189:f392fc9709a3 8281 #define LMEM_PSCCR_GO_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 8282 #define LMEM_PSCCR_GO_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 8283 #define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK)
AnnaBridge 189:f392fc9709a3 8284
AnnaBridge 189:f392fc9709a3 8285 /*! @name PSCLCR - Cache line control register */
AnnaBridge 189:f392fc9709a3 8286 #define LMEM_PSCLCR_LGO_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8287 #define LMEM_PSCLCR_LGO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8288 #define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK)
AnnaBridge 189:f392fc9709a3 8289 #define LMEM_PSCLCR_CACHEADDR_MASK (0xFFCU)
AnnaBridge 189:f392fc9709a3 8290 #define LMEM_PSCLCR_CACHEADDR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8291 #define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK)
AnnaBridge 189:f392fc9709a3 8292 #define LMEM_PSCLCR_WSEL_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 8293 #define LMEM_PSCLCR_WSEL_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8294 #define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK)
AnnaBridge 189:f392fc9709a3 8295 #define LMEM_PSCLCR_TDSEL_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 8296 #define LMEM_PSCLCR_TDSEL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8297 #define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK)
AnnaBridge 189:f392fc9709a3 8298 #define LMEM_PSCLCR_LCIVB_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 8299 #define LMEM_PSCLCR_LCIVB_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 8300 #define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK)
AnnaBridge 189:f392fc9709a3 8301 #define LMEM_PSCLCR_LCIMB_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 8302 #define LMEM_PSCLCR_LCIMB_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 8303 #define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK)
AnnaBridge 189:f392fc9709a3 8304 #define LMEM_PSCLCR_LCWAY_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 8305 #define LMEM_PSCLCR_LCWAY_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 8306 #define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK)
AnnaBridge 189:f392fc9709a3 8307 #define LMEM_PSCLCR_LCMD_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 8308 #define LMEM_PSCLCR_LCMD_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8309 #define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK)
AnnaBridge 189:f392fc9709a3 8310 #define LMEM_PSCLCR_LADSEL_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 8311 #define LMEM_PSCLCR_LADSEL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8312 #define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK)
AnnaBridge 189:f392fc9709a3 8313 #define LMEM_PSCLCR_LACC_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 8314 #define LMEM_PSCLCR_LACC_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 8315 #define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK)
AnnaBridge 189:f392fc9709a3 8316
AnnaBridge 189:f392fc9709a3 8317 /*! @name PSCSAR - Cache search address register */
AnnaBridge 189:f392fc9709a3 8318 #define LMEM_PSCSAR_LGO_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8319 #define LMEM_PSCSAR_LGO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8320 #define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK)
AnnaBridge 189:f392fc9709a3 8321 #define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFCU)
AnnaBridge 189:f392fc9709a3 8322 #define LMEM_PSCSAR_PHYADDR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8323 #define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK)
AnnaBridge 189:f392fc9709a3 8324
AnnaBridge 189:f392fc9709a3 8325 /*! @name PSCCVR - Cache read/write value register */
AnnaBridge 189:f392fc9709a3 8326 #define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 8327 #define LMEM_PSCCVR_DATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8328 #define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK)
AnnaBridge 189:f392fc9709a3 8329
AnnaBridge 189:f392fc9709a3 8330 /*! @name PSCRMR - Cache regions mode register */
AnnaBridge 189:f392fc9709a3 8331 #define LMEM_PSCRMR_R15_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 8332 #define LMEM_PSCRMR_R15_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8333 #define LMEM_PSCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R15_SHIFT)) & LMEM_PSCRMR_R15_MASK)
AnnaBridge 189:f392fc9709a3 8334 #define LMEM_PSCRMR_R14_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 8335 #define LMEM_PSCRMR_R14_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8336 #define LMEM_PSCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R14_SHIFT)) & LMEM_PSCRMR_R14_MASK)
AnnaBridge 189:f392fc9709a3 8337 #define LMEM_PSCRMR_R13_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 8338 #define LMEM_PSCRMR_R13_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8339 #define LMEM_PSCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R13_SHIFT)) & LMEM_PSCRMR_R13_MASK)
AnnaBridge 189:f392fc9709a3 8340 #define LMEM_PSCRMR_R12_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 8341 #define LMEM_PSCRMR_R12_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 8342 #define LMEM_PSCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R12_SHIFT)) & LMEM_PSCRMR_R12_MASK)
AnnaBridge 189:f392fc9709a3 8343 #define LMEM_PSCRMR_R11_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 8344 #define LMEM_PSCRMR_R11_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 8345 #define LMEM_PSCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R11_SHIFT)) & LMEM_PSCRMR_R11_MASK)
AnnaBridge 189:f392fc9709a3 8346 #define LMEM_PSCRMR_R10_MASK (0xC00U)
AnnaBridge 189:f392fc9709a3 8347 #define LMEM_PSCRMR_R10_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 8348 #define LMEM_PSCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R10_SHIFT)) & LMEM_PSCRMR_R10_MASK)
AnnaBridge 189:f392fc9709a3 8349 #define LMEM_PSCRMR_R9_MASK (0x3000U)
AnnaBridge 189:f392fc9709a3 8350 #define LMEM_PSCRMR_R9_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 8351 #define LMEM_PSCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R9_SHIFT)) & LMEM_PSCRMR_R9_MASK)
AnnaBridge 189:f392fc9709a3 8352 #define LMEM_PSCRMR_R8_MASK (0xC000U)
AnnaBridge 189:f392fc9709a3 8353 #define LMEM_PSCRMR_R8_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8354 #define LMEM_PSCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R8_SHIFT)) & LMEM_PSCRMR_R8_MASK)
AnnaBridge 189:f392fc9709a3 8355 #define LMEM_PSCRMR_R7_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 8356 #define LMEM_PSCRMR_R7_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8357 #define LMEM_PSCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R7_SHIFT)) & LMEM_PSCRMR_R7_MASK)
AnnaBridge 189:f392fc9709a3 8358 #define LMEM_PSCRMR_R6_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 8359 #define LMEM_PSCRMR_R6_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 8360 #define LMEM_PSCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R6_SHIFT)) & LMEM_PSCRMR_R6_MASK)
AnnaBridge 189:f392fc9709a3 8361 #define LMEM_PSCRMR_R5_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 8362 #define LMEM_PSCRMR_R5_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 8363 #define LMEM_PSCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R5_SHIFT)) & LMEM_PSCRMR_R5_MASK)
AnnaBridge 189:f392fc9709a3 8364 #define LMEM_PSCRMR_R4_MASK (0xC00000U)
AnnaBridge 189:f392fc9709a3 8365 #define LMEM_PSCRMR_R4_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 8366 #define LMEM_PSCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R4_SHIFT)) & LMEM_PSCRMR_R4_MASK)
AnnaBridge 189:f392fc9709a3 8367 #define LMEM_PSCRMR_R3_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 8368 #define LMEM_PSCRMR_R3_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8369 #define LMEM_PSCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R3_SHIFT)) & LMEM_PSCRMR_R3_MASK)
AnnaBridge 189:f392fc9709a3 8370 #define LMEM_PSCRMR_R2_MASK (0xC000000U)
AnnaBridge 189:f392fc9709a3 8371 #define LMEM_PSCRMR_R2_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8372 #define LMEM_PSCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R2_SHIFT)) & LMEM_PSCRMR_R2_MASK)
AnnaBridge 189:f392fc9709a3 8373 #define LMEM_PSCRMR_R1_MASK (0x30000000U)
AnnaBridge 189:f392fc9709a3 8374 #define LMEM_PSCRMR_R1_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 8375 #define LMEM_PSCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R1_SHIFT)) & LMEM_PSCRMR_R1_MASK)
AnnaBridge 189:f392fc9709a3 8376 #define LMEM_PSCRMR_R0_MASK (0xC0000000U)
AnnaBridge 189:f392fc9709a3 8377 #define LMEM_PSCRMR_R0_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 8378 #define LMEM_PSCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R0_SHIFT)) & LMEM_PSCRMR_R0_MASK)
AnnaBridge 189:f392fc9709a3 8379
AnnaBridge 189:f392fc9709a3 8380
AnnaBridge 189:f392fc9709a3 8381 /*!
AnnaBridge 189:f392fc9709a3 8382 * @}
AnnaBridge 189:f392fc9709a3 8383 */ /* end of group LMEM_Register_Masks */
AnnaBridge 189:f392fc9709a3 8384
AnnaBridge 189:f392fc9709a3 8385
AnnaBridge 189:f392fc9709a3 8386 /* LMEM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 8387 /** Peripheral LMEM base address */
AnnaBridge 189:f392fc9709a3 8388 #define LMEM_BASE (0xE0082000u)
AnnaBridge 189:f392fc9709a3 8389 /** Peripheral LMEM base pointer */
AnnaBridge 189:f392fc9709a3 8390 #define LMEM ((LMEM_Type *)LMEM_BASE)
AnnaBridge 189:f392fc9709a3 8391 /** Array initializer of LMEM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 8392 #define LMEM_BASE_ADDRS { LMEM_BASE }
AnnaBridge 189:f392fc9709a3 8393 /** Array initializer of LMEM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 8394 #define LMEM_BASE_PTRS { LMEM }
AnnaBridge 189:f392fc9709a3 8395
AnnaBridge 189:f392fc9709a3 8396 /*!
AnnaBridge 189:f392fc9709a3 8397 * @}
AnnaBridge 189:f392fc9709a3 8398 */ /* end of group LMEM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 8399
AnnaBridge 189:f392fc9709a3 8400
AnnaBridge 189:f392fc9709a3 8401 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8402 -- LPTMR Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8403 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8404
AnnaBridge 189:f392fc9709a3 8405 /*!
AnnaBridge 189:f392fc9709a3 8406 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8407 * @{
AnnaBridge 189:f392fc9709a3 8408 */
AnnaBridge 189:f392fc9709a3 8409
AnnaBridge 189:f392fc9709a3 8410 /** LPTMR - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 8411 typedef struct {
AnnaBridge 189:f392fc9709a3 8412 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 8413 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 8414 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 8415 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 8416 } LPTMR_Type;
AnnaBridge 189:f392fc9709a3 8417
AnnaBridge 189:f392fc9709a3 8418 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8419 -- LPTMR Register Masks
AnnaBridge 189:f392fc9709a3 8420 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8421
AnnaBridge 189:f392fc9709a3 8422 /*!
AnnaBridge 189:f392fc9709a3 8423 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 189:f392fc9709a3 8424 * @{
AnnaBridge 189:f392fc9709a3 8425 */
AnnaBridge 189:f392fc9709a3 8426
AnnaBridge 189:f392fc9709a3 8427 /*! @name CSR - Low Power Timer Control Status Register */
AnnaBridge 189:f392fc9709a3 8428 #define LPTMR_CSR_TEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8429 #define LPTMR_CSR_TEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8430 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
AnnaBridge 189:f392fc9709a3 8431 #define LPTMR_CSR_TMS_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 8432 #define LPTMR_CSR_TMS_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 8433 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
AnnaBridge 189:f392fc9709a3 8434 #define LPTMR_CSR_TFC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 8435 #define LPTMR_CSR_TFC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8436 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
AnnaBridge 189:f392fc9709a3 8437 #define LPTMR_CSR_TPP_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 8438 #define LPTMR_CSR_TPP_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8439 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
AnnaBridge 189:f392fc9709a3 8440 #define LPTMR_CSR_TPS_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 8441 #define LPTMR_CSR_TPS_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8442 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
AnnaBridge 189:f392fc9709a3 8443 #define LPTMR_CSR_TIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 8444 #define LPTMR_CSR_TIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 8445 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
AnnaBridge 189:f392fc9709a3 8446 #define LPTMR_CSR_TCF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8447 #define LPTMR_CSR_TCF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8448 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
AnnaBridge 189:f392fc9709a3 8449
AnnaBridge 189:f392fc9709a3 8450 /*! @name PSR - Low Power Timer Prescale Register */
AnnaBridge 189:f392fc9709a3 8451 #define LPTMR_PSR_PCS_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 8452 #define LPTMR_PSR_PCS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8453 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
AnnaBridge 189:f392fc9709a3 8454 #define LPTMR_PSR_PBYP_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 8455 #define LPTMR_PSR_PBYP_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8456 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
AnnaBridge 189:f392fc9709a3 8457 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
AnnaBridge 189:f392fc9709a3 8458 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8459 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 189:f392fc9709a3 8460
AnnaBridge 189:f392fc9709a3 8461 /*! @name CMR - Low Power Timer Compare Register */
AnnaBridge 189:f392fc9709a3 8462 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 8463 #define LPTMR_CMR_COMPARE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8464 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
AnnaBridge 189:f392fc9709a3 8465
AnnaBridge 189:f392fc9709a3 8466 /*! @name CNR - Low Power Timer Counter Register */
AnnaBridge 189:f392fc9709a3 8467 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 8468 #define LPTMR_CNR_COUNTER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8469 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
AnnaBridge 189:f392fc9709a3 8470
AnnaBridge 189:f392fc9709a3 8471
AnnaBridge 189:f392fc9709a3 8472 /*!
AnnaBridge 189:f392fc9709a3 8473 * @}
AnnaBridge 189:f392fc9709a3 8474 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 189:f392fc9709a3 8475
AnnaBridge 189:f392fc9709a3 8476
AnnaBridge 189:f392fc9709a3 8477 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 8478 /** Peripheral LPTMR0 base address */
AnnaBridge 189:f392fc9709a3 8479 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 189:f392fc9709a3 8480 /** Peripheral LPTMR0 base pointer */
AnnaBridge 189:f392fc9709a3 8481 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 189:f392fc9709a3 8482 /** Peripheral LPTMR1 base address */
AnnaBridge 189:f392fc9709a3 8483 #define LPTMR1_BASE (0x40044000u)
AnnaBridge 189:f392fc9709a3 8484 /** Peripheral LPTMR1 base pointer */
AnnaBridge 189:f392fc9709a3 8485 #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE)
AnnaBridge 189:f392fc9709a3 8486 /** Array initializer of LPTMR peripheral base addresses */
AnnaBridge 189:f392fc9709a3 8487 #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE }
AnnaBridge 189:f392fc9709a3 8488 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 189:f392fc9709a3 8489 #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 }
AnnaBridge 189:f392fc9709a3 8490 /** Interrupt vectors for the LPTMR peripheral type */
AnnaBridge 189:f392fc9709a3 8491 #define LPTMR_IRQS { LPTMR0_LPTMR1_IRQn, LPTMR0_LPTMR1_IRQn }
AnnaBridge 189:f392fc9709a3 8492
AnnaBridge 189:f392fc9709a3 8493 /*!
AnnaBridge 189:f392fc9709a3 8494 * @}
AnnaBridge 189:f392fc9709a3 8495 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 8496
AnnaBridge 189:f392fc9709a3 8497
AnnaBridge 189:f392fc9709a3 8498 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8499 -- LPUART Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8500 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8501
AnnaBridge 189:f392fc9709a3 8502 /*!
AnnaBridge 189:f392fc9709a3 8503 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8504 * @{
AnnaBridge 189:f392fc9709a3 8505 */
AnnaBridge 189:f392fc9709a3 8506
AnnaBridge 189:f392fc9709a3 8507 /** LPUART - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 8508 typedef struct {
AnnaBridge 189:f392fc9709a3 8509 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 8510 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 8511 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 8512 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 8513 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 8514 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 8515 __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 8516 __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 8517 } LPUART_Type;
AnnaBridge 189:f392fc9709a3 8518
AnnaBridge 189:f392fc9709a3 8519 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8520 -- LPUART Register Masks
AnnaBridge 189:f392fc9709a3 8521 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8522
AnnaBridge 189:f392fc9709a3 8523 /*!
AnnaBridge 189:f392fc9709a3 8524 * @addtogroup LPUART_Register_Masks LPUART Register Masks
AnnaBridge 189:f392fc9709a3 8525 * @{
AnnaBridge 189:f392fc9709a3 8526 */
AnnaBridge 189:f392fc9709a3 8527
AnnaBridge 189:f392fc9709a3 8528 /*! @name BAUD - LPUART Baud Rate Register */
AnnaBridge 189:f392fc9709a3 8529 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
AnnaBridge 189:f392fc9709a3 8530 #define LPUART_BAUD_SBR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8531 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
AnnaBridge 189:f392fc9709a3 8532 #define LPUART_BAUD_SBNS_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 8533 #define LPUART_BAUD_SBNS_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 8534 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
AnnaBridge 189:f392fc9709a3 8535 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 8536 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8537 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
AnnaBridge 189:f392fc9709a3 8538 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 8539 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 8540 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
AnnaBridge 189:f392fc9709a3 8541 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 8542 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8543 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
AnnaBridge 189:f392fc9709a3 8544 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 8545 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 8546 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
AnnaBridge 189:f392fc9709a3 8547 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 8548 #define LPUART_BAUD_MATCFG_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 8549 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
AnnaBridge 189:f392fc9709a3 8550 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 8551 #define LPUART_BAUD_RDMAE_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 8552 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
AnnaBridge 189:f392fc9709a3 8553 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 8554 #define LPUART_BAUD_TDMAE_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 8555 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
AnnaBridge 189:f392fc9709a3 8556 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
AnnaBridge 189:f392fc9709a3 8557 #define LPUART_BAUD_OSR_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8558 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
AnnaBridge 189:f392fc9709a3 8559 #define LPUART_BAUD_M10_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 8560 #define LPUART_BAUD_M10_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 8561 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
AnnaBridge 189:f392fc9709a3 8562 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 8563 #define LPUART_BAUD_MAEN2_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 8564 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
AnnaBridge 189:f392fc9709a3 8565 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 8566 #define LPUART_BAUD_MAEN1_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 8567 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
AnnaBridge 189:f392fc9709a3 8568
AnnaBridge 189:f392fc9709a3 8569 /*! @name STAT - LPUART Status Register */
AnnaBridge 189:f392fc9709a3 8570 #define LPUART_STAT_MA2F_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 8571 #define LPUART_STAT_MA2F_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8572 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
AnnaBridge 189:f392fc9709a3 8573 #define LPUART_STAT_MA1F_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 8574 #define LPUART_STAT_MA1F_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 8575 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
AnnaBridge 189:f392fc9709a3 8576 #define LPUART_STAT_PF_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 8577 #define LPUART_STAT_PF_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8578 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
AnnaBridge 189:f392fc9709a3 8579 #define LPUART_STAT_FE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 8580 #define LPUART_STAT_FE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 8581 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
AnnaBridge 189:f392fc9709a3 8582 #define LPUART_STAT_NF_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 8583 #define LPUART_STAT_NF_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 8584 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
AnnaBridge 189:f392fc9709a3 8585 #define LPUART_STAT_OR_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 8586 #define LPUART_STAT_OR_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 8587 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
AnnaBridge 189:f392fc9709a3 8588 #define LPUART_STAT_IDLE_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 8589 #define LPUART_STAT_IDLE_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 8590 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
AnnaBridge 189:f392fc9709a3 8591 #define LPUART_STAT_RDRF_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 8592 #define LPUART_STAT_RDRF_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 8593 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
AnnaBridge 189:f392fc9709a3 8594 #define LPUART_STAT_TC_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 8595 #define LPUART_STAT_TC_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 8596 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
AnnaBridge 189:f392fc9709a3 8597 #define LPUART_STAT_TDRE_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 8598 #define LPUART_STAT_TDRE_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 8599 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
AnnaBridge 189:f392fc9709a3 8600 #define LPUART_STAT_RAF_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 8601 #define LPUART_STAT_RAF_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8602 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
AnnaBridge 189:f392fc9709a3 8603 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 8604 #define LPUART_STAT_LBKDE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 8605 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
AnnaBridge 189:f392fc9709a3 8606 #define LPUART_STAT_BRK13_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 8607 #define LPUART_STAT_BRK13_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8608 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
AnnaBridge 189:f392fc9709a3 8609 #define LPUART_STAT_RWUID_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 8610 #define LPUART_STAT_RWUID_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 8611 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
AnnaBridge 189:f392fc9709a3 8612 #define LPUART_STAT_RXINV_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 8613 #define LPUART_STAT_RXINV_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 8614 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
AnnaBridge 189:f392fc9709a3 8615 #define LPUART_STAT_MSBF_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 8616 #define LPUART_STAT_MSBF_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 8617 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
AnnaBridge 189:f392fc9709a3 8618 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 8619 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 8620 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
AnnaBridge 189:f392fc9709a3 8621 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 8622 #define LPUART_STAT_LBKDIF_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 8623 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
AnnaBridge 189:f392fc9709a3 8624
AnnaBridge 189:f392fc9709a3 8625 /*! @name CTRL - LPUART Control Register */
AnnaBridge 189:f392fc9709a3 8626 #define LPUART_CTRL_PT_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8627 #define LPUART_CTRL_PT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8628 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
AnnaBridge 189:f392fc9709a3 8629 #define LPUART_CTRL_PE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 8630 #define LPUART_CTRL_PE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 8631 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
AnnaBridge 189:f392fc9709a3 8632 #define LPUART_CTRL_ILT_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 8633 #define LPUART_CTRL_ILT_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8634 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
AnnaBridge 189:f392fc9709a3 8635 #define LPUART_CTRL_WAKE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 8636 #define LPUART_CTRL_WAKE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8637 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
AnnaBridge 189:f392fc9709a3 8638 #define LPUART_CTRL_M_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 8639 #define LPUART_CTRL_M_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8640 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
AnnaBridge 189:f392fc9709a3 8641 #define LPUART_CTRL_RSRC_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 8642 #define LPUART_CTRL_RSRC_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8643 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
AnnaBridge 189:f392fc9709a3 8644 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 8645 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 8646 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
AnnaBridge 189:f392fc9709a3 8647 #define LPUART_CTRL_LOOPS_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8648 #define LPUART_CTRL_LOOPS_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8649 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
AnnaBridge 189:f392fc9709a3 8650 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
AnnaBridge 189:f392fc9709a3 8651 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 8652 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
AnnaBridge 189:f392fc9709a3 8653 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 8654 #define LPUART_CTRL_MA2IE_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8655 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
AnnaBridge 189:f392fc9709a3 8656 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 8657 #define LPUART_CTRL_MA1IE_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 8658 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
AnnaBridge 189:f392fc9709a3 8659 #define LPUART_CTRL_SBK_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 8660 #define LPUART_CTRL_SBK_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8661 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
AnnaBridge 189:f392fc9709a3 8662 #define LPUART_CTRL_RWU_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 8663 #define LPUART_CTRL_RWU_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 8664 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
AnnaBridge 189:f392fc9709a3 8665 #define LPUART_CTRL_RE_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 8666 #define LPUART_CTRL_RE_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 8667 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
AnnaBridge 189:f392fc9709a3 8668 #define LPUART_CTRL_TE_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 8669 #define LPUART_CTRL_TE_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 8670 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
AnnaBridge 189:f392fc9709a3 8671 #define LPUART_CTRL_ILIE_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 8672 #define LPUART_CTRL_ILIE_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 8673 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
AnnaBridge 189:f392fc9709a3 8674 #define LPUART_CTRL_RIE_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 8675 #define LPUART_CTRL_RIE_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 8676 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
AnnaBridge 189:f392fc9709a3 8677 #define LPUART_CTRL_TCIE_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 8678 #define LPUART_CTRL_TCIE_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 8679 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
AnnaBridge 189:f392fc9709a3 8680 #define LPUART_CTRL_TIE_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 8681 #define LPUART_CTRL_TIE_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 8682 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
AnnaBridge 189:f392fc9709a3 8683 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 8684 #define LPUART_CTRL_PEIE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8685 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
AnnaBridge 189:f392fc9709a3 8686 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 8687 #define LPUART_CTRL_FEIE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 8688 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
AnnaBridge 189:f392fc9709a3 8689 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 8690 #define LPUART_CTRL_NEIE_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 8691 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
AnnaBridge 189:f392fc9709a3 8692 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 8693 #define LPUART_CTRL_ORIE_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 8694 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
AnnaBridge 189:f392fc9709a3 8695 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 8696 #define LPUART_CTRL_TXINV_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 8697 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
AnnaBridge 189:f392fc9709a3 8698 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 8699 #define LPUART_CTRL_TXDIR_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 8700 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
AnnaBridge 189:f392fc9709a3 8701 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 8702 #define LPUART_CTRL_R9T8_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 8703 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
AnnaBridge 189:f392fc9709a3 8704 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 8705 #define LPUART_CTRL_R8T9_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 8706 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
AnnaBridge 189:f392fc9709a3 8707
AnnaBridge 189:f392fc9709a3 8708 /*! @name DATA - LPUART Data Register */
AnnaBridge 189:f392fc9709a3 8709 #define LPUART_DATA_R0T0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8710 #define LPUART_DATA_R0T0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8711 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
AnnaBridge 189:f392fc9709a3 8712 #define LPUART_DATA_R1T1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 8713 #define LPUART_DATA_R1T1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 8714 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
AnnaBridge 189:f392fc9709a3 8715 #define LPUART_DATA_R2T2_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 8716 #define LPUART_DATA_R2T2_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8717 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
AnnaBridge 189:f392fc9709a3 8718 #define LPUART_DATA_R3T3_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 8719 #define LPUART_DATA_R3T3_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8720 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
AnnaBridge 189:f392fc9709a3 8721 #define LPUART_DATA_R4T4_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 8722 #define LPUART_DATA_R4T4_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8723 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
AnnaBridge 189:f392fc9709a3 8724 #define LPUART_DATA_R5T5_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 8725 #define LPUART_DATA_R5T5_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8726 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
AnnaBridge 189:f392fc9709a3 8727 #define LPUART_DATA_R6T6_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 8728 #define LPUART_DATA_R6T6_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 8729 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
AnnaBridge 189:f392fc9709a3 8730 #define LPUART_DATA_R7T7_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8731 #define LPUART_DATA_R7T7_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8732 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
AnnaBridge 189:f392fc9709a3 8733 #define LPUART_DATA_R8T8_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 8734 #define LPUART_DATA_R8T8_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 8735 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
AnnaBridge 189:f392fc9709a3 8736 #define LPUART_DATA_R9T9_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 8737 #define LPUART_DATA_R9T9_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 8738 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
AnnaBridge 189:f392fc9709a3 8739 #define LPUART_DATA_IDLINE_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 8740 #define LPUART_DATA_IDLINE_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 8741 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
AnnaBridge 189:f392fc9709a3 8742 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 8743 #define LPUART_DATA_RXEMPT_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 8744 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
AnnaBridge 189:f392fc9709a3 8745 #define LPUART_DATA_FRETSC_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 8746 #define LPUART_DATA_FRETSC_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 8747 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
AnnaBridge 189:f392fc9709a3 8748 #define LPUART_DATA_PARITYE_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 8749 #define LPUART_DATA_PARITYE_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8750 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
AnnaBridge 189:f392fc9709a3 8751 #define LPUART_DATA_NOISY_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 8752 #define LPUART_DATA_NOISY_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 8753 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
AnnaBridge 189:f392fc9709a3 8754
AnnaBridge 189:f392fc9709a3 8755 /*! @name MATCH - LPUART Match Address Register */
AnnaBridge 189:f392fc9709a3 8756 #define LPUART_MATCH_MA1_MASK (0x3FFU)
AnnaBridge 189:f392fc9709a3 8757 #define LPUART_MATCH_MA1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8758 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
AnnaBridge 189:f392fc9709a3 8759 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
AnnaBridge 189:f392fc9709a3 8760 #define LPUART_MATCH_MA2_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8761 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
AnnaBridge 189:f392fc9709a3 8762
AnnaBridge 189:f392fc9709a3 8763 /*! @name MODIR - LPUART Modem IrDA Register */
AnnaBridge 189:f392fc9709a3 8764 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8765 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8766 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
AnnaBridge 189:f392fc9709a3 8767 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 8768 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 8769 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
AnnaBridge 189:f392fc9709a3 8770 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 8771 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 8772 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
AnnaBridge 189:f392fc9709a3 8773 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 8774 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8775 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
AnnaBridge 189:f392fc9709a3 8776 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 8777 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8778 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
AnnaBridge 189:f392fc9709a3 8779 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 8780 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 8781 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
AnnaBridge 189:f392fc9709a3 8782 #define LPUART_MODIR_RTSWATER_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 8783 #define LPUART_MODIR_RTSWATER_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 8784 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
AnnaBridge 189:f392fc9709a3 8785 #define LPUART_MODIR_TNP_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 8786 #define LPUART_MODIR_TNP_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8787 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
AnnaBridge 189:f392fc9709a3 8788 #define LPUART_MODIR_IREN_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 8789 #define LPUART_MODIR_IREN_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 8790 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
AnnaBridge 189:f392fc9709a3 8791
AnnaBridge 189:f392fc9709a3 8792 /*! @name FIFO - LPUART FIFO Register */
AnnaBridge 189:f392fc9709a3 8793 #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 8794 #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8795 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
AnnaBridge 189:f392fc9709a3 8796 #define LPUART_FIFO_RXFE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 8797 #define LPUART_FIFO_RXFE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 8798 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
AnnaBridge 189:f392fc9709a3 8799 #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
AnnaBridge 189:f392fc9709a3 8800 #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 8801 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
AnnaBridge 189:f392fc9709a3 8802 #define LPUART_FIFO_TXFE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 8803 #define LPUART_FIFO_TXFE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 8804 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
AnnaBridge 189:f392fc9709a3 8805 #define LPUART_FIFO_RXUFE_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 8806 #define LPUART_FIFO_RXUFE_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 8807 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
AnnaBridge 189:f392fc9709a3 8808 #define LPUART_FIFO_TXOFE_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 8809 #define LPUART_FIFO_TXOFE_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 8810 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
AnnaBridge 189:f392fc9709a3 8811 #define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
AnnaBridge 189:f392fc9709a3 8812 #define LPUART_FIFO_RXIDEN_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 8813 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
AnnaBridge 189:f392fc9709a3 8814 #define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 8815 #define LPUART_FIFO_RXFLUSH_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 8816 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
AnnaBridge 189:f392fc9709a3 8817 #define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 8818 #define LPUART_FIFO_TXFLUSH_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 8819 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
AnnaBridge 189:f392fc9709a3 8820 #define LPUART_FIFO_RXUF_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 8821 #define LPUART_FIFO_RXUF_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8822 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
AnnaBridge 189:f392fc9709a3 8823 #define LPUART_FIFO_TXOF_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 8824 #define LPUART_FIFO_TXOF_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 8825 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
AnnaBridge 189:f392fc9709a3 8826 #define LPUART_FIFO_RXEMPT_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 8827 #define LPUART_FIFO_RXEMPT_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 8828 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
AnnaBridge 189:f392fc9709a3 8829 #define LPUART_FIFO_TXEMPT_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 8830 #define LPUART_FIFO_TXEMPT_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 8831 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
AnnaBridge 189:f392fc9709a3 8832
AnnaBridge 189:f392fc9709a3 8833 /*! @name WATER - LPUART Watermark Register */
AnnaBridge 189:f392fc9709a3 8834 #define LPUART_WATER_TXWATER_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 8835 #define LPUART_WATER_TXWATER_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8836 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
AnnaBridge 189:f392fc9709a3 8837 #define LPUART_WATER_TXCOUNT_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 8838 #define LPUART_WATER_TXCOUNT_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 8839 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
AnnaBridge 189:f392fc9709a3 8840 #define LPUART_WATER_RXWATER_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 8841 #define LPUART_WATER_RXWATER_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 8842 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
AnnaBridge 189:f392fc9709a3 8843 #define LPUART_WATER_RXCOUNT_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 8844 #define LPUART_WATER_RXCOUNT_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 8845 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
AnnaBridge 189:f392fc9709a3 8846
AnnaBridge 189:f392fc9709a3 8847
AnnaBridge 189:f392fc9709a3 8848 /*!
AnnaBridge 189:f392fc9709a3 8849 * @}
AnnaBridge 189:f392fc9709a3 8850 */ /* end of group LPUART_Register_Masks */
AnnaBridge 189:f392fc9709a3 8851
AnnaBridge 189:f392fc9709a3 8852
AnnaBridge 189:f392fc9709a3 8853 /* LPUART - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 8854 /** Peripheral LPUART0 base address */
AnnaBridge 189:f392fc9709a3 8855 #define LPUART0_BASE (0x400C4000u)
AnnaBridge 189:f392fc9709a3 8856 /** Peripheral LPUART0 base pointer */
AnnaBridge 189:f392fc9709a3 8857 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
AnnaBridge 189:f392fc9709a3 8858 /** Peripheral LPUART1 base address */
AnnaBridge 189:f392fc9709a3 8859 #define LPUART1_BASE (0x400C5000u)
AnnaBridge 189:f392fc9709a3 8860 /** Peripheral LPUART1 base pointer */
AnnaBridge 189:f392fc9709a3 8861 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
AnnaBridge 189:f392fc9709a3 8862 /** Peripheral LPUART2 base address */
AnnaBridge 189:f392fc9709a3 8863 #define LPUART2_BASE (0x400C6000u)
AnnaBridge 189:f392fc9709a3 8864 /** Peripheral LPUART2 base pointer */
AnnaBridge 189:f392fc9709a3 8865 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
AnnaBridge 189:f392fc9709a3 8866 /** Peripheral LPUART3 base address */
AnnaBridge 189:f392fc9709a3 8867 #define LPUART3_BASE (0x400C7000u)
AnnaBridge 189:f392fc9709a3 8868 /** Peripheral LPUART3 base pointer */
AnnaBridge 189:f392fc9709a3 8869 #define LPUART3 ((LPUART_Type *)LPUART3_BASE)
AnnaBridge 189:f392fc9709a3 8870 /** Peripheral LPUART4 base address */
AnnaBridge 189:f392fc9709a3 8871 #define LPUART4_BASE (0x400D6000u)
AnnaBridge 189:f392fc9709a3 8872 /** Peripheral LPUART4 base pointer */
AnnaBridge 189:f392fc9709a3 8873 #define LPUART4 ((LPUART_Type *)LPUART4_BASE)
AnnaBridge 189:f392fc9709a3 8874 /** Array initializer of LPUART peripheral base addresses */
AnnaBridge 189:f392fc9709a3 8875 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE }
AnnaBridge 189:f392fc9709a3 8876 /** Array initializer of LPUART peripheral base pointers */
AnnaBridge 189:f392fc9709a3 8877 #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4 }
AnnaBridge 189:f392fc9709a3 8878 /** Interrupt vectors for the LPUART peripheral type */
AnnaBridge 189:f392fc9709a3 8879 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn }
AnnaBridge 189:f392fc9709a3 8880 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn }
AnnaBridge 189:f392fc9709a3 8881
AnnaBridge 189:f392fc9709a3 8882 /*!
AnnaBridge 189:f392fc9709a3 8883 * @}
AnnaBridge 189:f392fc9709a3 8884 */ /* end of group LPUART_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 8885
AnnaBridge 189:f392fc9709a3 8886
AnnaBridge 189:f392fc9709a3 8887 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8888 -- LTC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8889 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8890
AnnaBridge 189:f392fc9709a3 8891 /*!
AnnaBridge 189:f392fc9709a3 8892 * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 8893 * @{
AnnaBridge 189:f392fc9709a3 8894 */
AnnaBridge 189:f392fc9709a3 8895
AnnaBridge 189:f392fc9709a3 8896 /** LTC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 8897 typedef struct {
AnnaBridge 189:f392fc9709a3 8898 union { /* offset: 0x0 */
AnnaBridge 189:f392fc9709a3 8899 __IO uint32_t MD; /**< LTC Mode Register (non-PKHA/non-RNG use), offset: 0x0 */
AnnaBridge 189:f392fc9709a3 8900 __IO uint32_t MDPK; /**< LTC Mode Register (PublicKey), offset: 0x0 */
AnnaBridge 189:f392fc9709a3 8901 };
AnnaBridge 189:f392fc9709a3 8902 uint8_t RESERVED_0[4];
AnnaBridge 189:f392fc9709a3 8903 __IO uint32_t KS; /**< LTC Key Size Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 8904 uint8_t RESERVED_1[4];
AnnaBridge 189:f392fc9709a3 8905 __IO uint32_t DS; /**< LTC Data Size Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 8906 uint8_t RESERVED_2[4];
AnnaBridge 189:f392fc9709a3 8907 __IO uint32_t ICVS; /**< LTC ICV Size Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 8908 uint8_t RESERVED_3[20];
AnnaBridge 189:f392fc9709a3 8909 __IO uint32_t COM; /**< LTC Command Register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 8910 __IO uint32_t CTL; /**< LTC Control Register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 8911 uint8_t RESERVED_4[8];
AnnaBridge 189:f392fc9709a3 8912 __IO uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 8913 uint8_t RESERVED_5[4];
AnnaBridge 189:f392fc9709a3 8914 __IO uint32_t STA; /**< LTC Status Register, offset: 0x48 */
AnnaBridge 189:f392fc9709a3 8915 __I uint32_t ESTA; /**< LTC Error Status Register, offset: 0x4C */
AnnaBridge 189:f392fc9709a3 8916 uint8_t RESERVED_6[8];
AnnaBridge 189:f392fc9709a3 8917 __IO uint32_t AADSZ; /**< LTC AAD Size Register, offset: 0x58 */
AnnaBridge 189:f392fc9709a3 8918 uint8_t RESERVED_7[4];
AnnaBridge 189:f392fc9709a3 8919 __IO uint32_t IVSZ; /**< LTC IV Size Register, offset: 0x60 */
AnnaBridge 189:f392fc9709a3 8920 uint8_t RESERVED_8[4];
AnnaBridge 189:f392fc9709a3 8921 __O uint32_t DPAMS; /**< LTC DPA Mask Seed Register, offset: 0x68 */
AnnaBridge 189:f392fc9709a3 8922 uint8_t RESERVED_9[20];
AnnaBridge 189:f392fc9709a3 8923 __IO uint32_t PKASZ; /**< LTC PKHA A Size Register, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 8924 uint8_t RESERVED_10[4];
AnnaBridge 189:f392fc9709a3 8925 __IO uint32_t PKBSZ; /**< LTC PKHA B Size Register, offset: 0x88 */
AnnaBridge 189:f392fc9709a3 8926 uint8_t RESERVED_11[4];
AnnaBridge 189:f392fc9709a3 8927 __IO uint32_t PKNSZ; /**< LTC PKHA N Size Register, offset: 0x90 */
AnnaBridge 189:f392fc9709a3 8928 uint8_t RESERVED_12[4];
AnnaBridge 189:f392fc9709a3 8929 __IO uint32_t PKESZ; /**< LTC PKHA E Size Register, offset: 0x98 */
AnnaBridge 189:f392fc9709a3 8930 uint8_t RESERVED_13[100];
AnnaBridge 189:f392fc9709a3 8931 __IO uint32_t CTX[16]; /**< LTC Context Register, array offset: 0x100, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8932 uint8_t RESERVED_14[192];
AnnaBridge 189:f392fc9709a3 8933 __IO uint32_t KEY[8]; /**< LTC Key Registers, array offset: 0x200, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8934 uint8_t RESERVED_15[720];
AnnaBridge 189:f392fc9709a3 8935 __I uint32_t VID1; /**< LTC Version ID Register, offset: 0x4F0 */
AnnaBridge 189:f392fc9709a3 8936 uint8_t RESERVED_16[4];
AnnaBridge 189:f392fc9709a3 8937 __I uint32_t CHAVID; /**< LTC CHA Version ID Register, offset: 0x4F8 */
AnnaBridge 189:f392fc9709a3 8938 uint8_t RESERVED_17[708];
AnnaBridge 189:f392fc9709a3 8939 __I uint32_t FIFOSTA; /**< LTC FIFO Status Register, offset: 0x7C0 */
AnnaBridge 189:f392fc9709a3 8940 uint8_t RESERVED_18[28];
AnnaBridge 189:f392fc9709a3 8941 __O uint32_t IFIFO; /**< LTC Input Data FIFO, offset: 0x7E0 */
AnnaBridge 189:f392fc9709a3 8942 uint8_t RESERVED_19[12];
AnnaBridge 189:f392fc9709a3 8943 __I uint32_t OFIFO; /**< LTC Output Data FIFO, offset: 0x7F0 */
AnnaBridge 189:f392fc9709a3 8944 uint8_t RESERVED_20[12];
AnnaBridge 189:f392fc9709a3 8945 union { /* offset: 0x800 */
AnnaBridge 189:f392fc9709a3 8946 __IO uint32_t PKA[64]; /**< LTC PKHA A 0 Register..LTC PKHA A 63 Register, array offset: 0x800, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8947 struct { /* offset: 0x800 */
AnnaBridge 189:f392fc9709a3 8948 __IO uint32_t PKA0[16]; /**< LTC PKHA A0 0 Register..LTC PKHA A0 15 Register, array offset: 0x800, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8949 __IO uint32_t PKA1[16]; /**< LTC PKHA A1 0 Register..LTC PKHA A1 15 Register, array offset: 0x840, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8950 __IO uint32_t PKA2[16]; /**< LTC PKHA A2 0 Register..LTC PKHA A2 15 Register, array offset: 0x880, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8951 __IO uint32_t PKA3[16]; /**< LTC PKHA A3 0 Register..LTC PKHA A3 15 Register, array offset: 0x8C0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8952 } PKA_SHORT;
AnnaBridge 189:f392fc9709a3 8953 };
AnnaBridge 189:f392fc9709a3 8954 uint8_t RESERVED_21[256];
AnnaBridge 189:f392fc9709a3 8955 union { /* offset: 0xA00 */
AnnaBridge 189:f392fc9709a3 8956 __IO uint32_t PKB[64]; /**< LTC PKHA B 0 Register..LTC PKHA B 63 Register, array offset: 0xA00, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8957 struct { /* offset: 0xA00 */
AnnaBridge 189:f392fc9709a3 8958 __IO uint32_t PKB0[16]; /**< LTC PKHA B0 0 Register..LTC PKHA B0 15 Register, array offset: 0xA00, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8959 __IO uint32_t PKB1[16]; /**< LTC PKHA B1 0 Register..LTC PKHA B1 15 Register, array offset: 0xA40, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8960 __IO uint32_t PKB2[16]; /**< LTC PKHA B2 0 Register..LTC PKHA B2 15 Register, array offset: 0xA80, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8961 __IO uint32_t PKB3[16]; /**< LTC PKHA B3 0 Register..LTC PKHA B3 15 Register, array offset: 0xAC0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8962 } PKB_SHORT;
AnnaBridge 189:f392fc9709a3 8963 };
AnnaBridge 189:f392fc9709a3 8964 uint8_t RESERVED_22[256];
AnnaBridge 189:f392fc9709a3 8965 union { /* offset: 0xC00 */
AnnaBridge 189:f392fc9709a3 8966 __IO uint32_t PKN[64]; /**< LTC PKHA N 0 Register..LTC PKHA N 63 Register, array offset: 0xC00, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8967 struct { /* offset: 0xC00 */
AnnaBridge 189:f392fc9709a3 8968 __IO uint32_t PKN0[16]; /**< LTC PKHA N0 0 Register..LTC PKHA N0 15 Register, array offset: 0xC00, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8969 __IO uint32_t PKN1[16]; /**< LTC PKHA N1 0 Register..LTC PKHA N1 15 Register, array offset: 0xC40, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8970 __IO uint32_t PKN2[16]; /**< LTC PKHA N2 0 Register..LTC PKHA N2 15 Register, array offset: 0xC80, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8971 __IO uint32_t PKN3[16]; /**< LTC PKHA N3 0 Register..LTC PKHA N3 15 Register, array offset: 0xCC0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8972 } PKN_SHORT;
AnnaBridge 189:f392fc9709a3 8973 };
AnnaBridge 189:f392fc9709a3 8974 uint8_t RESERVED_23[256];
AnnaBridge 189:f392fc9709a3 8975 union { /* offset: 0xE00 */
AnnaBridge 189:f392fc9709a3 8976 __IO uint32_t PKE[64]; /**< LTC PKHA E 0 Register..LTC PKHA E 63 Register, array offset: 0xE00, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8977 struct { /* offset: 0xE00 */
AnnaBridge 189:f392fc9709a3 8978 __IO uint32_t PKE0[16]; /**< LTC PKHA E0 0 Register..LTC PKHA E0 15 Register, array offset: 0xE00, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8979 __IO uint32_t PKE1[16]; /**< LTC PKHA E1 0 Register..LTC PKHA E1 15 Register, array offset: 0xE40, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8980 __IO uint32_t PKE2[16]; /**< LTC PKHA E2 0 Register..LTC PKHA E2 15 Register, array offset: 0xE80, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8981 __IO uint32_t PKE3[16]; /**< LTC PKHA E3 0 Register..LTC PKHA E3 15 Register, array offset: 0xEC0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 8982 } PKE_SHORT;
AnnaBridge 189:f392fc9709a3 8983 };
AnnaBridge 189:f392fc9709a3 8984 } LTC_Type;
AnnaBridge 189:f392fc9709a3 8985
AnnaBridge 189:f392fc9709a3 8986 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 8987 -- LTC Register Masks
AnnaBridge 189:f392fc9709a3 8988 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 8989
AnnaBridge 189:f392fc9709a3 8990 /*!
AnnaBridge 189:f392fc9709a3 8991 * @addtogroup LTC_Register_Masks LTC Register Masks
AnnaBridge 189:f392fc9709a3 8992 * @{
AnnaBridge 189:f392fc9709a3 8993 */
AnnaBridge 189:f392fc9709a3 8994
AnnaBridge 189:f392fc9709a3 8995 /*! @name MD - LTC Mode Register (non-PKHA/non-RNG use) */
AnnaBridge 189:f392fc9709a3 8996 #define LTC_MD_ENC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 8997 #define LTC_MD_ENC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 8998 #define LTC_MD_ENC(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK)
AnnaBridge 189:f392fc9709a3 8999 #define LTC_MD_ICV_TEST_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9000 #define LTC_MD_ICV_TEST_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9001 #define LTC_MD_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
AnnaBridge 189:f392fc9709a3 9002 #define LTC_MD_AS_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 9003 #define LTC_MD_AS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9004 #define LTC_MD_AS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK)
AnnaBridge 189:f392fc9709a3 9005 #define LTC_MD_AAI_MASK (0x1FF0U)
AnnaBridge 189:f392fc9709a3 9006 #define LTC_MD_AAI_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9007 #define LTC_MD_AAI(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK)
AnnaBridge 189:f392fc9709a3 9008 #define LTC_MD_ALG_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 9009 #define LTC_MD_ALG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9010 #define LTC_MD_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK)
AnnaBridge 189:f392fc9709a3 9011
AnnaBridge 189:f392fc9709a3 9012 /*! @name MDPK - LTC Mode Register (PublicKey) */
AnnaBridge 189:f392fc9709a3 9013 #define LTC_MDPK_PKHA_MODE_LS_MASK (0xFFFU)
AnnaBridge 189:f392fc9709a3 9014 #define LTC_MDPK_PKHA_MODE_LS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9015 #define LTC_MDPK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_LS_SHIFT)) & LTC_MDPK_PKHA_MODE_LS_MASK)
AnnaBridge 189:f392fc9709a3 9016 #define LTC_MDPK_PKHA_MODE_MS_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 9017 #define LTC_MDPK_PKHA_MODE_MS_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9018 #define LTC_MDPK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_MS_SHIFT)) & LTC_MDPK_PKHA_MODE_MS_MASK)
AnnaBridge 189:f392fc9709a3 9019 #define LTC_MDPK_ALG_MASK (0xF00000U)
AnnaBridge 189:f392fc9709a3 9020 #define LTC_MDPK_ALG_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 9021 #define LTC_MDPK_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_ALG_SHIFT)) & LTC_MDPK_ALG_MASK)
AnnaBridge 189:f392fc9709a3 9022
AnnaBridge 189:f392fc9709a3 9023 /*! @name KS - LTC Key Size Register */
AnnaBridge 189:f392fc9709a3 9024 #define LTC_KS_KS_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 9025 #define LTC_KS_KS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9026 #define LTC_KS_KS(x) (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK)
AnnaBridge 189:f392fc9709a3 9027
AnnaBridge 189:f392fc9709a3 9028 /*! @name DS - LTC Data Size Register */
AnnaBridge 189:f392fc9709a3 9029 #define LTC_DS_DS_MASK (0xFFFU)
AnnaBridge 189:f392fc9709a3 9030 #define LTC_DS_DS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9031 #define LTC_DS_DS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK)
AnnaBridge 189:f392fc9709a3 9032
AnnaBridge 189:f392fc9709a3 9033 /*! @name ICVS - LTC ICV Size Register */
AnnaBridge 189:f392fc9709a3 9034 #define LTC_ICVS_ICVS_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 9035 #define LTC_ICVS_ICVS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9036 #define LTC_ICVS_ICVS(x) (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK)
AnnaBridge 189:f392fc9709a3 9037
AnnaBridge 189:f392fc9709a3 9038 /*! @name COM - LTC Command Register */
AnnaBridge 189:f392fc9709a3 9039 #define LTC_COM_ALL_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9040 #define LTC_COM_ALL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9041 #define LTC_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK)
AnnaBridge 189:f392fc9709a3 9042 #define LTC_COM_AES_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9043 #define LTC_COM_AES_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9044 #define LTC_COM_AES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK)
AnnaBridge 189:f392fc9709a3 9045 #define LTC_COM_DES_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 9046 #define LTC_COM_DES_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9047 #define LTC_COM_DES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_DES_SHIFT)) & LTC_COM_DES_MASK)
AnnaBridge 189:f392fc9709a3 9048 #define LTC_COM_PK_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9049 #define LTC_COM_PK_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9050 #define LTC_COM_PK(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_PK_SHIFT)) & LTC_COM_PK_MASK)
AnnaBridge 189:f392fc9709a3 9051
AnnaBridge 189:f392fc9709a3 9052 /*! @name CTL - LTC Control Register */
AnnaBridge 189:f392fc9709a3 9053 #define LTC_CTL_IM_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9054 #define LTC_CTL_IM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9055 #define LTC_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK)
AnnaBridge 189:f392fc9709a3 9056 #define LTC_CTL_PDE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 9057 #define LTC_CTL_PDE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9058 #define LTC_CTL_PDE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_PDE_SHIFT)) & LTC_CTL_PDE_MASK)
AnnaBridge 189:f392fc9709a3 9059 #define LTC_CTL_IFE_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 9060 #define LTC_CTL_IFE_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9061 #define LTC_CTL_IFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK)
AnnaBridge 189:f392fc9709a3 9062 #define LTC_CTL_IFR_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 9063 #define LTC_CTL_IFR_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 9064 #define LTC_CTL_IFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
AnnaBridge 189:f392fc9709a3 9065 #define LTC_CTL_OFE_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 9066 #define LTC_CTL_OFE_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 9067 #define LTC_CTL_OFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK)
AnnaBridge 189:f392fc9709a3 9068 #define LTC_CTL_OFR_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 9069 #define LTC_CTL_OFR_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 9070 #define LTC_CTL_OFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK)
AnnaBridge 189:f392fc9709a3 9071 #define LTC_CTL_IFS_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 9072 #define LTC_CTL_IFS_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9073 #define LTC_CTL_IFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK)
AnnaBridge 189:f392fc9709a3 9074 #define LTC_CTL_OFS_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 9075 #define LTC_CTL_OFS_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 9076 #define LTC_CTL_OFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK)
AnnaBridge 189:f392fc9709a3 9077 #define LTC_CTL_KIS_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 9078 #define LTC_CTL_KIS_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 9079 #define LTC_CTL_KIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK)
AnnaBridge 189:f392fc9709a3 9080 #define LTC_CTL_KOS_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 9081 #define LTC_CTL_KOS_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 9082 #define LTC_CTL_KOS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK)
AnnaBridge 189:f392fc9709a3 9083 #define LTC_CTL_CIS_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 9084 #define LTC_CTL_CIS_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 9085 #define LTC_CTL_CIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK)
AnnaBridge 189:f392fc9709a3 9086 #define LTC_CTL_COS_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 9087 #define LTC_CTL_COS_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 9088 #define LTC_CTL_COS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK)
AnnaBridge 189:f392fc9709a3 9089 #define LTC_CTL_KAL_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9090 #define LTC_CTL_KAL_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9091 #define LTC_CTL_KAL(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK)
AnnaBridge 189:f392fc9709a3 9092
AnnaBridge 189:f392fc9709a3 9093 /*! @name CW - LTC Clear Written Register */
AnnaBridge 189:f392fc9709a3 9094 #define LTC_CW_CM_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9095 #define LTC_CW_CM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9096 #define LTC_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK)
AnnaBridge 189:f392fc9709a3 9097 #define LTC_CW_CDS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 9098 #define LTC_CW_CDS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9099 #define LTC_CW_CDS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK)
AnnaBridge 189:f392fc9709a3 9100 #define LTC_CW_CICV_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 9101 #define LTC_CW_CICV_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 9102 #define LTC_CW_CICV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK)
AnnaBridge 189:f392fc9709a3 9103 #define LTC_CW_CCR_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 9104 #define LTC_CW_CCR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9105 #define LTC_CW_CCR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK)
AnnaBridge 189:f392fc9709a3 9106 #define LTC_CW_CKR_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9107 #define LTC_CW_CKR_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9108 #define LTC_CW_CKR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK)
AnnaBridge 189:f392fc9709a3 9109 #define LTC_CW_CPKA_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 9110 #define LTC_CW_CPKA_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 9111 #define LTC_CW_CPKA(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKA_SHIFT)) & LTC_CW_CPKA_MASK)
AnnaBridge 189:f392fc9709a3 9112 #define LTC_CW_CPKB_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 9113 #define LTC_CW_CPKB_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 9114 #define LTC_CW_CPKB(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKB_SHIFT)) & LTC_CW_CPKB_MASK)
AnnaBridge 189:f392fc9709a3 9115 #define LTC_CW_CPKN_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 9116 #define LTC_CW_CPKN_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 9117 #define LTC_CW_CPKN(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKN_SHIFT)) & LTC_CW_CPKN_MASK)
AnnaBridge 189:f392fc9709a3 9118 #define LTC_CW_CPKE_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 9119 #define LTC_CW_CPKE_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 9120 #define LTC_CW_CPKE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKE_SHIFT)) & LTC_CW_CPKE_MASK)
AnnaBridge 189:f392fc9709a3 9121 #define LTC_CW_COF_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 9122 #define LTC_CW_COF_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 9123 #define LTC_CW_COF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK)
AnnaBridge 189:f392fc9709a3 9124 #define LTC_CW_CIF_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9125 #define LTC_CW_CIF_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9126 #define LTC_CW_CIF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK)
AnnaBridge 189:f392fc9709a3 9127
AnnaBridge 189:f392fc9709a3 9128 /*! @name STA - LTC Status Register */
AnnaBridge 189:f392fc9709a3 9129 #define LTC_STA_AB_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9130 #define LTC_STA_AB_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9131 #define LTC_STA_AB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK)
AnnaBridge 189:f392fc9709a3 9132 #define LTC_STA_DB_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 9133 #define LTC_STA_DB_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9134 #define LTC_STA_DB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DB_SHIFT)) & LTC_STA_DB_MASK)
AnnaBridge 189:f392fc9709a3 9135 #define LTC_STA_PB_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9136 #define LTC_STA_PB_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9137 #define LTC_STA_PB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PB_SHIFT)) & LTC_STA_PB_MASK)
AnnaBridge 189:f392fc9709a3 9138 #define LTC_STA_DI_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 9139 #define LTC_STA_DI_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9140 #define LTC_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK)
AnnaBridge 189:f392fc9709a3 9141 #define LTC_STA_EI_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 9142 #define LTC_STA_EI_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 9143 #define LTC_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK)
AnnaBridge 189:f392fc9709a3 9144 #define LTC_STA_PKP_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 9145 #define LTC_STA_PKP_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 9146 #define LTC_STA_PKP(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKP_SHIFT)) & LTC_STA_PKP_MASK)
AnnaBridge 189:f392fc9709a3 9147 #define LTC_STA_PKO_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 9148 #define LTC_STA_PKO_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 9149 #define LTC_STA_PKO(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKO_SHIFT)) & LTC_STA_PKO_MASK)
AnnaBridge 189:f392fc9709a3 9150 #define LTC_STA_PKZ_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 9151 #define LTC_STA_PKZ_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 9152 #define LTC_STA_PKZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKZ_SHIFT)) & LTC_STA_PKZ_MASK)
AnnaBridge 189:f392fc9709a3 9153
AnnaBridge 189:f392fc9709a3 9154 /*! @name ESTA - LTC Error Status Register */
AnnaBridge 189:f392fc9709a3 9155 #define LTC_ESTA_ERRID1_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 9156 #define LTC_ESTA_ERRID1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9157 #define LTC_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK)
AnnaBridge 189:f392fc9709a3 9158 #define LTC_ESTA_CL1_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 9159 #define LTC_ESTA_CL1_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9160 #define LTC_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK)
AnnaBridge 189:f392fc9709a3 9161
AnnaBridge 189:f392fc9709a3 9162 /*! @name AADSZ - LTC AAD Size Register */
AnnaBridge 189:f392fc9709a3 9163 #define LTC_AADSZ_AADSZ_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 9164 #define LTC_AADSZ_AADSZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9165 #define LTC_AADSZ_AADSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK)
AnnaBridge 189:f392fc9709a3 9166 #define LTC_AADSZ_AL_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9167 #define LTC_AADSZ_AL_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9168 #define LTC_AADSZ_AL(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK)
AnnaBridge 189:f392fc9709a3 9169
AnnaBridge 189:f392fc9709a3 9170 /*! @name IVSZ - LTC IV Size Register */
AnnaBridge 189:f392fc9709a3 9171 #define LTC_IVSZ_IVSZ_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 9172 #define LTC_IVSZ_IVSZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9173 #define LTC_IVSZ_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IVSZ_SHIFT)) & LTC_IVSZ_IVSZ_MASK)
AnnaBridge 189:f392fc9709a3 9174 #define LTC_IVSZ_IL_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9175 #define LTC_IVSZ_IL_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9176 #define LTC_IVSZ_IL(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IL_SHIFT)) & LTC_IVSZ_IL_MASK)
AnnaBridge 189:f392fc9709a3 9177
AnnaBridge 189:f392fc9709a3 9178 /*! @name DPAMS - LTC DPA Mask Seed Register */
AnnaBridge 189:f392fc9709a3 9179 #define LTC_DPAMS_DPAMS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9180 #define LTC_DPAMS_DPAMS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9181 #define LTC_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DPAMS_DPAMS_SHIFT)) & LTC_DPAMS_DPAMS_MASK)
AnnaBridge 189:f392fc9709a3 9182
AnnaBridge 189:f392fc9709a3 9183 /*! @name PKASZ - LTC PKHA A Size Register */
AnnaBridge 189:f392fc9709a3 9184 #define LTC_PKASZ_PKASZ_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 9185 #define LTC_PKASZ_PKASZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9186 #define LTC_PKASZ_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKASZ_PKASZ_SHIFT)) & LTC_PKASZ_PKASZ_MASK)
AnnaBridge 189:f392fc9709a3 9187
AnnaBridge 189:f392fc9709a3 9188 /*! @name PKBSZ - LTC PKHA B Size Register */
AnnaBridge 189:f392fc9709a3 9189 #define LTC_PKBSZ_PKBSZ_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 9190 #define LTC_PKBSZ_PKBSZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9191 #define LTC_PKBSZ_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKBSZ_PKBSZ_SHIFT)) & LTC_PKBSZ_PKBSZ_MASK)
AnnaBridge 189:f392fc9709a3 9192
AnnaBridge 189:f392fc9709a3 9193 /*! @name PKNSZ - LTC PKHA N Size Register */
AnnaBridge 189:f392fc9709a3 9194 #define LTC_PKNSZ_PKNSZ_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 9195 #define LTC_PKNSZ_PKNSZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9196 #define LTC_PKNSZ_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKNSZ_PKNSZ_SHIFT)) & LTC_PKNSZ_PKNSZ_MASK)
AnnaBridge 189:f392fc9709a3 9197
AnnaBridge 189:f392fc9709a3 9198 /*! @name PKESZ - LTC PKHA E Size Register */
AnnaBridge 189:f392fc9709a3 9199 #define LTC_PKESZ_PKESZ_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 9200 #define LTC_PKESZ_PKESZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9201 #define LTC_PKESZ_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKESZ_PKESZ_SHIFT)) & LTC_PKESZ_PKESZ_MASK)
AnnaBridge 189:f392fc9709a3 9202
AnnaBridge 189:f392fc9709a3 9203 /*! @name CTX - LTC Context Register */
AnnaBridge 189:f392fc9709a3 9204 #define LTC_CTX_CTX_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9205 #define LTC_CTX_CTX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9206 #define LTC_CTX_CTX(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK)
AnnaBridge 189:f392fc9709a3 9207
AnnaBridge 189:f392fc9709a3 9208 /* The count of LTC_CTX */
AnnaBridge 189:f392fc9709a3 9209 #define LTC_CTX_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9210
AnnaBridge 189:f392fc9709a3 9211 /*! @name KEY - LTC Key Registers */
AnnaBridge 189:f392fc9709a3 9212 #define LTC_KEY_KEY_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9213 #define LTC_KEY_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9214 #define LTC_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK)
AnnaBridge 189:f392fc9709a3 9215
AnnaBridge 189:f392fc9709a3 9216 /* The count of LTC_KEY */
AnnaBridge 189:f392fc9709a3 9217 #define LTC_KEY_COUNT (8U)
AnnaBridge 189:f392fc9709a3 9218
AnnaBridge 189:f392fc9709a3 9219 /*! @name VID1 - LTC Version ID Register */
AnnaBridge 189:f392fc9709a3 9220 #define LTC_VID1_MIN_REV_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 9221 #define LTC_VID1_MIN_REV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9222 #define LTC_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK)
AnnaBridge 189:f392fc9709a3 9223 #define LTC_VID1_MAJ_REV_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 9224 #define LTC_VID1_MAJ_REV_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9225 #define LTC_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK)
AnnaBridge 189:f392fc9709a3 9226 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 9227 #define LTC_VID1_IP_ID_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9228 #define LTC_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
AnnaBridge 189:f392fc9709a3 9229
AnnaBridge 189:f392fc9709a3 9230 /*! @name CHAVID - LTC CHA Version ID Register */
AnnaBridge 189:f392fc9709a3 9231 #define LTC_CHAVID_AESREV_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 9232 #define LTC_CHAVID_AESREV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9233 #define LTC_CHAVID_AESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK)
AnnaBridge 189:f392fc9709a3 9234 #define LTC_CHAVID_AESVID_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 9235 #define LTC_CHAVID_AESVID_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9236 #define LTC_CHAVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
AnnaBridge 189:f392fc9709a3 9237 #define LTC_CHAVID_DESREV_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 9238 #define LTC_CHAVID_DESREV_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9239 #define LTC_CHAVID_DESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESREV_SHIFT)) & LTC_CHAVID_DESREV_MASK)
AnnaBridge 189:f392fc9709a3 9240 #define LTC_CHAVID_DESVID_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 9241 #define LTC_CHAVID_DESVID_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 9242 #define LTC_CHAVID_DESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESVID_SHIFT)) & LTC_CHAVID_DESVID_MASK)
AnnaBridge 189:f392fc9709a3 9243 #define LTC_CHAVID_PKHAREV_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 9244 #define LTC_CHAVID_PKHAREV_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9245 #define LTC_CHAVID_PKHAREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAREV_SHIFT)) & LTC_CHAVID_PKHAREV_MASK)
AnnaBridge 189:f392fc9709a3 9246 #define LTC_CHAVID_PKHAVID_MASK (0xF00000U)
AnnaBridge 189:f392fc9709a3 9247 #define LTC_CHAVID_PKHAVID_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 9248 #define LTC_CHAVID_PKHAVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAVID_SHIFT)) & LTC_CHAVID_PKHAVID_MASK)
AnnaBridge 189:f392fc9709a3 9249
AnnaBridge 189:f392fc9709a3 9250 /*! @name FIFOSTA - LTC FIFO Status Register */
AnnaBridge 189:f392fc9709a3 9251 #define LTC_FIFOSTA_IFL_MASK (0x7FU)
AnnaBridge 189:f392fc9709a3 9252 #define LTC_FIFOSTA_IFL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9253 #define LTC_FIFOSTA_IFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK)
AnnaBridge 189:f392fc9709a3 9254 #define LTC_FIFOSTA_IFF_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 9255 #define LTC_FIFOSTA_IFF_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 9256 #define LTC_FIFOSTA_IFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK)
AnnaBridge 189:f392fc9709a3 9257 #define LTC_FIFOSTA_OFL_MASK (0x7F0000U)
AnnaBridge 189:f392fc9709a3 9258 #define LTC_FIFOSTA_OFL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9259 #define LTC_FIFOSTA_OFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK)
AnnaBridge 189:f392fc9709a3 9260 #define LTC_FIFOSTA_OFF_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9261 #define LTC_FIFOSTA_OFF_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9262 #define LTC_FIFOSTA_OFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK)
AnnaBridge 189:f392fc9709a3 9263
AnnaBridge 189:f392fc9709a3 9264 /*! @name IFIFO - LTC Input Data FIFO */
AnnaBridge 189:f392fc9709a3 9265 #define LTC_IFIFO_IFIFO_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9266 #define LTC_IFIFO_IFIFO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9267 #define LTC_IFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK)
AnnaBridge 189:f392fc9709a3 9268
AnnaBridge 189:f392fc9709a3 9269 /*! @name OFIFO - LTC Output Data FIFO */
AnnaBridge 189:f392fc9709a3 9270 #define LTC_OFIFO_OFIFO_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9271 #define LTC_OFIFO_OFIFO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9272 #define LTC_OFIFO_OFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK)
AnnaBridge 189:f392fc9709a3 9273
AnnaBridge 189:f392fc9709a3 9274 /* The count of LTC_PKA */
AnnaBridge 189:f392fc9709a3 9275 #define LTC_PKA_COUNT (64U)
AnnaBridge 189:f392fc9709a3 9276
AnnaBridge 189:f392fc9709a3 9277 /*! @name PKA0 - LTC PKHA A0 0 Register..LTC PKHA A0 15 Register */
AnnaBridge 189:f392fc9709a3 9278 #define LTC_PKA0_PKHA_A0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9279 #define LTC_PKA0_PKHA_A0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9280 #define LTC_PKA0_PKHA_A0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA0_PKHA_A0_SHIFT)) & LTC_PKA0_PKHA_A0_MASK)
AnnaBridge 189:f392fc9709a3 9281
AnnaBridge 189:f392fc9709a3 9282 /* The count of LTC_PKA0 */
AnnaBridge 189:f392fc9709a3 9283 #define LTC_PKA0_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9284
AnnaBridge 189:f392fc9709a3 9285 /*! @name PKA1 - LTC PKHA A1 0 Register..LTC PKHA A1 15 Register */
AnnaBridge 189:f392fc9709a3 9286 #define LTC_PKA1_PKHA_A1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9287 #define LTC_PKA1_PKHA_A1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9288 #define LTC_PKA1_PKHA_A1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA1_PKHA_A1_SHIFT)) & LTC_PKA1_PKHA_A1_MASK)
AnnaBridge 189:f392fc9709a3 9289
AnnaBridge 189:f392fc9709a3 9290 /* The count of LTC_PKA1 */
AnnaBridge 189:f392fc9709a3 9291 #define LTC_PKA1_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9292
AnnaBridge 189:f392fc9709a3 9293 /*! @name PKA2 - LTC PKHA A2 0 Register..LTC PKHA A2 15 Register */
AnnaBridge 189:f392fc9709a3 9294 #define LTC_PKA2_PKHA_A2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9295 #define LTC_PKA2_PKHA_A2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9296 #define LTC_PKA2_PKHA_A2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA2_PKHA_A2_SHIFT)) & LTC_PKA2_PKHA_A2_MASK)
AnnaBridge 189:f392fc9709a3 9297
AnnaBridge 189:f392fc9709a3 9298 /* The count of LTC_PKA2 */
AnnaBridge 189:f392fc9709a3 9299 #define LTC_PKA2_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9300
AnnaBridge 189:f392fc9709a3 9301 /*! @name PKA3 - LTC PKHA A3 0 Register..LTC PKHA A3 15 Register */
AnnaBridge 189:f392fc9709a3 9302 #define LTC_PKA3_PKHA_A3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9303 #define LTC_PKA3_PKHA_A3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9304 #define LTC_PKA3_PKHA_A3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA3_PKHA_A3_SHIFT)) & LTC_PKA3_PKHA_A3_MASK)
AnnaBridge 189:f392fc9709a3 9305
AnnaBridge 189:f392fc9709a3 9306 /* The count of LTC_PKA3 */
AnnaBridge 189:f392fc9709a3 9307 #define LTC_PKA3_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9308
AnnaBridge 189:f392fc9709a3 9309 /* The count of LTC_PKB */
AnnaBridge 189:f392fc9709a3 9310 #define LTC_PKB_COUNT (64U)
AnnaBridge 189:f392fc9709a3 9311
AnnaBridge 189:f392fc9709a3 9312 /*! @name PKB0 - LTC PKHA B0 0 Register..LTC PKHA B0 15 Register */
AnnaBridge 189:f392fc9709a3 9313 #define LTC_PKB0_PKHA_B0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9314 #define LTC_PKB0_PKHA_B0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9315 #define LTC_PKB0_PKHA_B0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB0_PKHA_B0_SHIFT)) & LTC_PKB0_PKHA_B0_MASK)
AnnaBridge 189:f392fc9709a3 9316
AnnaBridge 189:f392fc9709a3 9317 /* The count of LTC_PKB0 */
AnnaBridge 189:f392fc9709a3 9318 #define LTC_PKB0_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9319
AnnaBridge 189:f392fc9709a3 9320 /*! @name PKB1 - LTC PKHA B1 0 Register..LTC PKHA B1 15 Register */
AnnaBridge 189:f392fc9709a3 9321 #define LTC_PKB1_PKHA_B1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9322 #define LTC_PKB1_PKHA_B1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9323 #define LTC_PKB1_PKHA_B1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB1_PKHA_B1_SHIFT)) & LTC_PKB1_PKHA_B1_MASK)
AnnaBridge 189:f392fc9709a3 9324
AnnaBridge 189:f392fc9709a3 9325 /* The count of LTC_PKB1 */
AnnaBridge 189:f392fc9709a3 9326 #define LTC_PKB1_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9327
AnnaBridge 189:f392fc9709a3 9328 /*! @name PKB2 - LTC PKHA B2 0 Register..LTC PKHA B2 15 Register */
AnnaBridge 189:f392fc9709a3 9329 #define LTC_PKB2_PKHA_B2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9330 #define LTC_PKB2_PKHA_B2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9331 #define LTC_PKB2_PKHA_B2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB2_PKHA_B2_SHIFT)) & LTC_PKB2_PKHA_B2_MASK)
AnnaBridge 189:f392fc9709a3 9332
AnnaBridge 189:f392fc9709a3 9333 /* The count of LTC_PKB2 */
AnnaBridge 189:f392fc9709a3 9334 #define LTC_PKB2_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9335
AnnaBridge 189:f392fc9709a3 9336 /*! @name PKB3 - LTC PKHA B3 0 Register..LTC PKHA B3 15 Register */
AnnaBridge 189:f392fc9709a3 9337 #define LTC_PKB3_PKHA_B3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9338 #define LTC_PKB3_PKHA_B3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9339 #define LTC_PKB3_PKHA_B3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB3_PKHA_B3_SHIFT)) & LTC_PKB3_PKHA_B3_MASK)
AnnaBridge 189:f392fc9709a3 9340
AnnaBridge 189:f392fc9709a3 9341 /* The count of LTC_PKB3 */
AnnaBridge 189:f392fc9709a3 9342 #define LTC_PKB3_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9343
AnnaBridge 189:f392fc9709a3 9344 /* The count of LTC_PKN */
AnnaBridge 189:f392fc9709a3 9345 #define LTC_PKN_COUNT (64U)
AnnaBridge 189:f392fc9709a3 9346
AnnaBridge 189:f392fc9709a3 9347 /*! @name PKN0 - LTC PKHA N0 0 Register..LTC PKHA N0 15 Register */
AnnaBridge 189:f392fc9709a3 9348 #define LTC_PKN0_PKHA_N0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9349 #define LTC_PKN0_PKHA_N0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9350 #define LTC_PKN0_PKHA_N0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN0_PKHA_N0_SHIFT)) & LTC_PKN0_PKHA_N0_MASK)
AnnaBridge 189:f392fc9709a3 9351
AnnaBridge 189:f392fc9709a3 9352 /* The count of LTC_PKN0 */
AnnaBridge 189:f392fc9709a3 9353 #define LTC_PKN0_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9354
AnnaBridge 189:f392fc9709a3 9355 /*! @name PKN1 - LTC PKHA N1 0 Register..LTC PKHA N1 15 Register */
AnnaBridge 189:f392fc9709a3 9356 #define LTC_PKN1_PKHA_N1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9357 #define LTC_PKN1_PKHA_N1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9358 #define LTC_PKN1_PKHA_N1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN1_PKHA_N1_SHIFT)) & LTC_PKN1_PKHA_N1_MASK)
AnnaBridge 189:f392fc9709a3 9359
AnnaBridge 189:f392fc9709a3 9360 /* The count of LTC_PKN1 */
AnnaBridge 189:f392fc9709a3 9361 #define LTC_PKN1_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9362
AnnaBridge 189:f392fc9709a3 9363 /*! @name PKN2 - LTC PKHA N2 0 Register..LTC PKHA N2 15 Register */
AnnaBridge 189:f392fc9709a3 9364 #define LTC_PKN2_PKHA_N2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9365 #define LTC_PKN2_PKHA_N2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9366 #define LTC_PKN2_PKHA_N2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN2_PKHA_N2_SHIFT)) & LTC_PKN2_PKHA_N2_MASK)
AnnaBridge 189:f392fc9709a3 9367
AnnaBridge 189:f392fc9709a3 9368 /* The count of LTC_PKN2 */
AnnaBridge 189:f392fc9709a3 9369 #define LTC_PKN2_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9370
AnnaBridge 189:f392fc9709a3 9371 /*! @name PKN3 - LTC PKHA N3 0 Register..LTC PKHA N3 15 Register */
AnnaBridge 189:f392fc9709a3 9372 #define LTC_PKN3_PKHA_N3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9373 #define LTC_PKN3_PKHA_N3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9374 #define LTC_PKN3_PKHA_N3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN3_PKHA_N3_SHIFT)) & LTC_PKN3_PKHA_N3_MASK)
AnnaBridge 189:f392fc9709a3 9375
AnnaBridge 189:f392fc9709a3 9376 /* The count of LTC_PKN3 */
AnnaBridge 189:f392fc9709a3 9377 #define LTC_PKN3_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9378
AnnaBridge 189:f392fc9709a3 9379 /* The count of LTC_PKE */
AnnaBridge 189:f392fc9709a3 9380 #define LTC_PKE_COUNT (64U)
AnnaBridge 189:f392fc9709a3 9381
AnnaBridge 189:f392fc9709a3 9382 /*! @name PKE0 - LTC PKHA E0 0 Register..LTC PKHA E0 15 Register */
AnnaBridge 189:f392fc9709a3 9383 #define LTC_PKE0_PKHA_E0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9384 #define LTC_PKE0_PKHA_E0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9385 #define LTC_PKE0_PKHA_E0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE0_PKHA_E0_SHIFT)) & LTC_PKE0_PKHA_E0_MASK)
AnnaBridge 189:f392fc9709a3 9386
AnnaBridge 189:f392fc9709a3 9387 /* The count of LTC_PKE0 */
AnnaBridge 189:f392fc9709a3 9388 #define LTC_PKE0_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9389
AnnaBridge 189:f392fc9709a3 9390 /*! @name PKE1 - LTC PKHA E1 0 Register..LTC PKHA E1 15 Register */
AnnaBridge 189:f392fc9709a3 9391 #define LTC_PKE1_PKHA_E1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9392 #define LTC_PKE1_PKHA_E1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9393 #define LTC_PKE1_PKHA_E1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE1_PKHA_E1_SHIFT)) & LTC_PKE1_PKHA_E1_MASK)
AnnaBridge 189:f392fc9709a3 9394
AnnaBridge 189:f392fc9709a3 9395 /* The count of LTC_PKE1 */
AnnaBridge 189:f392fc9709a3 9396 #define LTC_PKE1_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9397
AnnaBridge 189:f392fc9709a3 9398 /*! @name PKE2 - LTC PKHA E2 0 Register..LTC PKHA E2 15 Register */
AnnaBridge 189:f392fc9709a3 9399 #define LTC_PKE2_PKHA_E2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9400 #define LTC_PKE2_PKHA_E2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9401 #define LTC_PKE2_PKHA_E2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE2_PKHA_E2_SHIFT)) & LTC_PKE2_PKHA_E2_MASK)
AnnaBridge 189:f392fc9709a3 9402
AnnaBridge 189:f392fc9709a3 9403 /* The count of LTC_PKE2 */
AnnaBridge 189:f392fc9709a3 9404 #define LTC_PKE2_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9405
AnnaBridge 189:f392fc9709a3 9406 /*! @name PKE3 - LTC PKHA E3 0 Register..LTC PKHA E3 15 Register */
AnnaBridge 189:f392fc9709a3 9407 #define LTC_PKE3_PKHA_E3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9408 #define LTC_PKE3_PKHA_E3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9409 #define LTC_PKE3_PKHA_E3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE3_PKHA_E3_SHIFT)) & LTC_PKE3_PKHA_E3_MASK)
AnnaBridge 189:f392fc9709a3 9410
AnnaBridge 189:f392fc9709a3 9411 /* The count of LTC_PKE3 */
AnnaBridge 189:f392fc9709a3 9412 #define LTC_PKE3_COUNT (16U)
AnnaBridge 189:f392fc9709a3 9413
AnnaBridge 189:f392fc9709a3 9414
AnnaBridge 189:f392fc9709a3 9415 /*!
AnnaBridge 189:f392fc9709a3 9416 * @}
AnnaBridge 189:f392fc9709a3 9417 */ /* end of group LTC_Register_Masks */
AnnaBridge 189:f392fc9709a3 9418
AnnaBridge 189:f392fc9709a3 9419
AnnaBridge 189:f392fc9709a3 9420 /* LTC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 9421 /** Peripheral LTC0 base address */
AnnaBridge 189:f392fc9709a3 9422 #define LTC0_BASE (0x400D1000u)
AnnaBridge 189:f392fc9709a3 9423 /** Peripheral LTC0 base pointer */
AnnaBridge 189:f392fc9709a3 9424 #define LTC0 ((LTC_Type *)LTC0_BASE)
AnnaBridge 189:f392fc9709a3 9425 /** Array initializer of LTC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 9426 #define LTC_BASE_ADDRS { LTC0_BASE }
AnnaBridge 189:f392fc9709a3 9427 /** Array initializer of LTC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 9428 #define LTC_BASE_PTRS { LTC0 }
AnnaBridge 189:f392fc9709a3 9429 /** Interrupt vectors for the LTC peripheral type */
AnnaBridge 189:f392fc9709a3 9430 #define LTC_IRQS { LTC0_IRQn }
AnnaBridge 189:f392fc9709a3 9431
AnnaBridge 189:f392fc9709a3 9432 /*!
AnnaBridge 189:f392fc9709a3 9433 * @}
AnnaBridge 189:f392fc9709a3 9434 */ /* end of group LTC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 9435
AnnaBridge 189:f392fc9709a3 9436
AnnaBridge 189:f392fc9709a3 9437 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 9438 -- MCG Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 9439 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 9440
AnnaBridge 189:f392fc9709a3 9441 /*!
AnnaBridge 189:f392fc9709a3 9442 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 9443 * @{
AnnaBridge 189:f392fc9709a3 9444 */
AnnaBridge 189:f392fc9709a3 9445
AnnaBridge 189:f392fc9709a3 9446 /** MCG - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 9447 typedef struct {
AnnaBridge 189:f392fc9709a3 9448 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 9449 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 9450 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 9451 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 9452 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 9453 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 9454 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 189:f392fc9709a3 9455 uint8_t RESERVED_0[1];
AnnaBridge 189:f392fc9709a3 9456 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 9457 uint8_t RESERVED_1[1];
AnnaBridge 189:f392fc9709a3 9458 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 189:f392fc9709a3 9459 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 189:f392fc9709a3 9460 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 9461 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 189:f392fc9709a3 9462 } MCG_Type;
AnnaBridge 189:f392fc9709a3 9463
AnnaBridge 189:f392fc9709a3 9464 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 9465 -- MCG Register Masks
AnnaBridge 189:f392fc9709a3 9466 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 9467
AnnaBridge 189:f392fc9709a3 9468 /*!
AnnaBridge 189:f392fc9709a3 9469 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 189:f392fc9709a3 9470 * @{
AnnaBridge 189:f392fc9709a3 9471 */
AnnaBridge 189:f392fc9709a3 9472
AnnaBridge 189:f392fc9709a3 9473 /*! @name C1 - MCG Control 1 Register */
AnnaBridge 189:f392fc9709a3 9474 #define MCG_C1_IREFSTEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9475 #define MCG_C1_IREFSTEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9476 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
AnnaBridge 189:f392fc9709a3 9477 #define MCG_C1_IRCLKEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9478 #define MCG_C1_IRCLKEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9479 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
AnnaBridge 189:f392fc9709a3 9480 #define MCG_C1_IREFS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 9481 #define MCG_C1_IREFS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9482 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
AnnaBridge 189:f392fc9709a3 9483 #define MCG_C1_FRDIV_MASK (0x38U)
AnnaBridge 189:f392fc9709a3 9484 #define MCG_C1_FRDIV_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 9485 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
AnnaBridge 189:f392fc9709a3 9486 #define MCG_C1_CLKS_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 9487 #define MCG_C1_CLKS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9488 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
AnnaBridge 189:f392fc9709a3 9489
AnnaBridge 189:f392fc9709a3 9490 /*! @name C2 - MCG Control 2 Register */
AnnaBridge 189:f392fc9709a3 9491 #define MCG_C2_IRCS_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9492 #define MCG_C2_IRCS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9493 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
AnnaBridge 189:f392fc9709a3 9494 #define MCG_C2_LP_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9495 #define MCG_C2_LP_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9496 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
AnnaBridge 189:f392fc9709a3 9497 #define MCG_C2_EREFS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 9498 #define MCG_C2_EREFS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9499 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
AnnaBridge 189:f392fc9709a3 9500 #define MCG_C2_HGO_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 9501 #define MCG_C2_HGO_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 9502 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
AnnaBridge 189:f392fc9709a3 9503 #define MCG_C2_RANGE_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 9504 #define MCG_C2_RANGE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9505 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
AnnaBridge 189:f392fc9709a3 9506 #define MCG_C2_FCFTRIM_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9507 #define MCG_C2_FCFTRIM_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9508 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
AnnaBridge 189:f392fc9709a3 9509 #define MCG_C2_LOCRE0_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 9510 #define MCG_C2_LOCRE0_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 9511 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
AnnaBridge 189:f392fc9709a3 9512
AnnaBridge 189:f392fc9709a3 9513 /*! @name C3 - MCG Control 3 Register */
AnnaBridge 189:f392fc9709a3 9514 #define MCG_C3_SCTRIM_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 9515 #define MCG_C3_SCTRIM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9516 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
AnnaBridge 189:f392fc9709a3 9517
AnnaBridge 189:f392fc9709a3 9518 /*! @name C4 - MCG Control 4 Register */
AnnaBridge 189:f392fc9709a3 9519 #define MCG_C4_SCFTRIM_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9520 #define MCG_C4_SCFTRIM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9521 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
AnnaBridge 189:f392fc9709a3 9522 #define MCG_C4_FCTRIM_MASK (0x1EU)
AnnaBridge 189:f392fc9709a3 9523 #define MCG_C4_FCTRIM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9524 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
AnnaBridge 189:f392fc9709a3 9525 #define MCG_C4_DRST_DRS_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 9526 #define MCG_C4_DRST_DRS_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9527 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
AnnaBridge 189:f392fc9709a3 9528 #define MCG_C4_DMX32_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 9529 #define MCG_C4_DMX32_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 9530 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
AnnaBridge 189:f392fc9709a3 9531
AnnaBridge 189:f392fc9709a3 9532 /*! @name C5 - MCG Control 5 Register */
AnnaBridge 189:f392fc9709a3 9533 #define MCG_C5_PRDIV_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 9534 #define MCG_C5_PRDIV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9535 #define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
AnnaBridge 189:f392fc9709a3 9536 #define MCG_C5_PLLSTEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 9537 #define MCG_C5_PLLSTEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9538 #define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
AnnaBridge 189:f392fc9709a3 9539 #define MCG_C5_PLLCLKEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9540 #define MCG_C5_PLLCLKEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9541 #define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
AnnaBridge 189:f392fc9709a3 9542
AnnaBridge 189:f392fc9709a3 9543 /*! @name C6 - MCG Control 6 Register */
AnnaBridge 189:f392fc9709a3 9544 #define MCG_C6_VDIV_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 9545 #define MCG_C6_VDIV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9546 #define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
AnnaBridge 189:f392fc9709a3 9547 #define MCG_C6_CME0_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 9548 #define MCG_C6_CME0_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9549 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
AnnaBridge 189:f392fc9709a3 9550 #define MCG_C6_PLLS_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9551 #define MCG_C6_PLLS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9552 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
AnnaBridge 189:f392fc9709a3 9553 #define MCG_C6_LOLIE0_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 9554 #define MCG_C6_LOLIE0_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 9555 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
AnnaBridge 189:f392fc9709a3 9556
AnnaBridge 189:f392fc9709a3 9557 /*! @name S - MCG Status Register */
AnnaBridge 189:f392fc9709a3 9558 #define MCG_S_IRCST_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9559 #define MCG_S_IRCST_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9560 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
AnnaBridge 189:f392fc9709a3 9561 #define MCG_S_OSCINIT0_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9562 #define MCG_S_OSCINIT0_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9563 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
AnnaBridge 189:f392fc9709a3 9564 #define MCG_S_CLKST_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 9565 #define MCG_S_CLKST_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9566 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
AnnaBridge 189:f392fc9709a3 9567 #define MCG_S_IREFST_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 9568 #define MCG_S_IREFST_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9569 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
AnnaBridge 189:f392fc9709a3 9570 #define MCG_S_PLLST_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 9571 #define MCG_S_PLLST_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9572 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
AnnaBridge 189:f392fc9709a3 9573 #define MCG_S_LOCK0_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9574 #define MCG_S_LOCK0_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9575 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
AnnaBridge 189:f392fc9709a3 9576 #define MCG_S_LOLS0_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 9577 #define MCG_S_LOLS0_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 9578 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
AnnaBridge 189:f392fc9709a3 9579
AnnaBridge 189:f392fc9709a3 9580 /*! @name SC - MCG Status and Control Register */
AnnaBridge 189:f392fc9709a3 9581 #define MCG_SC_LOCS0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9582 #define MCG_SC_LOCS0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9583 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
AnnaBridge 189:f392fc9709a3 9584 #define MCG_SC_FCRDIV_MASK (0xEU)
AnnaBridge 189:f392fc9709a3 9585 #define MCG_SC_FCRDIV_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9586 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
AnnaBridge 189:f392fc9709a3 9587 #define MCG_SC_FLTPRSRV_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 9588 #define MCG_SC_FLTPRSRV_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9589 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
AnnaBridge 189:f392fc9709a3 9590 #define MCG_SC_ATMF_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 9591 #define MCG_SC_ATMF_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9592 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
AnnaBridge 189:f392fc9709a3 9593 #define MCG_SC_ATMS_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9594 #define MCG_SC_ATMS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9595 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
AnnaBridge 189:f392fc9709a3 9596 #define MCG_SC_ATME_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 9597 #define MCG_SC_ATME_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 9598 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
AnnaBridge 189:f392fc9709a3 9599
AnnaBridge 189:f392fc9709a3 9600 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
AnnaBridge 189:f392fc9709a3 9601 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 9602 #define MCG_ATCVH_ATCVH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9603 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
AnnaBridge 189:f392fc9709a3 9604
AnnaBridge 189:f392fc9709a3 9605 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
AnnaBridge 189:f392fc9709a3 9606 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 9607 #define MCG_ATCVL_ATCVL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9608 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
AnnaBridge 189:f392fc9709a3 9609
AnnaBridge 189:f392fc9709a3 9610 /*! @name C7 - MCG Control 7 Register */
AnnaBridge 189:f392fc9709a3 9611 #define MCG_C7_OSCSEL_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 9612 #define MCG_C7_OSCSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9613 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
AnnaBridge 189:f392fc9709a3 9614
AnnaBridge 189:f392fc9709a3 9615 /*! @name C8 - MCG Control 8 Register */
AnnaBridge 189:f392fc9709a3 9616 #define MCG_C8_LOCS1_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9617 #define MCG_C8_LOCS1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9618 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
AnnaBridge 189:f392fc9709a3 9619 #define MCG_C8_CME1_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 9620 #define MCG_C8_CME1_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9621 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
AnnaBridge 189:f392fc9709a3 9622 #define MCG_C8_LOLRE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 9623 #define MCG_C8_LOLRE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9624 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
AnnaBridge 189:f392fc9709a3 9625 #define MCG_C8_LOCRE1_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 9626 #define MCG_C8_LOCRE1_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 9627 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
AnnaBridge 189:f392fc9709a3 9628
AnnaBridge 189:f392fc9709a3 9629
AnnaBridge 189:f392fc9709a3 9630 /*!
AnnaBridge 189:f392fc9709a3 9631 * @}
AnnaBridge 189:f392fc9709a3 9632 */ /* end of group MCG_Register_Masks */
AnnaBridge 189:f392fc9709a3 9633
AnnaBridge 189:f392fc9709a3 9634
AnnaBridge 189:f392fc9709a3 9635 /* MCG - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 9636 /** Peripheral MCG base address */
AnnaBridge 189:f392fc9709a3 9637 #define MCG_BASE (0x40064000u)
AnnaBridge 189:f392fc9709a3 9638 /** Peripheral MCG base pointer */
AnnaBridge 189:f392fc9709a3 9639 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 189:f392fc9709a3 9640 /** Array initializer of MCG peripheral base addresses */
AnnaBridge 189:f392fc9709a3 9641 #define MCG_BASE_ADDRS { MCG_BASE }
AnnaBridge 189:f392fc9709a3 9642 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 189:f392fc9709a3 9643 #define MCG_BASE_PTRS { MCG }
AnnaBridge 189:f392fc9709a3 9644 /** Interrupt vectors for the MCG peripheral type */
AnnaBridge 189:f392fc9709a3 9645 #define MCG_IRQS { MCG_IRQn }
AnnaBridge 189:f392fc9709a3 9646 /* MCG C5[PLLCLKEN0] backward compatibility */
AnnaBridge 189:f392fc9709a3 9647 #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
AnnaBridge 189:f392fc9709a3 9648 #define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
AnnaBridge 189:f392fc9709a3 9649 #define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
AnnaBridge 189:f392fc9709a3 9650 #define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
AnnaBridge 189:f392fc9709a3 9651
AnnaBridge 189:f392fc9709a3 9652 /* MCG C5[PLLSTEN0] backward compatibility */
AnnaBridge 189:f392fc9709a3 9653 #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
AnnaBridge 189:f392fc9709a3 9654 #define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
AnnaBridge 189:f392fc9709a3 9655 #define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
AnnaBridge 189:f392fc9709a3 9656 #define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
AnnaBridge 189:f392fc9709a3 9657
AnnaBridge 189:f392fc9709a3 9658 /* MCG C5[PRDIV0] backward compatibility */
AnnaBridge 189:f392fc9709a3 9659 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
AnnaBridge 189:f392fc9709a3 9660 #define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
AnnaBridge 189:f392fc9709a3 9661 #define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
AnnaBridge 189:f392fc9709a3 9662 #define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
AnnaBridge 189:f392fc9709a3 9663
AnnaBridge 189:f392fc9709a3 9664 /* MCG C6[VDIV0] backward compatibility */
AnnaBridge 189:f392fc9709a3 9665 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
AnnaBridge 189:f392fc9709a3 9666 #define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
AnnaBridge 189:f392fc9709a3 9667 #define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
AnnaBridge 189:f392fc9709a3 9668 #define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
AnnaBridge 189:f392fc9709a3 9669
AnnaBridge 189:f392fc9709a3 9670
AnnaBridge 189:f392fc9709a3 9671 /*!
AnnaBridge 189:f392fc9709a3 9672 * @}
AnnaBridge 189:f392fc9709a3 9673 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 9674
AnnaBridge 189:f392fc9709a3 9675
AnnaBridge 189:f392fc9709a3 9676 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 9677 -- MCM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 9678 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 9679
AnnaBridge 189:f392fc9709a3 9680 /*!
AnnaBridge 189:f392fc9709a3 9681 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 9682 * @{
AnnaBridge 189:f392fc9709a3 9683 */
AnnaBridge 189:f392fc9709a3 9684
AnnaBridge 189:f392fc9709a3 9685 /** MCM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 9686 typedef struct {
AnnaBridge 189:f392fc9709a3 9687 uint8_t RESERVED_0[8];
AnnaBridge 189:f392fc9709a3 9688 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 9689 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 189:f392fc9709a3 9690 __IO uint32_t CR; /**< Control Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 9691 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 9692 uint8_t RESERVED_1[12];
AnnaBridge 189:f392fc9709a3 9693 __I uint32_t FADR; /**< Fault address register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 9694 __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 9695 __I uint32_t FDR; /**< Fault data register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 9696 uint8_t RESERVED_2[4];
AnnaBridge 189:f392fc9709a3 9697 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 9698 uint8_t RESERVED_3[12];
AnnaBridge 189:f392fc9709a3 9699 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 9700 } MCM_Type;
AnnaBridge 189:f392fc9709a3 9701
AnnaBridge 189:f392fc9709a3 9702 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 9703 -- MCM Register Masks
AnnaBridge 189:f392fc9709a3 9704 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 9705
AnnaBridge 189:f392fc9709a3 9706 /*!
AnnaBridge 189:f392fc9709a3 9707 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 189:f392fc9709a3 9708 * @{
AnnaBridge 189:f392fc9709a3 9709 */
AnnaBridge 189:f392fc9709a3 9710
AnnaBridge 189:f392fc9709a3 9711 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
AnnaBridge 189:f392fc9709a3 9712 #define MCM_PLASC_ASC_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 9713 #define MCM_PLASC_ASC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9714 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
AnnaBridge 189:f392fc9709a3 9715
AnnaBridge 189:f392fc9709a3 9716 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
AnnaBridge 189:f392fc9709a3 9717 #define MCM_PLAMC_AMC_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 9718 #define MCM_PLAMC_AMC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9719 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
AnnaBridge 189:f392fc9709a3 9720
AnnaBridge 189:f392fc9709a3 9721 /*! @name CR - Control Register */
AnnaBridge 189:f392fc9709a3 9722 #define MCM_CR_SRAMUAP_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 9723 #define MCM_CR_SRAMUAP_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 9724 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
AnnaBridge 189:f392fc9709a3 9725 #define MCM_CR_SRAMUWP_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 9726 #define MCM_CR_SRAMUWP_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 9727 #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
AnnaBridge 189:f392fc9709a3 9728 #define MCM_CR_SRAMLAP_MASK (0x30000000U)
AnnaBridge 189:f392fc9709a3 9729 #define MCM_CR_SRAMLAP_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 9730 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
AnnaBridge 189:f392fc9709a3 9731 #define MCM_CR_SRAMLWP_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 9732 #define MCM_CR_SRAMLWP_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 9733 #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
AnnaBridge 189:f392fc9709a3 9734
AnnaBridge 189:f392fc9709a3 9735 /*! @name ISCR - Interrupt Status Register */
AnnaBridge 189:f392fc9709a3 9736 #define MCM_ISCR_FIOC_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 9737 #define MCM_ISCR_FIOC_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9738 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
AnnaBridge 189:f392fc9709a3 9739 #define MCM_ISCR_FDZC_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 9740 #define MCM_ISCR_FDZC_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 9741 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
AnnaBridge 189:f392fc9709a3 9742 #define MCM_ISCR_FOFC_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 9743 #define MCM_ISCR_FOFC_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 9744 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
AnnaBridge 189:f392fc9709a3 9745 #define MCM_ISCR_FUFC_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 9746 #define MCM_ISCR_FUFC_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 9747 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
AnnaBridge 189:f392fc9709a3 9748 #define MCM_ISCR_FIXC_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 9749 #define MCM_ISCR_FIXC_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 9750 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
AnnaBridge 189:f392fc9709a3 9751 #define MCM_ISCR_FIDC_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 9752 #define MCM_ISCR_FIDC_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 9753 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
AnnaBridge 189:f392fc9709a3 9754 #define MCM_ISCR_FIOCE_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 9755 #define MCM_ISCR_FIOCE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 9756 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
AnnaBridge 189:f392fc9709a3 9757 #define MCM_ISCR_FDZCE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 9758 #define MCM_ISCR_FDZCE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 9759 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
AnnaBridge 189:f392fc9709a3 9760 #define MCM_ISCR_FOFCE_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 9761 #define MCM_ISCR_FOFCE_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 9762 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
AnnaBridge 189:f392fc9709a3 9763 #define MCM_ISCR_FUFCE_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 9764 #define MCM_ISCR_FUFCE_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 9765 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
AnnaBridge 189:f392fc9709a3 9766 #define MCM_ISCR_FIXCE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 9767 #define MCM_ISCR_FIXCE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 9768 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
AnnaBridge 189:f392fc9709a3 9769 #define MCM_ISCR_FIDCE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9770 #define MCM_ISCR_FIDCE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9771 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
AnnaBridge 189:f392fc9709a3 9772
AnnaBridge 189:f392fc9709a3 9773 /*! @name FADR - Fault address register */
AnnaBridge 189:f392fc9709a3 9774 #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9775 #define MCM_FADR_ADDRESS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9776 #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
AnnaBridge 189:f392fc9709a3 9777
AnnaBridge 189:f392fc9709a3 9778 /*! @name FATR - Fault attributes register */
AnnaBridge 189:f392fc9709a3 9779 #define MCM_FATR_BEDA_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9780 #define MCM_FATR_BEDA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9781 #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
AnnaBridge 189:f392fc9709a3 9782 #define MCM_FATR_BEMD_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9783 #define MCM_FATR_BEMD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9784 #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
AnnaBridge 189:f392fc9709a3 9785 #define MCM_FATR_BESZ_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 9786 #define MCM_FATR_BESZ_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9787 #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
AnnaBridge 189:f392fc9709a3 9788 #define MCM_FATR_BEWT_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 9789 #define MCM_FATR_BEWT_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 9790 #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
AnnaBridge 189:f392fc9709a3 9791 #define MCM_FATR_BEMN_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 9792 #define MCM_FATR_BEMN_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9793 #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
AnnaBridge 189:f392fc9709a3 9794 #define MCM_FATR_BEOVR_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9795 #define MCM_FATR_BEOVR_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9796 #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
AnnaBridge 189:f392fc9709a3 9797
AnnaBridge 189:f392fc9709a3 9798 /*! @name FDR - Fault data register */
AnnaBridge 189:f392fc9709a3 9799 #define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9800 #define MCM_FDR_DATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9801 #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
AnnaBridge 189:f392fc9709a3 9802
AnnaBridge 189:f392fc9709a3 9803 /*! @name PID - Process ID register */
AnnaBridge 189:f392fc9709a3 9804 #define MCM_PID_PID_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 9805 #define MCM_PID_PID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9806 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
AnnaBridge 189:f392fc9709a3 9807
AnnaBridge 189:f392fc9709a3 9808 /*! @name CPO - Compute Operation Control Register */
AnnaBridge 189:f392fc9709a3 9809 #define MCM_CPO_CPOREQ_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9810 #define MCM_CPO_CPOREQ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9811 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
AnnaBridge 189:f392fc9709a3 9812 #define MCM_CPO_CPOACK_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 9813 #define MCM_CPO_CPOACK_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9814 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
AnnaBridge 189:f392fc9709a3 9815 #define MCM_CPO_CPOWOI_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 9816 #define MCM_CPO_CPOWOI_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 9817 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
AnnaBridge 189:f392fc9709a3 9818
AnnaBridge 189:f392fc9709a3 9819
AnnaBridge 189:f392fc9709a3 9820 /*!
AnnaBridge 189:f392fc9709a3 9821 * @}
AnnaBridge 189:f392fc9709a3 9822 */ /* end of group MCM_Register_Masks */
AnnaBridge 189:f392fc9709a3 9823
AnnaBridge 189:f392fc9709a3 9824
AnnaBridge 189:f392fc9709a3 9825 /* MCM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 9826 /** Peripheral MCM base address */
AnnaBridge 189:f392fc9709a3 9827 #define MCM_BASE (0xE0080000u)
AnnaBridge 189:f392fc9709a3 9828 /** Peripheral MCM base pointer */
AnnaBridge 189:f392fc9709a3 9829 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 189:f392fc9709a3 9830 /** Array initializer of MCM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 9831 #define MCM_BASE_ADDRS { MCM_BASE }
AnnaBridge 189:f392fc9709a3 9832 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 9833 #define MCM_BASE_PTRS { MCM }
AnnaBridge 189:f392fc9709a3 9834 /** Interrupt vectors for the MCM peripheral type */
AnnaBridge 189:f392fc9709a3 9835 #define MCM_IRQS { MCM_IRQn }
AnnaBridge 189:f392fc9709a3 9836
AnnaBridge 189:f392fc9709a3 9837 /*!
AnnaBridge 189:f392fc9709a3 9838 * @}
AnnaBridge 189:f392fc9709a3 9839 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 9840
AnnaBridge 189:f392fc9709a3 9841
AnnaBridge 189:f392fc9709a3 9842 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 9843 -- MPU Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 9844 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 9845
AnnaBridge 189:f392fc9709a3 9846 /*!
AnnaBridge 189:f392fc9709a3 9847 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 9848 * @{
AnnaBridge 189:f392fc9709a3 9849 */
AnnaBridge 189:f392fc9709a3 9850
AnnaBridge 189:f392fc9709a3 9851 /** MPU - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 9852 typedef struct {
AnnaBridge 189:f392fc9709a3 9853 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 9854 uint8_t RESERVED_0[12];
AnnaBridge 189:f392fc9709a3 9855 struct { /* offset: 0x10, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 9856 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 9857 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 9858 } SP[5];
AnnaBridge 189:f392fc9709a3 9859 uint8_t RESERVED_1[968];
AnnaBridge 189:f392fc9709a3 9860 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
AnnaBridge 189:f392fc9709a3 9861 uint8_t RESERVED_2[832];
AnnaBridge 189:f392fc9709a3 9862 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 9863 } MPU_Type;
AnnaBridge 189:f392fc9709a3 9864
AnnaBridge 189:f392fc9709a3 9865 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 9866 -- MPU Register Masks
AnnaBridge 189:f392fc9709a3 9867 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 9868
AnnaBridge 189:f392fc9709a3 9869 /*!
AnnaBridge 189:f392fc9709a3 9870 * @addtogroup MPU_Register_Masks MPU Register Masks
AnnaBridge 189:f392fc9709a3 9871 * @{
AnnaBridge 189:f392fc9709a3 9872 */
AnnaBridge 189:f392fc9709a3 9873
AnnaBridge 189:f392fc9709a3 9874 /*! @name CESR - Control/Error Status Register */
AnnaBridge 189:f392fc9709a3 9875 #define MPU_CESR_VLD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9876 #define MPU_CESR_VLD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9877 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
AnnaBridge 189:f392fc9709a3 9878 #define MPU_CESR_NRGD_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 9879 #define MPU_CESR_NRGD_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9880 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
AnnaBridge 189:f392fc9709a3 9881 #define MPU_CESR_NSP_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 9882 #define MPU_CESR_NSP_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 9883 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
AnnaBridge 189:f392fc9709a3 9884 #define MPU_CESR_HRL_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 9885 #define MPU_CESR_HRL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9886 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
AnnaBridge 189:f392fc9709a3 9887 #define MPU_CESR_SPERR_MASK (0xF8000000U)
AnnaBridge 189:f392fc9709a3 9888 #define MPU_CESR_SPERR_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 9889 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
AnnaBridge 189:f392fc9709a3 9890
AnnaBridge 189:f392fc9709a3 9891 /*! @name EAR - Error Address Register, slave port n */
AnnaBridge 189:f392fc9709a3 9892 #define MPU_EAR_EADDR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 9893 #define MPU_EAR_EADDR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9894 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
AnnaBridge 189:f392fc9709a3 9895
AnnaBridge 189:f392fc9709a3 9896 /* The count of MPU_EAR */
AnnaBridge 189:f392fc9709a3 9897 #define MPU_EAR_COUNT (5U)
AnnaBridge 189:f392fc9709a3 9898
AnnaBridge 189:f392fc9709a3 9899 /*! @name EDR - Error Detail Register, slave port n */
AnnaBridge 189:f392fc9709a3 9900 #define MPU_EDR_ERW_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9901 #define MPU_EDR_ERW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9902 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
AnnaBridge 189:f392fc9709a3 9903 #define MPU_EDR_EATTR_MASK (0xEU)
AnnaBridge 189:f392fc9709a3 9904 #define MPU_EDR_EATTR_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 9905 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
AnnaBridge 189:f392fc9709a3 9906 #define MPU_EDR_EMN_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 9907 #define MPU_EDR_EMN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 9908 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
AnnaBridge 189:f392fc9709a3 9909 #define MPU_EDR_EPID_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 9910 #define MPU_EDR_EPID_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 9911 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
AnnaBridge 189:f392fc9709a3 9912 #define MPU_EDR_EACD_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 9913 #define MPU_EDR_EACD_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9914 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
AnnaBridge 189:f392fc9709a3 9915
AnnaBridge 189:f392fc9709a3 9916 /* The count of MPU_EDR */
AnnaBridge 189:f392fc9709a3 9917 #define MPU_EDR_COUNT (5U)
AnnaBridge 189:f392fc9709a3 9918
AnnaBridge 189:f392fc9709a3 9919 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
AnnaBridge 189:f392fc9709a3 9920 #define MPU_WORD_VLD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 9921 #define MPU_WORD_VLD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9922 #define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
AnnaBridge 189:f392fc9709a3 9923 #define MPU_WORD_M0UM_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 9924 #define MPU_WORD_M0UM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 9925 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
AnnaBridge 189:f392fc9709a3 9926 #define MPU_WORD_M0SM_MASK (0x18U)
AnnaBridge 189:f392fc9709a3 9927 #define MPU_WORD_M0SM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 9928 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
AnnaBridge 189:f392fc9709a3 9929 #define MPU_WORD_M0PE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 9930 #define MPU_WORD_M0PE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9931 #define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
AnnaBridge 189:f392fc9709a3 9932 #define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
AnnaBridge 189:f392fc9709a3 9933 #define MPU_WORD_ENDADDR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9934 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
AnnaBridge 189:f392fc9709a3 9935 #define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
AnnaBridge 189:f392fc9709a3 9936 #define MPU_WORD_SRTADDR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 9937 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
AnnaBridge 189:f392fc9709a3 9938 #define MPU_WORD_M1UM_MASK (0x1C0U)
AnnaBridge 189:f392fc9709a3 9939 #define MPU_WORD_M1UM_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 9940 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
AnnaBridge 189:f392fc9709a3 9941 #define MPU_WORD_M1SM_MASK (0x600U)
AnnaBridge 189:f392fc9709a3 9942 #define MPU_WORD_M1SM_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 9943 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
AnnaBridge 189:f392fc9709a3 9944 #define MPU_WORD_M1PE_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 9945 #define MPU_WORD_M1PE_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 9946 #define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
AnnaBridge 189:f392fc9709a3 9947 #define MPU_WORD_M2UM_MASK (0x7000U)
AnnaBridge 189:f392fc9709a3 9948 #define MPU_WORD_M2UM_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 9949 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
AnnaBridge 189:f392fc9709a3 9950 #define MPU_WORD_M2SM_MASK (0x18000U)
AnnaBridge 189:f392fc9709a3 9951 #define MPU_WORD_M2SM_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 9952 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
AnnaBridge 189:f392fc9709a3 9953 #define MPU_WORD_PIDMASK_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 9954 #define MPU_WORD_PIDMASK_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 9955 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
AnnaBridge 189:f392fc9709a3 9956 #define MPU_WORD_M2PE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 9957 #define MPU_WORD_M2PE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 9958 #define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
AnnaBridge 189:f392fc9709a3 9959 #define MPU_WORD_M3UM_MASK (0x1C0000U)
AnnaBridge 189:f392fc9709a3 9960 #define MPU_WORD_M3UM_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 9961 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
AnnaBridge 189:f392fc9709a3 9962 #define MPU_WORD_M3SM_MASK (0x600000U)
AnnaBridge 189:f392fc9709a3 9963 #define MPU_WORD_M3SM_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 9964 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
AnnaBridge 189:f392fc9709a3 9965 #define MPU_WORD_M3PE_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 9966 #define MPU_WORD_M3PE_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 9967 #define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
AnnaBridge 189:f392fc9709a3 9968 #define MPU_WORD_PID_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 9969 #define MPU_WORD_PID_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 9970 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
AnnaBridge 189:f392fc9709a3 9971 #define MPU_WORD_M4WE_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 9972 #define MPU_WORD_M4WE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 9973 #define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
AnnaBridge 189:f392fc9709a3 9974 #define MPU_WORD_M4RE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 9975 #define MPU_WORD_M4RE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 9976 #define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
AnnaBridge 189:f392fc9709a3 9977 #define MPU_WORD_M5WE_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 9978 #define MPU_WORD_M5WE_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 9979 #define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
AnnaBridge 189:f392fc9709a3 9980 #define MPU_WORD_M5RE_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 9981 #define MPU_WORD_M5RE_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 9982 #define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
AnnaBridge 189:f392fc9709a3 9983 #define MPU_WORD_M6WE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 9984 #define MPU_WORD_M6WE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 9985 #define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
AnnaBridge 189:f392fc9709a3 9986 #define MPU_WORD_M6RE_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 9987 #define MPU_WORD_M6RE_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 9988 #define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
AnnaBridge 189:f392fc9709a3 9989 #define MPU_WORD_M7WE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 9990 #define MPU_WORD_M7WE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 9991 #define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
AnnaBridge 189:f392fc9709a3 9992 #define MPU_WORD_M7RE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 9993 #define MPU_WORD_M7RE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 9994 #define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
AnnaBridge 189:f392fc9709a3 9995
AnnaBridge 189:f392fc9709a3 9996 /* The count of MPU_WORD */
AnnaBridge 189:f392fc9709a3 9997 #define MPU_WORD_COUNT (12U)
AnnaBridge 189:f392fc9709a3 9998
AnnaBridge 189:f392fc9709a3 9999 /* The count of MPU_WORD */
AnnaBridge 189:f392fc9709a3 10000 #define MPU_WORD_COUNT2 (4U)
AnnaBridge 189:f392fc9709a3 10001
AnnaBridge 189:f392fc9709a3 10002 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
AnnaBridge 189:f392fc9709a3 10003 #define MPU_RGDAAC_M0UM_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 10004 #define MPU_RGDAAC_M0UM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10005 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
AnnaBridge 189:f392fc9709a3 10006 #define MPU_RGDAAC_M0SM_MASK (0x18U)
AnnaBridge 189:f392fc9709a3 10007 #define MPU_RGDAAC_M0SM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 10008 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
AnnaBridge 189:f392fc9709a3 10009 #define MPU_RGDAAC_M0PE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10010 #define MPU_RGDAAC_M0PE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10011 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
AnnaBridge 189:f392fc9709a3 10012 #define MPU_RGDAAC_M1UM_MASK (0x1C0U)
AnnaBridge 189:f392fc9709a3 10013 #define MPU_RGDAAC_M1UM_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10014 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
AnnaBridge 189:f392fc9709a3 10015 #define MPU_RGDAAC_M1SM_MASK (0x600U)
AnnaBridge 189:f392fc9709a3 10016 #define MPU_RGDAAC_M1SM_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 10017 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
AnnaBridge 189:f392fc9709a3 10018 #define MPU_RGDAAC_M1PE_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 10019 #define MPU_RGDAAC_M1PE_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 10020 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
AnnaBridge 189:f392fc9709a3 10021 #define MPU_RGDAAC_M2UM_MASK (0x7000U)
AnnaBridge 189:f392fc9709a3 10022 #define MPU_RGDAAC_M2UM_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 10023 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
AnnaBridge 189:f392fc9709a3 10024 #define MPU_RGDAAC_M2SM_MASK (0x18000U)
AnnaBridge 189:f392fc9709a3 10025 #define MPU_RGDAAC_M2SM_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 10026 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
AnnaBridge 189:f392fc9709a3 10027 #define MPU_RGDAAC_M2PE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 10028 #define MPU_RGDAAC_M2PE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 10029 #define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
AnnaBridge 189:f392fc9709a3 10030 #define MPU_RGDAAC_M3UM_MASK (0x1C0000U)
AnnaBridge 189:f392fc9709a3 10031 #define MPU_RGDAAC_M3UM_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 10032 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
AnnaBridge 189:f392fc9709a3 10033 #define MPU_RGDAAC_M3SM_MASK (0x600000U)
AnnaBridge 189:f392fc9709a3 10034 #define MPU_RGDAAC_M3SM_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 10035 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
AnnaBridge 189:f392fc9709a3 10036 #define MPU_RGDAAC_M3PE_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 10037 #define MPU_RGDAAC_M3PE_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 10038 #define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
AnnaBridge 189:f392fc9709a3 10039 #define MPU_RGDAAC_M4WE_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 10040 #define MPU_RGDAAC_M4WE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 10041 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
AnnaBridge 189:f392fc9709a3 10042 #define MPU_RGDAAC_M4RE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 10043 #define MPU_RGDAAC_M4RE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 10044 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
AnnaBridge 189:f392fc9709a3 10045 #define MPU_RGDAAC_M5WE_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 10046 #define MPU_RGDAAC_M5WE_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 10047 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
AnnaBridge 189:f392fc9709a3 10048 #define MPU_RGDAAC_M5RE_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 10049 #define MPU_RGDAAC_M5RE_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 10050 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
AnnaBridge 189:f392fc9709a3 10051 #define MPU_RGDAAC_M6WE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 10052 #define MPU_RGDAAC_M6WE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 10053 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
AnnaBridge 189:f392fc9709a3 10054 #define MPU_RGDAAC_M6RE_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 10055 #define MPU_RGDAAC_M6RE_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 10056 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
AnnaBridge 189:f392fc9709a3 10057 #define MPU_RGDAAC_M7WE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 10058 #define MPU_RGDAAC_M7WE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 10059 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
AnnaBridge 189:f392fc9709a3 10060 #define MPU_RGDAAC_M7RE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 10061 #define MPU_RGDAAC_M7RE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 10062 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
AnnaBridge 189:f392fc9709a3 10063
AnnaBridge 189:f392fc9709a3 10064 /* The count of MPU_RGDAAC */
AnnaBridge 189:f392fc9709a3 10065 #define MPU_RGDAAC_COUNT (12U)
AnnaBridge 189:f392fc9709a3 10066
AnnaBridge 189:f392fc9709a3 10067
AnnaBridge 189:f392fc9709a3 10068 /*!
AnnaBridge 189:f392fc9709a3 10069 * @}
AnnaBridge 189:f392fc9709a3 10070 */ /* end of group MPU_Register_Masks */
AnnaBridge 189:f392fc9709a3 10071
AnnaBridge 189:f392fc9709a3 10072
AnnaBridge 189:f392fc9709a3 10073 /* MPU - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10074 /** Peripheral MPU base address */
AnnaBridge 189:f392fc9709a3 10075 #define MPU_BASE (0x4000D000u)
AnnaBridge 189:f392fc9709a3 10076 /** Peripheral MPU base pointer */
AnnaBridge 189:f392fc9709a3 10077 #define MPU ((MPU_Type *)MPU_BASE)
AnnaBridge 189:f392fc9709a3 10078 /** Array initializer of MPU peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10079 #define MPU_BASE_ADDRS { MPU_BASE }
AnnaBridge 189:f392fc9709a3 10080 /** Array initializer of MPU peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10081 #define MPU_BASE_PTRS { MPU }
AnnaBridge 189:f392fc9709a3 10082
AnnaBridge 189:f392fc9709a3 10083 /*!
AnnaBridge 189:f392fc9709a3 10084 * @}
AnnaBridge 189:f392fc9709a3 10085 */ /* end of group MPU_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 10086
AnnaBridge 189:f392fc9709a3 10087
AnnaBridge 189:f392fc9709a3 10088 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10089 -- NV Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10090 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10091
AnnaBridge 189:f392fc9709a3 10092 /*!
AnnaBridge 189:f392fc9709a3 10093 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10094 * @{
AnnaBridge 189:f392fc9709a3 10095 */
AnnaBridge 189:f392fc9709a3 10096
AnnaBridge 189:f392fc9709a3 10097 /** NV - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 10098 typedef struct {
AnnaBridge 189:f392fc9709a3 10099 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 189:f392fc9709a3 10100 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 189:f392fc9709a3 10101 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 189:f392fc9709a3 10102 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 189:f392fc9709a3 10103 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 189:f392fc9709a3 10104 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 189:f392fc9709a3 10105 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 189:f392fc9709a3 10106 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 189:f392fc9709a3 10107 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 10108 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 189:f392fc9709a3 10109 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 189:f392fc9709a3 10110 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 189:f392fc9709a3 10111 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 10112 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 189:f392fc9709a3 10113 } NV_Type;
AnnaBridge 189:f392fc9709a3 10114
AnnaBridge 189:f392fc9709a3 10115 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10116 -- NV Register Masks
AnnaBridge 189:f392fc9709a3 10117 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10118
AnnaBridge 189:f392fc9709a3 10119 /*!
AnnaBridge 189:f392fc9709a3 10120 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 189:f392fc9709a3 10121 * @{
AnnaBridge 189:f392fc9709a3 10122 */
AnnaBridge 189:f392fc9709a3 10123
AnnaBridge 189:f392fc9709a3 10124 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
AnnaBridge 189:f392fc9709a3 10125 #define NV_BACKKEY3_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10126 #define NV_BACKKEY3_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10127 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10128
AnnaBridge 189:f392fc9709a3 10129 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
AnnaBridge 189:f392fc9709a3 10130 #define NV_BACKKEY2_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10131 #define NV_BACKKEY2_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10132 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10133
AnnaBridge 189:f392fc9709a3 10134 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
AnnaBridge 189:f392fc9709a3 10135 #define NV_BACKKEY1_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10136 #define NV_BACKKEY1_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10137 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10138
AnnaBridge 189:f392fc9709a3 10139 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
AnnaBridge 189:f392fc9709a3 10140 #define NV_BACKKEY0_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10141 #define NV_BACKKEY0_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10142 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10143
AnnaBridge 189:f392fc9709a3 10144 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
AnnaBridge 189:f392fc9709a3 10145 #define NV_BACKKEY7_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10146 #define NV_BACKKEY7_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10147 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10148
AnnaBridge 189:f392fc9709a3 10149 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
AnnaBridge 189:f392fc9709a3 10150 #define NV_BACKKEY6_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10151 #define NV_BACKKEY6_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10152 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10153
AnnaBridge 189:f392fc9709a3 10154 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
AnnaBridge 189:f392fc9709a3 10155 #define NV_BACKKEY5_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10156 #define NV_BACKKEY5_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10157 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10158
AnnaBridge 189:f392fc9709a3 10159 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
AnnaBridge 189:f392fc9709a3 10160 #define NV_BACKKEY4_KEY_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10161 #define NV_BACKKEY4_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10162 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
AnnaBridge 189:f392fc9709a3 10163
AnnaBridge 189:f392fc9709a3 10164 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
AnnaBridge 189:f392fc9709a3 10165 #define NV_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10166 #define NV_FPROT3_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10167 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
AnnaBridge 189:f392fc9709a3 10168
AnnaBridge 189:f392fc9709a3 10169 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
AnnaBridge 189:f392fc9709a3 10170 #define NV_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10171 #define NV_FPROT2_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10172 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
AnnaBridge 189:f392fc9709a3 10173
AnnaBridge 189:f392fc9709a3 10174 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
AnnaBridge 189:f392fc9709a3 10175 #define NV_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10176 #define NV_FPROT1_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10177 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
AnnaBridge 189:f392fc9709a3 10178
AnnaBridge 189:f392fc9709a3 10179 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
AnnaBridge 189:f392fc9709a3 10180 #define NV_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10181 #define NV_FPROT0_PROT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10182 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
AnnaBridge 189:f392fc9709a3 10183
AnnaBridge 189:f392fc9709a3 10184 /*! @name FSEC - Non-volatile Flash Security Register */
AnnaBridge 189:f392fc9709a3 10185 #define NV_FSEC_SEC_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 10186 #define NV_FSEC_SEC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10187 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
AnnaBridge 189:f392fc9709a3 10188 #define NV_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 10189 #define NV_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10190 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
AnnaBridge 189:f392fc9709a3 10191 #define NV_FSEC_MEEN_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 10192 #define NV_FSEC_MEEN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 10193 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
AnnaBridge 189:f392fc9709a3 10194 #define NV_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 10195 #define NV_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10196 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
AnnaBridge 189:f392fc9709a3 10197
AnnaBridge 189:f392fc9709a3 10198 /*! @name FOPT - Non-volatile Flash Option Register */
AnnaBridge 189:f392fc9709a3 10199 #define NV_FOPT_LPBOOT_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10200 #define NV_FOPT_LPBOOT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10201 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
AnnaBridge 189:f392fc9709a3 10202 #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10203 #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10204 #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
AnnaBridge 189:f392fc9709a3 10205 #define NV_FOPT_NMI_DIS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 10206 #define NV_FOPT_NMI_DIS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10207 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
AnnaBridge 189:f392fc9709a3 10208 #define NV_FOPT_FAST_INIT_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10209 #define NV_FOPT_FAST_INIT_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10210 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
AnnaBridge 189:f392fc9709a3 10211 #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 10212 #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10213 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
AnnaBridge 189:f392fc9709a3 10214
AnnaBridge 189:f392fc9709a3 10215
AnnaBridge 189:f392fc9709a3 10216 /*!
AnnaBridge 189:f392fc9709a3 10217 * @}
AnnaBridge 189:f392fc9709a3 10218 */ /* end of group NV_Register_Masks */
AnnaBridge 189:f392fc9709a3 10219
AnnaBridge 189:f392fc9709a3 10220
AnnaBridge 189:f392fc9709a3 10221 /* NV - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10222 /** Peripheral FTFA_FlashConfig base address */
AnnaBridge 189:f392fc9709a3 10223 #define FTFA_FlashConfig_BASE (0x400u)
AnnaBridge 189:f392fc9709a3 10224 /** Peripheral FTFA_FlashConfig base pointer */
AnnaBridge 189:f392fc9709a3 10225 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
AnnaBridge 189:f392fc9709a3 10226 /** Array initializer of NV peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10227 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
AnnaBridge 189:f392fc9709a3 10228 /** Array initializer of NV peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10229 #define NV_BASE_PTRS { FTFA_FlashConfig }
AnnaBridge 189:f392fc9709a3 10230
AnnaBridge 189:f392fc9709a3 10231 /*!
AnnaBridge 189:f392fc9709a3 10232 * @}
AnnaBridge 189:f392fc9709a3 10233 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 10234
AnnaBridge 189:f392fc9709a3 10235
AnnaBridge 189:f392fc9709a3 10236 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10237 -- OSC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10238 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10239
AnnaBridge 189:f392fc9709a3 10240 /*!
AnnaBridge 189:f392fc9709a3 10241 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10242 * @{
AnnaBridge 189:f392fc9709a3 10243 */
AnnaBridge 189:f392fc9709a3 10244
AnnaBridge 189:f392fc9709a3 10245 /** OSC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 10246 typedef struct {
AnnaBridge 189:f392fc9709a3 10247 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 10248 uint8_t RESERVED_0[1];
AnnaBridge 189:f392fc9709a3 10249 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 10250 } OSC_Type;
AnnaBridge 189:f392fc9709a3 10251
AnnaBridge 189:f392fc9709a3 10252 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10253 -- OSC Register Masks
AnnaBridge 189:f392fc9709a3 10254 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10255
AnnaBridge 189:f392fc9709a3 10256 /*!
AnnaBridge 189:f392fc9709a3 10257 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 189:f392fc9709a3 10258 * @{
AnnaBridge 189:f392fc9709a3 10259 */
AnnaBridge 189:f392fc9709a3 10260
AnnaBridge 189:f392fc9709a3 10261 /*! @name CR - OSC Control Register */
AnnaBridge 189:f392fc9709a3 10262 #define OSC_CR_SC16P_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10263 #define OSC_CR_SC16P_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10264 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
AnnaBridge 189:f392fc9709a3 10265 #define OSC_CR_SC8P_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10266 #define OSC_CR_SC8P_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10267 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
AnnaBridge 189:f392fc9709a3 10268 #define OSC_CR_SC4P_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 10269 #define OSC_CR_SC4P_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10270 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
AnnaBridge 189:f392fc9709a3 10271 #define OSC_CR_SC2P_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 10272 #define OSC_CR_SC2P_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 10273 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
AnnaBridge 189:f392fc9709a3 10274 #define OSC_CR_EREFSTEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10275 #define OSC_CR_EREFSTEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10276 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
AnnaBridge 189:f392fc9709a3 10277 #define OSC_CR_ERCLKEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 10278 #define OSC_CR_ERCLKEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 10279 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
AnnaBridge 189:f392fc9709a3 10280
AnnaBridge 189:f392fc9709a3 10281 /*! @name DIV - OSC_DIV */
AnnaBridge 189:f392fc9709a3 10282 #define OSC_DIV_ERPS_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 10283 #define OSC_DIV_ERPS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10284 #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
AnnaBridge 189:f392fc9709a3 10285
AnnaBridge 189:f392fc9709a3 10286
AnnaBridge 189:f392fc9709a3 10287 /*!
AnnaBridge 189:f392fc9709a3 10288 * @}
AnnaBridge 189:f392fc9709a3 10289 */ /* end of group OSC_Register_Masks */
AnnaBridge 189:f392fc9709a3 10290
AnnaBridge 189:f392fc9709a3 10291
AnnaBridge 189:f392fc9709a3 10292 /* OSC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10293 /** Peripheral OSC base address */
AnnaBridge 189:f392fc9709a3 10294 #define OSC_BASE (0x40065000u)
AnnaBridge 189:f392fc9709a3 10295 /** Peripheral OSC base pointer */
AnnaBridge 189:f392fc9709a3 10296 #define OSC ((OSC_Type *)OSC_BASE)
AnnaBridge 189:f392fc9709a3 10297 /** Array initializer of OSC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10298 #define OSC_BASE_ADDRS { OSC_BASE }
AnnaBridge 189:f392fc9709a3 10299 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10300 #define OSC_BASE_PTRS { OSC }
AnnaBridge 189:f392fc9709a3 10301
AnnaBridge 189:f392fc9709a3 10302 /*!
AnnaBridge 189:f392fc9709a3 10303 * @}
AnnaBridge 189:f392fc9709a3 10304 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 10305
AnnaBridge 189:f392fc9709a3 10306
AnnaBridge 189:f392fc9709a3 10307 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10308 -- OTFAD Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10309 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10310
AnnaBridge 189:f392fc9709a3 10311 /*!
AnnaBridge 189:f392fc9709a3 10312 * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10313 * @{
AnnaBridge 189:f392fc9709a3 10314 */
AnnaBridge 189:f392fc9709a3 10315
AnnaBridge 189:f392fc9709a3 10316 /** OTFAD - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 10317 typedef struct {
AnnaBridge 189:f392fc9709a3 10318 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 10319 __I uint32_t SR; /**< Status Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 10320 __IO uint32_t CRC; /**< Cyclic Redundancy Check Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 10321 uint8_t RESERVED_0[244];
AnnaBridge 189:f392fc9709a3 10322 struct { /* offset: 0x100, array step: 0x40 */
AnnaBridge 189:f392fc9709a3 10323 __IO uint32_t CTX_KEY[4]; /**< AES Key Word0..AES Key Word3, array offset: 0x100, array step: index*0x40, index2*0x4 */
AnnaBridge 189:f392fc9709a3 10324 __IO uint32_t CTX_CTR[2]; /**< AES Counter Word0..AES Counter Word1, array offset: 0x110, array step: index*0x40, index2*0x4 */
AnnaBridge 189:f392fc9709a3 10325 __IO uint32_t CTX_RGD[2]; /**< AES Region Descriptor Word0..AES Region Descriptor Word1, array offset: 0x118, array step: index*0x40, index2*0x4 */
AnnaBridge 189:f392fc9709a3 10326 uint8_t RESERVED_0[32];
AnnaBridge 189:f392fc9709a3 10327 } CTX[4];
AnnaBridge 189:f392fc9709a3 10328 } OTFAD_Type;
AnnaBridge 189:f392fc9709a3 10329
AnnaBridge 189:f392fc9709a3 10330 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10331 -- OTFAD Register Masks
AnnaBridge 189:f392fc9709a3 10332 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10333
AnnaBridge 189:f392fc9709a3 10334 /*!
AnnaBridge 189:f392fc9709a3 10335 * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
AnnaBridge 189:f392fc9709a3 10336 * @{
AnnaBridge 189:f392fc9709a3 10337 */
AnnaBridge 189:f392fc9709a3 10338
AnnaBridge 189:f392fc9709a3 10339 /*! @name CR - Control Register */
AnnaBridge 189:f392fc9709a3 10340 #define OTFAD_CR_FSVM_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 10341 #define OTFAD_CR_FSVM_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10342 #define OTFAD_CR_FSVM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FSVM_SHIFT)) & OTFAD_CR_FSVM_MASK)
AnnaBridge 189:f392fc9709a3 10343 #define OTFAD_CR_FLDM_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 10344 #define OTFAD_CR_FLDM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 10345 #define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
AnnaBridge 189:f392fc9709a3 10346 #define OTFAD_CR_RRAE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 10347 #define OTFAD_CR_RRAE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 10348 #define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
AnnaBridge 189:f392fc9709a3 10349 #define OTFAD_CR_CCTX_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 10350 #define OTFAD_CR_CCTX_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10351 #define OTFAD_CR_CCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CCTX_SHIFT)) & OTFAD_CR_CCTX_MASK)
AnnaBridge 189:f392fc9709a3 10352 #define OTFAD_CR_CRCE_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 10353 #define OTFAD_CR_CRCE_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 10354 #define OTFAD_CR_CRCE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCE_SHIFT)) & OTFAD_CR_CRCE_MASK)
AnnaBridge 189:f392fc9709a3 10355 #define OTFAD_CR_CRCI_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 10356 #define OTFAD_CR_CRCI_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 10357 #define OTFAD_CR_CRCI(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCI_SHIFT)) & OTFAD_CR_CRCI_MASK)
AnnaBridge 189:f392fc9709a3 10358 #define OTFAD_CR_GE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 10359 #define OTFAD_CR_GE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 10360 #define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
AnnaBridge 189:f392fc9709a3 10361
AnnaBridge 189:f392fc9709a3 10362 /*! @name SR - Status Register */
AnnaBridge 189:f392fc9709a3 10363 #define OTFAD_SR_MDPCP_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10364 #define OTFAD_SR_MDPCP_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10365 #define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
AnnaBridge 189:f392fc9709a3 10366 #define OTFAD_SR_MODE_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 10367 #define OTFAD_SR_MODE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10368 #define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
AnnaBridge 189:f392fc9709a3 10369 #define OTFAD_SR_NCTX_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 10370 #define OTFAD_SR_NCTX_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 10371 #define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
AnnaBridge 189:f392fc9709a3 10372 #define OTFAD_SR_HRL_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 10373 #define OTFAD_SR_HRL_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 10374 #define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
AnnaBridge 189:f392fc9709a3 10375 #define OTFAD_SR_RRAM_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 10376 #define OTFAD_SR_RRAM_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 10377 #define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
AnnaBridge 189:f392fc9709a3 10378 #define OTFAD_SR_GEM_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 10379 #define OTFAD_SR_GEM_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 10380 #define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
AnnaBridge 189:f392fc9709a3 10381
AnnaBridge 189:f392fc9709a3 10382 /*! @name CRC - Cyclic Redundancy Check Register */
AnnaBridge 189:f392fc9709a3 10383 #define OTFAD_CRC_CRCD_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10384 #define OTFAD_CRC_CRCD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10385 #define OTFAD_CRC_CRCD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CRC_CRCD_SHIFT)) & OTFAD_CRC_CRCD_MASK)
AnnaBridge 189:f392fc9709a3 10386
AnnaBridge 189:f392fc9709a3 10387 /*! @name CTX_KEY - AES Key Word0..AES Key Word3 */
AnnaBridge 189:f392fc9709a3 10388 #define OTFAD_CTX_KEY_W0KEY_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10389 #define OTFAD_CTX_KEY_W0KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10390 #define OTFAD_CTX_KEY_W0KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W0KEY_SHIFT)) & OTFAD_CTX_KEY_W0KEY_MASK)
AnnaBridge 189:f392fc9709a3 10391 #define OTFAD_CTX_KEY_W1KEY_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10392 #define OTFAD_CTX_KEY_W1KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10393 #define OTFAD_CTX_KEY_W1KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W1KEY_SHIFT)) & OTFAD_CTX_KEY_W1KEY_MASK)
AnnaBridge 189:f392fc9709a3 10394 #define OTFAD_CTX_KEY_W2KEY_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10395 #define OTFAD_CTX_KEY_W2KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10396 #define OTFAD_CTX_KEY_W2KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W2KEY_SHIFT)) & OTFAD_CTX_KEY_W2KEY_MASK)
AnnaBridge 189:f392fc9709a3 10397 #define OTFAD_CTX_KEY_W3KEY_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10398 #define OTFAD_CTX_KEY_W3KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10399 #define OTFAD_CTX_KEY_W3KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_KEY_W3KEY_SHIFT)) & OTFAD_CTX_KEY_W3KEY_MASK)
AnnaBridge 189:f392fc9709a3 10400
AnnaBridge 189:f392fc9709a3 10401 /* The count of OTFAD_CTX_KEY */
AnnaBridge 189:f392fc9709a3 10402 #define OTFAD_CTX_KEY_COUNT (4U)
AnnaBridge 189:f392fc9709a3 10403
AnnaBridge 189:f392fc9709a3 10404 /* The count of OTFAD_CTX_KEY */
AnnaBridge 189:f392fc9709a3 10405 #define OTFAD_CTX_KEY_COUNT2 (4U)
AnnaBridge 189:f392fc9709a3 10406
AnnaBridge 189:f392fc9709a3 10407 /*! @name CTX_CTR - AES Counter Word0..AES Counter Word1 */
AnnaBridge 189:f392fc9709a3 10408 #define OTFAD_CTX_CTR_W0CTR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10409 #define OTFAD_CTX_CTR_W0CTR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10410 #define OTFAD_CTX_CTR_W0CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_CTR_W0CTR_SHIFT)) & OTFAD_CTX_CTR_W0CTR_MASK)
AnnaBridge 189:f392fc9709a3 10411 #define OTFAD_CTX_CTR_W1CTR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10412 #define OTFAD_CTX_CTR_W1CTR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10413 #define OTFAD_CTX_CTR_W1CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_CTR_W1CTR_SHIFT)) & OTFAD_CTX_CTR_W1CTR_MASK)
AnnaBridge 189:f392fc9709a3 10414
AnnaBridge 189:f392fc9709a3 10415 /* The count of OTFAD_CTX_CTR */
AnnaBridge 189:f392fc9709a3 10416 #define OTFAD_CTX_CTR_COUNT (4U)
AnnaBridge 189:f392fc9709a3 10417
AnnaBridge 189:f392fc9709a3 10418 /* The count of OTFAD_CTX_CTR */
AnnaBridge 189:f392fc9709a3 10419 #define OTFAD_CTX_CTR_COUNT2 (2U)
AnnaBridge 189:f392fc9709a3 10420
AnnaBridge 189:f392fc9709a3 10421 /*! @name CTX_RGD - AES Region Descriptor Word0..AES Region Descriptor Word1 */
AnnaBridge 189:f392fc9709a3 10422 #define OTFAD_CTX_RGD_VLD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10423 #define OTFAD_CTX_RGD_VLD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10424 #define OTFAD_CTX_RGD_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_VLD_SHIFT)) & OTFAD_CTX_RGD_VLD_MASK)
AnnaBridge 189:f392fc9709a3 10425 #define OTFAD_CTX_RGD_ADE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10426 #define OTFAD_CTX_RGD_ADE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10427 #define OTFAD_CTX_RGD_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_ADE_SHIFT)) & OTFAD_CTX_RGD_ADE_MASK)
AnnaBridge 189:f392fc9709a3 10428 #define OTFAD_CTX_RGD_RO_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 10429 #define OTFAD_CTX_RGD_RO_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10430 #define OTFAD_CTX_RGD_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_RO_SHIFT)) & OTFAD_CTX_RGD_RO_MASK)
AnnaBridge 189:f392fc9709a3 10431 #define OTFAD_CTX_RGD_ENDADDR_MASK (0xFFFFFC00U)
AnnaBridge 189:f392fc9709a3 10432 #define OTFAD_CTX_RGD_ENDADDR_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 10433 #define OTFAD_CTX_RGD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_ENDADDR_SHIFT)) & OTFAD_CTX_RGD_ENDADDR_MASK)
AnnaBridge 189:f392fc9709a3 10434 #define OTFAD_CTX_RGD_SRTADDR_MASK (0xFFFFFC00U)
AnnaBridge 189:f392fc9709a3 10435 #define OTFAD_CTX_RGD_SRTADDR_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 10436 #define OTFAD_CTX_RGD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTX_RGD_SRTADDR_SHIFT)) & OTFAD_CTX_RGD_SRTADDR_MASK)
AnnaBridge 189:f392fc9709a3 10437
AnnaBridge 189:f392fc9709a3 10438 /* The count of OTFAD_CTX_RGD */
AnnaBridge 189:f392fc9709a3 10439 #define OTFAD_CTX_RGD_COUNT (4U)
AnnaBridge 189:f392fc9709a3 10440
AnnaBridge 189:f392fc9709a3 10441 /* The count of OTFAD_CTX_RGD */
AnnaBridge 189:f392fc9709a3 10442 #define OTFAD_CTX_RGD_COUNT2 (2U)
AnnaBridge 189:f392fc9709a3 10443
AnnaBridge 189:f392fc9709a3 10444
AnnaBridge 189:f392fc9709a3 10445 /*!
AnnaBridge 189:f392fc9709a3 10446 * @}
AnnaBridge 189:f392fc9709a3 10447 */ /* end of group OTFAD_Register_Masks */
AnnaBridge 189:f392fc9709a3 10448
AnnaBridge 189:f392fc9709a3 10449
AnnaBridge 189:f392fc9709a3 10450 /* OTFAD - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10451 /** Peripheral OTFAD base address */
AnnaBridge 189:f392fc9709a3 10452 #define OTFAD_BASE (0x400DAC00u)
AnnaBridge 189:f392fc9709a3 10453 /** Peripheral OTFAD base pointer */
AnnaBridge 189:f392fc9709a3 10454 #define OTFAD ((OTFAD_Type *)OTFAD_BASE)
AnnaBridge 189:f392fc9709a3 10455 /** Array initializer of OTFAD peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10456 #define OTFAD_BASE_ADDRS { OTFAD_BASE }
AnnaBridge 189:f392fc9709a3 10457 /** Array initializer of OTFAD peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10458 #define OTFAD_BASE_PTRS { OTFAD }
AnnaBridge 189:f392fc9709a3 10459
AnnaBridge 189:f392fc9709a3 10460 /*!
AnnaBridge 189:f392fc9709a3 10461 * @}
AnnaBridge 189:f392fc9709a3 10462 */ /* end of group OTFAD_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 10463
AnnaBridge 189:f392fc9709a3 10464
AnnaBridge 189:f392fc9709a3 10465 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10466 -- PDB Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10467 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10468
AnnaBridge 189:f392fc9709a3 10469 /*!
AnnaBridge 189:f392fc9709a3 10470 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10471 * @{
AnnaBridge 189:f392fc9709a3 10472 */
AnnaBridge 189:f392fc9709a3 10473
AnnaBridge 189:f392fc9709a3 10474 /** PDB - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 10475 typedef struct {
AnnaBridge 189:f392fc9709a3 10476 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 10477 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 10478 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 10479 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 10480 struct { /* offset: 0x10, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10481 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10482 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10483 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x10, index2*0x4 */
AnnaBridge 189:f392fc9709a3 10484 } CH[1];
AnnaBridge 189:f392fc9709a3 10485 uint8_t RESERVED_0[304];
AnnaBridge 189:f392fc9709a3 10486 struct { /* offset: 0x150, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 10487 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 10488 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 10489 } DAC[1];
AnnaBridge 189:f392fc9709a3 10490 uint8_t RESERVED_1[56];
AnnaBridge 189:f392fc9709a3 10491 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
AnnaBridge 189:f392fc9709a3 10492 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 10493 } PDB_Type;
AnnaBridge 189:f392fc9709a3 10494
AnnaBridge 189:f392fc9709a3 10495 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10496 -- PDB Register Masks
AnnaBridge 189:f392fc9709a3 10497 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10498
AnnaBridge 189:f392fc9709a3 10499 /*!
AnnaBridge 189:f392fc9709a3 10500 * @addtogroup PDB_Register_Masks PDB Register Masks
AnnaBridge 189:f392fc9709a3 10501 * @{
AnnaBridge 189:f392fc9709a3 10502 */
AnnaBridge 189:f392fc9709a3 10503
AnnaBridge 189:f392fc9709a3 10504 /*! @name SC - Status and Control register */
AnnaBridge 189:f392fc9709a3 10505 #define PDB_SC_LDOK_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10506 #define PDB_SC_LDOK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10507 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
AnnaBridge 189:f392fc9709a3 10508 #define PDB_SC_CONT_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10509 #define PDB_SC_CONT_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10510 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
AnnaBridge 189:f392fc9709a3 10511 #define PDB_SC_MULT_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 10512 #define PDB_SC_MULT_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10513 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
AnnaBridge 189:f392fc9709a3 10514 #define PDB_SC_PDBIE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10515 #define PDB_SC_PDBIE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10516 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
AnnaBridge 189:f392fc9709a3 10517 #define PDB_SC_PDBIF_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 10518 #define PDB_SC_PDBIF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10519 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
AnnaBridge 189:f392fc9709a3 10520 #define PDB_SC_PDBEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 10521 #define PDB_SC_PDBEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 10522 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
AnnaBridge 189:f392fc9709a3 10523 #define PDB_SC_TRGSEL_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 10524 #define PDB_SC_TRGSEL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 10525 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
AnnaBridge 189:f392fc9709a3 10526 #define PDB_SC_PRESCALER_MASK (0x7000U)
AnnaBridge 189:f392fc9709a3 10527 #define PDB_SC_PRESCALER_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 10528 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
AnnaBridge 189:f392fc9709a3 10529 #define PDB_SC_DMAEN_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 10530 #define PDB_SC_DMAEN_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 10531 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
AnnaBridge 189:f392fc9709a3 10532 #define PDB_SC_SWTRIG_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 10533 #define PDB_SC_SWTRIG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10534 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
AnnaBridge 189:f392fc9709a3 10535 #define PDB_SC_PDBEIE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 10536 #define PDB_SC_PDBEIE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 10537 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
AnnaBridge 189:f392fc9709a3 10538 #define PDB_SC_LDMOD_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 10539 #define PDB_SC_LDMOD_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 10540 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
AnnaBridge 189:f392fc9709a3 10541
AnnaBridge 189:f392fc9709a3 10542 /*! @name MOD - Modulus register */
AnnaBridge 189:f392fc9709a3 10543 #define PDB_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10544 #define PDB_MOD_MOD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10545 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
AnnaBridge 189:f392fc9709a3 10546
AnnaBridge 189:f392fc9709a3 10547 /*! @name CNT - Counter register */
AnnaBridge 189:f392fc9709a3 10548 #define PDB_CNT_CNT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10549 #define PDB_CNT_CNT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10550 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
AnnaBridge 189:f392fc9709a3 10551
AnnaBridge 189:f392fc9709a3 10552 /*! @name IDLY - Interrupt Delay register */
AnnaBridge 189:f392fc9709a3 10553 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10554 #define PDB_IDLY_IDLY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10555 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
AnnaBridge 189:f392fc9709a3 10556
AnnaBridge 189:f392fc9709a3 10557 /*! @name C1 - Channel n Control register 1 */
AnnaBridge 189:f392fc9709a3 10558 #define PDB_C1_EN_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10559 #define PDB_C1_EN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10560 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
AnnaBridge 189:f392fc9709a3 10561 #define PDB_C1_TOS_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 10562 #define PDB_C1_TOS_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 10563 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
AnnaBridge 189:f392fc9709a3 10564 #define PDB_C1_BB_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 10565 #define PDB_C1_BB_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10566 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
AnnaBridge 189:f392fc9709a3 10567
AnnaBridge 189:f392fc9709a3 10568 /* The count of PDB_C1 */
AnnaBridge 189:f392fc9709a3 10569 #define PDB_C1_COUNT (1U)
AnnaBridge 189:f392fc9709a3 10570
AnnaBridge 189:f392fc9709a3 10571 /*! @name S - Channel n Status register */
AnnaBridge 189:f392fc9709a3 10572 #define PDB_S_ERR_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10573 #define PDB_S_ERR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10574 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
AnnaBridge 189:f392fc9709a3 10575 #define PDB_S_CF_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 10576 #define PDB_S_CF_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10577 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
AnnaBridge 189:f392fc9709a3 10578
AnnaBridge 189:f392fc9709a3 10579 /* The count of PDB_S */
AnnaBridge 189:f392fc9709a3 10580 #define PDB_S_COUNT (1U)
AnnaBridge 189:f392fc9709a3 10581
AnnaBridge 189:f392fc9709a3 10582 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
AnnaBridge 189:f392fc9709a3 10583 #define PDB_DLY_DLY_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10584 #define PDB_DLY_DLY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10585 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
AnnaBridge 189:f392fc9709a3 10586
AnnaBridge 189:f392fc9709a3 10587 /* The count of PDB_DLY */
AnnaBridge 189:f392fc9709a3 10588 #define PDB_DLY_COUNT (1U)
AnnaBridge 189:f392fc9709a3 10589
AnnaBridge 189:f392fc9709a3 10590 /* The count of PDB_DLY */
AnnaBridge 189:f392fc9709a3 10591 #define PDB_DLY_COUNT2 (2U)
AnnaBridge 189:f392fc9709a3 10592
AnnaBridge 189:f392fc9709a3 10593 /*! @name INTC - DAC Interval Trigger n Control register */
AnnaBridge 189:f392fc9709a3 10594 #define PDB_INTC_TOE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10595 #define PDB_INTC_TOE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10596 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
AnnaBridge 189:f392fc9709a3 10597 #define PDB_INTC_EXT_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10598 #define PDB_INTC_EXT_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10599 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
AnnaBridge 189:f392fc9709a3 10600
AnnaBridge 189:f392fc9709a3 10601 /* The count of PDB_INTC */
AnnaBridge 189:f392fc9709a3 10602 #define PDB_INTC_COUNT (1U)
AnnaBridge 189:f392fc9709a3 10603
AnnaBridge 189:f392fc9709a3 10604 /*! @name INT - DAC Interval n register */
AnnaBridge 189:f392fc9709a3 10605 #define PDB_INT_INT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10606 #define PDB_INT_INT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10607 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
AnnaBridge 189:f392fc9709a3 10608
AnnaBridge 189:f392fc9709a3 10609 /* The count of PDB_INT */
AnnaBridge 189:f392fc9709a3 10610 #define PDB_INT_COUNT (1U)
AnnaBridge 189:f392fc9709a3 10611
AnnaBridge 189:f392fc9709a3 10612 /*! @name POEN - Pulse-Out n Enable register */
AnnaBridge 189:f392fc9709a3 10613 #define PDB_POEN_POEN_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 10614 #define PDB_POEN_POEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10615 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
AnnaBridge 189:f392fc9709a3 10616
AnnaBridge 189:f392fc9709a3 10617 /*! @name PODLY - Pulse-Out n Delay register */
AnnaBridge 189:f392fc9709a3 10618 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10619 #define PDB_PODLY_DLY2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10620 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
AnnaBridge 189:f392fc9709a3 10621 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 10622 #define PDB_PODLY_DLY1_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10623 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
AnnaBridge 189:f392fc9709a3 10624
AnnaBridge 189:f392fc9709a3 10625 /* The count of PDB_PODLY */
AnnaBridge 189:f392fc9709a3 10626 #define PDB_PODLY_COUNT (2U)
AnnaBridge 189:f392fc9709a3 10627
AnnaBridge 189:f392fc9709a3 10628
AnnaBridge 189:f392fc9709a3 10629 /*!
AnnaBridge 189:f392fc9709a3 10630 * @}
AnnaBridge 189:f392fc9709a3 10631 */ /* end of group PDB_Register_Masks */
AnnaBridge 189:f392fc9709a3 10632
AnnaBridge 189:f392fc9709a3 10633
AnnaBridge 189:f392fc9709a3 10634 /* PDB - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10635 /** Peripheral PDB0 base address */
AnnaBridge 189:f392fc9709a3 10636 #define PDB0_BASE (0x40036000u)
AnnaBridge 189:f392fc9709a3 10637 /** Peripheral PDB0 base pointer */
AnnaBridge 189:f392fc9709a3 10638 #define PDB0 ((PDB_Type *)PDB0_BASE)
AnnaBridge 189:f392fc9709a3 10639 /** Array initializer of PDB peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10640 #define PDB_BASE_ADDRS { PDB0_BASE }
AnnaBridge 189:f392fc9709a3 10641 /** Array initializer of PDB peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10642 #define PDB_BASE_PTRS { PDB0 }
AnnaBridge 189:f392fc9709a3 10643 /** Interrupt vectors for the PDB peripheral type */
AnnaBridge 189:f392fc9709a3 10644 #define PDB_IRQS { PDB0_IRQn }
AnnaBridge 189:f392fc9709a3 10645
AnnaBridge 189:f392fc9709a3 10646 /*!
AnnaBridge 189:f392fc9709a3 10647 * @}
AnnaBridge 189:f392fc9709a3 10648 */ /* end of group PDB_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 10649
AnnaBridge 189:f392fc9709a3 10650
AnnaBridge 189:f392fc9709a3 10651 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10652 -- PIT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10653 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10654
AnnaBridge 189:f392fc9709a3 10655 /*!
AnnaBridge 189:f392fc9709a3 10656 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10657 * @{
AnnaBridge 189:f392fc9709a3 10658 */
AnnaBridge 189:f392fc9709a3 10659
AnnaBridge 189:f392fc9709a3 10660 /** PIT - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 10661 typedef struct {
AnnaBridge 189:f392fc9709a3 10662 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 10663 uint8_t RESERVED_0[252];
AnnaBridge 189:f392fc9709a3 10664 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10665 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10666 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10667 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10668 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 189:f392fc9709a3 10669 } CHANNEL[4];
AnnaBridge 189:f392fc9709a3 10670 } PIT_Type;
AnnaBridge 189:f392fc9709a3 10671
AnnaBridge 189:f392fc9709a3 10672 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10673 -- PIT Register Masks
AnnaBridge 189:f392fc9709a3 10674 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10675
AnnaBridge 189:f392fc9709a3 10676 /*!
AnnaBridge 189:f392fc9709a3 10677 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 189:f392fc9709a3 10678 * @{
AnnaBridge 189:f392fc9709a3 10679 */
AnnaBridge 189:f392fc9709a3 10680
AnnaBridge 189:f392fc9709a3 10681 /*! @name MCR - PIT Module Control Register */
AnnaBridge 189:f392fc9709a3 10682 #define PIT_MCR_FRZ_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10683 #define PIT_MCR_FRZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10684 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
AnnaBridge 189:f392fc9709a3 10685 #define PIT_MCR_MDIS_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10686 #define PIT_MCR_MDIS_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10687 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
AnnaBridge 189:f392fc9709a3 10688
AnnaBridge 189:f392fc9709a3 10689 /*! @name LDVAL - Timer Load Value Register */
AnnaBridge 189:f392fc9709a3 10690 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10691 #define PIT_LDVAL_TSV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10692 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
AnnaBridge 189:f392fc9709a3 10693
AnnaBridge 189:f392fc9709a3 10694 /* The count of PIT_LDVAL */
AnnaBridge 189:f392fc9709a3 10695 #define PIT_LDVAL_COUNT (4U)
AnnaBridge 189:f392fc9709a3 10696
AnnaBridge 189:f392fc9709a3 10697 /*! @name CVAL - Current Timer Value Register */
AnnaBridge 189:f392fc9709a3 10698 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10699 #define PIT_CVAL_TVL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10700 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
AnnaBridge 189:f392fc9709a3 10701
AnnaBridge 189:f392fc9709a3 10702 /* The count of PIT_CVAL */
AnnaBridge 189:f392fc9709a3 10703 #define PIT_CVAL_COUNT (4U)
AnnaBridge 189:f392fc9709a3 10704
AnnaBridge 189:f392fc9709a3 10705 /*! @name TCTRL - Timer Control Register */
AnnaBridge 189:f392fc9709a3 10706 #define PIT_TCTRL_TEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10707 #define PIT_TCTRL_TEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10708 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
AnnaBridge 189:f392fc9709a3 10709 #define PIT_TCTRL_TIE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10710 #define PIT_TCTRL_TIE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10711 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
AnnaBridge 189:f392fc9709a3 10712 #define PIT_TCTRL_CHN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 10713 #define PIT_TCTRL_CHN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10714 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
AnnaBridge 189:f392fc9709a3 10715
AnnaBridge 189:f392fc9709a3 10716 /* The count of PIT_TCTRL */
AnnaBridge 189:f392fc9709a3 10717 #define PIT_TCTRL_COUNT (4U)
AnnaBridge 189:f392fc9709a3 10718
AnnaBridge 189:f392fc9709a3 10719 /*! @name TFLG - Timer Flag Register */
AnnaBridge 189:f392fc9709a3 10720 #define PIT_TFLG_TIF_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10721 #define PIT_TFLG_TIF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10722 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
AnnaBridge 189:f392fc9709a3 10723
AnnaBridge 189:f392fc9709a3 10724 /* The count of PIT_TFLG */
AnnaBridge 189:f392fc9709a3 10725 #define PIT_TFLG_COUNT (4U)
AnnaBridge 189:f392fc9709a3 10726
AnnaBridge 189:f392fc9709a3 10727
AnnaBridge 189:f392fc9709a3 10728 /*!
AnnaBridge 189:f392fc9709a3 10729 * @}
AnnaBridge 189:f392fc9709a3 10730 */ /* end of group PIT_Register_Masks */
AnnaBridge 189:f392fc9709a3 10731
AnnaBridge 189:f392fc9709a3 10732
AnnaBridge 189:f392fc9709a3 10733 /* PIT - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10734 /** Peripheral PIT0 base address */
AnnaBridge 189:f392fc9709a3 10735 #define PIT0_BASE (0x40037000u)
AnnaBridge 189:f392fc9709a3 10736 /** Peripheral PIT0 base pointer */
AnnaBridge 189:f392fc9709a3 10737 #define PIT0 ((PIT_Type *)PIT0_BASE)
AnnaBridge 189:f392fc9709a3 10738 /** Array initializer of PIT peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10739 #define PIT_BASE_ADDRS { PIT0_BASE }
AnnaBridge 189:f392fc9709a3 10740 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10741 #define PIT_BASE_PTRS { PIT0 }
AnnaBridge 189:f392fc9709a3 10742 /** Interrupt vectors for the PIT peripheral type */
AnnaBridge 189:f392fc9709a3 10743 #define PIT_IRQS { PIT0CH0_IRQn, PIT0CH1_IRQn, PIT0CH2_IRQn, PIT0CH3_IRQn }
AnnaBridge 189:f392fc9709a3 10744
AnnaBridge 189:f392fc9709a3 10745 /*!
AnnaBridge 189:f392fc9709a3 10746 * @}
AnnaBridge 189:f392fc9709a3 10747 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 10748
AnnaBridge 189:f392fc9709a3 10749
AnnaBridge 189:f392fc9709a3 10750 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10751 -- PMC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10752 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10753
AnnaBridge 189:f392fc9709a3 10754 /*!
AnnaBridge 189:f392fc9709a3 10755 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10756 * @{
AnnaBridge 189:f392fc9709a3 10757 */
AnnaBridge 189:f392fc9709a3 10758
AnnaBridge 189:f392fc9709a3 10759 /** PMC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 10760 typedef struct {
AnnaBridge 189:f392fc9709a3 10761 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 10762 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 10763 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 10764 uint8_t RESERVED_0[8];
AnnaBridge 189:f392fc9709a3 10765 __IO uint8_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0xB */
AnnaBridge 189:f392fc9709a3 10766 } PMC_Type;
AnnaBridge 189:f392fc9709a3 10767
AnnaBridge 189:f392fc9709a3 10768 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10769 -- PMC Register Masks
AnnaBridge 189:f392fc9709a3 10770 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10771
AnnaBridge 189:f392fc9709a3 10772 /*!
AnnaBridge 189:f392fc9709a3 10773 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 189:f392fc9709a3 10774 * @{
AnnaBridge 189:f392fc9709a3 10775 */
AnnaBridge 189:f392fc9709a3 10776
AnnaBridge 189:f392fc9709a3 10777 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
AnnaBridge 189:f392fc9709a3 10778 #define PMC_LVDSC1_LVDV_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 10779 #define PMC_LVDSC1_LVDV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10780 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
AnnaBridge 189:f392fc9709a3 10781 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 10782 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 10783 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
AnnaBridge 189:f392fc9709a3 10784 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10785 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10786 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
AnnaBridge 189:f392fc9709a3 10787 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 10788 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10789 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
AnnaBridge 189:f392fc9709a3 10790 #define PMC_LVDSC1_LVDF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 10791 #define PMC_LVDSC1_LVDF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 10792 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
AnnaBridge 189:f392fc9709a3 10793
AnnaBridge 189:f392fc9709a3 10794 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
AnnaBridge 189:f392fc9709a3 10795 #define PMC_LVDSC2_LVWV_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 10796 #define PMC_LVDSC2_LVWV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10797 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
AnnaBridge 189:f392fc9709a3 10798 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10799 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10800 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
AnnaBridge 189:f392fc9709a3 10801 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 10802 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10803 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
AnnaBridge 189:f392fc9709a3 10804 #define PMC_LVDSC2_LVWF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 10805 #define PMC_LVDSC2_LVWF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 10806 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
AnnaBridge 189:f392fc9709a3 10807
AnnaBridge 189:f392fc9709a3 10808 /*! @name REGSC - Regulator Status And Control register */
AnnaBridge 189:f392fc9709a3 10809 #define PMC_REGSC_BGBE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10810 #define PMC_REGSC_BGBE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10811 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
AnnaBridge 189:f392fc9709a3 10812 #define PMC_REGSC_REGONS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 10813 #define PMC_REGSC_REGONS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10814 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
AnnaBridge 189:f392fc9709a3 10815 #define PMC_REGSC_ACKISO_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 10816 #define PMC_REGSC_ACKISO_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 10817 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
AnnaBridge 189:f392fc9709a3 10818 #define PMC_REGSC_BGEN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 10819 #define PMC_REGSC_BGEN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 10820 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
AnnaBridge 189:f392fc9709a3 10821
AnnaBridge 189:f392fc9709a3 10822 /*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */
AnnaBridge 189:f392fc9709a3 10823 #define PMC_HVDSC1_HVDV_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10824 #define PMC_HVDSC1_HVDV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10825 #define PMC_HVDSC1_HVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK)
AnnaBridge 189:f392fc9709a3 10826 #define PMC_HVDSC1_HVDRE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 10827 #define PMC_HVDSC1_HVDRE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 10828 #define PMC_HVDSC1_HVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK)
AnnaBridge 189:f392fc9709a3 10829 #define PMC_HVDSC1_HVDIE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10830 #define PMC_HVDSC1_HVDIE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10831 #define PMC_HVDSC1_HVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK)
AnnaBridge 189:f392fc9709a3 10832 #define PMC_HVDSC1_HVDACK_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 10833 #define PMC_HVDSC1_HVDACK_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10834 #define PMC_HVDSC1_HVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK)
AnnaBridge 189:f392fc9709a3 10835 #define PMC_HVDSC1_HVDF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 10836 #define PMC_HVDSC1_HVDF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 10837 #define PMC_HVDSC1_HVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK)
AnnaBridge 189:f392fc9709a3 10838
AnnaBridge 189:f392fc9709a3 10839
AnnaBridge 189:f392fc9709a3 10840 /*!
AnnaBridge 189:f392fc9709a3 10841 * @}
AnnaBridge 189:f392fc9709a3 10842 */ /* end of group PMC_Register_Masks */
AnnaBridge 189:f392fc9709a3 10843
AnnaBridge 189:f392fc9709a3 10844
AnnaBridge 189:f392fc9709a3 10845 /* PMC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10846 /** Peripheral PMC base address */
AnnaBridge 189:f392fc9709a3 10847 #define PMC_BASE (0x4007D000u)
AnnaBridge 189:f392fc9709a3 10848 /** Peripheral PMC base pointer */
AnnaBridge 189:f392fc9709a3 10849 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 189:f392fc9709a3 10850 /** Array initializer of PMC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10851 #define PMC_BASE_ADDRS { PMC_BASE }
AnnaBridge 189:f392fc9709a3 10852 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10853 #define PMC_BASE_PTRS { PMC }
AnnaBridge 189:f392fc9709a3 10854 /** Interrupt vectors for the PMC peripheral type */
AnnaBridge 189:f392fc9709a3 10855 #define PMC_IRQS { LVD_LVW_IRQn }
AnnaBridge 189:f392fc9709a3 10856
AnnaBridge 189:f392fc9709a3 10857 /*!
AnnaBridge 189:f392fc9709a3 10858 * @}
AnnaBridge 189:f392fc9709a3 10859 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 10860
AnnaBridge 189:f392fc9709a3 10861
AnnaBridge 189:f392fc9709a3 10862 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10863 -- PORT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10864 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10865
AnnaBridge 189:f392fc9709a3 10866 /*!
AnnaBridge 189:f392fc9709a3 10867 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 10868 * @{
AnnaBridge 189:f392fc9709a3 10869 */
AnnaBridge 189:f392fc9709a3 10870
AnnaBridge 189:f392fc9709a3 10871 /** PORT - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 10872 typedef struct {
AnnaBridge 189:f392fc9709a3 10873 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 10874 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 10875 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 189:f392fc9709a3 10876 uint8_t RESERVED_0[24];
AnnaBridge 189:f392fc9709a3 10877 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 189:f392fc9709a3 10878 uint8_t RESERVED_1[28];
AnnaBridge 189:f392fc9709a3 10879 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
AnnaBridge 189:f392fc9709a3 10880 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
AnnaBridge 189:f392fc9709a3 10881 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
AnnaBridge 189:f392fc9709a3 10882 } PORT_Type;
AnnaBridge 189:f392fc9709a3 10883
AnnaBridge 189:f392fc9709a3 10884 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 10885 -- PORT Register Masks
AnnaBridge 189:f392fc9709a3 10886 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 10887
AnnaBridge 189:f392fc9709a3 10888 /*!
AnnaBridge 189:f392fc9709a3 10889 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 189:f392fc9709a3 10890 * @{
AnnaBridge 189:f392fc9709a3 10891 */
AnnaBridge 189:f392fc9709a3 10892
AnnaBridge 189:f392fc9709a3 10893 /*! @name PCR - Pin Control Register n */
AnnaBridge 189:f392fc9709a3 10894 #define PORT_PCR_PS_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10895 #define PORT_PCR_PS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10896 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
AnnaBridge 189:f392fc9709a3 10897 #define PORT_PCR_PE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 10898 #define PORT_PCR_PE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 10899 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
AnnaBridge 189:f392fc9709a3 10900 #define PORT_PCR_SRE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 10901 #define PORT_PCR_SRE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 10902 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
AnnaBridge 189:f392fc9709a3 10903 #define PORT_PCR_PFE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 10904 #define PORT_PCR_PFE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 10905 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
AnnaBridge 189:f392fc9709a3 10906 #define PORT_PCR_ODE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 10907 #define PORT_PCR_ODE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 10908 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
AnnaBridge 189:f392fc9709a3 10909 #define PORT_PCR_DSE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 10910 #define PORT_PCR_DSE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 10911 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
AnnaBridge 189:f392fc9709a3 10912 #define PORT_PCR_MUX_MASK (0x700U)
AnnaBridge 189:f392fc9709a3 10913 #define PORT_PCR_MUX_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 10914 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
AnnaBridge 189:f392fc9709a3 10915 #define PORT_PCR_LK_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 10916 #define PORT_PCR_LK_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 10917 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
AnnaBridge 189:f392fc9709a3 10918 #define PORT_PCR_IRQC_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 10919 #define PORT_PCR_IRQC_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10920 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
AnnaBridge 189:f392fc9709a3 10921 #define PORT_PCR_ISF_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 10922 #define PORT_PCR_ISF_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 10923 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
AnnaBridge 189:f392fc9709a3 10924
AnnaBridge 189:f392fc9709a3 10925 /* The count of PORT_PCR */
AnnaBridge 189:f392fc9709a3 10926 #define PORT_PCR_COUNT (32U)
AnnaBridge 189:f392fc9709a3 10927
AnnaBridge 189:f392fc9709a3 10928 /*! @name GPCLR - Global Pin Control Low Register */
AnnaBridge 189:f392fc9709a3 10929 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10930 #define PORT_GPCLR_GPWD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10931 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
AnnaBridge 189:f392fc9709a3 10932 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 10933 #define PORT_GPCLR_GPWE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10934 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
AnnaBridge 189:f392fc9709a3 10935
AnnaBridge 189:f392fc9709a3 10936 /*! @name GPCHR - Global Pin Control High Register */
AnnaBridge 189:f392fc9709a3 10937 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 10938 #define PORT_GPCHR_GPWD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10939 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
AnnaBridge 189:f392fc9709a3 10940 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 10941 #define PORT_GPCHR_GPWE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 10942 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
AnnaBridge 189:f392fc9709a3 10943
AnnaBridge 189:f392fc9709a3 10944 /*! @name ISFR - Interrupt Status Flag Register */
AnnaBridge 189:f392fc9709a3 10945 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10946 #define PORT_ISFR_ISF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10947 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
AnnaBridge 189:f392fc9709a3 10948
AnnaBridge 189:f392fc9709a3 10949 /*! @name DFER - Digital Filter Enable Register */
AnnaBridge 189:f392fc9709a3 10950 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 10951 #define PORT_DFER_DFE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10952 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
AnnaBridge 189:f392fc9709a3 10953
AnnaBridge 189:f392fc9709a3 10954 /*! @name DFCR - Digital Filter Clock Register */
AnnaBridge 189:f392fc9709a3 10955 #define PORT_DFCR_CS_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 10956 #define PORT_DFCR_CS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10957 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
AnnaBridge 189:f392fc9709a3 10958
AnnaBridge 189:f392fc9709a3 10959 /*! @name DFWR - Digital Filter Width Register */
AnnaBridge 189:f392fc9709a3 10960 #define PORT_DFWR_FILT_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 10961 #define PORT_DFWR_FILT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 10962 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
AnnaBridge 189:f392fc9709a3 10963
AnnaBridge 189:f392fc9709a3 10964
AnnaBridge 189:f392fc9709a3 10965 /*!
AnnaBridge 189:f392fc9709a3 10966 * @}
AnnaBridge 189:f392fc9709a3 10967 */ /* end of group PORT_Register_Masks */
AnnaBridge 189:f392fc9709a3 10968
AnnaBridge 189:f392fc9709a3 10969
AnnaBridge 189:f392fc9709a3 10970 /* PORT - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 10971 /** Peripheral PORTA base address */
AnnaBridge 189:f392fc9709a3 10972 #define PORTA_BASE (0x40049000u)
AnnaBridge 189:f392fc9709a3 10973 /** Peripheral PORTA base pointer */
AnnaBridge 189:f392fc9709a3 10974 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 189:f392fc9709a3 10975 /** Peripheral PORTB base address */
AnnaBridge 189:f392fc9709a3 10976 #define PORTB_BASE (0x4004A000u)
AnnaBridge 189:f392fc9709a3 10977 /** Peripheral PORTB base pointer */
AnnaBridge 189:f392fc9709a3 10978 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 189:f392fc9709a3 10979 /** Peripheral PORTC base address */
AnnaBridge 189:f392fc9709a3 10980 #define PORTC_BASE (0x4004B000u)
AnnaBridge 189:f392fc9709a3 10981 /** Peripheral PORTC base pointer */
AnnaBridge 189:f392fc9709a3 10982 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 189:f392fc9709a3 10983 /** Peripheral PORTD base address */
AnnaBridge 189:f392fc9709a3 10984 #define PORTD_BASE (0x4004C000u)
AnnaBridge 189:f392fc9709a3 10985 /** Peripheral PORTD base pointer */
AnnaBridge 189:f392fc9709a3 10986 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 189:f392fc9709a3 10987 /** Peripheral PORTE base address */
AnnaBridge 189:f392fc9709a3 10988 #define PORTE_BASE (0x4004D000u)
AnnaBridge 189:f392fc9709a3 10989 /** Peripheral PORTE base pointer */
AnnaBridge 189:f392fc9709a3 10990 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 189:f392fc9709a3 10991 /** Array initializer of PORT peripheral base addresses */
AnnaBridge 189:f392fc9709a3 10992 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
AnnaBridge 189:f392fc9709a3 10993 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 189:f392fc9709a3 10994 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 189:f392fc9709a3 10995 /** Interrupt vectors for the PORT peripheral type */
AnnaBridge 189:f392fc9709a3 10996 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
AnnaBridge 189:f392fc9709a3 10997
AnnaBridge 189:f392fc9709a3 10998 /*!
AnnaBridge 189:f392fc9709a3 10999 * @}
AnnaBridge 189:f392fc9709a3 11000 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 11001
AnnaBridge 189:f392fc9709a3 11002
AnnaBridge 189:f392fc9709a3 11003 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11004 -- QuadSPI Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11005 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11006
AnnaBridge 189:f392fc9709a3 11007 /*!
AnnaBridge 189:f392fc9709a3 11008 * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11009 * @{
AnnaBridge 189:f392fc9709a3 11010 */
AnnaBridge 189:f392fc9709a3 11011
AnnaBridge 189:f392fc9709a3 11012 /** QuadSPI - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 11013 typedef struct {
AnnaBridge 189:f392fc9709a3 11014 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 11015 uint8_t RESERVED_0[4];
AnnaBridge 189:f392fc9709a3 11016 union { /* offset: 0x8 */
AnnaBridge 189:f392fc9709a3 11017 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 11018 struct {
AnnaBridge 189:f392fc9709a3 11019 __IO uint16_t IDATZ; /**< IP data transfer size, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 11020 __IO uint8_t PAR_EN; /**< IP data transfer size, offset: 0xA */
AnnaBridge 189:f392fc9709a3 11021 __IO uint8_t SEQID; /**< IP data transfer size, offset: 0xB */
AnnaBridge 189:f392fc9709a3 11022 } IPCR_ACCESSBIT;
AnnaBridge 189:f392fc9709a3 11023 };
AnnaBridge 189:f392fc9709a3 11024 __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 11025 __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 11026 __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 11027 __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 11028 __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 11029 __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 11030 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 11031 uint8_t RESERVED_1[8];
AnnaBridge 189:f392fc9709a3 11032 __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 11033 __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 11034 __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */
AnnaBridge 189:f392fc9709a3 11035 uint8_t RESERVED_2[196];
AnnaBridge 189:f392fc9709a3 11036 __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */
AnnaBridge 189:f392fc9709a3 11037 __IO uint32_t SFACR; /**< Serial Flash Address Configuration Register, offset: 0x104 */
AnnaBridge 189:f392fc9709a3 11038 __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */
AnnaBridge 189:f392fc9709a3 11039 __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */
AnnaBridge 189:f392fc9709a3 11040 __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */
AnnaBridge 189:f392fc9709a3 11041 uint8_t RESERVED_3[60];
AnnaBridge 189:f392fc9709a3 11042 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */
AnnaBridge 189:f392fc9709a3 11043 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */
AnnaBridge 189:f392fc9709a3 11044 __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */
AnnaBridge 189:f392fc9709a3 11045 __I uint32_t SR; /**< Status Register, offset: 0x15C */
AnnaBridge 189:f392fc9709a3 11046 __IO uint32_t FR; /**< Flag Register, offset: 0x160 */
AnnaBridge 189:f392fc9709a3 11047 __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */
AnnaBridge 189:f392fc9709a3 11048 __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */
AnnaBridge 189:f392fc9709a3 11049 __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */
AnnaBridge 189:f392fc9709a3 11050 uint8_t RESERVED_4[16];
AnnaBridge 189:f392fc9709a3 11051 __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */
AnnaBridge 189:f392fc9709a3 11052 __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */
AnnaBridge 189:f392fc9709a3 11053 __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */
AnnaBridge 189:f392fc9709a3 11054 __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */
AnnaBridge 189:f392fc9709a3 11055 __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0x190 */
AnnaBridge 189:f392fc9709a3 11056 uint8_t RESERVED_5[108];
AnnaBridge 189:f392fc9709a3 11057 __I uint32_t RBDR[16]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 11058 uint8_t RESERVED_6[192];
AnnaBridge 189:f392fc9709a3 11059 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */
AnnaBridge 189:f392fc9709a3 11060 __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */
AnnaBridge 189:f392fc9709a3 11061 uint8_t RESERVED_7[8];
AnnaBridge 189:f392fc9709a3 11062 __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 11063 } QuadSPI_Type;
AnnaBridge 189:f392fc9709a3 11064
AnnaBridge 189:f392fc9709a3 11065 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11066 -- QuadSPI Register Masks
AnnaBridge 189:f392fc9709a3 11067 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11068
AnnaBridge 189:f392fc9709a3 11069 /*!
AnnaBridge 189:f392fc9709a3 11070 * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks
AnnaBridge 189:f392fc9709a3 11071 * @{
AnnaBridge 189:f392fc9709a3 11072 */
AnnaBridge 189:f392fc9709a3 11073
AnnaBridge 189:f392fc9709a3 11074 /*! @name MCR - Module Configuration Register */
AnnaBridge 189:f392fc9709a3 11075 #define QuadSPI_MCR_SWRSTSD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11076 #define QuadSPI_MCR_SWRSTSD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11077 #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK)
AnnaBridge 189:f392fc9709a3 11078 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11079 #define QuadSPI_MCR_SWRSTHD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11080 #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK)
AnnaBridge 189:f392fc9709a3 11081 #define QuadSPI_MCR_END_CFG_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 11082 #define QuadSPI_MCR_END_CFG_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11083 #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK)
AnnaBridge 189:f392fc9709a3 11084 #define QuadSPI_MCR_DQS_LAT_EN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11085 #define QuadSPI_MCR_DQS_LAT_EN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11086 #define QuadSPI_MCR_DQS_LAT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LAT_EN_SHIFT)) & QuadSPI_MCR_DQS_LAT_EN_MASK)
AnnaBridge 189:f392fc9709a3 11087 #define QuadSPI_MCR_DQS_EN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11088 #define QuadSPI_MCR_DQS_EN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11089 #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK)
AnnaBridge 189:f392fc9709a3 11090 #define QuadSPI_MCR_DDR_EN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 11091 #define QuadSPI_MCR_DDR_EN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 11092 #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK)
AnnaBridge 189:f392fc9709a3 11093 #define QuadSPI_MCR_CLR_RXF_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 11094 #define QuadSPI_MCR_CLR_RXF_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11095 #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK)
AnnaBridge 189:f392fc9709a3 11096 #define QuadSPI_MCR_CLR_TXF_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 11097 #define QuadSPI_MCR_CLR_TXF_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 11098 #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK)
AnnaBridge 189:f392fc9709a3 11099 #define QuadSPI_MCR_MDIS_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 11100 #define QuadSPI_MCR_MDIS_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 11101 #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK)
AnnaBridge 189:f392fc9709a3 11102 #define QuadSPI_MCR_SCLKCFG_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 11103 #define QuadSPI_MCR_SCLKCFG_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11104 #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SCLKCFG_SHIFT)) & QuadSPI_MCR_SCLKCFG_MASK)
AnnaBridge 189:f392fc9709a3 11105
AnnaBridge 189:f392fc9709a3 11106 /*! @name IPCR - IP Configuration Register */
AnnaBridge 189:f392fc9709a3 11107 #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 11108 #define QuadSPI_IPCR_IDATSZ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11109 #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK)
AnnaBridge 189:f392fc9709a3 11110 #define QuadSPI_IPCR_PAR_EN_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 11111 #define QuadSPI_IPCR_PAR_EN_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11112 #define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK)
AnnaBridge 189:f392fc9709a3 11113 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 11114 #define QuadSPI_IPCR_SEQID_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11115 #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK)
AnnaBridge 189:f392fc9709a3 11116
AnnaBridge 189:f392fc9709a3 11117 /*! @name FLSHCR - Flash Configuration Register */
AnnaBridge 189:f392fc9709a3 11118 #define QuadSPI_FLSHCR_TCSS_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11119 #define QuadSPI_FLSHCR_TCSS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11120 #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK)
AnnaBridge 189:f392fc9709a3 11121 #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 11122 #define QuadSPI_FLSHCR_TCSH_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11123 #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK)
AnnaBridge 189:f392fc9709a3 11124 #define QuadSPI_FLSHCR_TDH_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 11125 #define QuadSPI_FLSHCR_TDH_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11126 #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK)
AnnaBridge 189:f392fc9709a3 11127
AnnaBridge 189:f392fc9709a3 11128 /*! @name BUF0CR - Buffer0 Configuration Register */
AnnaBridge 189:f392fc9709a3 11129 #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11130 #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11131 #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK)
AnnaBridge 189:f392fc9709a3 11132 #define QuadSPI_BUF0CR_ADATSZ_MASK (0x7F00U)
AnnaBridge 189:f392fc9709a3 11133 #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11134 #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK)
AnnaBridge 189:f392fc9709a3 11135 #define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 11136 #define QuadSPI_BUF0CR_HP_EN_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 11137 #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK)
AnnaBridge 189:f392fc9709a3 11138
AnnaBridge 189:f392fc9709a3 11139 /*! @name BUF1CR - Buffer1 Configuration Register */
AnnaBridge 189:f392fc9709a3 11140 #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11141 #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11142 #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK)
AnnaBridge 189:f392fc9709a3 11143 #define QuadSPI_BUF1CR_ADATSZ_MASK (0x7F00U)
AnnaBridge 189:f392fc9709a3 11144 #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11145 #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK)
AnnaBridge 189:f392fc9709a3 11146
AnnaBridge 189:f392fc9709a3 11147 /*! @name BUF2CR - Buffer2 Configuration Register */
AnnaBridge 189:f392fc9709a3 11148 #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11149 #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11150 #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK)
AnnaBridge 189:f392fc9709a3 11151 #define QuadSPI_BUF2CR_ADATSZ_MASK (0x7F00U)
AnnaBridge 189:f392fc9709a3 11152 #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11153 #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK)
AnnaBridge 189:f392fc9709a3 11154
AnnaBridge 189:f392fc9709a3 11155 /*! @name BUF3CR - Buffer3 Configuration Register */
AnnaBridge 189:f392fc9709a3 11156 #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11157 #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11158 #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK)
AnnaBridge 189:f392fc9709a3 11159 #define QuadSPI_BUF3CR_ADATSZ_MASK (0x7F00U)
AnnaBridge 189:f392fc9709a3 11160 #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11161 #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK)
AnnaBridge 189:f392fc9709a3 11162 #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 11163 #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 11164 #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK)
AnnaBridge 189:f392fc9709a3 11165
AnnaBridge 189:f392fc9709a3 11166 /*! @name BFGENCR - Buffer Generic Configuration Register */
AnnaBridge 189:f392fc9709a3 11167 #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 11168 #define QuadSPI_BFGENCR_SEQID_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 11169 #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK)
AnnaBridge 189:f392fc9709a3 11170 #define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 11171 #define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11172 #define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK)
AnnaBridge 189:f392fc9709a3 11173
AnnaBridge 189:f392fc9709a3 11174 /*! @name SOCCR - SOC Configuration Register */
AnnaBridge 189:f392fc9709a3 11175 #define QuadSPI_SOCCR_QSPISRC_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 11176 #define QuadSPI_SOCCR_QSPISRC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11177 #define QuadSPI_SOCCR_QSPISRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_QSPISRC_SHIFT)) & QuadSPI_SOCCR_QSPISRC_MASK)
AnnaBridge 189:f392fc9709a3 11178 #define QuadSPI_SOCCR_DQSLPEN_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 11179 #define QuadSPI_SOCCR_DQSLPEN_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11180 #define QuadSPI_SOCCR_DQSLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSLPEN_SHIFT)) & QuadSPI_SOCCR_DQSLPEN_MASK)
AnnaBridge 189:f392fc9709a3 11181 #define QuadSPI_SOCCR_DQSPADLPEN_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 11182 #define QuadSPI_SOCCR_DQSPADLPEN_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 11183 #define QuadSPI_SOCCR_DQSPADLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPADLPEN_SHIFT)) & QuadSPI_SOCCR_DQSPADLPEN_MASK)
AnnaBridge 189:f392fc9709a3 11184 #define QuadSPI_SOCCR_DQSPHASEL_MASK (0xC00U)
AnnaBridge 189:f392fc9709a3 11185 #define QuadSPI_SOCCR_DQSPHASEL_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11186 #define QuadSPI_SOCCR_DQSPHASEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPHASEL_SHIFT)) & QuadSPI_SOCCR_DQSPHASEL_MASK)
AnnaBridge 189:f392fc9709a3 11187 #define QuadSPI_SOCCR_DQSINVSEL_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 11188 #define QuadSPI_SOCCR_DQSINVSEL_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 11189 #define QuadSPI_SOCCR_DQSINVSEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSINVSEL_SHIFT)) & QuadSPI_SOCCR_DQSINVSEL_MASK)
AnnaBridge 189:f392fc9709a3 11190 #define QuadSPI_SOCCR_CK2EN_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 11191 #define QuadSPI_SOCCR_CK2EN_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 11192 #define QuadSPI_SOCCR_CK2EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_CK2EN_SHIFT)) & QuadSPI_SOCCR_CK2EN_MASK)
AnnaBridge 189:f392fc9709a3 11193 #define QuadSPI_SOCCR_DIFFCKEN_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 11194 #define QuadSPI_SOCCR_DIFFCKEN_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 11195 #define QuadSPI_SOCCR_DIFFCKEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DIFFCKEN_SHIFT)) & QuadSPI_SOCCR_DIFFCKEN_MASK)
AnnaBridge 189:f392fc9709a3 11196 #define QuadSPI_SOCCR_OCTEN_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 11197 #define QuadSPI_SOCCR_OCTEN_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 11198 #define QuadSPI_SOCCR_OCTEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_OCTEN_SHIFT)) & QuadSPI_SOCCR_OCTEN_MASK)
AnnaBridge 189:f392fc9709a3 11199 #define QuadSPI_SOCCR_DLYTAPSELA_MASK (0x3F0000U)
AnnaBridge 189:f392fc9709a3 11200 #define QuadSPI_SOCCR_DLYTAPSELA_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11201 #define QuadSPI_SOCCR_DLYTAPSELA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELA_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELA_MASK)
AnnaBridge 189:f392fc9709a3 11202 #define QuadSPI_SOCCR_DLYTAPSELB_MASK (0x3F000000U)
AnnaBridge 189:f392fc9709a3 11203 #define QuadSPI_SOCCR_DLYTAPSELB_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11204 #define QuadSPI_SOCCR_DLYTAPSELB(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELB_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELB_MASK)
AnnaBridge 189:f392fc9709a3 11205
AnnaBridge 189:f392fc9709a3 11206 /*! @name BUF0IND - Buffer0 Top Index Register */
AnnaBridge 189:f392fc9709a3 11207 #define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U)
AnnaBridge 189:f392fc9709a3 11208 #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11209 #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK)
AnnaBridge 189:f392fc9709a3 11210
AnnaBridge 189:f392fc9709a3 11211 /*! @name BUF1IND - Buffer1 Top Index Register */
AnnaBridge 189:f392fc9709a3 11212 #define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U)
AnnaBridge 189:f392fc9709a3 11213 #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11214 #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK)
AnnaBridge 189:f392fc9709a3 11215
AnnaBridge 189:f392fc9709a3 11216 /*! @name BUF2IND - Buffer2 Top Index Register */
AnnaBridge 189:f392fc9709a3 11217 #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U)
AnnaBridge 189:f392fc9709a3 11218 #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11219 #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK)
AnnaBridge 189:f392fc9709a3 11220
AnnaBridge 189:f392fc9709a3 11221 /*! @name SFAR - Serial Flash Address Register */
AnnaBridge 189:f392fc9709a3 11222 #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 11223 #define QuadSPI_SFAR_SFADR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11224 #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK)
AnnaBridge 189:f392fc9709a3 11225
AnnaBridge 189:f392fc9709a3 11226 /*! @name SFACR - Serial Flash Address Configuration Register */
AnnaBridge 189:f392fc9709a3 11227 #define QuadSPI_SFACR_CAS_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11228 #define QuadSPI_SFACR_CAS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11229 #define QuadSPI_SFACR_CAS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK)
AnnaBridge 189:f392fc9709a3 11230 #define QuadSPI_SFACR_WA_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 11231 #define QuadSPI_SFACR_WA_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11232 #define QuadSPI_SFACR_WA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK)
AnnaBridge 189:f392fc9709a3 11233
AnnaBridge 189:f392fc9709a3 11234 /*! @name SMPR - Sampling Register */
AnnaBridge 189:f392fc9709a3 11235 #define QuadSPI_SMPR_HSENA_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11236 #define QuadSPI_SMPR_HSENA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11237 #define QuadSPI_SMPR_HSENA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK)
AnnaBridge 189:f392fc9709a3 11238 #define QuadSPI_SMPR_HSPHS_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11239 #define QuadSPI_SMPR_HSPHS_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11240 #define QuadSPI_SMPR_HSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSPHS_SHIFT)) & QuadSPI_SMPR_HSPHS_MASK)
AnnaBridge 189:f392fc9709a3 11241 #define QuadSPI_SMPR_HSDLY_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11242 #define QuadSPI_SMPR_HSDLY_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11243 #define QuadSPI_SMPR_HSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSDLY_SHIFT)) & QuadSPI_SMPR_HSDLY_MASK)
AnnaBridge 189:f392fc9709a3 11244 #define QuadSPI_SMPR_FSPHS_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11245 #define QuadSPI_SMPR_FSPHS_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11246 #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK)
AnnaBridge 189:f392fc9709a3 11247 #define QuadSPI_SMPR_FSDLY_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11248 #define QuadSPI_SMPR_FSDLY_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11249 #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK)
AnnaBridge 189:f392fc9709a3 11250 #define QuadSPI_SMPR_DDRSMP_MASK (0x70000U)
AnnaBridge 189:f392fc9709a3 11251 #define QuadSPI_SMPR_DDRSMP_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11252 #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK)
AnnaBridge 189:f392fc9709a3 11253
AnnaBridge 189:f392fc9709a3 11254 /*! @name RBSR - RX Buffer Status Register */
AnnaBridge 189:f392fc9709a3 11255 #define QuadSPI_RBSR_RDBFL_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 11256 #define QuadSPI_RBSR_RDBFL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11257 #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK)
AnnaBridge 189:f392fc9709a3 11258 #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 11259 #define QuadSPI_RBSR_RDCTR_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11260 #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK)
AnnaBridge 189:f392fc9709a3 11261
AnnaBridge 189:f392fc9709a3 11262 /*! @name RBCT - RX Buffer Control Register */
AnnaBridge 189:f392fc9709a3 11263 #define QuadSPI_RBCT_WMRK_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11264 #define QuadSPI_RBCT_WMRK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11265 #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK)
AnnaBridge 189:f392fc9709a3 11266 #define QuadSPI_RBCT_RXBRD_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 11267 #define QuadSPI_RBCT_RXBRD_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11268 #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK)
AnnaBridge 189:f392fc9709a3 11269
AnnaBridge 189:f392fc9709a3 11270 /*! @name TBSR - TX Buffer Status Register */
AnnaBridge 189:f392fc9709a3 11271 #define QuadSPI_TBSR_TRBFL_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 11272 #define QuadSPI_TBSR_TRBFL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11273 #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK)
AnnaBridge 189:f392fc9709a3 11274 #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 11275 #define QuadSPI_TBSR_TRCTR_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11276 #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK)
AnnaBridge 189:f392fc9709a3 11277
AnnaBridge 189:f392fc9709a3 11278 /*! @name TBDR - TX Buffer Data Register */
AnnaBridge 189:f392fc9709a3 11279 #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 11280 #define QuadSPI_TBDR_TXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11281 #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 11282
AnnaBridge 189:f392fc9709a3 11283 /*! @name TBCT - Tx Buffer Control Register */
AnnaBridge 189:f392fc9709a3 11284 #define QuadSPI_TBCT_WMRK_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 11285 #define QuadSPI_TBCT_WMRK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11286 #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK)
AnnaBridge 189:f392fc9709a3 11287
AnnaBridge 189:f392fc9709a3 11288 /*! @name SR - Status Register */
AnnaBridge 189:f392fc9709a3 11289 #define QuadSPI_SR_BUSY_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11290 #define QuadSPI_SR_BUSY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11291 #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK)
AnnaBridge 189:f392fc9709a3 11292 #define QuadSPI_SR_IP_ACC_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11293 #define QuadSPI_SR_IP_ACC_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11294 #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK)
AnnaBridge 189:f392fc9709a3 11295 #define QuadSPI_SR_AHB_ACC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11296 #define QuadSPI_SR_AHB_ACC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11297 #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK)
AnnaBridge 189:f392fc9709a3 11298 #define QuadSPI_SR_AHBGNT_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11299 #define QuadSPI_SR_AHBGNT_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11300 #define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK)
AnnaBridge 189:f392fc9709a3 11301 #define QuadSPI_SR_AHBTRN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11302 #define QuadSPI_SR_AHBTRN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11303 #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK)
AnnaBridge 189:f392fc9709a3 11304 #define QuadSPI_SR_AHB0NE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 11305 #define QuadSPI_SR_AHB0NE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 11306 #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK)
AnnaBridge 189:f392fc9709a3 11307 #define QuadSPI_SR_AHB1NE_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 11308 #define QuadSPI_SR_AHB1NE_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11309 #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK)
AnnaBridge 189:f392fc9709a3 11310 #define QuadSPI_SR_AHB2NE_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 11311 #define QuadSPI_SR_AHB2NE_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 11312 #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK)
AnnaBridge 189:f392fc9709a3 11313 #define QuadSPI_SR_AHB3NE_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 11314 #define QuadSPI_SR_AHB3NE_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11315 #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK)
AnnaBridge 189:f392fc9709a3 11316 #define QuadSPI_SR_AHB0FUL_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 11317 #define QuadSPI_SR_AHB0FUL_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 11318 #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK)
AnnaBridge 189:f392fc9709a3 11319 #define QuadSPI_SR_AHB1FUL_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 11320 #define QuadSPI_SR_AHB1FUL_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 11321 #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK)
AnnaBridge 189:f392fc9709a3 11322 #define QuadSPI_SR_AHB2FUL_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 11323 #define QuadSPI_SR_AHB2FUL_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 11324 #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK)
AnnaBridge 189:f392fc9709a3 11325 #define QuadSPI_SR_AHB3FUL_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 11326 #define QuadSPI_SR_AHB3FUL_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 11327 #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK)
AnnaBridge 189:f392fc9709a3 11328 #define QuadSPI_SR_RXWE_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 11329 #define QuadSPI_SR_RXWE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11330 #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK)
AnnaBridge 189:f392fc9709a3 11331 #define QuadSPI_SR_RXFULL_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 11332 #define QuadSPI_SR_RXFULL_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 11333 #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK)
AnnaBridge 189:f392fc9709a3 11334 #define QuadSPI_SR_RXDMA_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 11335 #define QuadSPI_SR_RXDMA_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 11336 #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK)
AnnaBridge 189:f392fc9709a3 11337 #define QuadSPI_SR_TXEDA_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 11338 #define QuadSPI_SR_TXEDA_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11339 #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK)
AnnaBridge 189:f392fc9709a3 11340 #define QuadSPI_SR_TXWA_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 11341 #define QuadSPI_SR_TXWA_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 11342 #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK)
AnnaBridge 189:f392fc9709a3 11343 #define QuadSPI_SR_TXDMA_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 11344 #define QuadSPI_SR_TXDMA_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 11345 #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK)
AnnaBridge 189:f392fc9709a3 11346 #define QuadSPI_SR_TXFULL_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 11347 #define QuadSPI_SR_TXFULL_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 11348 #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK)
AnnaBridge 189:f392fc9709a3 11349 #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U)
AnnaBridge 189:f392fc9709a3 11350 #define QuadSPI_SR_DLPSMP_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 11351 #define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK)
AnnaBridge 189:f392fc9709a3 11352
AnnaBridge 189:f392fc9709a3 11353 /*! @name FR - Flag Register */
AnnaBridge 189:f392fc9709a3 11354 #define QuadSPI_FR_TFF_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11355 #define QuadSPI_FR_TFF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11356 #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK)
AnnaBridge 189:f392fc9709a3 11357 #define QuadSPI_FR_IPGEF_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 11358 #define QuadSPI_FR_IPGEF_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 11359 #define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK)
AnnaBridge 189:f392fc9709a3 11360 #define QuadSPI_FR_IPIEF_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11361 #define QuadSPI_FR_IPIEF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11362 #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK)
AnnaBridge 189:f392fc9709a3 11363 #define QuadSPI_FR_IPAEF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 11364 #define QuadSPI_FR_IPAEF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 11365 #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK)
AnnaBridge 189:f392fc9709a3 11366 #define QuadSPI_FR_IUEF_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 11367 #define QuadSPI_FR_IUEF_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 11368 #define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK)
AnnaBridge 189:f392fc9709a3 11369 #define QuadSPI_FR_ABOF_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 11370 #define QuadSPI_FR_ABOF_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 11371 #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK)
AnnaBridge 189:f392fc9709a3 11372 #define QuadSPI_FR_AIBSEF_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 11373 #define QuadSPI_FR_AIBSEF_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 11374 #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK)
AnnaBridge 189:f392fc9709a3 11375 #define QuadSPI_FR_AITEF_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 11376 #define QuadSPI_FR_AITEF_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 11377 #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK)
AnnaBridge 189:f392fc9709a3 11378 #define QuadSPI_FR_ABSEF_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 11379 #define QuadSPI_FR_ABSEF_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 11380 #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK)
AnnaBridge 189:f392fc9709a3 11381 #define QuadSPI_FR_RBDF_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 11382 #define QuadSPI_FR_RBDF_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11383 #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK)
AnnaBridge 189:f392fc9709a3 11384 #define QuadSPI_FR_RBOF_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 11385 #define QuadSPI_FR_RBOF_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 11386 #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK)
AnnaBridge 189:f392fc9709a3 11387 #define QuadSPI_FR_ILLINE_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 11388 #define QuadSPI_FR_ILLINE_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 11389 #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK)
AnnaBridge 189:f392fc9709a3 11390 #define QuadSPI_FR_TBUF_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 11391 #define QuadSPI_FR_TBUF_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 11392 #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK)
AnnaBridge 189:f392fc9709a3 11393 #define QuadSPI_FR_TBFF_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 11394 #define QuadSPI_FR_TBFF_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 11395 #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK)
AnnaBridge 189:f392fc9709a3 11396 #define QuadSPI_FR_DLPFF_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 11397 #define QuadSPI_FR_DLPFF_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 11398 #define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK)
AnnaBridge 189:f392fc9709a3 11399
AnnaBridge 189:f392fc9709a3 11400 /*! @name RSER - Interrupt and DMA Request Select and Enable Register */
AnnaBridge 189:f392fc9709a3 11401 #define QuadSPI_RSER_TFIE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11402 #define QuadSPI_RSER_TFIE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11403 #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK)
AnnaBridge 189:f392fc9709a3 11404 #define QuadSPI_RSER_IPGEIE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 11405 #define QuadSPI_RSER_IPGEIE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 11406 #define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK)
AnnaBridge 189:f392fc9709a3 11407 #define QuadSPI_RSER_IPIEIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11408 #define QuadSPI_RSER_IPIEIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11409 #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK)
AnnaBridge 189:f392fc9709a3 11410 #define QuadSPI_RSER_IPAEIE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 11411 #define QuadSPI_RSER_IPAEIE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 11412 #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK)
AnnaBridge 189:f392fc9709a3 11413 #define QuadSPI_RSER_IUEIE_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 11414 #define QuadSPI_RSER_IUEIE_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 11415 #define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK)
AnnaBridge 189:f392fc9709a3 11416 #define QuadSPI_RSER_ABOIE_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 11417 #define QuadSPI_RSER_ABOIE_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 11418 #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK)
AnnaBridge 189:f392fc9709a3 11419 #define QuadSPI_RSER_AIBSIE_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 11420 #define QuadSPI_RSER_AIBSIE_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 11421 #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK)
AnnaBridge 189:f392fc9709a3 11422 #define QuadSPI_RSER_AITIE_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 11423 #define QuadSPI_RSER_AITIE_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 11424 #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK)
AnnaBridge 189:f392fc9709a3 11425 #define QuadSPI_RSER_ABSEIE_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 11426 #define QuadSPI_RSER_ABSEIE_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 11427 #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK)
AnnaBridge 189:f392fc9709a3 11428 #define QuadSPI_RSER_RBDIE_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 11429 #define QuadSPI_RSER_RBDIE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11430 #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK)
AnnaBridge 189:f392fc9709a3 11431 #define QuadSPI_RSER_RBOIE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 11432 #define QuadSPI_RSER_RBOIE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 11433 #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK)
AnnaBridge 189:f392fc9709a3 11434 #define QuadSPI_RSER_RBDDE_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 11435 #define QuadSPI_RSER_RBDDE_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 11436 #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK)
AnnaBridge 189:f392fc9709a3 11437 #define QuadSPI_RSER_ILLINIE_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 11438 #define QuadSPI_RSER_ILLINIE_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 11439 #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK)
AnnaBridge 189:f392fc9709a3 11440 #define QuadSPI_RSER_TBFDE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 11441 #define QuadSPI_RSER_TBFDE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 11442 #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK)
AnnaBridge 189:f392fc9709a3 11443 #define QuadSPI_RSER_TBUIE_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 11444 #define QuadSPI_RSER_TBUIE_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 11445 #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK)
AnnaBridge 189:f392fc9709a3 11446 #define QuadSPI_RSER_TBFIE_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 11447 #define QuadSPI_RSER_TBFIE_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 11448 #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK)
AnnaBridge 189:f392fc9709a3 11449 #define QuadSPI_RSER_DLPFIE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 11450 #define QuadSPI_RSER_DLPFIE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 11451 #define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK)
AnnaBridge 189:f392fc9709a3 11452
AnnaBridge 189:f392fc9709a3 11453 /*! @name SPNDST - Sequence Suspend Status Register */
AnnaBridge 189:f392fc9709a3 11454 #define QuadSPI_SPNDST_SUSPND_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11455 #define QuadSPI_SPNDST_SUSPND_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11456 #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK)
AnnaBridge 189:f392fc9709a3 11457 #define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 11458 #define QuadSPI_SPNDST_SPDBUF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11459 #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK)
AnnaBridge 189:f392fc9709a3 11460 #define QuadSPI_SPNDST_DATLFT_MASK (0x7E00U)
AnnaBridge 189:f392fc9709a3 11461 #define QuadSPI_SPNDST_DATLFT_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 11462 #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK)
AnnaBridge 189:f392fc9709a3 11463
AnnaBridge 189:f392fc9709a3 11464 /*! @name SPTRCLR - Sequence Pointer Clear Register */
AnnaBridge 189:f392fc9709a3 11465 #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11466 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11467 #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK)
AnnaBridge 189:f392fc9709a3 11468 #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 11469 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11470 #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK)
AnnaBridge 189:f392fc9709a3 11471
AnnaBridge 189:f392fc9709a3 11472 /*! @name SFA1AD - Serial Flash A1 Top Address */
AnnaBridge 189:f392fc9709a3 11473 #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U)
AnnaBridge 189:f392fc9709a3 11474 #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11475 #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK)
AnnaBridge 189:f392fc9709a3 11476
AnnaBridge 189:f392fc9709a3 11477 /*! @name SFA2AD - Serial Flash A2 Top Address */
AnnaBridge 189:f392fc9709a3 11478 #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U)
AnnaBridge 189:f392fc9709a3 11479 #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11480 #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK)
AnnaBridge 189:f392fc9709a3 11481
AnnaBridge 189:f392fc9709a3 11482 /*! @name SFB1AD - Serial Flash B1Top Address */
AnnaBridge 189:f392fc9709a3 11483 #define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U)
AnnaBridge 189:f392fc9709a3 11484 #define QuadSPI_SFB1AD_TPADB1_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11485 #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK)
AnnaBridge 189:f392fc9709a3 11486
AnnaBridge 189:f392fc9709a3 11487 /*! @name SFB2AD - Serial Flash B2Top Address */
AnnaBridge 189:f392fc9709a3 11488 #define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U)
AnnaBridge 189:f392fc9709a3 11489 #define QuadSPI_SFB2AD_TPADB2_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11490 #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK)
AnnaBridge 189:f392fc9709a3 11491
AnnaBridge 189:f392fc9709a3 11492 /*! @name DLPR - Data Learn Pattern Register */
AnnaBridge 189:f392fc9709a3 11493 #define QuadSPI_DLPR_DLPV_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 11494 #define QuadSPI_DLPR_DLPV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11495 #define QuadSPI_DLPR_DLPV(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLPR_DLPV_SHIFT)) & QuadSPI_DLPR_DLPV_MASK)
AnnaBridge 189:f392fc9709a3 11496
AnnaBridge 189:f392fc9709a3 11497 /*! @name RBDR - RX Buffer Data Register */
AnnaBridge 189:f392fc9709a3 11498 #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 11499 #define QuadSPI_RBDR_RXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11500 #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK)
AnnaBridge 189:f392fc9709a3 11501
AnnaBridge 189:f392fc9709a3 11502 /* The count of QuadSPI_RBDR */
AnnaBridge 189:f392fc9709a3 11503 #define QuadSPI_RBDR_COUNT (16U)
AnnaBridge 189:f392fc9709a3 11504
AnnaBridge 189:f392fc9709a3 11505 /*! @name LUTKEY - LUT Key Register */
AnnaBridge 189:f392fc9709a3 11506 #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 11507 #define QuadSPI_LUTKEY_KEY_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11508 #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK)
AnnaBridge 189:f392fc9709a3 11509
AnnaBridge 189:f392fc9709a3 11510 /*! @name LCKCR - LUT Lock Configuration Register */
AnnaBridge 189:f392fc9709a3 11511 #define QuadSPI_LCKCR_LOCK_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11512 #define QuadSPI_LCKCR_LOCK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11513 #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK)
AnnaBridge 189:f392fc9709a3 11514 #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11515 #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11516 #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK)
AnnaBridge 189:f392fc9709a3 11517
AnnaBridge 189:f392fc9709a3 11518 /*! @name LUT - Look-up Table register */
AnnaBridge 189:f392fc9709a3 11519 #define QuadSPI_LUT_OPRND0_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 11520 #define QuadSPI_LUT_OPRND0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11521 #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK)
AnnaBridge 189:f392fc9709a3 11522 #define QuadSPI_LUT_PAD0_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 11523 #define QuadSPI_LUT_PAD0_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11524 #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK)
AnnaBridge 189:f392fc9709a3 11525 #define QuadSPI_LUT_INSTR0_MASK (0xFC00U)
AnnaBridge 189:f392fc9709a3 11526 #define QuadSPI_LUT_INSTR0_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11527 #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK)
AnnaBridge 189:f392fc9709a3 11528 #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 11529 #define QuadSPI_LUT_OPRND1_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11530 #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK)
AnnaBridge 189:f392fc9709a3 11531 #define QuadSPI_LUT_PAD1_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 11532 #define QuadSPI_LUT_PAD1_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11533 #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK)
AnnaBridge 189:f392fc9709a3 11534 #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U)
AnnaBridge 189:f392fc9709a3 11535 #define QuadSPI_LUT_INSTR1_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 11536 #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK)
AnnaBridge 189:f392fc9709a3 11537
AnnaBridge 189:f392fc9709a3 11538 /* The count of QuadSPI_LUT */
AnnaBridge 189:f392fc9709a3 11539 #define QuadSPI_LUT_COUNT (64U)
AnnaBridge 189:f392fc9709a3 11540
AnnaBridge 189:f392fc9709a3 11541
AnnaBridge 189:f392fc9709a3 11542 /*!
AnnaBridge 189:f392fc9709a3 11543 * @}
AnnaBridge 189:f392fc9709a3 11544 */ /* end of group QuadSPI_Register_Masks */
AnnaBridge 189:f392fc9709a3 11545
AnnaBridge 189:f392fc9709a3 11546
AnnaBridge 189:f392fc9709a3 11547 /* QuadSPI - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 11548 /** Peripheral QuadSPI0 base address */
AnnaBridge 189:f392fc9709a3 11549 #define QuadSPI0_BASE (0x400DA000u)
AnnaBridge 189:f392fc9709a3 11550 /** Peripheral QuadSPI0 base pointer */
AnnaBridge 189:f392fc9709a3 11551 #define QuadSPI0 ((QuadSPI_Type *)QuadSPI0_BASE)
AnnaBridge 189:f392fc9709a3 11552 /** Array initializer of QuadSPI peripheral base addresses */
AnnaBridge 189:f392fc9709a3 11553 #define QuadSPI_BASE_ADDRS { QuadSPI0_BASE }
AnnaBridge 189:f392fc9709a3 11554 /** Array initializer of QuadSPI peripheral base pointers */
AnnaBridge 189:f392fc9709a3 11555 #define QuadSPI_BASE_PTRS { QuadSPI0 }
AnnaBridge 189:f392fc9709a3 11556 /** Interrupt vectors for the QuadSPI peripheral type */
AnnaBridge 189:f392fc9709a3 11557 #define QuadSPI_IRQS { QuadSPI0_IRQn }
AnnaBridge 189:f392fc9709a3 11558
AnnaBridge 189:f392fc9709a3 11559 /*!
AnnaBridge 189:f392fc9709a3 11560 * @}
AnnaBridge 189:f392fc9709a3 11561 */ /* end of group QuadSPI_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 11562
AnnaBridge 189:f392fc9709a3 11563
AnnaBridge 189:f392fc9709a3 11564 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11565 -- RCM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11566 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11567
AnnaBridge 189:f392fc9709a3 11568 /*!
AnnaBridge 189:f392fc9709a3 11569 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11570 * @{
AnnaBridge 189:f392fc9709a3 11571 */
AnnaBridge 189:f392fc9709a3 11572
AnnaBridge 189:f392fc9709a3 11573 /** RCM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 11574 typedef struct {
AnnaBridge 189:f392fc9709a3 11575 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 11576 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 11577 uint8_t RESERVED_0[2];
AnnaBridge 189:f392fc9709a3 11578 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 11579 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 189:f392fc9709a3 11580 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
AnnaBridge 189:f392fc9709a3 11581 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
AnnaBridge 189:f392fc9709a3 11582 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 11583 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
AnnaBridge 189:f392fc9709a3 11584 } RCM_Type;
AnnaBridge 189:f392fc9709a3 11585
AnnaBridge 189:f392fc9709a3 11586 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11587 -- RCM Register Masks
AnnaBridge 189:f392fc9709a3 11588 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11589
AnnaBridge 189:f392fc9709a3 11590 /*!
AnnaBridge 189:f392fc9709a3 11591 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 189:f392fc9709a3 11592 * @{
AnnaBridge 189:f392fc9709a3 11593 */
AnnaBridge 189:f392fc9709a3 11594
AnnaBridge 189:f392fc9709a3 11595 /*! @name SRS0 - System Reset Status Register 0 */
AnnaBridge 189:f392fc9709a3 11596 #define RCM_SRS0_WAKEUP_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11597 #define RCM_SRS0_WAKEUP_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11598 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
AnnaBridge 189:f392fc9709a3 11599 #define RCM_SRS0_LVD_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11600 #define RCM_SRS0_LVD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11601 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
AnnaBridge 189:f392fc9709a3 11602 #define RCM_SRS0_LOC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11603 #define RCM_SRS0_LOC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11604 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
AnnaBridge 189:f392fc9709a3 11605 #define RCM_SRS0_LOL_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 11606 #define RCM_SRS0_LOL_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11607 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
AnnaBridge 189:f392fc9709a3 11608 #define RCM_SRS0_WDOG_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11609 #define RCM_SRS0_WDOG_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11610 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
AnnaBridge 189:f392fc9709a3 11611 #define RCM_SRS0_PIN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11612 #define RCM_SRS0_PIN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11613 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
AnnaBridge 189:f392fc9709a3 11614 #define RCM_SRS0_POR_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 11615 #define RCM_SRS0_POR_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 11616 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
AnnaBridge 189:f392fc9709a3 11617
AnnaBridge 189:f392fc9709a3 11618 /*! @name SRS1 - System Reset Status Register 1 */
AnnaBridge 189:f392fc9709a3 11619 #define RCM_SRS1_JTAG_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11620 #define RCM_SRS1_JTAG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11621 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
AnnaBridge 189:f392fc9709a3 11622 #define RCM_SRS1_LOCKUP_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11623 #define RCM_SRS1_LOCKUP_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11624 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
AnnaBridge 189:f392fc9709a3 11625 #define RCM_SRS1_SW_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11626 #define RCM_SRS1_SW_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11627 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
AnnaBridge 189:f392fc9709a3 11628 #define RCM_SRS1_MDM_AP_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 11629 #define RCM_SRS1_MDM_AP_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11630 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
AnnaBridge 189:f392fc9709a3 11631 #define RCM_SRS1_SACKERR_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11632 #define RCM_SRS1_SACKERR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11633 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
AnnaBridge 189:f392fc9709a3 11634
AnnaBridge 189:f392fc9709a3 11635 /*! @name RPFC - Reset Pin Filter Control register */
AnnaBridge 189:f392fc9709a3 11636 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 11637 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11638 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 189:f392fc9709a3 11639 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11640 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11641 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
AnnaBridge 189:f392fc9709a3 11642
AnnaBridge 189:f392fc9709a3 11643 /*! @name RPFW - Reset Pin Filter Width register */
AnnaBridge 189:f392fc9709a3 11644 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
AnnaBridge 189:f392fc9709a3 11645 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11646 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 189:f392fc9709a3 11647
AnnaBridge 189:f392fc9709a3 11648 /*! @name FM - Force Mode Register */
AnnaBridge 189:f392fc9709a3 11649 #define RCM_FM_FORCEROM_MASK (0x6U)
AnnaBridge 189:f392fc9709a3 11650 #define RCM_FM_FORCEROM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11651 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
AnnaBridge 189:f392fc9709a3 11652
AnnaBridge 189:f392fc9709a3 11653 /*! @name MR - Mode Register */
AnnaBridge 189:f392fc9709a3 11654 #define RCM_MR_BOOTROM_MASK (0x6U)
AnnaBridge 189:f392fc9709a3 11655 #define RCM_MR_BOOTROM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11656 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
AnnaBridge 189:f392fc9709a3 11657
AnnaBridge 189:f392fc9709a3 11658 /*! @name SSRS0 - Sticky System Reset Status Register 0 */
AnnaBridge 189:f392fc9709a3 11659 #define RCM_SSRS0_SWAKEUP_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11660 #define RCM_SSRS0_SWAKEUP_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11661 #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
AnnaBridge 189:f392fc9709a3 11662 #define RCM_SSRS0_SLVD_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11663 #define RCM_SSRS0_SLVD_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11664 #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
AnnaBridge 189:f392fc9709a3 11665 #define RCM_SSRS0_SLOC_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11666 #define RCM_SSRS0_SLOC_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11667 #define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
AnnaBridge 189:f392fc9709a3 11668 #define RCM_SSRS0_SLOL_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 11669 #define RCM_SSRS0_SLOL_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11670 #define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
AnnaBridge 189:f392fc9709a3 11671 #define RCM_SSRS0_SWDOG_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11672 #define RCM_SSRS0_SWDOG_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11673 #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
AnnaBridge 189:f392fc9709a3 11674 #define RCM_SSRS0_SPIN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11675 #define RCM_SSRS0_SPIN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11676 #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
AnnaBridge 189:f392fc9709a3 11677 #define RCM_SSRS0_SPOR_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 11678 #define RCM_SSRS0_SPOR_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 11679 #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
AnnaBridge 189:f392fc9709a3 11680
AnnaBridge 189:f392fc9709a3 11681 /*! @name SSRS1 - Sticky System Reset Status Register 1 */
AnnaBridge 189:f392fc9709a3 11682 #define RCM_SSRS1_SJTAG_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11683 #define RCM_SSRS1_SJTAG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11684 #define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
AnnaBridge 189:f392fc9709a3 11685 #define RCM_SSRS1_SLOCKUP_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11686 #define RCM_SSRS1_SLOCKUP_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11687 #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
AnnaBridge 189:f392fc9709a3 11688 #define RCM_SSRS1_SSW_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11689 #define RCM_SSRS1_SSW_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11690 #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
AnnaBridge 189:f392fc9709a3 11691 #define RCM_SSRS1_SMDM_AP_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 11692 #define RCM_SSRS1_SMDM_AP_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11693 #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
AnnaBridge 189:f392fc9709a3 11694 #define RCM_SSRS1_SSACKERR_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11695 #define RCM_SSRS1_SSACKERR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11696 #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
AnnaBridge 189:f392fc9709a3 11697
AnnaBridge 189:f392fc9709a3 11698
AnnaBridge 189:f392fc9709a3 11699 /*!
AnnaBridge 189:f392fc9709a3 11700 * @}
AnnaBridge 189:f392fc9709a3 11701 */ /* end of group RCM_Register_Masks */
AnnaBridge 189:f392fc9709a3 11702
AnnaBridge 189:f392fc9709a3 11703
AnnaBridge 189:f392fc9709a3 11704 /* RCM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 11705 /** Peripheral RCM base address */
AnnaBridge 189:f392fc9709a3 11706 #define RCM_BASE (0x4007F000u)
AnnaBridge 189:f392fc9709a3 11707 /** Peripheral RCM base pointer */
AnnaBridge 189:f392fc9709a3 11708 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 189:f392fc9709a3 11709 /** Array initializer of RCM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 11710 #define RCM_BASE_ADDRS { RCM_BASE }
AnnaBridge 189:f392fc9709a3 11711 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 11712 #define RCM_BASE_PTRS { RCM }
AnnaBridge 189:f392fc9709a3 11713
AnnaBridge 189:f392fc9709a3 11714 /*!
AnnaBridge 189:f392fc9709a3 11715 * @}
AnnaBridge 189:f392fc9709a3 11716 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 11717
AnnaBridge 189:f392fc9709a3 11718
AnnaBridge 189:f392fc9709a3 11719 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11720 -- RFSYS Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11721 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11722
AnnaBridge 189:f392fc9709a3 11723 /*!
AnnaBridge 189:f392fc9709a3 11724 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11725 * @{
AnnaBridge 189:f392fc9709a3 11726 */
AnnaBridge 189:f392fc9709a3 11727
AnnaBridge 189:f392fc9709a3 11728 /** RFSYS - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 11729 typedef struct {
AnnaBridge 189:f392fc9709a3 11730 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 11731 } RFSYS_Type;
AnnaBridge 189:f392fc9709a3 11732
AnnaBridge 189:f392fc9709a3 11733 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11734 -- RFSYS Register Masks
AnnaBridge 189:f392fc9709a3 11735 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11736
AnnaBridge 189:f392fc9709a3 11737 /*!
AnnaBridge 189:f392fc9709a3 11738 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge 189:f392fc9709a3 11739 * @{
AnnaBridge 189:f392fc9709a3 11740 */
AnnaBridge 189:f392fc9709a3 11741
AnnaBridge 189:f392fc9709a3 11742 /*! @name REG - Register file register */
AnnaBridge 189:f392fc9709a3 11743 #define RFSYS_REG_LL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 11744 #define RFSYS_REG_LL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11745 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
AnnaBridge 189:f392fc9709a3 11746 #define RFSYS_REG_LH_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 11747 #define RFSYS_REG_LH_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11748 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
AnnaBridge 189:f392fc9709a3 11749 #define RFSYS_REG_HL_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 11750 #define RFSYS_REG_HL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11751 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
AnnaBridge 189:f392fc9709a3 11752 #define RFSYS_REG_HH_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 11753 #define RFSYS_REG_HH_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11754 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
AnnaBridge 189:f392fc9709a3 11755
AnnaBridge 189:f392fc9709a3 11756 /* The count of RFSYS_REG */
AnnaBridge 189:f392fc9709a3 11757 #define RFSYS_REG_COUNT (8U)
AnnaBridge 189:f392fc9709a3 11758
AnnaBridge 189:f392fc9709a3 11759
AnnaBridge 189:f392fc9709a3 11760 /*!
AnnaBridge 189:f392fc9709a3 11761 * @}
AnnaBridge 189:f392fc9709a3 11762 */ /* end of group RFSYS_Register_Masks */
AnnaBridge 189:f392fc9709a3 11763
AnnaBridge 189:f392fc9709a3 11764
AnnaBridge 189:f392fc9709a3 11765 /* RFSYS - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 11766 /** Peripheral RFSYS base address */
AnnaBridge 189:f392fc9709a3 11767 #define RFSYS_BASE (0x40041000u)
AnnaBridge 189:f392fc9709a3 11768 /** Peripheral RFSYS base pointer */
AnnaBridge 189:f392fc9709a3 11769 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge 189:f392fc9709a3 11770 /** Array initializer of RFSYS peripheral base addresses */
AnnaBridge 189:f392fc9709a3 11771 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
AnnaBridge 189:f392fc9709a3 11772 /** Array initializer of RFSYS peripheral base pointers */
AnnaBridge 189:f392fc9709a3 11773 #define RFSYS_BASE_PTRS { RFSYS }
AnnaBridge 189:f392fc9709a3 11774
AnnaBridge 189:f392fc9709a3 11775 /*!
AnnaBridge 189:f392fc9709a3 11776 * @}
AnnaBridge 189:f392fc9709a3 11777 */ /* end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 11778
AnnaBridge 189:f392fc9709a3 11779
AnnaBridge 189:f392fc9709a3 11780 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11781 -- RFVBAT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11782 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11783
AnnaBridge 189:f392fc9709a3 11784 /*!
AnnaBridge 189:f392fc9709a3 11785 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11786 * @{
AnnaBridge 189:f392fc9709a3 11787 */
AnnaBridge 189:f392fc9709a3 11788
AnnaBridge 189:f392fc9709a3 11789 /** RFVBAT - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 11790 typedef struct {
AnnaBridge 189:f392fc9709a3 11791 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 11792 } RFVBAT_Type;
AnnaBridge 189:f392fc9709a3 11793
AnnaBridge 189:f392fc9709a3 11794 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11795 -- RFVBAT Register Masks
AnnaBridge 189:f392fc9709a3 11796 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11797
AnnaBridge 189:f392fc9709a3 11798 /*!
AnnaBridge 189:f392fc9709a3 11799 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
AnnaBridge 189:f392fc9709a3 11800 * @{
AnnaBridge 189:f392fc9709a3 11801 */
AnnaBridge 189:f392fc9709a3 11802
AnnaBridge 189:f392fc9709a3 11803 /*! @name REG - VBAT register file register */
AnnaBridge 189:f392fc9709a3 11804 #define RFVBAT_REG_LL_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 11805 #define RFVBAT_REG_LL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11806 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
AnnaBridge 189:f392fc9709a3 11807 #define RFVBAT_REG_LH_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 11808 #define RFVBAT_REG_LH_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11809 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
AnnaBridge 189:f392fc9709a3 11810 #define RFVBAT_REG_HL_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 11811 #define RFVBAT_REG_HL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11812 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
AnnaBridge 189:f392fc9709a3 11813 #define RFVBAT_REG_HH_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 11814 #define RFVBAT_REG_HH_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11815 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
AnnaBridge 189:f392fc9709a3 11816
AnnaBridge 189:f392fc9709a3 11817 /* The count of RFVBAT_REG */
AnnaBridge 189:f392fc9709a3 11818 #define RFVBAT_REG_COUNT (8U)
AnnaBridge 189:f392fc9709a3 11819
AnnaBridge 189:f392fc9709a3 11820
AnnaBridge 189:f392fc9709a3 11821 /*!
AnnaBridge 189:f392fc9709a3 11822 * @}
AnnaBridge 189:f392fc9709a3 11823 */ /* end of group RFVBAT_Register_Masks */
AnnaBridge 189:f392fc9709a3 11824
AnnaBridge 189:f392fc9709a3 11825
AnnaBridge 189:f392fc9709a3 11826 /* RFVBAT - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 11827 /** Peripheral RFVBAT base address */
AnnaBridge 189:f392fc9709a3 11828 #define RFVBAT_BASE (0x4003E000u)
AnnaBridge 189:f392fc9709a3 11829 /** Peripheral RFVBAT base pointer */
AnnaBridge 189:f392fc9709a3 11830 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
AnnaBridge 189:f392fc9709a3 11831 /** Array initializer of RFVBAT peripheral base addresses */
AnnaBridge 189:f392fc9709a3 11832 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
AnnaBridge 189:f392fc9709a3 11833 /** Array initializer of RFVBAT peripheral base pointers */
AnnaBridge 189:f392fc9709a3 11834 #define RFVBAT_BASE_PTRS { RFVBAT }
AnnaBridge 189:f392fc9709a3 11835
AnnaBridge 189:f392fc9709a3 11836 /*!
AnnaBridge 189:f392fc9709a3 11837 * @}
AnnaBridge 189:f392fc9709a3 11838 */ /* end of group RFVBAT_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 11839
AnnaBridge 189:f392fc9709a3 11840
AnnaBridge 189:f392fc9709a3 11841 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11842 -- RTC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11843 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11844
AnnaBridge 189:f392fc9709a3 11845 /*!
AnnaBridge 189:f392fc9709a3 11846 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 11847 * @{
AnnaBridge 189:f392fc9709a3 11848 */
AnnaBridge 189:f392fc9709a3 11849
AnnaBridge 189:f392fc9709a3 11850 /** RTC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 11851 typedef struct {
AnnaBridge 189:f392fc9709a3 11852 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 11853 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 11854 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 11855 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 11856 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 11857 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 11858 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 11859 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 11860 uint8_t RESERVED_0[2016];
AnnaBridge 189:f392fc9709a3 11861 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
AnnaBridge 189:f392fc9709a3 11862 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
AnnaBridge 189:f392fc9709a3 11863 } RTC_Type;
AnnaBridge 189:f392fc9709a3 11864
AnnaBridge 189:f392fc9709a3 11865 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 11866 -- RTC Register Masks
AnnaBridge 189:f392fc9709a3 11867 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 11868
AnnaBridge 189:f392fc9709a3 11869 /*!
AnnaBridge 189:f392fc9709a3 11870 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 189:f392fc9709a3 11871 * @{
AnnaBridge 189:f392fc9709a3 11872 */
AnnaBridge 189:f392fc9709a3 11873
AnnaBridge 189:f392fc9709a3 11874 /*! @name TSR - RTC Time Seconds Register */
AnnaBridge 189:f392fc9709a3 11875 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 11876 #define RTC_TSR_TSR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11877 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
AnnaBridge 189:f392fc9709a3 11878
AnnaBridge 189:f392fc9709a3 11879 /*! @name TPR - RTC Time Prescaler Register */
AnnaBridge 189:f392fc9709a3 11880 #define RTC_TPR_TPR_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 11881 #define RTC_TPR_TPR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11882 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
AnnaBridge 189:f392fc9709a3 11883
AnnaBridge 189:f392fc9709a3 11884 /*! @name TAR - RTC Time Alarm Register */
AnnaBridge 189:f392fc9709a3 11885 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 11886 #define RTC_TAR_TAR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11887 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
AnnaBridge 189:f392fc9709a3 11888
AnnaBridge 189:f392fc9709a3 11889 /*! @name TCR - RTC Time Compensation Register */
AnnaBridge 189:f392fc9709a3 11890 #define RTC_TCR_TCR_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 11891 #define RTC_TCR_TCR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11892 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
AnnaBridge 189:f392fc9709a3 11893 #define RTC_TCR_CIR_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 11894 #define RTC_TCR_CIR_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11895 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
AnnaBridge 189:f392fc9709a3 11896 #define RTC_TCR_TCV_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 11897 #define RTC_TCR_TCV_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 11898 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
AnnaBridge 189:f392fc9709a3 11899 #define RTC_TCR_CIC_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 11900 #define RTC_TCR_CIC_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 11901 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
AnnaBridge 189:f392fc9709a3 11902
AnnaBridge 189:f392fc9709a3 11903 /*! @name CR - RTC Control Register */
AnnaBridge 189:f392fc9709a3 11904 #define RTC_CR_SWR_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11905 #define RTC_CR_SWR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11906 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
AnnaBridge 189:f392fc9709a3 11907 #define RTC_CR_WPE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11908 #define RTC_CR_WPE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11909 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
AnnaBridge 189:f392fc9709a3 11910 #define RTC_CR_SUP_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11911 #define RTC_CR_SUP_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11912 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
AnnaBridge 189:f392fc9709a3 11913 #define RTC_CR_UM_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 11914 #define RTC_CR_UM_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11915 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
AnnaBridge 189:f392fc9709a3 11916 #define RTC_CR_WPS_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 11917 #define RTC_CR_WPS_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 11918 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
AnnaBridge 189:f392fc9709a3 11919 #define RTC_CR_OSCE_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 11920 #define RTC_CR_OSCE_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 11921 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
AnnaBridge 189:f392fc9709a3 11922 #define RTC_CR_CLKO_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 11923 #define RTC_CR_CLKO_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 11924 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
AnnaBridge 189:f392fc9709a3 11925 #define RTC_CR_SC16P_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 11926 #define RTC_CR_SC16P_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 11927 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
AnnaBridge 189:f392fc9709a3 11928 #define RTC_CR_SC8P_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 11929 #define RTC_CR_SC8P_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 11930 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
AnnaBridge 189:f392fc9709a3 11931 #define RTC_CR_SC4P_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 11932 #define RTC_CR_SC4P_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 11933 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
AnnaBridge 189:f392fc9709a3 11934 #define RTC_CR_SC2P_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 11935 #define RTC_CR_SC2P_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 11936 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
AnnaBridge 189:f392fc9709a3 11937
AnnaBridge 189:f392fc9709a3 11938 /*! @name SR - RTC Status Register */
AnnaBridge 189:f392fc9709a3 11939 #define RTC_SR_TIF_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11940 #define RTC_SR_TIF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11941 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
AnnaBridge 189:f392fc9709a3 11942 #define RTC_SR_TOF_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11943 #define RTC_SR_TOF_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11944 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
AnnaBridge 189:f392fc9709a3 11945 #define RTC_SR_TAF_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11946 #define RTC_SR_TAF_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11947 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
AnnaBridge 189:f392fc9709a3 11948 #define RTC_SR_TCE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 11949 #define RTC_SR_TCE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 11950 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
AnnaBridge 189:f392fc9709a3 11951
AnnaBridge 189:f392fc9709a3 11952 /*! @name LR - RTC Lock Register */
AnnaBridge 189:f392fc9709a3 11953 #define RTC_LR_TCL_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 11954 #define RTC_LR_TCL_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11955 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
AnnaBridge 189:f392fc9709a3 11956 #define RTC_LR_CRL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 11957 #define RTC_LR_CRL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 11958 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
AnnaBridge 189:f392fc9709a3 11959 #define RTC_LR_SRL_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 11960 #define RTC_LR_SRL_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 11961 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
AnnaBridge 189:f392fc9709a3 11962 #define RTC_LR_LRL_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 11963 #define RTC_LR_LRL_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 11964 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
AnnaBridge 189:f392fc9709a3 11965
AnnaBridge 189:f392fc9709a3 11966 /*! @name IER - RTC Interrupt Enable Register */
AnnaBridge 189:f392fc9709a3 11967 #define RTC_IER_TIIE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11968 #define RTC_IER_TIIE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11969 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
AnnaBridge 189:f392fc9709a3 11970 #define RTC_IER_TOIE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11971 #define RTC_IER_TOIE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11972 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
AnnaBridge 189:f392fc9709a3 11973 #define RTC_IER_TAIE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11974 #define RTC_IER_TAIE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11975 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
AnnaBridge 189:f392fc9709a3 11976 #define RTC_IER_TSIE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 11977 #define RTC_IER_TSIE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 11978 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
AnnaBridge 189:f392fc9709a3 11979 #define RTC_IER_WPON_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 11980 #define RTC_IER_WPON_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 11981 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
AnnaBridge 189:f392fc9709a3 11982
AnnaBridge 189:f392fc9709a3 11983 /*! @name WAR - RTC Write Access Register */
AnnaBridge 189:f392fc9709a3 11984 #define RTC_WAR_TSRW_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 11985 #define RTC_WAR_TSRW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 11986 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
AnnaBridge 189:f392fc9709a3 11987 #define RTC_WAR_TPRW_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 11988 #define RTC_WAR_TPRW_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 11989 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
AnnaBridge 189:f392fc9709a3 11990 #define RTC_WAR_TARW_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 11991 #define RTC_WAR_TARW_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 11992 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
AnnaBridge 189:f392fc9709a3 11993 #define RTC_WAR_TCRW_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 11994 #define RTC_WAR_TCRW_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 11995 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
AnnaBridge 189:f392fc9709a3 11996 #define RTC_WAR_CRW_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 11997 #define RTC_WAR_CRW_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 11998 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
AnnaBridge 189:f392fc9709a3 11999 #define RTC_WAR_SRW_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12000 #define RTC_WAR_SRW_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12001 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
AnnaBridge 189:f392fc9709a3 12002 #define RTC_WAR_LRW_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12003 #define RTC_WAR_LRW_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12004 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
AnnaBridge 189:f392fc9709a3 12005 #define RTC_WAR_IERW_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12006 #define RTC_WAR_IERW_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12007 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
AnnaBridge 189:f392fc9709a3 12008
AnnaBridge 189:f392fc9709a3 12009 /*! @name RAR - RTC Read Access Register */
AnnaBridge 189:f392fc9709a3 12010 #define RTC_RAR_TSRR_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12011 #define RTC_RAR_TSRR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12012 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
AnnaBridge 189:f392fc9709a3 12013 #define RTC_RAR_TPRR_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12014 #define RTC_RAR_TPRR_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12015 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
AnnaBridge 189:f392fc9709a3 12016 #define RTC_RAR_TARR_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12017 #define RTC_RAR_TARR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12018 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
AnnaBridge 189:f392fc9709a3 12019 #define RTC_RAR_TCRR_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12020 #define RTC_RAR_TCRR_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12021 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
AnnaBridge 189:f392fc9709a3 12022 #define RTC_RAR_CRR_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12023 #define RTC_RAR_CRR_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12024 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
AnnaBridge 189:f392fc9709a3 12025 #define RTC_RAR_SRR_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12026 #define RTC_RAR_SRR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12027 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
AnnaBridge 189:f392fc9709a3 12028 #define RTC_RAR_LRR_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12029 #define RTC_RAR_LRR_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12030 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
AnnaBridge 189:f392fc9709a3 12031 #define RTC_RAR_IERR_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12032 #define RTC_RAR_IERR_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12033 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
AnnaBridge 189:f392fc9709a3 12034
AnnaBridge 189:f392fc9709a3 12035
AnnaBridge 189:f392fc9709a3 12036 /*!
AnnaBridge 189:f392fc9709a3 12037 * @}
AnnaBridge 189:f392fc9709a3 12038 */ /* end of group RTC_Register_Masks */
AnnaBridge 189:f392fc9709a3 12039
AnnaBridge 189:f392fc9709a3 12040
AnnaBridge 189:f392fc9709a3 12041 /* RTC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 12042 /** Peripheral RTC base address */
AnnaBridge 189:f392fc9709a3 12043 #define RTC_BASE (0x4003D000u)
AnnaBridge 189:f392fc9709a3 12044 /** Peripheral RTC base pointer */
AnnaBridge 189:f392fc9709a3 12045 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 189:f392fc9709a3 12046 /** Array initializer of RTC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 12047 #define RTC_BASE_ADDRS { RTC_BASE }
AnnaBridge 189:f392fc9709a3 12048 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 12049 #define RTC_BASE_PTRS { RTC }
AnnaBridge 189:f392fc9709a3 12050 /** Interrupt vectors for the RTC peripheral type */
AnnaBridge 189:f392fc9709a3 12051 #define RTC_IRQS { RTC_IRQn }
AnnaBridge 189:f392fc9709a3 12052 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
AnnaBridge 189:f392fc9709a3 12053
AnnaBridge 189:f392fc9709a3 12054 /*!
AnnaBridge 189:f392fc9709a3 12055 * @}
AnnaBridge 189:f392fc9709a3 12056 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 12057
AnnaBridge 189:f392fc9709a3 12058
AnnaBridge 189:f392fc9709a3 12059 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 12060 -- SDHC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 12061 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 12062
AnnaBridge 189:f392fc9709a3 12063 /*!
AnnaBridge 189:f392fc9709a3 12064 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 12065 * @{
AnnaBridge 189:f392fc9709a3 12066 */
AnnaBridge 189:f392fc9709a3 12067
AnnaBridge 189:f392fc9709a3 12068 /** SDHC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 12069 typedef struct {
AnnaBridge 189:f392fc9709a3 12070 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 12071 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 12072 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 12073 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 12074 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 12075 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 12076 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 12077 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 12078 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 12079 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 12080 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 12081 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
AnnaBridge 189:f392fc9709a3 12082 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
AnnaBridge 189:f392fc9709a3 12083 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 12084 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
AnnaBridge 189:f392fc9709a3 12085 uint8_t RESERVED_0[8];
AnnaBridge 189:f392fc9709a3 12086 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
AnnaBridge 189:f392fc9709a3 12087 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
AnnaBridge 189:f392fc9709a3 12088 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
AnnaBridge 189:f392fc9709a3 12089 uint8_t RESERVED_1[100];
AnnaBridge 189:f392fc9709a3 12090 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
AnnaBridge 189:f392fc9709a3 12091 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
AnnaBridge 189:f392fc9709a3 12092 uint8_t RESERVED_2[52];
AnnaBridge 189:f392fc9709a3 12093 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
AnnaBridge 189:f392fc9709a3 12094 } SDHC_Type;
AnnaBridge 189:f392fc9709a3 12095
AnnaBridge 189:f392fc9709a3 12096 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 12097 -- SDHC Register Masks
AnnaBridge 189:f392fc9709a3 12098 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 12099
AnnaBridge 189:f392fc9709a3 12100 /*!
AnnaBridge 189:f392fc9709a3 12101 * @addtogroup SDHC_Register_Masks SDHC Register Masks
AnnaBridge 189:f392fc9709a3 12102 * @{
AnnaBridge 189:f392fc9709a3 12103 */
AnnaBridge 189:f392fc9709a3 12104
AnnaBridge 189:f392fc9709a3 12105 /*! @name DSADDR - DMA System Address register */
AnnaBridge 189:f392fc9709a3 12106 #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 189:f392fc9709a3 12107 #define SDHC_DSADDR_DSADDR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12108 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
AnnaBridge 189:f392fc9709a3 12109
AnnaBridge 189:f392fc9709a3 12110 /*! @name BLKATTR - Block Attributes register */
AnnaBridge 189:f392fc9709a3 12111 #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
AnnaBridge 189:f392fc9709a3 12112 #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12113 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
AnnaBridge 189:f392fc9709a3 12114 #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 12115 #define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12116 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
AnnaBridge 189:f392fc9709a3 12117
AnnaBridge 189:f392fc9709a3 12118 /*! @name CMDARG - Command Argument register */
AnnaBridge 189:f392fc9709a3 12119 #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 12120 #define SDHC_CMDARG_CMDARG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12121 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
AnnaBridge 189:f392fc9709a3 12122
AnnaBridge 189:f392fc9709a3 12123 /*! @name XFERTYP - Transfer Type register */
AnnaBridge 189:f392fc9709a3 12124 #define SDHC_XFERTYP_DMAEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12125 #define SDHC_XFERTYP_DMAEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12126 #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
AnnaBridge 189:f392fc9709a3 12127 #define SDHC_XFERTYP_BCEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12128 #define SDHC_XFERTYP_BCEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12129 #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
AnnaBridge 189:f392fc9709a3 12130 #define SDHC_XFERTYP_AC12EN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12131 #define SDHC_XFERTYP_AC12EN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12132 #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
AnnaBridge 189:f392fc9709a3 12133 #define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12134 #define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12135 #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
AnnaBridge 189:f392fc9709a3 12136 #define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12137 #define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12138 #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
AnnaBridge 189:f392fc9709a3 12139 #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 12140 #define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12141 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
AnnaBridge 189:f392fc9709a3 12142 #define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 12143 #define SDHC_XFERTYP_CCCEN_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 12144 #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
AnnaBridge 189:f392fc9709a3 12145 #define SDHC_XFERTYP_CICEN_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 12146 #define SDHC_XFERTYP_CICEN_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12147 #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
AnnaBridge 189:f392fc9709a3 12148 #define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 12149 #define SDHC_XFERTYP_DPSEL_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 12150 #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
AnnaBridge 189:f392fc9709a3 12151 #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
AnnaBridge 189:f392fc9709a3 12152 #define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12153 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
AnnaBridge 189:f392fc9709a3 12154 #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
AnnaBridge 189:f392fc9709a3 12155 #define SDHC_XFERTYP_CMDINX_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12156 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
AnnaBridge 189:f392fc9709a3 12157
AnnaBridge 189:f392fc9709a3 12158 /*! @name CMDRSP - Command Response 0..Command Response 3 */
AnnaBridge 189:f392fc9709a3 12159 #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 12160 #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12161 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
AnnaBridge 189:f392fc9709a3 12162 #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 12163 #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12164 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
AnnaBridge 189:f392fc9709a3 12165 #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 12166 #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12167 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
AnnaBridge 189:f392fc9709a3 12168 #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 12169 #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12170 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
AnnaBridge 189:f392fc9709a3 12171
AnnaBridge 189:f392fc9709a3 12172 /* The count of SDHC_CMDRSP */
AnnaBridge 189:f392fc9709a3 12173 #define SDHC_CMDRSP_COUNT (4U)
AnnaBridge 189:f392fc9709a3 12174
AnnaBridge 189:f392fc9709a3 12175 /*! @name DATPORT - Buffer Data Port register */
AnnaBridge 189:f392fc9709a3 12176 #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 12177 #define SDHC_DATPORT_DATCONT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12178 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
AnnaBridge 189:f392fc9709a3 12179
AnnaBridge 189:f392fc9709a3 12180 /*! @name PRSSTAT - Present State register */
AnnaBridge 189:f392fc9709a3 12181 #define SDHC_PRSSTAT_CIHB_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12182 #define SDHC_PRSSTAT_CIHB_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12183 #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
AnnaBridge 189:f392fc9709a3 12184 #define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12185 #define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12186 #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
AnnaBridge 189:f392fc9709a3 12187 #define SDHC_PRSSTAT_DLA_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12188 #define SDHC_PRSSTAT_DLA_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12189 #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
AnnaBridge 189:f392fc9709a3 12190 #define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12191 #define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12192 #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
AnnaBridge 189:f392fc9709a3 12193 #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12194 #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12195 #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
AnnaBridge 189:f392fc9709a3 12196 #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12197 #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12198 #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
AnnaBridge 189:f392fc9709a3 12199 #define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12200 #define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12201 #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
AnnaBridge 189:f392fc9709a3 12202 #define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12203 #define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12204 #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
AnnaBridge 189:f392fc9709a3 12205 #define SDHC_PRSSTAT_WTA_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 12206 #define SDHC_PRSSTAT_WTA_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12207 #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
AnnaBridge 189:f392fc9709a3 12208 #define SDHC_PRSSTAT_RTA_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 12209 #define SDHC_PRSSTAT_RTA_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 12210 #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
AnnaBridge 189:f392fc9709a3 12211 #define SDHC_PRSSTAT_BWEN_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 12212 #define SDHC_PRSSTAT_BWEN_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 12213 #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
AnnaBridge 189:f392fc9709a3 12214 #define SDHC_PRSSTAT_BREN_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 12215 #define SDHC_PRSSTAT_BREN_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 12216 #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
AnnaBridge 189:f392fc9709a3 12217 #define SDHC_PRSSTAT_CINS_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 12218 #define SDHC_PRSSTAT_CINS_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12219 #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
AnnaBridge 189:f392fc9709a3 12220 #define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 12221 #define SDHC_PRSSTAT_CLSL_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 12222 #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
AnnaBridge 189:f392fc9709a3 12223 #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 12224 #define SDHC_PRSSTAT_DLSL_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12225 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
AnnaBridge 189:f392fc9709a3 12226
AnnaBridge 189:f392fc9709a3 12227 /*! @name PROCTL - Protocol Control register */
AnnaBridge 189:f392fc9709a3 12228 #define SDHC_PROCTL_LCTL_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12229 #define SDHC_PROCTL_LCTL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12230 #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
AnnaBridge 189:f392fc9709a3 12231 #define SDHC_PROCTL_DTW_MASK (0x6U)
AnnaBridge 189:f392fc9709a3 12232 #define SDHC_PROCTL_DTW_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12233 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
AnnaBridge 189:f392fc9709a3 12234 #define SDHC_PROCTL_D3CD_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12235 #define SDHC_PROCTL_D3CD_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12236 #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
AnnaBridge 189:f392fc9709a3 12237 #define SDHC_PROCTL_EMODE_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 12238 #define SDHC_PROCTL_EMODE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12239 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
AnnaBridge 189:f392fc9709a3 12240 #define SDHC_PROCTL_CDTL_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12241 #define SDHC_PROCTL_CDTL_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12242 #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
AnnaBridge 189:f392fc9709a3 12243 #define SDHC_PROCTL_CDSS_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12244 #define SDHC_PROCTL_CDSS_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12245 #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
AnnaBridge 189:f392fc9709a3 12246 #define SDHC_PROCTL_DMAS_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 12247 #define SDHC_PROCTL_DMAS_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12248 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
AnnaBridge 189:f392fc9709a3 12249 #define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 12250 #define SDHC_PROCTL_SABGREQ_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12251 #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
AnnaBridge 189:f392fc9709a3 12252 #define SDHC_PROCTL_CREQ_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 12253 #define SDHC_PROCTL_CREQ_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 12254 #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
AnnaBridge 189:f392fc9709a3 12255 #define SDHC_PROCTL_RWCTL_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 12256 #define SDHC_PROCTL_RWCTL_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12257 #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
AnnaBridge 189:f392fc9709a3 12258 #define SDHC_PROCTL_IABG_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 12259 #define SDHC_PROCTL_IABG_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 12260 #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
AnnaBridge 189:f392fc9709a3 12261 #define SDHC_PROCTL_WECINT_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12262 #define SDHC_PROCTL_WECINT_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12263 #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
AnnaBridge 189:f392fc9709a3 12264 #define SDHC_PROCTL_WECINS_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 12265 #define SDHC_PROCTL_WECINS_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 12266 #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
AnnaBridge 189:f392fc9709a3 12267 #define SDHC_PROCTL_WECRM_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 12268 #define SDHC_PROCTL_WECRM_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 12269 #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
AnnaBridge 189:f392fc9709a3 12270
AnnaBridge 189:f392fc9709a3 12271 /*! @name SYSCTL - System Control register */
AnnaBridge 189:f392fc9709a3 12272 #define SDHC_SYSCTL_IPGEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12273 #define SDHC_SYSCTL_IPGEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12274 #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
AnnaBridge 189:f392fc9709a3 12275 #define SDHC_SYSCTL_HCKEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12276 #define SDHC_SYSCTL_HCKEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12277 #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
AnnaBridge 189:f392fc9709a3 12278 #define SDHC_SYSCTL_PEREN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12279 #define SDHC_SYSCTL_PEREN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12280 #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
AnnaBridge 189:f392fc9709a3 12281 #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12282 #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12283 #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
AnnaBridge 189:f392fc9709a3 12284 #define SDHC_SYSCTL_DVS_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 12285 #define SDHC_SYSCTL_DVS_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12286 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
AnnaBridge 189:f392fc9709a3 12287 #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 12288 #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12289 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
AnnaBridge 189:f392fc9709a3 12290 #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 12291 #define SDHC_SYSCTL_DTOCV_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12292 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
AnnaBridge 189:f392fc9709a3 12293 #define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12294 #define SDHC_SYSCTL_RSTA_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12295 #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
AnnaBridge 189:f392fc9709a3 12296 #define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 12297 #define SDHC_SYSCTL_RSTC_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 12298 #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
AnnaBridge 189:f392fc9709a3 12299 #define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 12300 #define SDHC_SYSCTL_RSTD_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 12301 #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
AnnaBridge 189:f392fc9709a3 12302 #define SDHC_SYSCTL_INITA_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 12303 #define SDHC_SYSCTL_INITA_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 12304 #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
AnnaBridge 189:f392fc9709a3 12305
AnnaBridge 189:f392fc9709a3 12306 /*! @name IRQSTAT - Interrupt Status register */
AnnaBridge 189:f392fc9709a3 12307 #define SDHC_IRQSTAT_CC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12308 #define SDHC_IRQSTAT_CC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12309 #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
AnnaBridge 189:f392fc9709a3 12310 #define SDHC_IRQSTAT_TC_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12311 #define SDHC_IRQSTAT_TC_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12312 #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
AnnaBridge 189:f392fc9709a3 12313 #define SDHC_IRQSTAT_BGE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12314 #define SDHC_IRQSTAT_BGE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12315 #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
AnnaBridge 189:f392fc9709a3 12316 #define SDHC_IRQSTAT_DINT_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12317 #define SDHC_IRQSTAT_DINT_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12318 #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
AnnaBridge 189:f392fc9709a3 12319 #define SDHC_IRQSTAT_BWR_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12320 #define SDHC_IRQSTAT_BWR_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12321 #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
AnnaBridge 189:f392fc9709a3 12322 #define SDHC_IRQSTAT_BRR_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12323 #define SDHC_IRQSTAT_BRR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12324 #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
AnnaBridge 189:f392fc9709a3 12325 #define SDHC_IRQSTAT_CINS_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12326 #define SDHC_IRQSTAT_CINS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12327 #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
AnnaBridge 189:f392fc9709a3 12328 #define SDHC_IRQSTAT_CRM_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12329 #define SDHC_IRQSTAT_CRM_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12330 #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
AnnaBridge 189:f392fc9709a3 12331 #define SDHC_IRQSTAT_CINT_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 12332 #define SDHC_IRQSTAT_CINT_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12333 #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
AnnaBridge 189:f392fc9709a3 12334 #define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 12335 #define SDHC_IRQSTAT_CTOE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12336 #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
AnnaBridge 189:f392fc9709a3 12337 #define SDHC_IRQSTAT_CCE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 12338 #define SDHC_IRQSTAT_CCE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 12339 #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
AnnaBridge 189:f392fc9709a3 12340 #define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 12341 #define SDHC_IRQSTAT_CEBE_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12342 #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
AnnaBridge 189:f392fc9709a3 12343 #define SDHC_IRQSTAT_CIE_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 12344 #define SDHC_IRQSTAT_CIE_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 12345 #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
AnnaBridge 189:f392fc9709a3 12346 #define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 12347 #define SDHC_IRQSTAT_DTOE_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12348 #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
AnnaBridge 189:f392fc9709a3 12349 #define SDHC_IRQSTAT_DCE_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 12350 #define SDHC_IRQSTAT_DCE_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 12351 #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
AnnaBridge 189:f392fc9709a3 12352 #define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 12353 #define SDHC_IRQSTAT_DEBE_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12354 #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
AnnaBridge 189:f392fc9709a3 12355 #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12356 #define SDHC_IRQSTAT_AC12E_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12357 #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
AnnaBridge 189:f392fc9709a3 12358 #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 12359 #define SDHC_IRQSTAT_DMAE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 12360 #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
AnnaBridge 189:f392fc9709a3 12361
AnnaBridge 189:f392fc9709a3 12362 /*! @name IRQSTATEN - Interrupt Status Enable register */
AnnaBridge 189:f392fc9709a3 12363 #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12364 #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12365 #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
AnnaBridge 189:f392fc9709a3 12366 #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12367 #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12368 #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
AnnaBridge 189:f392fc9709a3 12369 #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12370 #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12371 #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
AnnaBridge 189:f392fc9709a3 12372 #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12373 #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12374 #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
AnnaBridge 189:f392fc9709a3 12375 #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12376 #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12377 #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
AnnaBridge 189:f392fc9709a3 12378 #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12379 #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12380 #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
AnnaBridge 189:f392fc9709a3 12381 #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12382 #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12383 #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
AnnaBridge 189:f392fc9709a3 12384 #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12385 #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12386 #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
AnnaBridge 189:f392fc9709a3 12387 #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 12388 #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12389 #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
AnnaBridge 189:f392fc9709a3 12390 #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 12391 #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12392 #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
AnnaBridge 189:f392fc9709a3 12393 #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 12394 #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 12395 #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
AnnaBridge 189:f392fc9709a3 12396 #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 12397 #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12398 #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
AnnaBridge 189:f392fc9709a3 12399 #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 12400 #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 12401 #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
AnnaBridge 189:f392fc9709a3 12402 #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 12403 #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12404 #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
AnnaBridge 189:f392fc9709a3 12405 #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 12406 #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 12407 #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
AnnaBridge 189:f392fc9709a3 12408 #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 12409 #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12410 #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
AnnaBridge 189:f392fc9709a3 12411 #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12412 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12413 #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
AnnaBridge 189:f392fc9709a3 12414 #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 12415 #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 12416 #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
AnnaBridge 189:f392fc9709a3 12417
AnnaBridge 189:f392fc9709a3 12418 /*! @name IRQSIGEN - Interrupt Signal Enable register */
AnnaBridge 189:f392fc9709a3 12419 #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12420 #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12421 #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
AnnaBridge 189:f392fc9709a3 12422 #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12423 #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12424 #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
AnnaBridge 189:f392fc9709a3 12425 #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12426 #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12427 #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12428 #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12429 #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12430 #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
AnnaBridge 189:f392fc9709a3 12431 #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12432 #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12433 #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
AnnaBridge 189:f392fc9709a3 12434 #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12435 #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12436 #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
AnnaBridge 189:f392fc9709a3 12437 #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12438 #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12439 #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
AnnaBridge 189:f392fc9709a3 12440 #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12441 #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12442 #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
AnnaBridge 189:f392fc9709a3 12443 #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 12444 #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12445 #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
AnnaBridge 189:f392fc9709a3 12446 #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 12447 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12448 #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12449 #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 12450 #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 12451 #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12452 #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 12453 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12454 #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12455 #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 12456 #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 12457 #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12458 #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 12459 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12460 #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12461 #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 12462 #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 12463 #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12464 #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 12465 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12466 #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12467 #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12468 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12469 #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
AnnaBridge 189:f392fc9709a3 12470 #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 12471 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 12472 #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
AnnaBridge 189:f392fc9709a3 12473
AnnaBridge 189:f392fc9709a3 12474 /*! @name AC12ERR - Auto CMD12 Error Status Register */
AnnaBridge 189:f392fc9709a3 12475 #define SDHC_AC12ERR_AC12NE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12476 #define SDHC_AC12ERR_AC12NE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12477 #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
AnnaBridge 189:f392fc9709a3 12478 #define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12479 #define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12480 #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
AnnaBridge 189:f392fc9709a3 12481 #define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12482 #define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12483 #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
AnnaBridge 189:f392fc9709a3 12484 #define SDHC_AC12ERR_AC12CE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12485 #define SDHC_AC12ERR_AC12CE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12486 #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
AnnaBridge 189:f392fc9709a3 12487 #define SDHC_AC12ERR_AC12IE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12488 #define SDHC_AC12ERR_AC12IE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12489 #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
AnnaBridge 189:f392fc9709a3 12490 #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12491 #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12492 #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
AnnaBridge 189:f392fc9709a3 12493
AnnaBridge 189:f392fc9709a3 12494 /*! @name HTCAPBLT - Host Controller Capabilities */
AnnaBridge 189:f392fc9709a3 12495 #define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
AnnaBridge 189:f392fc9709a3 12496 #define SDHC_HTCAPBLT_MBL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12497 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
AnnaBridge 189:f392fc9709a3 12498 #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 12499 #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12500 #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
AnnaBridge 189:f392fc9709a3 12501 #define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 12502 #define SDHC_HTCAPBLT_HSS_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 12503 #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
AnnaBridge 189:f392fc9709a3 12504 #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 12505 #define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12506 #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
AnnaBridge 189:f392fc9709a3 12507 #define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 12508 #define SDHC_HTCAPBLT_SRS_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 12509 #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
AnnaBridge 189:f392fc9709a3 12510 #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12511 #define SDHC_HTCAPBLT_VS33_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12512 #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
AnnaBridge 189:f392fc9709a3 12513
AnnaBridge 189:f392fc9709a3 12514 /*! @name WML - Watermark Level Register */
AnnaBridge 189:f392fc9709a3 12515 #define SDHC_WML_RDWML_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 12516 #define SDHC_WML_RDWML_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12517 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
AnnaBridge 189:f392fc9709a3 12518 #define SDHC_WML_WRWML_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 12519 #define SDHC_WML_WRWML_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12520 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
AnnaBridge 189:f392fc9709a3 12521
AnnaBridge 189:f392fc9709a3 12522 /*! @name FEVT - Force Event register */
AnnaBridge 189:f392fc9709a3 12523 #define SDHC_FEVT_AC12NE_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12524 #define SDHC_FEVT_AC12NE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12525 #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
AnnaBridge 189:f392fc9709a3 12526 #define SDHC_FEVT_AC12TOE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12527 #define SDHC_FEVT_AC12TOE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12528 #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
AnnaBridge 189:f392fc9709a3 12529 #define SDHC_FEVT_AC12CE_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12530 #define SDHC_FEVT_AC12CE_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12531 #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
AnnaBridge 189:f392fc9709a3 12532 #define SDHC_FEVT_AC12EBE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12533 #define SDHC_FEVT_AC12EBE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12534 #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
AnnaBridge 189:f392fc9709a3 12535 #define SDHC_FEVT_AC12IE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12536 #define SDHC_FEVT_AC12IE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12537 #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
AnnaBridge 189:f392fc9709a3 12538 #define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12539 #define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12540 #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
AnnaBridge 189:f392fc9709a3 12541 #define SDHC_FEVT_CTOE_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 12542 #define SDHC_FEVT_CTOE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12543 #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
AnnaBridge 189:f392fc9709a3 12544 #define SDHC_FEVT_CCE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 12545 #define SDHC_FEVT_CCE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 12546 #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
AnnaBridge 189:f392fc9709a3 12547 #define SDHC_FEVT_CEBE_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 12548 #define SDHC_FEVT_CEBE_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12549 #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
AnnaBridge 189:f392fc9709a3 12550 #define SDHC_FEVT_CIE_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 12551 #define SDHC_FEVT_CIE_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 12552 #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
AnnaBridge 189:f392fc9709a3 12553 #define SDHC_FEVT_DTOE_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 12554 #define SDHC_FEVT_DTOE_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12555 #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
AnnaBridge 189:f392fc9709a3 12556 #define SDHC_FEVT_DCE_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 12557 #define SDHC_FEVT_DCE_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 12558 #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
AnnaBridge 189:f392fc9709a3 12559 #define SDHC_FEVT_DEBE_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 12560 #define SDHC_FEVT_DEBE_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12561 #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
AnnaBridge 189:f392fc9709a3 12562 #define SDHC_FEVT_AC12E_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12563 #define SDHC_FEVT_AC12E_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12564 #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
AnnaBridge 189:f392fc9709a3 12565 #define SDHC_FEVT_DMAE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 12566 #define SDHC_FEVT_DMAE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 12567 #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
AnnaBridge 189:f392fc9709a3 12568 #define SDHC_FEVT_CINT_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 12569 #define SDHC_FEVT_CINT_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 12570 #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
AnnaBridge 189:f392fc9709a3 12571
AnnaBridge 189:f392fc9709a3 12572 /*! @name ADMAES - ADMA Error Status register */
AnnaBridge 189:f392fc9709a3 12573 #define SDHC_ADMAES_ADMAES_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 12574 #define SDHC_ADMAES_ADMAES_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12575 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
AnnaBridge 189:f392fc9709a3 12576 #define SDHC_ADMAES_ADMALME_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12577 #define SDHC_ADMAES_ADMALME_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12578 #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
AnnaBridge 189:f392fc9709a3 12579 #define SDHC_ADMAES_ADMADCE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12580 #define SDHC_ADMAES_ADMADCE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12581 #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
AnnaBridge 189:f392fc9709a3 12582
AnnaBridge 189:f392fc9709a3 12583 /*! @name ADSADDR - ADMA System Addressregister */
AnnaBridge 189:f392fc9709a3 12584 #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 189:f392fc9709a3 12585 #define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12586 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
AnnaBridge 189:f392fc9709a3 12587
AnnaBridge 189:f392fc9709a3 12588 /*! @name VENDOR - Vendor Specific register */
AnnaBridge 189:f392fc9709a3 12589 #define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12590 #define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12591 #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
AnnaBridge 189:f392fc9709a3 12592 #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 12593 #define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12594 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
AnnaBridge 189:f392fc9709a3 12595
AnnaBridge 189:f392fc9709a3 12596 /*! @name MMCBOOT - MMC Boot register */
AnnaBridge 189:f392fc9709a3 12597 #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 12598 #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12599 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
AnnaBridge 189:f392fc9709a3 12600 #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12601 #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12602 #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
AnnaBridge 189:f392fc9709a3 12603 #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 12604 #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12605 #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
AnnaBridge 189:f392fc9709a3 12606 #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12607 #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12608 #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
AnnaBridge 189:f392fc9709a3 12609 #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12610 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12611 #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
AnnaBridge 189:f392fc9709a3 12612 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 12613 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12614 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
AnnaBridge 189:f392fc9709a3 12615
AnnaBridge 189:f392fc9709a3 12616 /*! @name HOSTVER - Host Controller Version */
AnnaBridge 189:f392fc9709a3 12617 #define SDHC_HOSTVER_SVN_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 12618 #define SDHC_HOSTVER_SVN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12619 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
AnnaBridge 189:f392fc9709a3 12620 #define SDHC_HOSTVER_VVN_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 12621 #define SDHC_HOSTVER_VVN_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12622 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
AnnaBridge 189:f392fc9709a3 12623
AnnaBridge 189:f392fc9709a3 12624
AnnaBridge 189:f392fc9709a3 12625 /*!
AnnaBridge 189:f392fc9709a3 12626 * @}
AnnaBridge 189:f392fc9709a3 12627 */ /* end of group SDHC_Register_Masks */
AnnaBridge 189:f392fc9709a3 12628
AnnaBridge 189:f392fc9709a3 12629
AnnaBridge 189:f392fc9709a3 12630 /* SDHC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 12631 /** Peripheral SDHC base address */
AnnaBridge 189:f392fc9709a3 12632 #define SDHC_BASE (0x400B1000u)
AnnaBridge 189:f392fc9709a3 12633 /** Peripheral SDHC base pointer */
AnnaBridge 189:f392fc9709a3 12634 #define SDHC ((SDHC_Type *)SDHC_BASE)
AnnaBridge 189:f392fc9709a3 12635 /** Array initializer of SDHC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 12636 #define SDHC_BASE_ADDRS { SDHC_BASE }
AnnaBridge 189:f392fc9709a3 12637 /** Array initializer of SDHC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 12638 #define SDHC_BASE_PTRS { SDHC }
AnnaBridge 189:f392fc9709a3 12639 /** Interrupt vectors for the SDHC peripheral type */
AnnaBridge 189:f392fc9709a3 12640 #define SDHC_IRQS { SDHC_IRQn }
AnnaBridge 189:f392fc9709a3 12641
AnnaBridge 189:f392fc9709a3 12642 /*!
AnnaBridge 189:f392fc9709a3 12643 * @}
AnnaBridge 189:f392fc9709a3 12644 */ /* end of group SDHC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 12645
AnnaBridge 189:f392fc9709a3 12646
AnnaBridge 189:f392fc9709a3 12647 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 12648 -- SDRAM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 12649 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 12650
AnnaBridge 189:f392fc9709a3 12651 /*!
AnnaBridge 189:f392fc9709a3 12652 * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 12653 * @{
AnnaBridge 189:f392fc9709a3 12654 */
AnnaBridge 189:f392fc9709a3 12655
AnnaBridge 189:f392fc9709a3 12656 /** SDRAM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 12657 typedef struct {
AnnaBridge 189:f392fc9709a3 12658 uint8_t RESERVED_0[66];
AnnaBridge 189:f392fc9709a3 12659 __IO uint16_t CTRL; /**< Control Register, offset: 0x42 */
AnnaBridge 189:f392fc9709a3 12660 uint8_t RESERVED_1[4];
AnnaBridge 189:f392fc9709a3 12661 struct { /* offset: 0x48, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 12662 __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 12663 __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 12664 } BLOCK[2];
AnnaBridge 189:f392fc9709a3 12665 } SDRAM_Type;
AnnaBridge 189:f392fc9709a3 12666
AnnaBridge 189:f392fc9709a3 12667 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 12668 -- SDRAM Register Masks
AnnaBridge 189:f392fc9709a3 12669 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 12670
AnnaBridge 189:f392fc9709a3 12671 /*!
AnnaBridge 189:f392fc9709a3 12672 * @addtogroup SDRAM_Register_Masks SDRAM Register Masks
AnnaBridge 189:f392fc9709a3 12673 * @{
AnnaBridge 189:f392fc9709a3 12674 */
AnnaBridge 189:f392fc9709a3 12675
AnnaBridge 189:f392fc9709a3 12676 /*! @name CTRL - Control Register */
AnnaBridge 189:f392fc9709a3 12677 #define SDRAM_CTRL_RC_MASK (0x1FFU)
AnnaBridge 189:f392fc9709a3 12678 #define SDRAM_CTRL_RC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12679 #define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
AnnaBridge 189:f392fc9709a3 12680 #define SDRAM_CTRL_RTIM_MASK (0x600U)
AnnaBridge 189:f392fc9709a3 12681 #define SDRAM_CTRL_RTIM_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 12682 #define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
AnnaBridge 189:f392fc9709a3 12683 #define SDRAM_CTRL_IS_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 12684 #define SDRAM_CTRL_IS_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 12685 #define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
AnnaBridge 189:f392fc9709a3 12686
AnnaBridge 189:f392fc9709a3 12687 /*! @name AC - Address and Control Register */
AnnaBridge 189:f392fc9709a3 12688 #define SDRAM_AC_IP_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12689 #define SDRAM_AC_IP_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12690 #define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
AnnaBridge 189:f392fc9709a3 12691 #define SDRAM_AC_PS_MASK (0x30U)
AnnaBridge 189:f392fc9709a3 12692 #define SDRAM_AC_PS_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12693 #define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
AnnaBridge 189:f392fc9709a3 12694 #define SDRAM_AC_IMRS_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 12695 #define SDRAM_AC_IMRS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 12696 #define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
AnnaBridge 189:f392fc9709a3 12697 #define SDRAM_AC_CBM_MASK (0x700U)
AnnaBridge 189:f392fc9709a3 12698 #define SDRAM_AC_CBM_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12699 #define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
AnnaBridge 189:f392fc9709a3 12700 #define SDRAM_AC_CASL_MASK (0x3000U)
AnnaBridge 189:f392fc9709a3 12701 #define SDRAM_AC_CASL_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 12702 #define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
AnnaBridge 189:f392fc9709a3 12703 #define SDRAM_AC_RE_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 12704 #define SDRAM_AC_RE_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 12705 #define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
AnnaBridge 189:f392fc9709a3 12706 #define SDRAM_AC_BA_MASK (0xFFFC0000U)
AnnaBridge 189:f392fc9709a3 12707 #define SDRAM_AC_BA_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12708 #define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
AnnaBridge 189:f392fc9709a3 12709
AnnaBridge 189:f392fc9709a3 12710 /* The count of SDRAM_AC */
AnnaBridge 189:f392fc9709a3 12711 #define SDRAM_AC_COUNT (2U)
AnnaBridge 189:f392fc9709a3 12712
AnnaBridge 189:f392fc9709a3 12713 /*! @name CM - Control Mask */
AnnaBridge 189:f392fc9709a3 12714 #define SDRAM_CM_V_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12715 #define SDRAM_CM_V_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12716 #define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
AnnaBridge 189:f392fc9709a3 12717 #define SDRAM_CM_WP_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 12718 #define SDRAM_CM_WP_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12719 #define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
AnnaBridge 189:f392fc9709a3 12720 #define SDRAM_CM_BAM_MASK (0xFFFC0000U)
AnnaBridge 189:f392fc9709a3 12721 #define SDRAM_CM_BAM_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12722 #define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
AnnaBridge 189:f392fc9709a3 12723
AnnaBridge 189:f392fc9709a3 12724 /* The count of SDRAM_CM */
AnnaBridge 189:f392fc9709a3 12725 #define SDRAM_CM_COUNT (2U)
AnnaBridge 189:f392fc9709a3 12726
AnnaBridge 189:f392fc9709a3 12727
AnnaBridge 189:f392fc9709a3 12728 /*!
AnnaBridge 189:f392fc9709a3 12729 * @}
AnnaBridge 189:f392fc9709a3 12730 */ /* end of group SDRAM_Register_Masks */
AnnaBridge 189:f392fc9709a3 12731
AnnaBridge 189:f392fc9709a3 12732
AnnaBridge 189:f392fc9709a3 12733 /* SDRAM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 12734 /** Peripheral SDRAM base address */
AnnaBridge 189:f392fc9709a3 12735 #define SDRAM_BASE (0x4000F000u)
AnnaBridge 189:f392fc9709a3 12736 /** Peripheral SDRAM base pointer */
AnnaBridge 189:f392fc9709a3 12737 #define SDRAM ((SDRAM_Type *)SDRAM_BASE)
AnnaBridge 189:f392fc9709a3 12738 /** Array initializer of SDRAM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 12739 #define SDRAM_BASE_ADDRS { SDRAM_BASE }
AnnaBridge 189:f392fc9709a3 12740 /** Array initializer of SDRAM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 12741 #define SDRAM_BASE_PTRS { SDRAM }
AnnaBridge 189:f392fc9709a3 12742
AnnaBridge 189:f392fc9709a3 12743 /*!
AnnaBridge 189:f392fc9709a3 12744 * @}
AnnaBridge 189:f392fc9709a3 12745 */ /* end of group SDRAM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 12746
AnnaBridge 189:f392fc9709a3 12747
AnnaBridge 189:f392fc9709a3 12748 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 12749 -- SIM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 12750 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 12751
AnnaBridge 189:f392fc9709a3 12752 /*!
AnnaBridge 189:f392fc9709a3 12753 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 12754 * @{
AnnaBridge 189:f392fc9709a3 12755 */
AnnaBridge 189:f392fc9709a3 12756
AnnaBridge 189:f392fc9709a3 12757 /** SIM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 12758 typedef struct {
AnnaBridge 189:f392fc9709a3 12759 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 12760 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 12761 uint8_t RESERVED_0[4092];
AnnaBridge 189:f392fc9709a3 12762 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 189:f392fc9709a3 12763 uint8_t RESERVED_1[4];
AnnaBridge 189:f392fc9709a3 12764 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 189:f392fc9709a3 12765 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 189:f392fc9709a3 12766 uint8_t RESERVED_2[4];
AnnaBridge 189:f392fc9709a3 12767 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 189:f392fc9709a3 12768 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
AnnaBridge 189:f392fc9709a3 12769 __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */
AnnaBridge 189:f392fc9709a3 12770 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 189:f392fc9709a3 12771 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
AnnaBridge 189:f392fc9709a3 12772 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
AnnaBridge 189:f392fc9709a3 12773 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
AnnaBridge 189:f392fc9709a3 12774 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 189:f392fc9709a3 12775 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 189:f392fc9709a3 12776 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 189:f392fc9709a3 12777 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 189:f392fc9709a3 12778 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 189:f392fc9709a3 12779 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
AnnaBridge 189:f392fc9709a3 12780 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 189:f392fc9709a3 12781 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 189:f392fc9709a3 12782 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
AnnaBridge 189:f392fc9709a3 12783 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 189:f392fc9709a3 12784 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 189:f392fc9709a3 12785 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 189:f392fc9709a3 12786 __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */
AnnaBridge 189:f392fc9709a3 12787 __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x1068 */
AnnaBridge 189:f392fc9709a3 12788 } SIM_Type;
AnnaBridge 189:f392fc9709a3 12789
AnnaBridge 189:f392fc9709a3 12790 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 12791 -- SIM Register Masks
AnnaBridge 189:f392fc9709a3 12792 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 12793
AnnaBridge 189:f392fc9709a3 12794 /*!
AnnaBridge 189:f392fc9709a3 12795 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 189:f392fc9709a3 12796 * @{
AnnaBridge 189:f392fc9709a3 12797 */
AnnaBridge 189:f392fc9709a3 12798
AnnaBridge 189:f392fc9709a3 12799 /*! @name SOPT1 - System Options Register 1 */
AnnaBridge 189:f392fc9709a3 12800 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 12801 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 12802 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
AnnaBridge 189:f392fc9709a3 12803 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 12804 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12805 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 189:f392fc9709a3 12806 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 12807 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 12808 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
AnnaBridge 189:f392fc9709a3 12809 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 12810 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 12811 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
AnnaBridge 189:f392fc9709a3 12812 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 12813 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 12814 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
AnnaBridge 189:f392fc9709a3 12815
AnnaBridge 189:f392fc9709a3 12816 /*! @name SOPT1CFG - SOPT1 Configuration Register */
AnnaBridge 189:f392fc9709a3 12817 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12818 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12819 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
AnnaBridge 189:f392fc9709a3 12820 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 12821 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 12822 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
AnnaBridge 189:f392fc9709a3 12823 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 12824 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 12825 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
AnnaBridge 189:f392fc9709a3 12826
AnnaBridge 189:f392fc9709a3 12827 /*! @name SOPT2 - System Options Register 2 */
AnnaBridge 189:f392fc9709a3 12828 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12829 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12830 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
AnnaBridge 189:f392fc9709a3 12831 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
AnnaBridge 189:f392fc9709a3 12832 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 12833 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 189:f392fc9709a3 12834 #define SIM_SOPT2_FBSL_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 12835 #define SIM_SOPT2_FBSL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12836 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
AnnaBridge 189:f392fc9709a3 12837 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 12838 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 12839 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 12840 #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 12841 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12842 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
AnnaBridge 189:f392fc9709a3 12843 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 12844 #define SIM_SOPT2_USBSRC_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12845 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
AnnaBridge 189:f392fc9709a3 12846 #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U)
AnnaBridge 189:f392fc9709a3 12847 #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12848 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK)
AnnaBridge 189:f392fc9709a3 12849 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
AnnaBridge 189:f392fc9709a3 12850 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12851 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
AnnaBridge 189:f392fc9709a3 12852 #define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
AnnaBridge 189:f392fc9709a3 12853 #define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 12854 #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
AnnaBridge 189:f392fc9709a3 12855 #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
AnnaBridge 189:f392fc9709a3 12856 #define SIM_SOPT2_SDHCSRC_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 12857 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
AnnaBridge 189:f392fc9709a3 12858 #define SIM_SOPT2_EMVSIMSRC_MASK (0xC0000000U)
AnnaBridge 189:f392fc9709a3 12859 #define SIM_SOPT2_EMVSIMSRC_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 12860 #define SIM_SOPT2_EMVSIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_EMVSIMSRC_SHIFT)) & SIM_SOPT2_EMVSIMSRC_MASK)
AnnaBridge 189:f392fc9709a3 12861
AnnaBridge 189:f392fc9709a3 12862 /*! @name SOPT4 - System Options Register 4 */
AnnaBridge 189:f392fc9709a3 12863 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12864 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12865 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
AnnaBridge 189:f392fc9709a3 12866 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12867 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12868 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
AnnaBridge 189:f392fc9709a3 12869 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12870 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12871 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
AnnaBridge 189:f392fc9709a3 12872 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 12873 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 12874 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
AnnaBridge 189:f392fc9709a3 12875 #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 12876 #define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 12877 #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
AnnaBridge 189:f392fc9709a3 12878 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 12879 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12880 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
AnnaBridge 189:f392fc9709a3 12881 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 12882 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12883 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
AnnaBridge 189:f392fc9709a3 12884 #define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 12885 #define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12886 #define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
AnnaBridge 189:f392fc9709a3 12887 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12888 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12889 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 12890 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 12891 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 12892 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 12893 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 12894 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 12895 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 12896 #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 12897 #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 12898 #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 12899 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 12900 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 12901 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
AnnaBridge 189:f392fc9709a3 12902 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 12903 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 12904 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
AnnaBridge 189:f392fc9709a3 12905 #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 12906 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 12907 #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
AnnaBridge 189:f392fc9709a3 12908 #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 12909 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 12910 #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
AnnaBridge 189:f392fc9709a3 12911
AnnaBridge 189:f392fc9709a3 12912 /*! @name SOPT5 - System Options Register 5 */
AnnaBridge 189:f392fc9709a3 12913 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 12914 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12915 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
AnnaBridge 189:f392fc9709a3 12916 #define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 12917 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12918 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
AnnaBridge 189:f392fc9709a3 12919 #define SIM_SOPT5_LPUART1TXSRC_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 12920 #define SIM_SOPT5_LPUART1TXSRC_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12921 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK)
AnnaBridge 189:f392fc9709a3 12922 #define SIM_SOPT5_LPUART1RXSRC_MASK (0xC00000U)
AnnaBridge 189:f392fc9709a3 12923 #define SIM_SOPT5_LPUART1RXSRC_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12924 #define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK)
AnnaBridge 189:f392fc9709a3 12925
AnnaBridge 189:f392fc9709a3 12926 /*! @name SOPT7 - System Options Register 7 */
AnnaBridge 189:f392fc9709a3 12927 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 12928 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12929 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 189:f392fc9709a3 12930 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 12931 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 12932 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
AnnaBridge 189:f392fc9709a3 12933 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 12934 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 12935 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
AnnaBridge 189:f392fc9709a3 12936
AnnaBridge 189:f392fc9709a3 12937 /*! @name SOPT8 - System Options Register 8 */
AnnaBridge 189:f392fc9709a3 12938 #define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 12939 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 12940 #define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
AnnaBridge 189:f392fc9709a3 12941 #define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 12942 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 12943 #define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
AnnaBridge 189:f392fc9709a3 12944 #define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 12945 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 12946 #define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
AnnaBridge 189:f392fc9709a3 12947 #define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 12948 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 12949 #define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
AnnaBridge 189:f392fc9709a3 12950 #define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 12951 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 12952 #define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
AnnaBridge 189:f392fc9709a3 12953 #define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 12954 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 12955 #define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
AnnaBridge 189:f392fc9709a3 12956 #define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 12957 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 12958 #define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
AnnaBridge 189:f392fc9709a3 12959 #define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 12960 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 12961 #define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
AnnaBridge 189:f392fc9709a3 12962 #define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 12963 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 12964 #define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
AnnaBridge 189:f392fc9709a3 12965 #define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 12966 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 12967 #define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
AnnaBridge 189:f392fc9709a3 12968 #define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 12969 #define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 12970 #define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
AnnaBridge 189:f392fc9709a3 12971 #define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 12972 #define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 12973 #define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
AnnaBridge 189:f392fc9709a3 12974 #define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 12975 #define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 12976 #define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
AnnaBridge 189:f392fc9709a3 12977 #define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 12978 #define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 12979 #define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
AnnaBridge 189:f392fc9709a3 12980 #define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 12981 #define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 12982 #define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
AnnaBridge 189:f392fc9709a3 12983 #define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 12984 #define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 12985 #define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
AnnaBridge 189:f392fc9709a3 12986 #define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 12987 #define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 12988 #define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
AnnaBridge 189:f392fc9709a3 12989 #define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 12990 #define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 12991 #define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
AnnaBridge 189:f392fc9709a3 12992 #define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 12993 #define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 12994 #define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
AnnaBridge 189:f392fc9709a3 12995 #define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 12996 #define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 12997 #define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
AnnaBridge 189:f392fc9709a3 12998
AnnaBridge 189:f392fc9709a3 12999 /*! @name SOPT9 - System Options Register 9 */
AnnaBridge 189:f392fc9709a3 13000 #define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 13001 #define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 13002 #define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
AnnaBridge 189:f392fc9709a3 13003 #define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 13004 #define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 13005 #define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
AnnaBridge 189:f392fc9709a3 13006 #define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13007 #define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13008 #define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 13009 #define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 13010 #define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 13011 #define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
AnnaBridge 189:f392fc9709a3 13012
AnnaBridge 189:f392fc9709a3 13013 /*! @name SDID - System Device Identification Register */
AnnaBridge 189:f392fc9709a3 13014 #define SIM_SDID_PINID_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 13015 #define SIM_SDID_PINID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13016 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
AnnaBridge 189:f392fc9709a3 13017 #define SIM_SDID_FAMID_MASK (0x70U)
AnnaBridge 189:f392fc9709a3 13018 #define SIM_SDID_FAMID_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13019 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
AnnaBridge 189:f392fc9709a3 13020 #define SIM_SDID_DIEID_MASK (0xF80U)
AnnaBridge 189:f392fc9709a3 13021 #define SIM_SDID_DIEID_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 13022 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
AnnaBridge 189:f392fc9709a3 13023 #define SIM_SDID_REVID_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 13024 #define SIM_SDID_REVID_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13025 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
AnnaBridge 189:f392fc9709a3 13026 #define SIM_SDID_SERIESID_MASK (0xF00000U)
AnnaBridge 189:f392fc9709a3 13027 #define SIM_SDID_SERIESID_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 13028 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
AnnaBridge 189:f392fc9709a3 13029 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 13030 #define SIM_SDID_SUBFAMID_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13031 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
AnnaBridge 189:f392fc9709a3 13032 #define SIM_SDID_FAMILYID_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 13033 #define SIM_SDID_FAMILYID_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 13034 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
AnnaBridge 189:f392fc9709a3 13035
AnnaBridge 189:f392fc9709a3 13036 /*! @name SCGC1 - System Clock Gating Control Register 1 */
AnnaBridge 189:f392fc9709a3 13037 #define SIM_SCGC1_I2C2_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 13038 #define SIM_SCGC1_I2C2_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 13039 #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
AnnaBridge 189:f392fc9709a3 13040 #define SIM_SCGC1_I2C3_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 13041 #define SIM_SCGC1_I2C3_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 13042 #define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
AnnaBridge 189:f392fc9709a3 13043
AnnaBridge 189:f392fc9709a3 13044 /*! @name SCGC2 - System Clock Gating Control Register 2 */
AnnaBridge 189:f392fc9709a3 13045 #define SIM_SCGC2_LPUART0_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 13046 #define SIM_SCGC2_LPUART0_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13047 #define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
AnnaBridge 189:f392fc9709a3 13048 #define SIM_SCGC2_LPUART1_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 13049 #define SIM_SCGC2_LPUART1_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13050 #define SIM_SCGC2_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART1_SHIFT)) & SIM_SCGC2_LPUART1_MASK)
AnnaBridge 189:f392fc9709a3 13051 #define SIM_SCGC2_LPUART2_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 13052 #define SIM_SCGC2_LPUART2_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 13053 #define SIM_SCGC2_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART2_SHIFT)) & SIM_SCGC2_LPUART2_MASK)
AnnaBridge 189:f392fc9709a3 13054 #define SIM_SCGC2_LPUART3_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 13055 #define SIM_SCGC2_LPUART3_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 13056 #define SIM_SCGC2_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART3_SHIFT)) & SIM_SCGC2_LPUART3_MASK)
AnnaBridge 189:f392fc9709a3 13057 #define SIM_SCGC2_TPM1_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 13058 #define SIM_SCGC2_TPM1_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 13059 #define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
AnnaBridge 189:f392fc9709a3 13060 #define SIM_SCGC2_TPM2_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 13061 #define SIM_SCGC2_TPM2_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 13062 #define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
AnnaBridge 189:f392fc9709a3 13063 #define SIM_SCGC2_DAC0_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 13064 #define SIM_SCGC2_DAC0_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13065 #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
AnnaBridge 189:f392fc9709a3 13066 #define SIM_SCGC2_LTC_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 13067 #define SIM_SCGC2_LTC_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 13068 #define SIM_SCGC2_LTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LTC_SHIFT)) & SIM_SCGC2_LTC_MASK)
AnnaBridge 189:f392fc9709a3 13069 #define SIM_SCGC2_EMVSIM0_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 13070 #define SIM_SCGC2_EMVSIM0_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 13071 #define SIM_SCGC2_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_EMVSIM0_SHIFT)) & SIM_SCGC2_EMVSIM0_MASK)
AnnaBridge 189:f392fc9709a3 13072 #define SIM_SCGC2_EMVSIM1_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 13073 #define SIM_SCGC2_EMVSIM1_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 13074 #define SIM_SCGC2_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_EMVSIM1_SHIFT)) & SIM_SCGC2_EMVSIM1_MASK)
AnnaBridge 189:f392fc9709a3 13075 #define SIM_SCGC2_LPUART4_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 13076 #define SIM_SCGC2_LPUART4_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 13077 #define SIM_SCGC2_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART4_SHIFT)) & SIM_SCGC2_LPUART4_MASK)
AnnaBridge 189:f392fc9709a3 13078 #define SIM_SCGC2_QSPI_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 13079 #define SIM_SCGC2_QSPI_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 13080 #define SIM_SCGC2_QSPI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_QSPI_SHIFT)) & SIM_SCGC2_QSPI_MASK)
AnnaBridge 189:f392fc9709a3 13081 #define SIM_SCGC2_FLEXIO_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 13082 #define SIM_SCGC2_FLEXIO_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 13083 #define SIM_SCGC2_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_FLEXIO_SHIFT)) & SIM_SCGC2_FLEXIO_MASK)
AnnaBridge 189:f392fc9709a3 13084
AnnaBridge 189:f392fc9709a3 13085 /*! @name SCGC3 - System Clock Gating Control Register 3 */
AnnaBridge 189:f392fc9709a3 13086 #define SIM_SCGC3_TRNG_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13087 #define SIM_SCGC3_TRNG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13088 #define SIM_SCGC3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_TRNG_SHIFT)) & SIM_SCGC3_TRNG_MASK)
AnnaBridge 189:f392fc9709a3 13089 #define SIM_SCGC3_SPI2_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 13090 #define SIM_SCGC3_SPI2_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13091 #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
AnnaBridge 189:f392fc9709a3 13092 #define SIM_SCGC3_SDHC_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 13093 #define SIM_SCGC3_SDHC_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 13094 #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
AnnaBridge 189:f392fc9709a3 13095 #define SIM_SCGC3_FTM2_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 13096 #define SIM_SCGC3_FTM2_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13097 #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
AnnaBridge 189:f392fc9709a3 13098 #define SIM_SCGC3_FTM3_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13099 #define SIM_SCGC3_FTM3_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13100 #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
AnnaBridge 189:f392fc9709a3 13101
AnnaBridge 189:f392fc9709a3 13102 /*! @name SCGC4 - System Clock Gating Control Register 4 */
AnnaBridge 189:f392fc9709a3 13103 #define SIM_SCGC4_EWM_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13104 #define SIM_SCGC4_EWM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13105 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
AnnaBridge 189:f392fc9709a3 13106 #define SIM_SCGC4_CMT_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 13107 #define SIM_SCGC4_CMT_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 13108 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
AnnaBridge 189:f392fc9709a3 13109 #define SIM_SCGC4_I2C0_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 13110 #define SIM_SCGC4_I2C0_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 13111 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
AnnaBridge 189:f392fc9709a3 13112 #define SIM_SCGC4_I2C1_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 13113 #define SIM_SCGC4_I2C1_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 13114 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
AnnaBridge 189:f392fc9709a3 13115 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 13116 #define SIM_SCGC4_USBOTG_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 13117 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
AnnaBridge 189:f392fc9709a3 13118 #define SIM_SCGC4_CMP_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 13119 #define SIM_SCGC4_CMP_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 13120 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
AnnaBridge 189:f392fc9709a3 13121 #define SIM_SCGC4_VREF_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 13122 #define SIM_SCGC4_VREF_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 13123 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
AnnaBridge 189:f392fc9709a3 13124
AnnaBridge 189:f392fc9709a3 13125 /*! @name SCGC5 - System Clock Gating Control Register 5 */
AnnaBridge 189:f392fc9709a3 13126 #define SIM_SCGC5_LPTMR_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13127 #define SIM_SCGC5_LPTMR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13128 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
AnnaBridge 189:f392fc9709a3 13129 #define SIM_SCGC5_LPTMR1_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 13130 #define SIM_SCGC5_LPTMR1_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13131 #define SIM_SCGC5_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR1_SHIFT)) & SIM_SCGC5_LPTMR1_MASK)
AnnaBridge 189:f392fc9709a3 13132 #define SIM_SCGC5_TSI_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 13133 #define SIM_SCGC5_TSI_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13134 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
AnnaBridge 189:f392fc9709a3 13135 #define SIM_SCGC5_PORTA_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 13136 #define SIM_SCGC5_PORTA_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 13137 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
AnnaBridge 189:f392fc9709a3 13138 #define SIM_SCGC5_PORTB_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 13139 #define SIM_SCGC5_PORTB_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 13140 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
AnnaBridge 189:f392fc9709a3 13141 #define SIM_SCGC5_PORTC_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 13142 #define SIM_SCGC5_PORTC_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 13143 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
AnnaBridge 189:f392fc9709a3 13144 #define SIM_SCGC5_PORTD_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 13145 #define SIM_SCGC5_PORTD_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13146 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
AnnaBridge 189:f392fc9709a3 13147 #define SIM_SCGC5_PORTE_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 13148 #define SIM_SCGC5_PORTE_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 13149 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
AnnaBridge 189:f392fc9709a3 13150
AnnaBridge 189:f392fc9709a3 13151 /*! @name SCGC6 - System Clock Gating Control Register 6 */
AnnaBridge 189:f392fc9709a3 13152 #define SIM_SCGC6_FTF_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13153 #define SIM_SCGC6_FTF_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13154 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
AnnaBridge 189:f392fc9709a3 13155 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13156 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13157 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
AnnaBridge 189:f392fc9709a3 13158 #define SIM_SCGC6_SPI0_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 13159 #define SIM_SCGC6_SPI0_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13160 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
AnnaBridge 189:f392fc9709a3 13161 #define SIM_SCGC6_SPI1_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 13162 #define SIM_SCGC6_SPI1_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 13163 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
AnnaBridge 189:f392fc9709a3 13164 #define SIM_SCGC6_I2S_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 13165 #define SIM_SCGC6_I2S_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 13166 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
AnnaBridge 189:f392fc9709a3 13167 #define SIM_SCGC6_CRC_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 13168 #define SIM_SCGC6_CRC_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 13169 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
AnnaBridge 189:f392fc9709a3 13170 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 13171 #define SIM_SCGC6_USBDCD_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 13172 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
AnnaBridge 189:f392fc9709a3 13173 #define SIM_SCGC6_PDB_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 13174 #define SIM_SCGC6_PDB_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 13175 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
AnnaBridge 189:f392fc9709a3 13176 #define SIM_SCGC6_PIT_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 13177 #define SIM_SCGC6_PIT_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 13178 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
AnnaBridge 189:f392fc9709a3 13179 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 13180 #define SIM_SCGC6_FTM0_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13181 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
AnnaBridge 189:f392fc9709a3 13182 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13183 #define SIM_SCGC6_FTM1_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13184 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
AnnaBridge 189:f392fc9709a3 13185 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 13186 #define SIM_SCGC6_FTM2_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 13187 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
AnnaBridge 189:f392fc9709a3 13188 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 13189 #define SIM_SCGC6_ADC0_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 13190 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
AnnaBridge 189:f392fc9709a3 13191 #define SIM_SCGC6_RTC_MASK (0x20000000U)
AnnaBridge 189:f392fc9709a3 13192 #define SIM_SCGC6_RTC_SHIFT (29U)
AnnaBridge 189:f392fc9709a3 13193 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
AnnaBridge 189:f392fc9709a3 13194 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 13195 #define SIM_SCGC6_DAC0_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 13196 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
AnnaBridge 189:f392fc9709a3 13197
AnnaBridge 189:f392fc9709a3 13198 /*! @name SCGC7 - System Clock Gating Control Register 7 */
AnnaBridge 189:f392fc9709a3 13199 #define SIM_SCGC7_FLEXBUS_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13200 #define SIM_SCGC7_FLEXBUS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13201 #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
AnnaBridge 189:f392fc9709a3 13202 #define SIM_SCGC7_DMA_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13203 #define SIM_SCGC7_DMA_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13204 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
AnnaBridge 189:f392fc9709a3 13205 #define SIM_SCGC7_MPU_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 13206 #define SIM_SCGC7_MPU_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 13207 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
AnnaBridge 189:f392fc9709a3 13208 #define SIM_SCGC7_SDRAMC_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 13209 #define SIM_SCGC7_SDRAMC_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 13210 #define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
AnnaBridge 189:f392fc9709a3 13211
AnnaBridge 189:f392fc9709a3 13212 /*! @name CLKDIV1 - System Clock Divider Register 1 */
AnnaBridge 189:f392fc9709a3 13213 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 13214 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13215 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 189:f392fc9709a3 13216 #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
AnnaBridge 189:f392fc9709a3 13217 #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 13218 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
AnnaBridge 189:f392fc9709a3 13219 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 13220 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13221 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
AnnaBridge 189:f392fc9709a3 13222 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 13223 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 13224 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 189:f392fc9709a3 13225
AnnaBridge 189:f392fc9709a3 13226 /*! @name CLKDIV2 - System Clock Divider Register 2 */
AnnaBridge 189:f392fc9709a3 13227 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13228 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13229 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
AnnaBridge 189:f392fc9709a3 13230 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
AnnaBridge 189:f392fc9709a3 13231 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13232 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
AnnaBridge 189:f392fc9709a3 13233
AnnaBridge 189:f392fc9709a3 13234 /*! @name FCFG1 - Flash Configuration Register 1 */
AnnaBridge 189:f392fc9709a3 13235 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13236 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13237 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
AnnaBridge 189:f392fc9709a3 13238 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13239 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13240 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
AnnaBridge 189:f392fc9709a3 13241 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 13242 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13243 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 189:f392fc9709a3 13244
AnnaBridge 189:f392fc9709a3 13245 /*! @name FCFG2 - Flash Configuration Register 2 */
AnnaBridge 189:f392fc9709a3 13246 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
AnnaBridge 189:f392fc9709a3 13247 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13248 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge 189:f392fc9709a3 13249 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
AnnaBridge 189:f392fc9709a3 13250 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13251 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 189:f392fc9709a3 13252
AnnaBridge 189:f392fc9709a3 13253 /*! @name UIDH - Unique Identification Register High */
AnnaBridge 189:f392fc9709a3 13254 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13255 #define SIM_UIDH_UID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13256 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
AnnaBridge 189:f392fc9709a3 13257
AnnaBridge 189:f392fc9709a3 13258 /*! @name UIDMH - Unique Identification Register Mid-High */
AnnaBridge 189:f392fc9709a3 13259 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13260 #define SIM_UIDMH_UID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13261 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
AnnaBridge 189:f392fc9709a3 13262
AnnaBridge 189:f392fc9709a3 13263 /*! @name UIDML - Unique Identification Register Mid Low */
AnnaBridge 189:f392fc9709a3 13264 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13265 #define SIM_UIDML_UID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13266 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
AnnaBridge 189:f392fc9709a3 13267
AnnaBridge 189:f392fc9709a3 13268 /*! @name UIDL - Unique Identification Register Low */
AnnaBridge 189:f392fc9709a3 13269 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13270 #define SIM_UIDL_UID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13271 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
AnnaBridge 189:f392fc9709a3 13272
AnnaBridge 189:f392fc9709a3 13273 /*! @name CLKDIV3 - System Clock Divider Register 3 */
AnnaBridge 189:f392fc9709a3 13274 #define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13275 #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13276 #define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
AnnaBridge 189:f392fc9709a3 13277 #define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU)
AnnaBridge 189:f392fc9709a3 13278 #define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13279 #define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
AnnaBridge 189:f392fc9709a3 13280
AnnaBridge 189:f392fc9709a3 13281 /*! @name CLKDIV4 - System Clock Divider Register 4 */
AnnaBridge 189:f392fc9709a3 13282 #define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13283 #define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13284 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
AnnaBridge 189:f392fc9709a3 13285 #define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
AnnaBridge 189:f392fc9709a3 13286 #define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13287 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
AnnaBridge 189:f392fc9709a3 13288
AnnaBridge 189:f392fc9709a3 13289
AnnaBridge 189:f392fc9709a3 13290 /*!
AnnaBridge 189:f392fc9709a3 13291 * @}
AnnaBridge 189:f392fc9709a3 13292 */ /* end of group SIM_Register_Masks */
AnnaBridge 189:f392fc9709a3 13293
AnnaBridge 189:f392fc9709a3 13294
AnnaBridge 189:f392fc9709a3 13295 /* SIM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 13296 /** Peripheral SIM base address */
AnnaBridge 189:f392fc9709a3 13297 #define SIM_BASE (0x40047000u)
AnnaBridge 189:f392fc9709a3 13298 /** Peripheral SIM base pointer */
AnnaBridge 189:f392fc9709a3 13299 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 189:f392fc9709a3 13300 /** Array initializer of SIM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 13301 #define SIM_BASE_ADDRS { SIM_BASE }
AnnaBridge 189:f392fc9709a3 13302 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 13303 #define SIM_BASE_PTRS { SIM }
AnnaBridge 189:f392fc9709a3 13304
AnnaBridge 189:f392fc9709a3 13305 /*!
AnnaBridge 189:f392fc9709a3 13306 * @}
AnnaBridge 189:f392fc9709a3 13307 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 13308
AnnaBridge 189:f392fc9709a3 13309
AnnaBridge 189:f392fc9709a3 13310 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 13311 -- SMC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13312 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 13313
AnnaBridge 189:f392fc9709a3 13314 /*!
AnnaBridge 189:f392fc9709a3 13315 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13316 * @{
AnnaBridge 189:f392fc9709a3 13317 */
AnnaBridge 189:f392fc9709a3 13318
AnnaBridge 189:f392fc9709a3 13319 /** SMC - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 13320 typedef struct {
AnnaBridge 189:f392fc9709a3 13321 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 13322 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 13323 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 13324 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 189:f392fc9709a3 13325 } SMC_Type;
AnnaBridge 189:f392fc9709a3 13326
AnnaBridge 189:f392fc9709a3 13327 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 13328 -- SMC Register Masks
AnnaBridge 189:f392fc9709a3 13329 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 13330
AnnaBridge 189:f392fc9709a3 13331 /*!
AnnaBridge 189:f392fc9709a3 13332 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 189:f392fc9709a3 13333 * @{
AnnaBridge 189:f392fc9709a3 13334 */
AnnaBridge 189:f392fc9709a3 13335
AnnaBridge 189:f392fc9709a3 13336 /*! @name PMPROT - Power Mode Protection register */
AnnaBridge 189:f392fc9709a3 13337 #define SMC_PMPROT_AVLLS_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13338 #define SMC_PMPROT_AVLLS_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13339 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
AnnaBridge 189:f392fc9709a3 13340 #define SMC_PMPROT_ALLS_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 13341 #define SMC_PMPROT_ALLS_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 13342 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
AnnaBridge 189:f392fc9709a3 13343 #define SMC_PMPROT_AVLP_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 13344 #define SMC_PMPROT_AVLP_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13345 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
AnnaBridge 189:f392fc9709a3 13346 #define SMC_PMPROT_AHSRUN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 13347 #define SMC_PMPROT_AHSRUN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 13348 #define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
AnnaBridge 189:f392fc9709a3 13349
AnnaBridge 189:f392fc9709a3 13350 /*! @name PMCTRL - Power Mode Control register */
AnnaBridge 189:f392fc9709a3 13351 #define SMC_PMCTRL_STOPM_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 13352 #define SMC_PMCTRL_STOPM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13353 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
AnnaBridge 189:f392fc9709a3 13354 #define SMC_PMCTRL_STOPA_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 13355 #define SMC_PMCTRL_STOPA_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 13356 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 189:f392fc9709a3 13357 #define SMC_PMCTRL_RUNM_MASK (0x60U)
AnnaBridge 189:f392fc9709a3 13358 #define SMC_PMCTRL_RUNM_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13359 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
AnnaBridge 189:f392fc9709a3 13360
AnnaBridge 189:f392fc9709a3 13361 /*! @name STOPCTRL - Stop Control Register */
AnnaBridge 189:f392fc9709a3 13362 #define SMC_STOPCTRL_LLSM_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 13363 #define SMC_STOPCTRL_LLSM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13364 #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
AnnaBridge 189:f392fc9709a3 13365 #define SMC_STOPCTRL_LPOPO_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 13366 #define SMC_STOPCTRL_LPOPO_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 13367 #define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
AnnaBridge 189:f392fc9709a3 13368 #define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 13369 #define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13370 #define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
AnnaBridge 189:f392fc9709a3 13371 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 13372 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13373 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
AnnaBridge 189:f392fc9709a3 13374 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 13375 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 13376 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
AnnaBridge 189:f392fc9709a3 13377
AnnaBridge 189:f392fc9709a3 13378 /*! @name PMSTAT - Power Mode Status register */
AnnaBridge 189:f392fc9709a3 13379 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 13380 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13381 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 189:f392fc9709a3 13382
AnnaBridge 189:f392fc9709a3 13383
AnnaBridge 189:f392fc9709a3 13384 /*!
AnnaBridge 189:f392fc9709a3 13385 * @}
AnnaBridge 189:f392fc9709a3 13386 */ /* end of group SMC_Register_Masks */
AnnaBridge 189:f392fc9709a3 13387
AnnaBridge 189:f392fc9709a3 13388
AnnaBridge 189:f392fc9709a3 13389 /* SMC - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 13390 /** Peripheral SMC base address */
AnnaBridge 189:f392fc9709a3 13391 #define SMC_BASE (0x4007E000u)
AnnaBridge 189:f392fc9709a3 13392 /** Peripheral SMC base pointer */
AnnaBridge 189:f392fc9709a3 13393 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 189:f392fc9709a3 13394 /** Array initializer of SMC peripheral base addresses */
AnnaBridge 189:f392fc9709a3 13395 #define SMC_BASE_ADDRS { SMC_BASE }
AnnaBridge 189:f392fc9709a3 13396 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 189:f392fc9709a3 13397 #define SMC_BASE_PTRS { SMC }
AnnaBridge 189:f392fc9709a3 13398
AnnaBridge 189:f392fc9709a3 13399 /*!
AnnaBridge 189:f392fc9709a3 13400 * @}
AnnaBridge 189:f392fc9709a3 13401 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 13402
AnnaBridge 189:f392fc9709a3 13403
AnnaBridge 189:f392fc9709a3 13404 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 13405 -- SPI Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13406 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 13407
AnnaBridge 189:f392fc9709a3 13408 /*!
AnnaBridge 189:f392fc9709a3 13409 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13410 * @{
AnnaBridge 189:f392fc9709a3 13411 */
AnnaBridge 189:f392fc9709a3 13412
AnnaBridge 189:f392fc9709a3 13413 /** SPI - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 13414 typedef struct {
AnnaBridge 189:f392fc9709a3 13415 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 13416 uint8_t RESERVED_0[4];
AnnaBridge 189:f392fc9709a3 13417 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 13418 union { /* offset: 0xC */
AnnaBridge 189:f392fc9709a3 13419 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 13420 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 13421 };
AnnaBridge 189:f392fc9709a3 13422 uint8_t RESERVED_1[24];
AnnaBridge 189:f392fc9709a3 13423 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 13424 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 13425 union { /* offset: 0x34 */
AnnaBridge 189:f392fc9709a3 13426 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 13427 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 13428 };
AnnaBridge 189:f392fc9709a3 13429 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
AnnaBridge 189:f392fc9709a3 13430 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
AnnaBridge 189:f392fc9709a3 13431 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
AnnaBridge 189:f392fc9709a3 13432 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
AnnaBridge 189:f392fc9709a3 13433 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
AnnaBridge 189:f392fc9709a3 13434 uint8_t RESERVED_2[48];
AnnaBridge 189:f392fc9709a3 13435 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
AnnaBridge 189:f392fc9709a3 13436 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 13437 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
AnnaBridge 189:f392fc9709a3 13438 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
AnnaBridge 189:f392fc9709a3 13439 } SPI_Type;
AnnaBridge 189:f392fc9709a3 13440
AnnaBridge 189:f392fc9709a3 13441 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 13442 -- SPI Register Masks
AnnaBridge 189:f392fc9709a3 13443 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 13444
AnnaBridge 189:f392fc9709a3 13445 /*!
AnnaBridge 189:f392fc9709a3 13446 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 189:f392fc9709a3 13447 * @{
AnnaBridge 189:f392fc9709a3 13448 */
AnnaBridge 189:f392fc9709a3 13449
AnnaBridge 189:f392fc9709a3 13450 /*! @name MCR - Module Configuration Register */
AnnaBridge 189:f392fc9709a3 13451 #define SPI_MCR_HALT_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13452 #define SPI_MCR_HALT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13453 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
AnnaBridge 189:f392fc9709a3 13454 #define SPI_MCR_SMPL_PT_MASK (0x300U)
AnnaBridge 189:f392fc9709a3 13455 #define SPI_MCR_SMPL_PT_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 13456 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
AnnaBridge 189:f392fc9709a3 13457 #define SPI_MCR_CLR_RXF_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 13458 #define SPI_MCR_CLR_RXF_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 13459 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
AnnaBridge 189:f392fc9709a3 13460 #define SPI_MCR_CLR_TXF_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 13461 #define SPI_MCR_CLR_TXF_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 13462 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
AnnaBridge 189:f392fc9709a3 13463 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 13464 #define SPI_MCR_DIS_RXF_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13465 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
AnnaBridge 189:f392fc9709a3 13466 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 13467 #define SPI_MCR_DIS_TXF_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 13468 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
AnnaBridge 189:f392fc9709a3 13469 #define SPI_MCR_MDIS_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 13470 #define SPI_MCR_MDIS_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 13471 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
AnnaBridge 189:f392fc9709a3 13472 #define SPI_MCR_DOZE_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 13473 #define SPI_MCR_DOZE_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 13474 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
AnnaBridge 189:f392fc9709a3 13475 #define SPI_MCR_PCSIS_MASK (0x3F0000U)
AnnaBridge 189:f392fc9709a3 13476 #define SPI_MCR_PCSIS_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13477 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
AnnaBridge 189:f392fc9709a3 13478 #define SPI_MCR_ROOE_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 13479 #define SPI_MCR_ROOE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13480 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
AnnaBridge 189:f392fc9709a3 13481 #define SPI_MCR_PCSSE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13482 #define SPI_MCR_PCSSE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13483 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
AnnaBridge 189:f392fc9709a3 13484 #define SPI_MCR_MTFE_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 13485 #define SPI_MCR_MTFE_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 13486 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
AnnaBridge 189:f392fc9709a3 13487 #define SPI_MCR_FRZ_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 13488 #define SPI_MCR_FRZ_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 13489 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
AnnaBridge 189:f392fc9709a3 13490 #define SPI_MCR_DCONF_MASK (0x30000000U)
AnnaBridge 189:f392fc9709a3 13491 #define SPI_MCR_DCONF_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 13492 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
AnnaBridge 189:f392fc9709a3 13493 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 13494 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 13495 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
AnnaBridge 189:f392fc9709a3 13496 #define SPI_MCR_MSTR_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 13497 #define SPI_MCR_MSTR_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 13498 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
AnnaBridge 189:f392fc9709a3 13499
AnnaBridge 189:f392fc9709a3 13500 /*! @name TCR - Transfer Count Register */
AnnaBridge 189:f392fc9709a3 13501 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 13502 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13503 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
AnnaBridge 189:f392fc9709a3 13504
AnnaBridge 189:f392fc9709a3 13505 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
AnnaBridge 189:f392fc9709a3 13506 #define SPI_CTAR_BR_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 13507 #define SPI_CTAR_BR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13508 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
AnnaBridge 189:f392fc9709a3 13509 #define SPI_CTAR_DT_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 13510 #define SPI_CTAR_DT_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13511 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
AnnaBridge 189:f392fc9709a3 13512 #define SPI_CTAR_ASC_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 13513 #define SPI_CTAR_ASC_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 13514 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
AnnaBridge 189:f392fc9709a3 13515 #define SPI_CTAR_CSSCK_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 13516 #define SPI_CTAR_CSSCK_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13517 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
AnnaBridge 189:f392fc9709a3 13518 #define SPI_CTAR_PBR_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 13519 #define SPI_CTAR_PBR_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13520 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
AnnaBridge 189:f392fc9709a3 13521 #define SPI_CTAR_PDT_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 13522 #define SPI_CTAR_PDT_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 13523 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
AnnaBridge 189:f392fc9709a3 13524 #define SPI_CTAR_PASC_MASK (0x300000U)
AnnaBridge 189:f392fc9709a3 13525 #define SPI_CTAR_PASC_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 13526 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
AnnaBridge 189:f392fc9709a3 13527 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
AnnaBridge 189:f392fc9709a3 13528 #define SPI_CTAR_PCSSCK_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 13529 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
AnnaBridge 189:f392fc9709a3 13530 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 13531 #define SPI_CTAR_LSBFE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13532 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
AnnaBridge 189:f392fc9709a3 13533 #define SPI_CTAR_CPHA_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13534 #define SPI_CTAR_CPHA_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13535 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
AnnaBridge 189:f392fc9709a3 13536 #define SPI_CTAR_CPOL_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 13537 #define SPI_CTAR_CPOL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 13538 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
AnnaBridge 189:f392fc9709a3 13539 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
AnnaBridge 189:f392fc9709a3 13540 #define SPI_CTAR_FMSZ_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 13541 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
AnnaBridge 189:f392fc9709a3 13542 #define SPI_CTAR_DBR_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 13543 #define SPI_CTAR_DBR_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 13544 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
AnnaBridge 189:f392fc9709a3 13545
AnnaBridge 189:f392fc9709a3 13546 /* The count of SPI_CTAR */
AnnaBridge 189:f392fc9709a3 13547 #define SPI_CTAR_COUNT (2U)
AnnaBridge 189:f392fc9709a3 13548
AnnaBridge 189:f392fc9709a3 13549 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
AnnaBridge 189:f392fc9709a3 13550 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13551 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13552 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
AnnaBridge 189:f392fc9709a3 13553 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 13554 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 13555 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
AnnaBridge 189:f392fc9709a3 13556 #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
AnnaBridge 189:f392fc9709a3 13557 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 13558 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
AnnaBridge 189:f392fc9709a3 13559
AnnaBridge 189:f392fc9709a3 13560 /* The count of SPI_CTAR_SLAVE */
AnnaBridge 189:f392fc9709a3 13561 #define SPI_CTAR_SLAVE_COUNT (1U)
AnnaBridge 189:f392fc9709a3 13562
AnnaBridge 189:f392fc9709a3 13563 /*! @name SR - Status Register */
AnnaBridge 189:f392fc9709a3 13564 #define SPI_SR_POPNXTPTR_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 13565 #define SPI_SR_POPNXTPTR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13566 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
AnnaBridge 189:f392fc9709a3 13567 #define SPI_SR_RXCTR_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 13568 #define SPI_SR_RXCTR_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13569 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
AnnaBridge 189:f392fc9709a3 13570 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
AnnaBridge 189:f392fc9709a3 13571 #define SPI_SR_TXNXTPTR_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 13572 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
AnnaBridge 189:f392fc9709a3 13573 #define SPI_SR_TXCTR_MASK (0xF000U)
AnnaBridge 189:f392fc9709a3 13574 #define SPI_SR_TXCTR_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 13575 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
AnnaBridge 189:f392fc9709a3 13576 #define SPI_SR_RFDF_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 13577 #define SPI_SR_RFDF_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 13578 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
AnnaBridge 189:f392fc9709a3 13579 #define SPI_SR_RFOF_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 13580 #define SPI_SR_RFOF_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 13581 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
AnnaBridge 189:f392fc9709a3 13582 #define SPI_SR_TFFF_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13583 #define SPI_SR_TFFF_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13584 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
AnnaBridge 189:f392fc9709a3 13585 #define SPI_SR_TFUF_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 13586 #define SPI_SR_TFUF_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 13587 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
AnnaBridge 189:f392fc9709a3 13588 #define SPI_SR_EOQF_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 13589 #define SPI_SR_EOQF_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 13590 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
AnnaBridge 189:f392fc9709a3 13591 #define SPI_SR_TXRXS_MASK (0x40000000U)
AnnaBridge 189:f392fc9709a3 13592 #define SPI_SR_TXRXS_SHIFT (30U)
AnnaBridge 189:f392fc9709a3 13593 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
AnnaBridge 189:f392fc9709a3 13594 #define SPI_SR_TCF_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 13595 #define SPI_SR_TCF_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 13596 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
AnnaBridge 189:f392fc9709a3 13597
AnnaBridge 189:f392fc9709a3 13598 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
AnnaBridge 189:f392fc9709a3 13599 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 13600 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13601 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
AnnaBridge 189:f392fc9709a3 13602 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 13603 #define SPI_RSER_RFDF_RE_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 13604 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
AnnaBridge 189:f392fc9709a3 13605 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 13606 #define SPI_RSER_RFOF_RE_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 13607 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
AnnaBridge 189:f392fc9709a3 13608 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 13609 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13610 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
AnnaBridge 189:f392fc9709a3 13611 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 13612 #define SPI_RSER_TFFF_RE_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 13613 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
AnnaBridge 189:f392fc9709a3 13614 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 13615 #define SPI_RSER_TFUF_RE_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 13616 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
AnnaBridge 189:f392fc9709a3 13617 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 13618 #define SPI_RSER_EOQF_RE_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 13619 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
AnnaBridge 189:f392fc9709a3 13620 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 13621 #define SPI_RSER_TCF_RE_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 13622 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
AnnaBridge 189:f392fc9709a3 13623
AnnaBridge 189:f392fc9709a3 13624 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
AnnaBridge 189:f392fc9709a3 13625 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13626 #define SPI_PUSHR_TXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13627 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13628 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
AnnaBridge 189:f392fc9709a3 13629 #define SPI_PUSHR_PCS_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13630 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
AnnaBridge 189:f392fc9709a3 13631 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
AnnaBridge 189:f392fc9709a3 13632 #define SPI_PUSHR_CTCNT_SHIFT (26U)
AnnaBridge 189:f392fc9709a3 13633 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
AnnaBridge 189:f392fc9709a3 13634 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
AnnaBridge 189:f392fc9709a3 13635 #define SPI_PUSHR_EOQ_SHIFT (27U)
AnnaBridge 189:f392fc9709a3 13636 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
AnnaBridge 189:f392fc9709a3 13637 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
AnnaBridge 189:f392fc9709a3 13638 #define SPI_PUSHR_CTAS_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 13639 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
AnnaBridge 189:f392fc9709a3 13640 #define SPI_PUSHR_CONT_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 13641 #define SPI_PUSHR_CONT_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 13642 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
AnnaBridge 189:f392fc9709a3 13643
AnnaBridge 189:f392fc9709a3 13644 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
AnnaBridge 189:f392fc9709a3 13645 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13646 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13647 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13648
AnnaBridge 189:f392fc9709a3 13649 /*! @name POPR - POP RX FIFO Register */
AnnaBridge 189:f392fc9709a3 13650 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13651 #define SPI_POPR_RXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13652 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13653
AnnaBridge 189:f392fc9709a3 13654 /*! @name TXFR0 - Transmit FIFO Registers */
AnnaBridge 189:f392fc9709a3 13655 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13656 #define SPI_TXFR0_TXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13657 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13658 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 13659 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13660 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13661
AnnaBridge 189:f392fc9709a3 13662 /*! @name TXFR1 - Transmit FIFO Registers */
AnnaBridge 189:f392fc9709a3 13663 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13664 #define SPI_TXFR1_TXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13665 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13666 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 13667 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13668 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13669
AnnaBridge 189:f392fc9709a3 13670 /*! @name TXFR2 - Transmit FIFO Registers */
AnnaBridge 189:f392fc9709a3 13671 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13672 #define SPI_TXFR2_TXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13673 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13674 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 13675 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13676 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13677
AnnaBridge 189:f392fc9709a3 13678 /*! @name TXFR3 - Transmit FIFO Registers */
AnnaBridge 189:f392fc9709a3 13679 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13680 #define SPI_TXFR3_TXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13681 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13682 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 13683 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13684 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13685
AnnaBridge 189:f392fc9709a3 13686 /*! @name RXFR0 - Receive FIFO Registers */
AnnaBridge 189:f392fc9709a3 13687 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13688 #define SPI_RXFR0_RXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13689 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13690
AnnaBridge 189:f392fc9709a3 13691 /*! @name RXFR1 - Receive FIFO Registers */
AnnaBridge 189:f392fc9709a3 13692 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13693 #define SPI_RXFR1_RXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13694 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13695
AnnaBridge 189:f392fc9709a3 13696 /*! @name RXFR2 - Receive FIFO Registers */
AnnaBridge 189:f392fc9709a3 13697 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13698 #define SPI_RXFR2_RXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13699 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13700
AnnaBridge 189:f392fc9709a3 13701 /*! @name RXFR3 - Receive FIFO Registers */
AnnaBridge 189:f392fc9709a3 13702 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 13703 #define SPI_RXFR3_RXDATA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13704 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
AnnaBridge 189:f392fc9709a3 13705
AnnaBridge 189:f392fc9709a3 13706
AnnaBridge 189:f392fc9709a3 13707 /*!
AnnaBridge 189:f392fc9709a3 13708 * @}
AnnaBridge 189:f392fc9709a3 13709 */ /* end of group SPI_Register_Masks */
AnnaBridge 189:f392fc9709a3 13710
AnnaBridge 189:f392fc9709a3 13711
AnnaBridge 189:f392fc9709a3 13712 /* SPI - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 13713 /** Peripheral SPI0 base address */
AnnaBridge 189:f392fc9709a3 13714 #define SPI0_BASE (0x4002C000u)
AnnaBridge 189:f392fc9709a3 13715 /** Peripheral SPI0 base pointer */
AnnaBridge 189:f392fc9709a3 13716 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 189:f392fc9709a3 13717 /** Peripheral SPI1 base address */
AnnaBridge 189:f392fc9709a3 13718 #define SPI1_BASE (0x4002D000u)
AnnaBridge 189:f392fc9709a3 13719 /** Peripheral SPI1 base pointer */
AnnaBridge 189:f392fc9709a3 13720 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 189:f392fc9709a3 13721 /** Peripheral SPI2 base address */
AnnaBridge 189:f392fc9709a3 13722 #define SPI2_BASE (0x400AC000u)
AnnaBridge 189:f392fc9709a3 13723 /** Peripheral SPI2 base pointer */
AnnaBridge 189:f392fc9709a3 13724 #define SPI2 ((SPI_Type *)SPI2_BASE)
AnnaBridge 189:f392fc9709a3 13725 /** Array initializer of SPI peripheral base addresses */
AnnaBridge 189:f392fc9709a3 13726 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
AnnaBridge 189:f392fc9709a3 13727 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 189:f392fc9709a3 13728 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
AnnaBridge 189:f392fc9709a3 13729 /** Interrupt vectors for the SPI peripheral type */
AnnaBridge 189:f392fc9709a3 13730 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
AnnaBridge 189:f392fc9709a3 13731
AnnaBridge 189:f392fc9709a3 13732 /*!
AnnaBridge 189:f392fc9709a3 13733 * @}
AnnaBridge 189:f392fc9709a3 13734 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 13735
AnnaBridge 189:f392fc9709a3 13736
AnnaBridge 189:f392fc9709a3 13737 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 13738 -- TPM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13739 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 13740
AnnaBridge 189:f392fc9709a3 13741 /*!
AnnaBridge 189:f392fc9709a3 13742 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13743 * @{
AnnaBridge 189:f392fc9709a3 13744 */
AnnaBridge 189:f392fc9709a3 13745
AnnaBridge 189:f392fc9709a3 13746 /** TPM - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 13747 typedef struct {
AnnaBridge 189:f392fc9709a3 13748 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 13749 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 13750 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 13751 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 13752 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 13753 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 189:f392fc9709a3 13754 } CONTROLS[2];
AnnaBridge 189:f392fc9709a3 13755 uint8_t RESERVED_0[52];
AnnaBridge 189:f392fc9709a3 13756 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
AnnaBridge 189:f392fc9709a3 13757 uint8_t RESERVED_1[16];
AnnaBridge 189:f392fc9709a3 13758 __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
AnnaBridge 189:f392fc9709a3 13759 uint8_t RESERVED_2[8];
AnnaBridge 189:f392fc9709a3 13760 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
AnnaBridge 189:f392fc9709a3 13761 uint8_t RESERVED_3[4];
AnnaBridge 189:f392fc9709a3 13762 __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
AnnaBridge 189:f392fc9709a3 13763 uint8_t RESERVED_4[4];
AnnaBridge 189:f392fc9709a3 13764 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 13765 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 189:f392fc9709a3 13766 } TPM_Type;
AnnaBridge 189:f392fc9709a3 13767
AnnaBridge 189:f392fc9709a3 13768 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 13769 -- TPM Register Masks
AnnaBridge 189:f392fc9709a3 13770 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 13771
AnnaBridge 189:f392fc9709a3 13772 /*!
AnnaBridge 189:f392fc9709a3 13773 * @addtogroup TPM_Register_Masks TPM Register Masks
AnnaBridge 189:f392fc9709a3 13774 * @{
AnnaBridge 189:f392fc9709a3 13775 */
AnnaBridge 189:f392fc9709a3 13776
AnnaBridge 189:f392fc9709a3 13777 /*! @name SC - Status and Control */
AnnaBridge 189:f392fc9709a3 13778 #define TPM_SC_PS_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 13779 #define TPM_SC_PS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13780 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
AnnaBridge 189:f392fc9709a3 13781 #define TPM_SC_CMOD_MASK (0x18U)
AnnaBridge 189:f392fc9709a3 13782 #define TPM_SC_CMOD_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 13783 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
AnnaBridge 189:f392fc9709a3 13784 #define TPM_SC_CPWMS_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 13785 #define TPM_SC_CPWMS_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13786 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
AnnaBridge 189:f392fc9709a3 13787 #define TPM_SC_TOIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 13788 #define TPM_SC_TOIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 13789 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
AnnaBridge 189:f392fc9709a3 13790 #define TPM_SC_TOF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 13791 #define TPM_SC_TOF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 13792 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
AnnaBridge 189:f392fc9709a3 13793 #define TPM_SC_DMA_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 13794 #define TPM_SC_DMA_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 13795 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
AnnaBridge 189:f392fc9709a3 13796
AnnaBridge 189:f392fc9709a3 13797 /*! @name CNT - Counter */
AnnaBridge 189:f392fc9709a3 13798 #define TPM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13799 #define TPM_CNT_COUNT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13800 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
AnnaBridge 189:f392fc9709a3 13801
AnnaBridge 189:f392fc9709a3 13802 /*! @name MOD - Modulo */
AnnaBridge 189:f392fc9709a3 13803 #define TPM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13804 #define TPM_MOD_MOD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13805 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
AnnaBridge 189:f392fc9709a3 13806
AnnaBridge 189:f392fc9709a3 13807 /*! @name CnSC - Channel (n) Status and Control */
AnnaBridge 189:f392fc9709a3 13808 #define TPM_CnSC_DMA_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13809 #define TPM_CnSC_DMA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13810 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
AnnaBridge 189:f392fc9709a3 13811 #define TPM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 13812 #define TPM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 13813 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
AnnaBridge 189:f392fc9709a3 13814 #define TPM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 13815 #define TPM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 13816 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
AnnaBridge 189:f392fc9709a3 13817 #define TPM_CnSC_MSA_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 13818 #define TPM_CnSC_MSA_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13819 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
AnnaBridge 189:f392fc9709a3 13820 #define TPM_CnSC_MSB_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 13821 #define TPM_CnSC_MSB_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13822 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
AnnaBridge 189:f392fc9709a3 13823 #define TPM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 13824 #define TPM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 13825 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
AnnaBridge 189:f392fc9709a3 13826 #define TPM_CnSC_CHF_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 13827 #define TPM_CnSC_CHF_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 13828 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
AnnaBridge 189:f392fc9709a3 13829
AnnaBridge 189:f392fc9709a3 13830 /* The count of TPM_CnSC */
AnnaBridge 189:f392fc9709a3 13831 #define TPM_CnSC_COUNT (2U)
AnnaBridge 189:f392fc9709a3 13832
AnnaBridge 189:f392fc9709a3 13833 /*! @name CnV - Channel (n) Value */
AnnaBridge 189:f392fc9709a3 13834 #define TPM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 13835 #define TPM_CnV_VAL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13836 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
AnnaBridge 189:f392fc9709a3 13837
AnnaBridge 189:f392fc9709a3 13838 /* The count of TPM_CnV */
AnnaBridge 189:f392fc9709a3 13839 #define TPM_CnV_COUNT (2U)
AnnaBridge 189:f392fc9709a3 13840
AnnaBridge 189:f392fc9709a3 13841 /*! @name STATUS - Capture and Compare Status */
AnnaBridge 189:f392fc9709a3 13842 #define TPM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13843 #define TPM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13844 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
AnnaBridge 189:f392fc9709a3 13845 #define TPM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13846 #define TPM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13847 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
AnnaBridge 189:f392fc9709a3 13848 #define TPM_STATUS_TOF_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 13849 #define TPM_STATUS_TOF_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 13850 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
AnnaBridge 189:f392fc9709a3 13851
AnnaBridge 189:f392fc9709a3 13852 /*! @name COMBINE - Combine Channel Register */
AnnaBridge 189:f392fc9709a3 13853 #define TPM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13854 #define TPM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13855 #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
AnnaBridge 189:f392fc9709a3 13856 #define TPM_COMBINE_COMSWAP0_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13857 #define TPM_COMBINE_COMSWAP0_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13858 #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
AnnaBridge 189:f392fc9709a3 13859
AnnaBridge 189:f392fc9709a3 13860 /*! @name POL - Channel Polarity */
AnnaBridge 189:f392fc9709a3 13861 #define TPM_POL_POL0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13862 #define TPM_POL_POL0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13863 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
AnnaBridge 189:f392fc9709a3 13864 #define TPM_POL_POL1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13865 #define TPM_POL_POL1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13866 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
AnnaBridge 189:f392fc9709a3 13867
AnnaBridge 189:f392fc9709a3 13868 /*! @name FILTER - Filter Control */
AnnaBridge 189:f392fc9709a3 13869 #define TPM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 13870 #define TPM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13871 #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
AnnaBridge 189:f392fc9709a3 13872 #define TPM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 13873 #define TPM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 13874 #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
AnnaBridge 189:f392fc9709a3 13875
AnnaBridge 189:f392fc9709a3 13876 /*! @name QDCTRL - Quadrature Decoder Control and Status */
AnnaBridge 189:f392fc9709a3 13877 #define TPM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 13878 #define TPM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 13879 #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
AnnaBridge 189:f392fc9709a3 13880 #define TPM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 13881 #define TPM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 13882 #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
AnnaBridge 189:f392fc9709a3 13883 #define TPM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 13884 #define TPM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 13885 #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
AnnaBridge 189:f392fc9709a3 13886 #define TPM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 13887 #define TPM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 13888 #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
AnnaBridge 189:f392fc9709a3 13889
AnnaBridge 189:f392fc9709a3 13890 /*! @name CONF - Configuration */
AnnaBridge 189:f392fc9709a3 13891 #define TPM_CONF_DOZEEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 13892 #define TPM_CONF_DOZEEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 13893 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
AnnaBridge 189:f392fc9709a3 13894 #define TPM_CONF_DBGMODE_MASK (0xC0U)
AnnaBridge 189:f392fc9709a3 13895 #define TPM_CONF_DBGMODE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 13896 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
AnnaBridge 189:f392fc9709a3 13897 #define TPM_CONF_GTBSYNC_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 13898 #define TPM_CONF_GTBSYNC_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 13899 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
AnnaBridge 189:f392fc9709a3 13900 #define TPM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 13901 #define TPM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 13902 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
AnnaBridge 189:f392fc9709a3 13903 #define TPM_CONF_CSOT_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 13904 #define TPM_CONF_CSOT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 13905 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
AnnaBridge 189:f392fc9709a3 13906 #define TPM_CONF_CSOO_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 13907 #define TPM_CONF_CSOO_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 13908 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
AnnaBridge 189:f392fc9709a3 13909 #define TPM_CONF_CROT_MASK (0x40000U)
AnnaBridge 189:f392fc9709a3 13910 #define TPM_CONF_CROT_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 13911 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
AnnaBridge 189:f392fc9709a3 13912 #define TPM_CONF_CPOT_MASK (0x80000U)
AnnaBridge 189:f392fc9709a3 13913 #define TPM_CONF_CPOT_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 13914 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
AnnaBridge 189:f392fc9709a3 13915 #define TPM_CONF_TRGPOL_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 13916 #define TPM_CONF_TRGPOL_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 13917 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
AnnaBridge 189:f392fc9709a3 13918 #define TPM_CONF_TRGSRC_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 13919 #define TPM_CONF_TRGSRC_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 13920 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
AnnaBridge 189:f392fc9709a3 13921 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 13922 #define TPM_CONF_TRGSEL_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 13923 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
AnnaBridge 189:f392fc9709a3 13924
AnnaBridge 189:f392fc9709a3 13925
AnnaBridge 189:f392fc9709a3 13926 /*!
AnnaBridge 189:f392fc9709a3 13927 * @}
AnnaBridge 189:f392fc9709a3 13928 */ /* end of group TPM_Register_Masks */
AnnaBridge 189:f392fc9709a3 13929
AnnaBridge 189:f392fc9709a3 13930
AnnaBridge 189:f392fc9709a3 13931 /* TPM - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 13932 /** Peripheral TPM1 base address */
AnnaBridge 189:f392fc9709a3 13933 #define TPM1_BASE (0x400C9000u)
AnnaBridge 189:f392fc9709a3 13934 /** Peripheral TPM1 base pointer */
AnnaBridge 189:f392fc9709a3 13935 #define TPM1 ((TPM_Type *)TPM1_BASE)
AnnaBridge 189:f392fc9709a3 13936 /** Peripheral TPM2 base address */
AnnaBridge 189:f392fc9709a3 13937 #define TPM2_BASE (0x400CA000u)
AnnaBridge 189:f392fc9709a3 13938 /** Peripheral TPM2 base pointer */
AnnaBridge 189:f392fc9709a3 13939 #define TPM2 ((TPM_Type *)TPM2_BASE)
AnnaBridge 189:f392fc9709a3 13940 /** Array initializer of TPM peripheral base addresses */
AnnaBridge 189:f392fc9709a3 13941 #define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE }
AnnaBridge 189:f392fc9709a3 13942 /** Array initializer of TPM peripheral base pointers */
AnnaBridge 189:f392fc9709a3 13943 #define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 }
AnnaBridge 189:f392fc9709a3 13944 /** Interrupt vectors for the TPM peripheral type */
AnnaBridge 189:f392fc9709a3 13945 #define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
AnnaBridge 189:f392fc9709a3 13946
AnnaBridge 189:f392fc9709a3 13947 /*!
AnnaBridge 189:f392fc9709a3 13948 * @}
AnnaBridge 189:f392fc9709a3 13949 */ /* end of group TPM_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 13950
AnnaBridge 189:f392fc9709a3 13951
AnnaBridge 189:f392fc9709a3 13952 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 13953 -- TRNG Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13954 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 13955
AnnaBridge 189:f392fc9709a3 13956 /*!
AnnaBridge 189:f392fc9709a3 13957 * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 13958 * @{
AnnaBridge 189:f392fc9709a3 13959 */
AnnaBridge 189:f392fc9709a3 13960
AnnaBridge 189:f392fc9709a3 13961 /** TRNG - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 13962 typedef struct {
AnnaBridge 189:f392fc9709a3 13963 __IO uint32_t MCTL; /**< RNG Miscellaneous Control Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 13964 __IO uint32_t SCMISC; /**< RNG Statistical Check Miscellaneous Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 13965 __IO uint32_t PKRRNG; /**< RNG Poker Range Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 13966 union { /* offset: 0xC */
AnnaBridge 189:f392fc9709a3 13967 __IO uint32_t PKRMAX; /**< RNG Poker Maximum Limit Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 13968 __I uint32_t PKRSQ; /**< RNG Poker Square Calculation Result Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 13969 };
AnnaBridge 189:f392fc9709a3 13970 __IO uint32_t SDCTL; /**< RNG Seed Control Register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 13971 union { /* offset: 0x14 */
AnnaBridge 189:f392fc9709a3 13972 __IO uint32_t SBLIM; /**< RNG Sparse Bit Limit Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 13973 __I uint32_t TOTSAM; /**< RNG Total Samples Register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 13974 };
AnnaBridge 189:f392fc9709a3 13975 __IO uint32_t FRQMIN; /**< RNG Frequency Count Minimum Limit Register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 13976 union { /* offset: 0x1C */
AnnaBridge 189:f392fc9709a3 13977 __I uint32_t FRQCNT; /**< RNG Frequency Count Register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 13978 __IO uint32_t FRQMAX; /**< RNG Frequency Count Maximum Limit Register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 13979 };
AnnaBridge 189:f392fc9709a3 13980 union { /* offset: 0x20 */
AnnaBridge 189:f392fc9709a3 13981 __I uint32_t SCMC; /**< RNG Statistical Check Monobit Count Register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 13982 __IO uint32_t SCML; /**< RNG Statistical Check Monobit Limit Register, offset: 0x20 */
AnnaBridge 189:f392fc9709a3 13983 };
AnnaBridge 189:f392fc9709a3 13984 union { /* offset: 0x24 */
AnnaBridge 189:f392fc9709a3 13985 __I uint32_t SCR1C; /**< RNG Statistical Check Run Length 1 Count Register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 13986 __IO uint32_t SCR1L; /**< RNG Statistical Check Run Length 1 Limit Register, offset: 0x24 */
AnnaBridge 189:f392fc9709a3 13987 };
AnnaBridge 189:f392fc9709a3 13988 union { /* offset: 0x28 */
AnnaBridge 189:f392fc9709a3 13989 __I uint32_t SCR2C; /**< RNG Statistical Check Run Length 2 Count Register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 13990 __IO uint32_t SCR2L; /**< RNG Statistical Check Run Length 2 Limit Register, offset: 0x28 */
AnnaBridge 189:f392fc9709a3 13991 };
AnnaBridge 189:f392fc9709a3 13992 union { /* offset: 0x2C */
AnnaBridge 189:f392fc9709a3 13993 __I uint32_t SCR3C; /**< RNG Statistical Check Run Length 3 Count Register, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 13994 __IO uint32_t SCR3L; /**< RNG Statistical Check Run Length 3 Limit Register, offset: 0x2C */
AnnaBridge 189:f392fc9709a3 13995 };
AnnaBridge 189:f392fc9709a3 13996 union { /* offset: 0x30 */
AnnaBridge 189:f392fc9709a3 13997 __I uint32_t SCR4C; /**< RNG Statistical Check Run Length 4 Count Register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 13998 __IO uint32_t SCR4L; /**< RNG Statistical Check Run Length 4 Limit Register, offset: 0x30 */
AnnaBridge 189:f392fc9709a3 13999 };
AnnaBridge 189:f392fc9709a3 14000 union { /* offset: 0x34 */
AnnaBridge 189:f392fc9709a3 14001 __I uint32_t SCR5C; /**< RNG Statistical Check Run Length 5 Count Register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 14002 __IO uint32_t SCR5L; /**< RNG Statistical Check Run Length 5 Limit Register, offset: 0x34 */
AnnaBridge 189:f392fc9709a3 14003 };
AnnaBridge 189:f392fc9709a3 14004 union { /* offset: 0x38 */
AnnaBridge 189:f392fc9709a3 14005 __I uint32_t SCR6PC; /**< RNG Statistical Check Run Length 6+ Count Register, offset: 0x38 */
AnnaBridge 189:f392fc9709a3 14006 __IO uint32_t SCR6PL; /**< RNG Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
AnnaBridge 189:f392fc9709a3 14007 };
AnnaBridge 189:f392fc9709a3 14008 __I uint32_t STATUS; /**< RNG Status Register, offset: 0x3C */
AnnaBridge 189:f392fc9709a3 14009 __I uint32_t ENT[16]; /**< RNG TRNG Entropy Read Register, array offset: 0x40, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 14010 __I uint32_t PKRCNT10; /**< RNG Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 14011 __I uint32_t PKRCNT32; /**< RNG Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
AnnaBridge 189:f392fc9709a3 14012 __I uint32_t PKRCNT54; /**< RNG Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
AnnaBridge 189:f392fc9709a3 14013 __I uint32_t PKRCNT76; /**< RNG Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
AnnaBridge 189:f392fc9709a3 14014 __I uint32_t PKRCNT98; /**< RNG Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
AnnaBridge 189:f392fc9709a3 14015 __I uint32_t PKRCNTBA; /**< RNG Statistical Check Poker Count B and A Register, offset: 0x94 */
AnnaBridge 189:f392fc9709a3 14016 __I uint32_t PKRCNTDC; /**< RNG Statistical Check Poker Count D and C Register, offset: 0x98 */
AnnaBridge 189:f392fc9709a3 14017 __I uint32_t PKRCNTFE; /**< RNG Statistical Check Poker Count F and E Register, offset: 0x9C */
AnnaBridge 189:f392fc9709a3 14018 uint8_t RESERVED_0[16];
AnnaBridge 189:f392fc9709a3 14019 __IO uint32_t SEC_CFG; /**< RNG Security Configuration Register, offset: 0xB0 */
AnnaBridge 189:f392fc9709a3 14020 __IO uint32_t INT_CTRL; /**< RNG Interrupt Control Register, offset: 0xB4 */
AnnaBridge 189:f392fc9709a3 14021 __IO uint32_t INT_MASK; /**< RNG Mask Register, offset: 0xB8 */
AnnaBridge 189:f392fc9709a3 14022 __IO uint32_t INT_STATUS; /**< RNG Interrupt Status Register, offset: 0xBC */
AnnaBridge 189:f392fc9709a3 14023 uint8_t RESERVED_1[48];
AnnaBridge 189:f392fc9709a3 14024 __I uint32_t VID1; /**< RNG Version ID Register (MS), offset: 0xF0 */
AnnaBridge 189:f392fc9709a3 14025 __I uint32_t VID2; /**< RNG Version ID Register (LS), offset: 0xF4 */
AnnaBridge 189:f392fc9709a3 14026 } TRNG_Type;
AnnaBridge 189:f392fc9709a3 14027
AnnaBridge 189:f392fc9709a3 14028 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 14029 -- TRNG Register Masks
AnnaBridge 189:f392fc9709a3 14030 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 14031
AnnaBridge 189:f392fc9709a3 14032 /*!
AnnaBridge 189:f392fc9709a3 14033 * @addtogroup TRNG_Register_Masks TRNG Register Masks
AnnaBridge 189:f392fc9709a3 14034 * @{
AnnaBridge 189:f392fc9709a3 14035 */
AnnaBridge 189:f392fc9709a3 14036
AnnaBridge 189:f392fc9709a3 14037 /*! @name MCTL - RNG Miscellaneous Control Register */
AnnaBridge 189:f392fc9709a3 14038 #define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 14039 #define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14040 #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
AnnaBridge 189:f392fc9709a3 14041 #define TRNG_MCTL_OSC_DIV_MASK (0xCU)
AnnaBridge 189:f392fc9709a3 14042 #define TRNG_MCTL_OSC_DIV_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14043 #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
AnnaBridge 189:f392fc9709a3 14044 #define TRNG_MCTL_UNUSED_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14045 #define TRNG_MCTL_UNUSED_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14046 #define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
AnnaBridge 189:f392fc9709a3 14047 #define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14048 #define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14049 #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
AnnaBridge 189:f392fc9709a3 14050 #define TRNG_MCTL_RST_DEF_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14051 #define TRNG_MCTL_RST_DEF_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14052 #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
AnnaBridge 189:f392fc9709a3 14053 #define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14054 #define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14055 #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
AnnaBridge 189:f392fc9709a3 14056 #define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 14057 #define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 14058 #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
AnnaBridge 189:f392fc9709a3 14059 #define TRNG_MCTL_FCT_VAL_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 14060 #define TRNG_MCTL_FCT_VAL_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 14061 #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
AnnaBridge 189:f392fc9709a3 14062 #define TRNG_MCTL_ENT_VAL_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 14063 #define TRNG_MCTL_ENT_VAL_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 14064 #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
AnnaBridge 189:f392fc9709a3 14065 #define TRNG_MCTL_TST_OUT_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 14066 #define TRNG_MCTL_TST_OUT_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 14067 #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
AnnaBridge 189:f392fc9709a3 14068 #define TRNG_MCTL_ERR_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 14069 #define TRNG_MCTL_ERR_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 14070 #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
AnnaBridge 189:f392fc9709a3 14071 #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 14072 #define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 14073 #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
AnnaBridge 189:f392fc9709a3 14074 #define TRNG_MCTL_PRGM_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 14075 #define TRNG_MCTL_PRGM_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14076 #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
AnnaBridge 189:f392fc9709a3 14077
AnnaBridge 189:f392fc9709a3 14078 /*! @name SCMISC - RNG Statistical Check Miscellaneous Register */
AnnaBridge 189:f392fc9709a3 14079 #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14080 #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14081 #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14082 #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 14083 #define TRNG_SCMISC_RTY_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14084 #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
AnnaBridge 189:f392fc9709a3 14085
AnnaBridge 189:f392fc9709a3 14086 /*! @name PKRRNG - RNG Poker Range Register */
AnnaBridge 189:f392fc9709a3 14087 #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14088 #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14089 #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14090
AnnaBridge 189:f392fc9709a3 14091 /*! @name PKRMAX - RNG Poker Maximum Limit Register */
AnnaBridge 189:f392fc9709a3 14092 #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
AnnaBridge 189:f392fc9709a3 14093 #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14094 #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14095
AnnaBridge 189:f392fc9709a3 14096 /*! @name PKRSQ - RNG Poker Square Calculation Result Register */
AnnaBridge 189:f392fc9709a3 14097 #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
AnnaBridge 189:f392fc9709a3 14098 #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14099 #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
AnnaBridge 189:f392fc9709a3 14100
AnnaBridge 189:f392fc9709a3 14101 /*! @name SDCTL - RNG Seed Control Register */
AnnaBridge 189:f392fc9709a3 14102 #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14103 #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14104 #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
AnnaBridge 189:f392fc9709a3 14105 #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14106 #define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14107 #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
AnnaBridge 189:f392fc9709a3 14108
AnnaBridge 189:f392fc9709a3 14109 /*! @name SBLIM - RNG Sparse Bit Limit Register */
AnnaBridge 189:f392fc9709a3 14110 #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
AnnaBridge 189:f392fc9709a3 14111 #define TRNG_SBLIM_SB_LIM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14112 #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
AnnaBridge 189:f392fc9709a3 14113
AnnaBridge 189:f392fc9709a3 14114 /*! @name TOTSAM - RNG Total Samples Register */
AnnaBridge 189:f392fc9709a3 14115 #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
AnnaBridge 189:f392fc9709a3 14116 #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14117 #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
AnnaBridge 189:f392fc9709a3 14118
AnnaBridge 189:f392fc9709a3 14119 /*! @name FRQMIN - RNG Frequency Count Minimum Limit Register */
AnnaBridge 189:f392fc9709a3 14120 #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
AnnaBridge 189:f392fc9709a3 14121 #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14122 #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
AnnaBridge 189:f392fc9709a3 14123
AnnaBridge 189:f392fc9709a3 14124 /*! @name FRQCNT - RNG Frequency Count Register */
AnnaBridge 189:f392fc9709a3 14125 #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
AnnaBridge 189:f392fc9709a3 14126 #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14127 #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
AnnaBridge 189:f392fc9709a3 14128
AnnaBridge 189:f392fc9709a3 14129 /*! @name FRQMAX - RNG Frequency Count Maximum Limit Register */
AnnaBridge 189:f392fc9709a3 14130 #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
AnnaBridge 189:f392fc9709a3 14131 #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14132 #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14133
AnnaBridge 189:f392fc9709a3 14134 /*! @name SCMC - RNG Statistical Check Monobit Count Register */
AnnaBridge 189:f392fc9709a3 14135 #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14136 #define TRNG_SCMC_MONO_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14137 #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
AnnaBridge 189:f392fc9709a3 14138
AnnaBridge 189:f392fc9709a3 14139 /*! @name SCML - RNG Statistical Check Monobit Limit Register */
AnnaBridge 189:f392fc9709a3 14140 #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14141 #define TRNG_SCML_MONO_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14142 #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14143 #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14144 #define TRNG_SCML_MONO_RNG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14145 #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14146
AnnaBridge 189:f392fc9709a3 14147 /*! @name SCR1C - RNG Statistical Check Run Length 1 Count Register */
AnnaBridge 189:f392fc9709a3 14148 #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
AnnaBridge 189:f392fc9709a3 14149 #define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14150 #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
AnnaBridge 189:f392fc9709a3 14151 #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
AnnaBridge 189:f392fc9709a3 14152 #define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14153 #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
AnnaBridge 189:f392fc9709a3 14154
AnnaBridge 189:f392fc9709a3 14155 /*! @name SCR1L - RNG Statistical Check Run Length 1 Limit Register */
AnnaBridge 189:f392fc9709a3 14156 #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
AnnaBridge 189:f392fc9709a3 14157 #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14158 #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14159 #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
AnnaBridge 189:f392fc9709a3 14160 #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14161 #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14162
AnnaBridge 189:f392fc9709a3 14163 /*! @name SCR2C - RNG Statistical Check Run Length 2 Count Register */
AnnaBridge 189:f392fc9709a3 14164 #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
AnnaBridge 189:f392fc9709a3 14165 #define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14166 #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
AnnaBridge 189:f392fc9709a3 14167 #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
AnnaBridge 189:f392fc9709a3 14168 #define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14169 #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
AnnaBridge 189:f392fc9709a3 14170
AnnaBridge 189:f392fc9709a3 14171 /*! @name SCR2L - RNG Statistical Check Run Length 2 Limit Register */
AnnaBridge 189:f392fc9709a3 14172 #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
AnnaBridge 189:f392fc9709a3 14173 #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14174 #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14175 #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
AnnaBridge 189:f392fc9709a3 14176 #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14177 #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14178
AnnaBridge 189:f392fc9709a3 14179 /*! @name SCR3C - RNG Statistical Check Run Length 3 Count Register */
AnnaBridge 189:f392fc9709a3 14180 #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
AnnaBridge 189:f392fc9709a3 14181 #define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14182 #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
AnnaBridge 189:f392fc9709a3 14183 #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
AnnaBridge 189:f392fc9709a3 14184 #define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14185 #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
AnnaBridge 189:f392fc9709a3 14186
AnnaBridge 189:f392fc9709a3 14187 /*! @name SCR3L - RNG Statistical Check Run Length 3 Limit Register */
AnnaBridge 189:f392fc9709a3 14188 #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
AnnaBridge 189:f392fc9709a3 14189 #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14190 #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14191 #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
AnnaBridge 189:f392fc9709a3 14192 #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14193 #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14194
AnnaBridge 189:f392fc9709a3 14195 /*! @name SCR4C - RNG Statistical Check Run Length 4 Count Register */
AnnaBridge 189:f392fc9709a3 14196 #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
AnnaBridge 189:f392fc9709a3 14197 #define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14198 #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
AnnaBridge 189:f392fc9709a3 14199 #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
AnnaBridge 189:f392fc9709a3 14200 #define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14201 #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
AnnaBridge 189:f392fc9709a3 14202
AnnaBridge 189:f392fc9709a3 14203 /*! @name SCR4L - RNG Statistical Check Run Length 4 Limit Register */
AnnaBridge 189:f392fc9709a3 14204 #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
AnnaBridge 189:f392fc9709a3 14205 #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14206 #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14207 #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
AnnaBridge 189:f392fc9709a3 14208 #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14209 #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14210
AnnaBridge 189:f392fc9709a3 14211 /*! @name SCR5C - RNG Statistical Check Run Length 5 Count Register */
AnnaBridge 189:f392fc9709a3 14212 #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
AnnaBridge 189:f392fc9709a3 14213 #define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14214 #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
AnnaBridge 189:f392fc9709a3 14215 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
AnnaBridge 189:f392fc9709a3 14216 #define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14217 #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
AnnaBridge 189:f392fc9709a3 14218
AnnaBridge 189:f392fc9709a3 14219 /*! @name SCR5L - RNG Statistical Check Run Length 5 Limit Register */
AnnaBridge 189:f392fc9709a3 14220 #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
AnnaBridge 189:f392fc9709a3 14221 #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14222 #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14223 #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
AnnaBridge 189:f392fc9709a3 14224 #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14225 #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14226
AnnaBridge 189:f392fc9709a3 14227 /*! @name SCR6PC - RNG Statistical Check Run Length 6+ Count Register */
AnnaBridge 189:f392fc9709a3 14228 #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
AnnaBridge 189:f392fc9709a3 14229 #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14230 #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
AnnaBridge 189:f392fc9709a3 14231 #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
AnnaBridge 189:f392fc9709a3 14232 #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14233 #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
AnnaBridge 189:f392fc9709a3 14234
AnnaBridge 189:f392fc9709a3 14235 /*! @name SCR6PL - RNG Statistical Check Run Length 6+ Limit Register */
AnnaBridge 189:f392fc9709a3 14236 #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
AnnaBridge 189:f392fc9709a3 14237 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14238 #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
AnnaBridge 189:f392fc9709a3 14239 #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
AnnaBridge 189:f392fc9709a3 14240 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14241 #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
AnnaBridge 189:f392fc9709a3 14242
AnnaBridge 189:f392fc9709a3 14243 /*! @name STATUS - RNG Status Register */
AnnaBridge 189:f392fc9709a3 14244 #define TRNG_STATUS_TF1BR0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14245 #define TRNG_STATUS_TF1BR0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14246 #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
AnnaBridge 189:f392fc9709a3 14247 #define TRNG_STATUS_TF1BR1_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14248 #define TRNG_STATUS_TF1BR1_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14249 #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
AnnaBridge 189:f392fc9709a3 14250 #define TRNG_STATUS_TF2BR0_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14251 #define TRNG_STATUS_TF2BR0_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14252 #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
AnnaBridge 189:f392fc9709a3 14253 #define TRNG_STATUS_TF2BR1_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14254 #define TRNG_STATUS_TF2BR1_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14255 #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
AnnaBridge 189:f392fc9709a3 14256 #define TRNG_STATUS_TF3BR0_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14257 #define TRNG_STATUS_TF3BR0_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14258 #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
AnnaBridge 189:f392fc9709a3 14259 #define TRNG_STATUS_TF3BR1_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14260 #define TRNG_STATUS_TF3BR1_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14261 #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
AnnaBridge 189:f392fc9709a3 14262 #define TRNG_STATUS_TF4BR0_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14263 #define TRNG_STATUS_TF4BR0_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14264 #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
AnnaBridge 189:f392fc9709a3 14265 #define TRNG_STATUS_TF4BR1_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14266 #define TRNG_STATUS_TF4BR1_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14267 #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
AnnaBridge 189:f392fc9709a3 14268 #define TRNG_STATUS_TF5BR0_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 14269 #define TRNG_STATUS_TF5BR0_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 14270 #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
AnnaBridge 189:f392fc9709a3 14271 #define TRNG_STATUS_TF5BR1_MASK (0x200U)
AnnaBridge 189:f392fc9709a3 14272 #define TRNG_STATUS_TF5BR1_SHIFT (9U)
AnnaBridge 189:f392fc9709a3 14273 #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
AnnaBridge 189:f392fc9709a3 14274 #define TRNG_STATUS_TF6PBR0_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 14275 #define TRNG_STATUS_TF6PBR0_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 14276 #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
AnnaBridge 189:f392fc9709a3 14277 #define TRNG_STATUS_TF6PBR1_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 14278 #define TRNG_STATUS_TF6PBR1_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 14279 #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
AnnaBridge 189:f392fc9709a3 14280 #define TRNG_STATUS_TFSB_MASK (0x1000U)
AnnaBridge 189:f392fc9709a3 14281 #define TRNG_STATUS_TFSB_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 14282 #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
AnnaBridge 189:f392fc9709a3 14283 #define TRNG_STATUS_TFLR_MASK (0x2000U)
AnnaBridge 189:f392fc9709a3 14284 #define TRNG_STATUS_TFLR_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 14285 #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
AnnaBridge 189:f392fc9709a3 14286 #define TRNG_STATUS_TFP_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 14287 #define TRNG_STATUS_TFP_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 14288 #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
AnnaBridge 189:f392fc9709a3 14289 #define TRNG_STATUS_TFMB_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 14290 #define TRNG_STATUS_TFMB_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 14291 #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
AnnaBridge 189:f392fc9709a3 14292 #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
AnnaBridge 189:f392fc9709a3 14293 #define TRNG_STATUS_RETRY_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14294 #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
AnnaBridge 189:f392fc9709a3 14295
AnnaBridge 189:f392fc9709a3 14296 /*! @name ENT - RNG TRNG Entropy Read Register */
AnnaBridge 189:f392fc9709a3 14297 #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
AnnaBridge 189:f392fc9709a3 14298 #define TRNG_ENT_ENT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14299 #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
AnnaBridge 189:f392fc9709a3 14300
AnnaBridge 189:f392fc9709a3 14301 /* The count of TRNG_ENT */
AnnaBridge 189:f392fc9709a3 14302 #define TRNG_ENT_COUNT (16U)
AnnaBridge 189:f392fc9709a3 14303
AnnaBridge 189:f392fc9709a3 14304 /*! @name PKRCNT10 - RNG Statistical Check Poker Count 1 and 0 Register */
AnnaBridge 189:f392fc9709a3 14305 #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14306 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14307 #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
AnnaBridge 189:f392fc9709a3 14308 #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14309 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14310 #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
AnnaBridge 189:f392fc9709a3 14311
AnnaBridge 189:f392fc9709a3 14312 /*! @name PKRCNT32 - RNG Statistical Check Poker Count 3 and 2 Register */
AnnaBridge 189:f392fc9709a3 14313 #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14314 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14315 #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
AnnaBridge 189:f392fc9709a3 14316 #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14317 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14318 #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
AnnaBridge 189:f392fc9709a3 14319
AnnaBridge 189:f392fc9709a3 14320 /*! @name PKRCNT54 - RNG Statistical Check Poker Count 5 and 4 Register */
AnnaBridge 189:f392fc9709a3 14321 #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14322 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14323 #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
AnnaBridge 189:f392fc9709a3 14324 #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14325 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14326 #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
AnnaBridge 189:f392fc9709a3 14327
AnnaBridge 189:f392fc9709a3 14328 /*! @name PKRCNT76 - RNG Statistical Check Poker Count 7 and 6 Register */
AnnaBridge 189:f392fc9709a3 14329 #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14330 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14331 #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
AnnaBridge 189:f392fc9709a3 14332 #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14333 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14334 #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
AnnaBridge 189:f392fc9709a3 14335
AnnaBridge 189:f392fc9709a3 14336 /*! @name PKRCNT98 - RNG Statistical Check Poker Count 9 and 8 Register */
AnnaBridge 189:f392fc9709a3 14337 #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14338 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14339 #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
AnnaBridge 189:f392fc9709a3 14340 #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14341 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14342 #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
AnnaBridge 189:f392fc9709a3 14343
AnnaBridge 189:f392fc9709a3 14344 /*! @name PKRCNTBA - RNG Statistical Check Poker Count B and A Register */
AnnaBridge 189:f392fc9709a3 14345 #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14346 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14347 #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
AnnaBridge 189:f392fc9709a3 14348 #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14349 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14350 #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
AnnaBridge 189:f392fc9709a3 14351
AnnaBridge 189:f392fc9709a3 14352 /*! @name PKRCNTDC - RNG Statistical Check Poker Count D and C Register */
AnnaBridge 189:f392fc9709a3 14353 #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14354 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14355 #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
AnnaBridge 189:f392fc9709a3 14356 #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14357 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14358 #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
AnnaBridge 189:f392fc9709a3 14359
AnnaBridge 189:f392fc9709a3 14360 /*! @name PKRCNTFE - RNG Statistical Check Poker Count F and E Register */
AnnaBridge 189:f392fc9709a3 14361 #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14362 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14363 #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
AnnaBridge 189:f392fc9709a3 14364 #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14365 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14366 #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
AnnaBridge 189:f392fc9709a3 14367
AnnaBridge 189:f392fc9709a3 14368 /*! @name SEC_CFG - RNG Security Configuration Register */
AnnaBridge 189:f392fc9709a3 14369 #define TRNG_SEC_CFG_SH0_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14370 #define TRNG_SEC_CFG_SH0_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14371 #define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
AnnaBridge 189:f392fc9709a3 14372 #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14373 #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14374 #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
AnnaBridge 189:f392fc9709a3 14375 #define TRNG_SEC_CFG_SK_VAL_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14376 #define TRNG_SEC_CFG_SK_VAL_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14377 #define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
AnnaBridge 189:f392fc9709a3 14378
AnnaBridge 189:f392fc9709a3 14379 /*! @name INT_CTRL - RNG Interrupt Control Register */
AnnaBridge 189:f392fc9709a3 14380 #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14381 #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14382 #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
AnnaBridge 189:f392fc9709a3 14383 #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14384 #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14385 #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
AnnaBridge 189:f392fc9709a3 14386 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14387 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14388 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
AnnaBridge 189:f392fc9709a3 14389 #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
AnnaBridge 189:f392fc9709a3 14390 #define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14391 #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
AnnaBridge 189:f392fc9709a3 14392
AnnaBridge 189:f392fc9709a3 14393 /*! @name INT_MASK - RNG Mask Register */
AnnaBridge 189:f392fc9709a3 14394 #define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14395 #define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14396 #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
AnnaBridge 189:f392fc9709a3 14397 #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14398 #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14399 #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
AnnaBridge 189:f392fc9709a3 14400 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14401 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14402 #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
AnnaBridge 189:f392fc9709a3 14403
AnnaBridge 189:f392fc9709a3 14404 /*! @name INT_STATUS - RNG Interrupt Status Register */
AnnaBridge 189:f392fc9709a3 14405 #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14406 #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14407 #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
AnnaBridge 189:f392fc9709a3 14408 #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14409 #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14410 #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
AnnaBridge 189:f392fc9709a3 14411 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14412 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14413 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
AnnaBridge 189:f392fc9709a3 14414
AnnaBridge 189:f392fc9709a3 14415 /*! @name VID1 - RNG Version ID Register (MS) */
AnnaBridge 189:f392fc9709a3 14416 #define TRNG_VID1_RNG_MIN_REV_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14417 #define TRNG_VID1_RNG_MIN_REV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14418 #define TRNG_VID1_RNG_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MIN_REV_SHIFT)) & TRNG_VID1_RNG_MIN_REV_MASK)
AnnaBridge 189:f392fc9709a3 14419 #define TRNG_VID1_RNG_MAJ_REV_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 14420 #define TRNG_VID1_RNG_MAJ_REV_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 14421 #define TRNG_VID1_RNG_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_MAJ_REV_SHIFT)) & TRNG_VID1_RNG_MAJ_REV_MASK)
AnnaBridge 189:f392fc9709a3 14422 #define TRNG_VID1_RNG_IP_ID_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14423 #define TRNG_VID1_RNG_IP_ID_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14424 #define TRNG_VID1_RNG_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_RNG_IP_ID_SHIFT)) & TRNG_VID1_RNG_IP_ID_MASK)
AnnaBridge 189:f392fc9709a3 14425
AnnaBridge 189:f392fc9709a3 14426 /*! @name VID2 - RNG Version ID Register (LS) */
AnnaBridge 189:f392fc9709a3 14427 #define TRNG_VID2_RNG_CONFIG_OPT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14428 #define TRNG_VID2_RNG_CONFIG_OPT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14429 #define TRNG_VID2_RNG_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_CONFIG_OPT_SHIFT)) & TRNG_VID2_RNG_CONFIG_OPT_MASK)
AnnaBridge 189:f392fc9709a3 14430 #define TRNG_VID2_RNG_ECO_REV_MASK (0xFF00U)
AnnaBridge 189:f392fc9709a3 14431 #define TRNG_VID2_RNG_ECO_REV_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 14432 #define TRNG_VID2_RNG_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ECO_REV_SHIFT)) & TRNG_VID2_RNG_ECO_REV_MASK)
AnnaBridge 189:f392fc9709a3 14433 #define TRNG_VID2_RNG_INTG_OPT_MASK (0xFF0000U)
AnnaBridge 189:f392fc9709a3 14434 #define TRNG_VID2_RNG_INTG_OPT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14435 #define TRNG_VID2_RNG_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_INTG_OPT_SHIFT)) & TRNG_VID2_RNG_INTG_OPT_MASK)
AnnaBridge 189:f392fc9709a3 14436 #define TRNG_VID2_RNG_ERA_MASK (0xFF000000U)
AnnaBridge 189:f392fc9709a3 14437 #define TRNG_VID2_RNG_ERA_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 14438 #define TRNG_VID2_RNG_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_RNG_ERA_SHIFT)) & TRNG_VID2_RNG_ERA_MASK)
AnnaBridge 189:f392fc9709a3 14439
AnnaBridge 189:f392fc9709a3 14440
AnnaBridge 189:f392fc9709a3 14441 /*!
AnnaBridge 189:f392fc9709a3 14442 * @}
AnnaBridge 189:f392fc9709a3 14443 */ /* end of group TRNG_Register_Masks */
AnnaBridge 189:f392fc9709a3 14444
AnnaBridge 189:f392fc9709a3 14445
AnnaBridge 189:f392fc9709a3 14446 /* TRNG - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 14447 /** Peripheral TRNG0 base address */
AnnaBridge 189:f392fc9709a3 14448 #define TRNG0_BASE (0x400A0000u)
AnnaBridge 189:f392fc9709a3 14449 /** Peripheral TRNG0 base pointer */
AnnaBridge 189:f392fc9709a3 14450 #define TRNG0 ((TRNG_Type *)TRNG0_BASE)
AnnaBridge 189:f392fc9709a3 14451 /** Array initializer of TRNG peripheral base addresses */
AnnaBridge 189:f392fc9709a3 14452 #define TRNG_BASE_ADDRS { TRNG0_BASE }
AnnaBridge 189:f392fc9709a3 14453 /** Array initializer of TRNG peripheral base pointers */
AnnaBridge 189:f392fc9709a3 14454 #define TRNG_BASE_PTRS { TRNG0 }
AnnaBridge 189:f392fc9709a3 14455 /** Interrupt vectors for the TRNG peripheral type */
AnnaBridge 189:f392fc9709a3 14456 #define TRNG_IRQS { TRNG0_IRQn }
AnnaBridge 189:f392fc9709a3 14457
AnnaBridge 189:f392fc9709a3 14458 /*!
AnnaBridge 189:f392fc9709a3 14459 * @}
AnnaBridge 189:f392fc9709a3 14460 */ /* end of group TRNG_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 14461
AnnaBridge 189:f392fc9709a3 14462
AnnaBridge 189:f392fc9709a3 14463 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 14464 -- TSI Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 14465 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 14466
AnnaBridge 189:f392fc9709a3 14467 /*!
AnnaBridge 189:f392fc9709a3 14468 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 14469 * @{
AnnaBridge 189:f392fc9709a3 14470 */
AnnaBridge 189:f392fc9709a3 14471
AnnaBridge 189:f392fc9709a3 14472 /** TSI - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 14473 typedef struct {
AnnaBridge 189:f392fc9709a3 14474 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 14475 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 14476 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 14477 } TSI_Type;
AnnaBridge 189:f392fc9709a3 14478
AnnaBridge 189:f392fc9709a3 14479 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 14480 -- TSI Register Masks
AnnaBridge 189:f392fc9709a3 14481 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 14482
AnnaBridge 189:f392fc9709a3 14483 /*!
AnnaBridge 189:f392fc9709a3 14484 * @addtogroup TSI_Register_Masks TSI Register Masks
AnnaBridge 189:f392fc9709a3 14485 * @{
AnnaBridge 189:f392fc9709a3 14486 */
AnnaBridge 189:f392fc9709a3 14487
AnnaBridge 189:f392fc9709a3 14488 /*! @name GENCS - TSI General Control and Status Register */
AnnaBridge 189:f392fc9709a3 14489 #define TSI_GENCS_EOSDMEO_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14490 #define TSI_GENCS_EOSDMEO_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14491 #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
AnnaBridge 189:f392fc9709a3 14492 #define TSI_GENCS_CURSW_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14493 #define TSI_GENCS_CURSW_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14494 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
AnnaBridge 189:f392fc9709a3 14495 #define TSI_GENCS_EOSF_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14496 #define TSI_GENCS_EOSF_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14497 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
AnnaBridge 189:f392fc9709a3 14498 #define TSI_GENCS_SCNIP_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14499 #define TSI_GENCS_SCNIP_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14500 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
AnnaBridge 189:f392fc9709a3 14501 #define TSI_GENCS_STM_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14502 #define TSI_GENCS_STM_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14503 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
AnnaBridge 189:f392fc9709a3 14504 #define TSI_GENCS_STPE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14505 #define TSI_GENCS_STPE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14506 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
AnnaBridge 189:f392fc9709a3 14507 #define TSI_GENCS_TSIIEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14508 #define TSI_GENCS_TSIIEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14509 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
AnnaBridge 189:f392fc9709a3 14510 #define TSI_GENCS_TSIEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14511 #define TSI_GENCS_TSIEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14512 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
AnnaBridge 189:f392fc9709a3 14513 #define TSI_GENCS_NSCN_MASK (0x1F00U)
AnnaBridge 189:f392fc9709a3 14514 #define TSI_GENCS_NSCN_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 14515 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
AnnaBridge 189:f392fc9709a3 14516 #define TSI_GENCS_PS_MASK (0xE000U)
AnnaBridge 189:f392fc9709a3 14517 #define TSI_GENCS_PS_SHIFT (13U)
AnnaBridge 189:f392fc9709a3 14518 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
AnnaBridge 189:f392fc9709a3 14519 #define TSI_GENCS_EXTCHRG_MASK (0x70000U)
AnnaBridge 189:f392fc9709a3 14520 #define TSI_GENCS_EXTCHRG_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14521 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
AnnaBridge 189:f392fc9709a3 14522 #define TSI_GENCS_DVOLT_MASK (0x180000U)
AnnaBridge 189:f392fc9709a3 14523 #define TSI_GENCS_DVOLT_SHIFT (19U)
AnnaBridge 189:f392fc9709a3 14524 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
AnnaBridge 189:f392fc9709a3 14525 #define TSI_GENCS_REFCHRG_MASK (0xE00000U)
AnnaBridge 189:f392fc9709a3 14526 #define TSI_GENCS_REFCHRG_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 14527 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
AnnaBridge 189:f392fc9709a3 14528 #define TSI_GENCS_MODE_MASK (0xF000000U)
AnnaBridge 189:f392fc9709a3 14529 #define TSI_GENCS_MODE_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 14530 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
AnnaBridge 189:f392fc9709a3 14531 #define TSI_GENCS_ESOR_MASK (0x10000000U)
AnnaBridge 189:f392fc9709a3 14532 #define TSI_GENCS_ESOR_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 14533 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
AnnaBridge 189:f392fc9709a3 14534 #define TSI_GENCS_OUTRGF_MASK (0x80000000U)
AnnaBridge 189:f392fc9709a3 14535 #define TSI_GENCS_OUTRGF_SHIFT (31U)
AnnaBridge 189:f392fc9709a3 14536 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
AnnaBridge 189:f392fc9709a3 14537
AnnaBridge 189:f392fc9709a3 14538 /*! @name DATA - TSI DATA Register */
AnnaBridge 189:f392fc9709a3 14539 #define TSI_DATA_TSICNT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14540 #define TSI_DATA_TSICNT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14541 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
AnnaBridge 189:f392fc9709a3 14542 #define TSI_DATA_SWTS_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 14543 #define TSI_DATA_SWTS_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 14544 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
AnnaBridge 189:f392fc9709a3 14545 #define TSI_DATA_DMAEN_MASK (0x800000U)
AnnaBridge 189:f392fc9709a3 14546 #define TSI_DATA_DMAEN_SHIFT (23U)
AnnaBridge 189:f392fc9709a3 14547 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
AnnaBridge 189:f392fc9709a3 14548 #define TSI_DATA_TSICH_MASK (0xF0000000U)
AnnaBridge 189:f392fc9709a3 14549 #define TSI_DATA_TSICH_SHIFT (28U)
AnnaBridge 189:f392fc9709a3 14550 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
AnnaBridge 189:f392fc9709a3 14551
AnnaBridge 189:f392fc9709a3 14552 /*! @name TSHD - TSI Threshold Register */
AnnaBridge 189:f392fc9709a3 14553 #define TSI_TSHD_THRESL_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 14554 #define TSI_TSHD_THRESL_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14555 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
AnnaBridge 189:f392fc9709a3 14556 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
AnnaBridge 189:f392fc9709a3 14557 #define TSI_TSHD_THRESH_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 14558 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
AnnaBridge 189:f392fc9709a3 14559
AnnaBridge 189:f392fc9709a3 14560
AnnaBridge 189:f392fc9709a3 14561 /*!
AnnaBridge 189:f392fc9709a3 14562 * @}
AnnaBridge 189:f392fc9709a3 14563 */ /* end of group TSI_Register_Masks */
AnnaBridge 189:f392fc9709a3 14564
AnnaBridge 189:f392fc9709a3 14565
AnnaBridge 189:f392fc9709a3 14566 /* TSI - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 14567 /** Peripheral TSI0 base address */
AnnaBridge 189:f392fc9709a3 14568 #define TSI0_BASE (0x40045000u)
AnnaBridge 189:f392fc9709a3 14569 /** Peripheral TSI0 base pointer */
AnnaBridge 189:f392fc9709a3 14570 #define TSI0 ((TSI_Type *)TSI0_BASE)
AnnaBridge 189:f392fc9709a3 14571 /** Array initializer of TSI peripheral base addresses */
AnnaBridge 189:f392fc9709a3 14572 #define TSI_BASE_ADDRS { TSI0_BASE }
AnnaBridge 189:f392fc9709a3 14573 /** Array initializer of TSI peripheral base pointers */
AnnaBridge 189:f392fc9709a3 14574 #define TSI_BASE_PTRS { TSI0 }
AnnaBridge 189:f392fc9709a3 14575 /** Interrupt vectors for the TSI peripheral type */
AnnaBridge 189:f392fc9709a3 14576 #define TSI_IRQS { TSI0_IRQn }
AnnaBridge 189:f392fc9709a3 14577
AnnaBridge 189:f392fc9709a3 14578 /*!
AnnaBridge 189:f392fc9709a3 14579 * @}
AnnaBridge 189:f392fc9709a3 14580 */ /* end of group TSI_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 14581
AnnaBridge 189:f392fc9709a3 14582
AnnaBridge 189:f392fc9709a3 14583 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 14584 -- USB Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 14585 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 14586
AnnaBridge 189:f392fc9709a3 14587 /*!
AnnaBridge 189:f392fc9709a3 14588 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 14589 * @{
AnnaBridge 189:f392fc9709a3 14590 */
AnnaBridge 189:f392fc9709a3 14591
AnnaBridge 189:f392fc9709a3 14592 /** USB - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 14593 typedef struct {
AnnaBridge 189:f392fc9709a3 14594 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 14595 uint8_t RESERVED_0[3];
AnnaBridge 189:f392fc9709a3 14596 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 14597 uint8_t RESERVED_1[3];
AnnaBridge 189:f392fc9709a3 14598 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 14599 uint8_t RESERVED_2[3];
AnnaBridge 189:f392fc9709a3 14600 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 14601 uint8_t RESERVED_3[3];
AnnaBridge 189:f392fc9709a3 14602 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 14603 uint8_t RESERVED_4[3];
AnnaBridge 189:f392fc9709a3 14604 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 14605 uint8_t RESERVED_5[3];
AnnaBridge 189:f392fc9709a3 14606 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 14607 uint8_t RESERVED_6[3];
AnnaBridge 189:f392fc9709a3 14608 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 189:f392fc9709a3 14609 uint8_t RESERVED_7[99];
AnnaBridge 189:f392fc9709a3 14610 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 189:f392fc9709a3 14611 uint8_t RESERVED_8[3];
AnnaBridge 189:f392fc9709a3 14612 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 189:f392fc9709a3 14613 uint8_t RESERVED_9[3];
AnnaBridge 189:f392fc9709a3 14614 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 189:f392fc9709a3 14615 uint8_t RESERVED_10[3];
AnnaBridge 189:f392fc9709a3 14616 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 189:f392fc9709a3 14617 uint8_t RESERVED_11[3];
AnnaBridge 189:f392fc9709a3 14618 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 189:f392fc9709a3 14619 uint8_t RESERVED_12[3];
AnnaBridge 189:f392fc9709a3 14620 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 189:f392fc9709a3 14621 uint8_t RESERVED_13[3];
AnnaBridge 189:f392fc9709a3 14622 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 189:f392fc9709a3 14623 uint8_t RESERVED_14[3];
AnnaBridge 189:f392fc9709a3 14624 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
AnnaBridge 189:f392fc9709a3 14625 uint8_t RESERVED_15[3];
AnnaBridge 189:f392fc9709a3 14626 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
AnnaBridge 189:f392fc9709a3 14627 uint8_t RESERVED_16[3];
AnnaBridge 189:f392fc9709a3 14628 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
AnnaBridge 189:f392fc9709a3 14629 uint8_t RESERVED_17[3];
AnnaBridge 189:f392fc9709a3 14630 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
AnnaBridge 189:f392fc9709a3 14631 uint8_t RESERVED_18[3];
AnnaBridge 189:f392fc9709a3 14632 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
AnnaBridge 189:f392fc9709a3 14633 uint8_t RESERVED_19[3];
AnnaBridge 189:f392fc9709a3 14634 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 189:f392fc9709a3 14635 uint8_t RESERVED_20[3];
AnnaBridge 189:f392fc9709a3 14636 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 189:f392fc9709a3 14637 uint8_t RESERVED_21[11];
AnnaBridge 189:f392fc9709a3 14638 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 14639 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 189:f392fc9709a3 14640 uint8_t RESERVED_0[3];
AnnaBridge 189:f392fc9709a3 14641 } ENDPOINT[16];
AnnaBridge 189:f392fc9709a3 14642 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 189:f392fc9709a3 14643 uint8_t RESERVED_22[3];
AnnaBridge 189:f392fc9709a3 14644 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 189:f392fc9709a3 14645 uint8_t RESERVED_23[3];
AnnaBridge 189:f392fc9709a3 14646 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 189:f392fc9709a3 14647 uint8_t RESERVED_24[3];
AnnaBridge 189:f392fc9709a3 14648 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
AnnaBridge 189:f392fc9709a3 14649 uint8_t RESERVED_25[7];
AnnaBridge 189:f392fc9709a3 14650 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
AnnaBridge 189:f392fc9709a3 14651 uint8_t RESERVED_26[23];
AnnaBridge 189:f392fc9709a3 14652 __IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */
AnnaBridge 189:f392fc9709a3 14653 uint8_t RESERVED_27[19];
AnnaBridge 189:f392fc9709a3 14654 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
AnnaBridge 189:f392fc9709a3 14655 uint8_t RESERVED_28[3];
AnnaBridge 189:f392fc9709a3 14656 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
AnnaBridge 189:f392fc9709a3 14657 uint8_t RESERVED_29[15];
AnnaBridge 189:f392fc9709a3 14658 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
AnnaBridge 189:f392fc9709a3 14659 uint8_t RESERVED_30[7];
AnnaBridge 189:f392fc9709a3 14660 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
AnnaBridge 189:f392fc9709a3 14661 } USB_Type;
AnnaBridge 189:f392fc9709a3 14662
AnnaBridge 189:f392fc9709a3 14663 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 14664 -- USB Register Masks
AnnaBridge 189:f392fc9709a3 14665 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 14666
AnnaBridge 189:f392fc9709a3 14667 /*!
AnnaBridge 189:f392fc9709a3 14668 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 189:f392fc9709a3 14669 * @{
AnnaBridge 189:f392fc9709a3 14670 */
AnnaBridge 189:f392fc9709a3 14671
AnnaBridge 189:f392fc9709a3 14672 /*! @name PERID - Peripheral ID register */
AnnaBridge 189:f392fc9709a3 14673 #define USB_PERID_ID_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 14674 #define USB_PERID_ID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14675 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
AnnaBridge 189:f392fc9709a3 14676
AnnaBridge 189:f392fc9709a3 14677 /*! @name IDCOMP - Peripheral ID Complement register */
AnnaBridge 189:f392fc9709a3 14678 #define USB_IDCOMP_NID_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 14679 #define USB_IDCOMP_NID_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14680 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
AnnaBridge 189:f392fc9709a3 14681
AnnaBridge 189:f392fc9709a3 14682 /*! @name REV - Peripheral Revision register */
AnnaBridge 189:f392fc9709a3 14683 #define USB_REV_REV_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14684 #define USB_REV_REV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14685 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
AnnaBridge 189:f392fc9709a3 14686
AnnaBridge 189:f392fc9709a3 14687 /*! @name ADDINFO - Peripheral Additional Info register */
AnnaBridge 189:f392fc9709a3 14688 #define USB_ADDINFO_IEHOST_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14689 #define USB_ADDINFO_IEHOST_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14690 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
AnnaBridge 189:f392fc9709a3 14691
AnnaBridge 189:f392fc9709a3 14692 /*! @name OTGISTAT - OTG Interrupt Status register */
AnnaBridge 189:f392fc9709a3 14693 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14694 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14695 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
AnnaBridge 189:f392fc9709a3 14696 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14697 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14698 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
AnnaBridge 189:f392fc9709a3 14699 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14700 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14701 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
AnnaBridge 189:f392fc9709a3 14702 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14703 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14704 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
AnnaBridge 189:f392fc9709a3 14705 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14706 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14707 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
AnnaBridge 189:f392fc9709a3 14708 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14709 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14710 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
AnnaBridge 189:f392fc9709a3 14711
AnnaBridge 189:f392fc9709a3 14712 /*! @name OTGICR - OTG Interrupt Control register */
AnnaBridge 189:f392fc9709a3 14713 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14714 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14715 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
AnnaBridge 189:f392fc9709a3 14716 #define USB_OTGICR_BSESSEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14717 #define USB_OTGICR_BSESSEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14718 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
AnnaBridge 189:f392fc9709a3 14719 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14720 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14721 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
AnnaBridge 189:f392fc9709a3 14722 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14723 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14724 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
AnnaBridge 189:f392fc9709a3 14725 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14726 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14727 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
AnnaBridge 189:f392fc9709a3 14728 #define USB_OTGICR_IDEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14729 #define USB_OTGICR_IDEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14730 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
AnnaBridge 189:f392fc9709a3 14731
AnnaBridge 189:f392fc9709a3 14732 /*! @name OTGSTAT - OTG Status register */
AnnaBridge 189:f392fc9709a3 14733 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14734 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14735 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
AnnaBridge 189:f392fc9709a3 14736 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14737 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14738 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
AnnaBridge 189:f392fc9709a3 14739 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14740 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14741 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
AnnaBridge 189:f392fc9709a3 14742 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14743 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14744 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
AnnaBridge 189:f392fc9709a3 14745 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14746 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14747 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
AnnaBridge 189:f392fc9709a3 14748 #define USB_OTGSTAT_ID_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14749 #define USB_OTGSTAT_ID_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14750 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
AnnaBridge 189:f392fc9709a3 14751
AnnaBridge 189:f392fc9709a3 14752 /*! @name OTGCTL - OTG Control register */
AnnaBridge 189:f392fc9709a3 14753 #define USB_OTGCTL_OTGEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14754 #define USB_OTGCTL_OTGEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14755 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
AnnaBridge 189:f392fc9709a3 14756 #define USB_OTGCTL_DMLOW_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14757 #define USB_OTGCTL_DMLOW_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14758 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
AnnaBridge 189:f392fc9709a3 14759 #define USB_OTGCTL_DPLOW_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14760 #define USB_OTGCTL_DPLOW_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14761 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
AnnaBridge 189:f392fc9709a3 14762 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14763 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14764 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
AnnaBridge 189:f392fc9709a3 14765
AnnaBridge 189:f392fc9709a3 14766 /*! @name ISTAT - Interrupt Status register */
AnnaBridge 189:f392fc9709a3 14767 #define USB_ISTAT_USBRST_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14768 #define USB_ISTAT_USBRST_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14769 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
AnnaBridge 189:f392fc9709a3 14770 #define USB_ISTAT_ERROR_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14771 #define USB_ISTAT_ERROR_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14772 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
AnnaBridge 189:f392fc9709a3 14773 #define USB_ISTAT_SOFTOK_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14774 #define USB_ISTAT_SOFTOK_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14775 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
AnnaBridge 189:f392fc9709a3 14776 #define USB_ISTAT_TOKDNE_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14777 #define USB_ISTAT_TOKDNE_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14778 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
AnnaBridge 189:f392fc9709a3 14779 #define USB_ISTAT_SLEEP_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14780 #define USB_ISTAT_SLEEP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14781 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
AnnaBridge 189:f392fc9709a3 14782 #define USB_ISTAT_RESUME_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14783 #define USB_ISTAT_RESUME_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14784 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
AnnaBridge 189:f392fc9709a3 14785 #define USB_ISTAT_ATTACH_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14786 #define USB_ISTAT_ATTACH_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14787 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
AnnaBridge 189:f392fc9709a3 14788 #define USB_ISTAT_STALL_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14789 #define USB_ISTAT_STALL_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14790 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
AnnaBridge 189:f392fc9709a3 14791
AnnaBridge 189:f392fc9709a3 14792 /*! @name INTEN - Interrupt Enable register */
AnnaBridge 189:f392fc9709a3 14793 #define USB_INTEN_USBRSTEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14794 #define USB_INTEN_USBRSTEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14795 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
AnnaBridge 189:f392fc9709a3 14796 #define USB_INTEN_ERROREN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14797 #define USB_INTEN_ERROREN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14798 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
AnnaBridge 189:f392fc9709a3 14799 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14800 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14801 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
AnnaBridge 189:f392fc9709a3 14802 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14803 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14804 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
AnnaBridge 189:f392fc9709a3 14805 #define USB_INTEN_SLEEPEN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14806 #define USB_INTEN_SLEEPEN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14807 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
AnnaBridge 189:f392fc9709a3 14808 #define USB_INTEN_RESUMEEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14809 #define USB_INTEN_RESUMEEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14810 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
AnnaBridge 189:f392fc9709a3 14811 #define USB_INTEN_ATTACHEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14812 #define USB_INTEN_ATTACHEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14813 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
AnnaBridge 189:f392fc9709a3 14814 #define USB_INTEN_STALLEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14815 #define USB_INTEN_STALLEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14816 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
AnnaBridge 189:f392fc9709a3 14817
AnnaBridge 189:f392fc9709a3 14818 /*! @name ERRSTAT - Error Interrupt Status register */
AnnaBridge 189:f392fc9709a3 14819 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14820 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14821 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
AnnaBridge 189:f392fc9709a3 14822 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14823 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14824 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
AnnaBridge 189:f392fc9709a3 14825 #define USB_ERRSTAT_CRC16_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14826 #define USB_ERRSTAT_CRC16_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14827 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
AnnaBridge 189:f392fc9709a3 14828 #define USB_ERRSTAT_DFN8_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14829 #define USB_ERRSTAT_DFN8_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14830 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
AnnaBridge 189:f392fc9709a3 14831 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14832 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14833 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
AnnaBridge 189:f392fc9709a3 14834 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14835 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14836 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
AnnaBridge 189:f392fc9709a3 14837 #define USB_ERRSTAT_OWNERR_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14838 #define USB_ERRSTAT_OWNERR_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14839 #define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK)
AnnaBridge 189:f392fc9709a3 14840 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14841 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14842 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
AnnaBridge 189:f392fc9709a3 14843
AnnaBridge 189:f392fc9709a3 14844 /*! @name ERREN - Error Interrupt Enable register */
AnnaBridge 189:f392fc9709a3 14845 #define USB_ERREN_PIDERREN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14846 #define USB_ERREN_PIDERREN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14847 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
AnnaBridge 189:f392fc9709a3 14848 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14849 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14850 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
AnnaBridge 189:f392fc9709a3 14851 #define USB_ERREN_CRC16EN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14852 #define USB_ERREN_CRC16EN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14853 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
AnnaBridge 189:f392fc9709a3 14854 #define USB_ERREN_DFN8EN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14855 #define USB_ERREN_DFN8EN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14856 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
AnnaBridge 189:f392fc9709a3 14857 #define USB_ERREN_BTOERREN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14858 #define USB_ERREN_BTOERREN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14859 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
AnnaBridge 189:f392fc9709a3 14860 #define USB_ERREN_DMAERREN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14861 #define USB_ERREN_DMAERREN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14862 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
AnnaBridge 189:f392fc9709a3 14863 #define USB_ERREN_OWNERREN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14864 #define USB_ERREN_OWNERREN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14865 #define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK)
AnnaBridge 189:f392fc9709a3 14866 #define USB_ERREN_BTSERREN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14867 #define USB_ERREN_BTSERREN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14868 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
AnnaBridge 189:f392fc9709a3 14869
AnnaBridge 189:f392fc9709a3 14870 /*! @name STAT - Status register */
AnnaBridge 189:f392fc9709a3 14871 #define USB_STAT_ODD_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14872 #define USB_STAT_ODD_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14873 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
AnnaBridge 189:f392fc9709a3 14874 #define USB_STAT_TX_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14875 #define USB_STAT_TX_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14876 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
AnnaBridge 189:f392fc9709a3 14877 #define USB_STAT_ENDP_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 14878 #define USB_STAT_ENDP_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14879 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
AnnaBridge 189:f392fc9709a3 14880
AnnaBridge 189:f392fc9709a3 14881 /*! @name CTL - Control register */
AnnaBridge 189:f392fc9709a3 14882 #define USB_CTL_USBENSOFEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14883 #define USB_CTL_USBENSOFEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14884 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
AnnaBridge 189:f392fc9709a3 14885 #define USB_CTL_ODDRST_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14886 #define USB_CTL_ODDRST_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14887 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
AnnaBridge 189:f392fc9709a3 14888 #define USB_CTL_RESUME_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14889 #define USB_CTL_RESUME_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14890 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
AnnaBridge 189:f392fc9709a3 14891 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14892 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14893 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
AnnaBridge 189:f392fc9709a3 14894 #define USB_CTL_RESET_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14895 #define USB_CTL_RESET_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14896 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
AnnaBridge 189:f392fc9709a3 14897 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14898 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14899 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
AnnaBridge 189:f392fc9709a3 14900 #define USB_CTL_SE0_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14901 #define USB_CTL_SE0_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14902 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
AnnaBridge 189:f392fc9709a3 14903 #define USB_CTL_JSTATE_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14904 #define USB_CTL_JSTATE_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14905 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
AnnaBridge 189:f392fc9709a3 14906
AnnaBridge 189:f392fc9709a3 14907 /*! @name ADDR - Address register */
AnnaBridge 189:f392fc9709a3 14908 #define USB_ADDR_ADDR_MASK (0x7FU)
AnnaBridge 189:f392fc9709a3 14909 #define USB_ADDR_ADDR_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14910 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
AnnaBridge 189:f392fc9709a3 14911 #define USB_ADDR_LSEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14912 #define USB_ADDR_LSEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14913 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
AnnaBridge 189:f392fc9709a3 14914
AnnaBridge 189:f392fc9709a3 14915 /*! @name BDTPAGE1 - BDT Page register 1 */
AnnaBridge 189:f392fc9709a3 14916 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
AnnaBridge 189:f392fc9709a3 14917 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14918 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 189:f392fc9709a3 14919
AnnaBridge 189:f392fc9709a3 14920 /*! @name FRMNUML - Frame Number register Low */
AnnaBridge 189:f392fc9709a3 14921 #define USB_FRMNUML_FRM_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14922 #define USB_FRMNUML_FRM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14923 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
AnnaBridge 189:f392fc9709a3 14924
AnnaBridge 189:f392fc9709a3 14925 /*! @name FRMNUMH - Frame Number register High */
AnnaBridge 189:f392fc9709a3 14926 #define USB_FRMNUMH_FRM_MASK (0x7U)
AnnaBridge 189:f392fc9709a3 14927 #define USB_FRMNUMH_FRM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14928 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
AnnaBridge 189:f392fc9709a3 14929
AnnaBridge 189:f392fc9709a3 14930 /*! @name TOKEN - Token register */
AnnaBridge 189:f392fc9709a3 14931 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 14932 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14933 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge 189:f392fc9709a3 14934 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
AnnaBridge 189:f392fc9709a3 14935 #define USB_TOKEN_TOKENPID_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14936 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
AnnaBridge 189:f392fc9709a3 14937
AnnaBridge 189:f392fc9709a3 14938 /*! @name SOFTHLD - SOF Threshold register */
AnnaBridge 189:f392fc9709a3 14939 #define USB_SOFTHLD_CNT_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14940 #define USB_SOFTHLD_CNT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14941 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
AnnaBridge 189:f392fc9709a3 14942
AnnaBridge 189:f392fc9709a3 14943 /*! @name BDTPAGE2 - BDT Page Register 2 */
AnnaBridge 189:f392fc9709a3 14944 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14945 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14946 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 189:f392fc9709a3 14947
AnnaBridge 189:f392fc9709a3 14948 /*! @name BDTPAGE3 - BDT Page Register 3 */
AnnaBridge 189:f392fc9709a3 14949 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 14950 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14951 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 189:f392fc9709a3 14952
AnnaBridge 189:f392fc9709a3 14953 /*! @name ENDPT - Endpoint Control register */
AnnaBridge 189:f392fc9709a3 14954 #define USB_ENDPT_EPHSHK_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 14955 #define USB_ENDPT_EPHSHK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 14956 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
AnnaBridge 189:f392fc9709a3 14957 #define USB_ENDPT_EPSTALL_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 14958 #define USB_ENDPT_EPSTALL_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 14959 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
AnnaBridge 189:f392fc9709a3 14960 #define USB_ENDPT_EPTXEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 14961 #define USB_ENDPT_EPTXEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 14962 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
AnnaBridge 189:f392fc9709a3 14963 #define USB_ENDPT_EPRXEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 14964 #define USB_ENDPT_EPRXEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 14965 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
AnnaBridge 189:f392fc9709a3 14966 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14967 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14968 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
AnnaBridge 189:f392fc9709a3 14969 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14970 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14971 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
AnnaBridge 189:f392fc9709a3 14972 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14973 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14974 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
AnnaBridge 189:f392fc9709a3 14975
AnnaBridge 189:f392fc9709a3 14976 /* The count of USB_ENDPT */
AnnaBridge 189:f392fc9709a3 14977 #define USB_ENDPT_COUNT (16U)
AnnaBridge 189:f392fc9709a3 14978
AnnaBridge 189:f392fc9709a3 14979 /*! @name USBCTRL - USB Control register */
AnnaBridge 189:f392fc9709a3 14980 #define USB_USBCTRL_UARTSEL_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14981 #define USB_USBCTRL_UARTSEL_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14982 #define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK)
AnnaBridge 189:f392fc9709a3 14983 #define USB_USBCTRL_UARTCHLS_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 14984 #define USB_USBCTRL_UARTCHLS_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 14985 #define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK)
AnnaBridge 189:f392fc9709a3 14986 #define USB_USBCTRL_PDE_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14987 #define USB_USBCTRL_PDE_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14988 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
AnnaBridge 189:f392fc9709a3 14989 #define USB_USBCTRL_SUSP_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 14990 #define USB_USBCTRL_SUSP_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 14991 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
AnnaBridge 189:f392fc9709a3 14992
AnnaBridge 189:f392fc9709a3 14993 /*! @name OBSERVE - USB OTG Observe register */
AnnaBridge 189:f392fc9709a3 14994 #define USB_OBSERVE_DMPD_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 14995 #define USB_OBSERVE_DMPD_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 14996 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
AnnaBridge 189:f392fc9709a3 14997 #define USB_OBSERVE_DPPD_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 14998 #define USB_OBSERVE_DPPD_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 14999 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
AnnaBridge 189:f392fc9709a3 15000 #define USB_OBSERVE_DPPU_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 15001 #define USB_OBSERVE_DPPU_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 15002 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
AnnaBridge 189:f392fc9709a3 15003
AnnaBridge 189:f392fc9709a3 15004 /*! @name CONTROL - USB OTG Control register */
AnnaBridge 189:f392fc9709a3 15005 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 15006 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 15007 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
AnnaBridge 189:f392fc9709a3 15008
AnnaBridge 189:f392fc9709a3 15009 /*! @name USBTRC0 - USB Transceiver Control register 0 */
AnnaBridge 189:f392fc9709a3 15010 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 15011 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15012 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
AnnaBridge 189:f392fc9709a3 15013 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 15014 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 15015 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
AnnaBridge 189:f392fc9709a3 15016 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 15017 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 15018 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
AnnaBridge 189:f392fc9709a3 15019 #define USB_USBTRC0_VREDG_DET_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 15020 #define USB_USBTRC0_VREDG_DET_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 15021 #define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK)
AnnaBridge 189:f392fc9709a3 15022 #define USB_USBTRC0_VFEDG_DET_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 15023 #define USB_USBTRC0_VFEDG_DET_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 15024 #define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK)
AnnaBridge 189:f392fc9709a3 15025 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 15026 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 15027 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
AnnaBridge 189:f392fc9709a3 15028 #define USB_USBTRC0_USBRESET_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 15029 #define USB_USBTRC0_USBRESET_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 15030 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
AnnaBridge 189:f392fc9709a3 15031
AnnaBridge 189:f392fc9709a3 15032 /*! @name USBFRMADJUST - Frame Adjust Register */
AnnaBridge 189:f392fc9709a3 15033 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
AnnaBridge 189:f392fc9709a3 15034 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15035 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge 189:f392fc9709a3 15036
AnnaBridge 189:f392fc9709a3 15037 /*! @name MISCCTRL - Miscellaneous Control register */
AnnaBridge 189:f392fc9709a3 15038 #define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 15039 #define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15040 #define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK)
AnnaBridge 189:f392fc9709a3 15041 #define USB_MISCCTRL_SOFBUSSET_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 15042 #define USB_MISCCTRL_SOFBUSSET_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 15043 #define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK)
AnnaBridge 189:f392fc9709a3 15044 #define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 15045 #define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 15046 #define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK)
AnnaBridge 189:f392fc9709a3 15047 #define USB_MISCCTRL_VREDG_EN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 15048 #define USB_MISCCTRL_VREDG_EN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 15049 #define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK)
AnnaBridge 189:f392fc9709a3 15050 #define USB_MISCCTRL_VFEDG_EN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 15051 #define USB_MISCCTRL_VFEDG_EN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 15052 #define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK)
AnnaBridge 189:f392fc9709a3 15053
AnnaBridge 189:f392fc9709a3 15054 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
AnnaBridge 189:f392fc9709a3 15055 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 15056 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 15057 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
AnnaBridge 189:f392fc9709a3 15058 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 15059 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 15060 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
AnnaBridge 189:f392fc9709a3 15061 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 15062 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 15063 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
AnnaBridge 189:f392fc9709a3 15064
AnnaBridge 189:f392fc9709a3 15065 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
AnnaBridge 189:f392fc9709a3 15066 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 15067 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15068 #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
AnnaBridge 189:f392fc9709a3 15069 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 15070 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 15071 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
AnnaBridge 189:f392fc9709a3 15072
AnnaBridge 189:f392fc9709a3 15073 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
AnnaBridge 189:f392fc9709a3 15074 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 15075 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 15076 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
AnnaBridge 189:f392fc9709a3 15077
AnnaBridge 189:f392fc9709a3 15078 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
AnnaBridge 189:f392fc9709a3 15079 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 15080 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 15081 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
AnnaBridge 189:f392fc9709a3 15082
AnnaBridge 189:f392fc9709a3 15083
AnnaBridge 189:f392fc9709a3 15084 /*!
AnnaBridge 189:f392fc9709a3 15085 * @}
AnnaBridge 189:f392fc9709a3 15086 */ /* end of group USB_Register_Masks */
AnnaBridge 189:f392fc9709a3 15087
AnnaBridge 189:f392fc9709a3 15088
AnnaBridge 189:f392fc9709a3 15089 /* USB - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 15090 /** Peripheral USB0 base address */
AnnaBridge 189:f392fc9709a3 15091 #define USB0_BASE (0x40072000u)
AnnaBridge 189:f392fc9709a3 15092 /** Peripheral USB0 base pointer */
AnnaBridge 189:f392fc9709a3 15093 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 189:f392fc9709a3 15094 /** Array initializer of USB peripheral base addresses */
AnnaBridge 189:f392fc9709a3 15095 #define USB_BASE_ADDRS { USB0_BASE }
AnnaBridge 189:f392fc9709a3 15096 /** Array initializer of USB peripheral base pointers */
AnnaBridge 189:f392fc9709a3 15097 #define USB_BASE_PTRS { USB0 }
AnnaBridge 189:f392fc9709a3 15098 /** Interrupt vectors for the USB peripheral type */
AnnaBridge 189:f392fc9709a3 15099 #define USB_IRQS { USB0_IRQn }
AnnaBridge 189:f392fc9709a3 15100
AnnaBridge 189:f392fc9709a3 15101 /*!
AnnaBridge 189:f392fc9709a3 15102 * @}
AnnaBridge 189:f392fc9709a3 15103 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 15104
AnnaBridge 189:f392fc9709a3 15105
AnnaBridge 189:f392fc9709a3 15106 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 15107 -- USBDCD Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 15108 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 15109
AnnaBridge 189:f392fc9709a3 15110 /*!
AnnaBridge 189:f392fc9709a3 15111 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 15112 * @{
AnnaBridge 189:f392fc9709a3 15113 */
AnnaBridge 189:f392fc9709a3 15114
AnnaBridge 189:f392fc9709a3 15115 /** USBDCD - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 15116 typedef struct {
AnnaBridge 189:f392fc9709a3 15117 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 15118 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 15119 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 15120 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 15121 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 15122 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 15123 union { /* offset: 0x18 */
AnnaBridge 189:f392fc9709a3 15124 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 15125 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
AnnaBridge 189:f392fc9709a3 15126 };
AnnaBridge 189:f392fc9709a3 15127 } USBDCD_Type;
AnnaBridge 189:f392fc9709a3 15128
AnnaBridge 189:f392fc9709a3 15129 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 15130 -- USBDCD Register Masks
AnnaBridge 189:f392fc9709a3 15131 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 15132
AnnaBridge 189:f392fc9709a3 15133 /*!
AnnaBridge 189:f392fc9709a3 15134 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
AnnaBridge 189:f392fc9709a3 15135 * @{
AnnaBridge 189:f392fc9709a3 15136 */
AnnaBridge 189:f392fc9709a3 15137
AnnaBridge 189:f392fc9709a3 15138 /*! @name CONTROL - Control register */
AnnaBridge 189:f392fc9709a3 15139 #define USBDCD_CONTROL_IACK_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 15140 #define USBDCD_CONTROL_IACK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15141 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
AnnaBridge 189:f392fc9709a3 15142 #define USBDCD_CONTROL_IF_MASK (0x100U)
AnnaBridge 189:f392fc9709a3 15143 #define USBDCD_CONTROL_IF_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 15144 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
AnnaBridge 189:f392fc9709a3 15145 #define USBDCD_CONTROL_IE_MASK (0x10000U)
AnnaBridge 189:f392fc9709a3 15146 #define USBDCD_CONTROL_IE_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 15147 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
AnnaBridge 189:f392fc9709a3 15148 #define USBDCD_CONTROL_BC12_MASK (0x20000U)
AnnaBridge 189:f392fc9709a3 15149 #define USBDCD_CONTROL_BC12_SHIFT (17U)
AnnaBridge 189:f392fc9709a3 15150 #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
AnnaBridge 189:f392fc9709a3 15151 #define USBDCD_CONTROL_START_MASK (0x1000000U)
AnnaBridge 189:f392fc9709a3 15152 #define USBDCD_CONTROL_START_SHIFT (24U)
AnnaBridge 189:f392fc9709a3 15153 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
AnnaBridge 189:f392fc9709a3 15154 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
AnnaBridge 189:f392fc9709a3 15155 #define USBDCD_CONTROL_SR_SHIFT (25U)
AnnaBridge 189:f392fc9709a3 15156 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
AnnaBridge 189:f392fc9709a3 15157
AnnaBridge 189:f392fc9709a3 15158 /*! @name CLOCK - Clock register */
AnnaBridge 189:f392fc9709a3 15159 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 15160 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15161 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
AnnaBridge 189:f392fc9709a3 15162 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
AnnaBridge 189:f392fc9709a3 15163 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 15164 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
AnnaBridge 189:f392fc9709a3 15165
AnnaBridge 189:f392fc9709a3 15166 /*! @name STATUS - Status register */
AnnaBridge 189:f392fc9709a3 15167 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
AnnaBridge 189:f392fc9709a3 15168 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 15169 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
AnnaBridge 189:f392fc9709a3 15170 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
AnnaBridge 189:f392fc9709a3 15171 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
AnnaBridge 189:f392fc9709a3 15172 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
AnnaBridge 189:f392fc9709a3 15173 #define USBDCD_STATUS_ERR_MASK (0x100000U)
AnnaBridge 189:f392fc9709a3 15174 #define USBDCD_STATUS_ERR_SHIFT (20U)
AnnaBridge 189:f392fc9709a3 15175 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
AnnaBridge 189:f392fc9709a3 15176 #define USBDCD_STATUS_TO_MASK (0x200000U)
AnnaBridge 189:f392fc9709a3 15177 #define USBDCD_STATUS_TO_SHIFT (21U)
AnnaBridge 189:f392fc9709a3 15178 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
AnnaBridge 189:f392fc9709a3 15179 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
AnnaBridge 189:f392fc9709a3 15180 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
AnnaBridge 189:f392fc9709a3 15181 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
AnnaBridge 189:f392fc9709a3 15182
AnnaBridge 189:f392fc9709a3 15183 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
AnnaBridge 189:f392fc9709a3 15184 #define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 15185 #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15186 #define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
AnnaBridge 189:f392fc9709a3 15187
AnnaBridge 189:f392fc9709a3 15188 /*! @name TIMER0 - TIMER0 register */
AnnaBridge 189:f392fc9709a3 15189 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
AnnaBridge 189:f392fc9709a3 15190 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15191 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
AnnaBridge 189:f392fc9709a3 15192 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
AnnaBridge 189:f392fc9709a3 15193 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 15194 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
AnnaBridge 189:f392fc9709a3 15195
AnnaBridge 189:f392fc9709a3 15196 /*! @name TIMER1 - TIMER1 register */
AnnaBridge 189:f392fc9709a3 15197 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
AnnaBridge 189:f392fc9709a3 15198 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15199 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
AnnaBridge 189:f392fc9709a3 15200 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
AnnaBridge 189:f392fc9709a3 15201 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 15202 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
AnnaBridge 189:f392fc9709a3 15203
AnnaBridge 189:f392fc9709a3 15204 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
AnnaBridge 189:f392fc9709a3 15205 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
AnnaBridge 189:f392fc9709a3 15206 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15207 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
AnnaBridge 189:f392fc9709a3 15208 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
AnnaBridge 189:f392fc9709a3 15209 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 15210 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
AnnaBridge 189:f392fc9709a3 15211
AnnaBridge 189:f392fc9709a3 15212 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
AnnaBridge 189:f392fc9709a3 15213 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
AnnaBridge 189:f392fc9709a3 15214 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15215 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
AnnaBridge 189:f392fc9709a3 15216 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
AnnaBridge 189:f392fc9709a3 15217 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
AnnaBridge 189:f392fc9709a3 15218 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
AnnaBridge 189:f392fc9709a3 15219
AnnaBridge 189:f392fc9709a3 15220
AnnaBridge 189:f392fc9709a3 15221 /*!
AnnaBridge 189:f392fc9709a3 15222 * @}
AnnaBridge 189:f392fc9709a3 15223 */ /* end of group USBDCD_Register_Masks */
AnnaBridge 189:f392fc9709a3 15224
AnnaBridge 189:f392fc9709a3 15225
AnnaBridge 189:f392fc9709a3 15226 /* USBDCD - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 15227 /** Peripheral USBDCD base address */
AnnaBridge 189:f392fc9709a3 15228 #define USBDCD_BASE (0x40035000u)
AnnaBridge 189:f392fc9709a3 15229 /** Peripheral USBDCD base pointer */
AnnaBridge 189:f392fc9709a3 15230 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
AnnaBridge 189:f392fc9709a3 15231 /** Array initializer of USBDCD peripheral base addresses */
AnnaBridge 189:f392fc9709a3 15232 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
AnnaBridge 189:f392fc9709a3 15233 /** Array initializer of USBDCD peripheral base pointers */
AnnaBridge 189:f392fc9709a3 15234 #define USBDCD_BASE_PTRS { USBDCD }
AnnaBridge 189:f392fc9709a3 15235 /** Interrupt vectors for the USBDCD peripheral type */
AnnaBridge 189:f392fc9709a3 15236 #define USBDCD_IRQS { USBDCD_IRQn }
AnnaBridge 189:f392fc9709a3 15237
AnnaBridge 189:f392fc9709a3 15238 /*!
AnnaBridge 189:f392fc9709a3 15239 * @}
AnnaBridge 189:f392fc9709a3 15240 */ /* end of group USBDCD_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 15241
AnnaBridge 189:f392fc9709a3 15242
AnnaBridge 189:f392fc9709a3 15243 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 15244 -- VREF Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 15245 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 15246
AnnaBridge 189:f392fc9709a3 15247 /*!
AnnaBridge 189:f392fc9709a3 15248 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 15249 * @{
AnnaBridge 189:f392fc9709a3 15250 */
AnnaBridge 189:f392fc9709a3 15251
AnnaBridge 189:f392fc9709a3 15252 /** VREF - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 15253 typedef struct {
AnnaBridge 189:f392fc9709a3 15254 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 15255 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
AnnaBridge 189:f392fc9709a3 15256 } VREF_Type;
AnnaBridge 189:f392fc9709a3 15257
AnnaBridge 189:f392fc9709a3 15258 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 15259 -- VREF Register Masks
AnnaBridge 189:f392fc9709a3 15260 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 15261
AnnaBridge 189:f392fc9709a3 15262 /*!
AnnaBridge 189:f392fc9709a3 15263 * @addtogroup VREF_Register_Masks VREF Register Masks
AnnaBridge 189:f392fc9709a3 15264 * @{
AnnaBridge 189:f392fc9709a3 15265 */
AnnaBridge 189:f392fc9709a3 15266
AnnaBridge 189:f392fc9709a3 15267 /*! @name TRM - VREF Trim Register */
AnnaBridge 189:f392fc9709a3 15268 #define VREF_TRM_TRIM_MASK (0x3FU)
AnnaBridge 189:f392fc9709a3 15269 #define VREF_TRM_TRIM_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15270 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
AnnaBridge 189:f392fc9709a3 15271 #define VREF_TRM_CHOPEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 15272 #define VREF_TRM_CHOPEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 15273 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
AnnaBridge 189:f392fc9709a3 15274
AnnaBridge 189:f392fc9709a3 15275 /*! @name SC - VREF Status and Control Register */
AnnaBridge 189:f392fc9709a3 15276 #define VREF_SC_MODE_LV_MASK (0x3U)
AnnaBridge 189:f392fc9709a3 15277 #define VREF_SC_MODE_LV_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15278 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
AnnaBridge 189:f392fc9709a3 15279 #define VREF_SC_VREFST_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 15280 #define VREF_SC_VREFST_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 15281 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
AnnaBridge 189:f392fc9709a3 15282 #define VREF_SC_ICOMPEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 15283 #define VREF_SC_ICOMPEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 15284 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
AnnaBridge 189:f392fc9709a3 15285 #define VREF_SC_REGEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 15286 #define VREF_SC_REGEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 15287 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
AnnaBridge 189:f392fc9709a3 15288 #define VREF_SC_VREFEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 15289 #define VREF_SC_VREFEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 15290 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
AnnaBridge 189:f392fc9709a3 15291
AnnaBridge 189:f392fc9709a3 15292
AnnaBridge 189:f392fc9709a3 15293 /*!
AnnaBridge 189:f392fc9709a3 15294 * @}
AnnaBridge 189:f392fc9709a3 15295 */ /* end of group VREF_Register_Masks */
AnnaBridge 189:f392fc9709a3 15296
AnnaBridge 189:f392fc9709a3 15297
AnnaBridge 189:f392fc9709a3 15298 /* VREF - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 15299 /** Peripheral VREF base address */
AnnaBridge 189:f392fc9709a3 15300 #define VREF_BASE (0x40074000u)
AnnaBridge 189:f392fc9709a3 15301 /** Peripheral VREF base pointer */
AnnaBridge 189:f392fc9709a3 15302 #define VREF ((VREF_Type *)VREF_BASE)
AnnaBridge 189:f392fc9709a3 15303 /** Array initializer of VREF peripheral base addresses */
AnnaBridge 189:f392fc9709a3 15304 #define VREF_BASE_ADDRS { VREF_BASE }
AnnaBridge 189:f392fc9709a3 15305 /** Array initializer of VREF peripheral base pointers */
AnnaBridge 189:f392fc9709a3 15306 #define VREF_BASE_PTRS { VREF }
AnnaBridge 189:f392fc9709a3 15307
AnnaBridge 189:f392fc9709a3 15308 /*!
AnnaBridge 189:f392fc9709a3 15309 * @}
AnnaBridge 189:f392fc9709a3 15310 */ /* end of group VREF_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 15311
AnnaBridge 189:f392fc9709a3 15312
AnnaBridge 189:f392fc9709a3 15313 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 15314 -- WDOG Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 15315 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 15316
AnnaBridge 189:f392fc9709a3 15317 /*!
AnnaBridge 189:f392fc9709a3 15318 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
AnnaBridge 189:f392fc9709a3 15319 * @{
AnnaBridge 189:f392fc9709a3 15320 */
AnnaBridge 189:f392fc9709a3 15321
AnnaBridge 189:f392fc9709a3 15322 /** WDOG - Register Layout Typedef */
AnnaBridge 189:f392fc9709a3 15323 typedef struct {
AnnaBridge 189:f392fc9709a3 15324 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
AnnaBridge 189:f392fc9709a3 15325 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
AnnaBridge 189:f392fc9709a3 15326 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
AnnaBridge 189:f392fc9709a3 15327 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
AnnaBridge 189:f392fc9709a3 15328 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
AnnaBridge 189:f392fc9709a3 15329 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
AnnaBridge 189:f392fc9709a3 15330 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
AnnaBridge 189:f392fc9709a3 15331 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
AnnaBridge 189:f392fc9709a3 15332 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
AnnaBridge 189:f392fc9709a3 15333 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
AnnaBridge 189:f392fc9709a3 15334 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
AnnaBridge 189:f392fc9709a3 15335 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
AnnaBridge 189:f392fc9709a3 15336 } WDOG_Type;
AnnaBridge 189:f392fc9709a3 15337
AnnaBridge 189:f392fc9709a3 15338 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 15339 -- WDOG Register Masks
AnnaBridge 189:f392fc9709a3 15340 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 15341
AnnaBridge 189:f392fc9709a3 15342 /*!
AnnaBridge 189:f392fc9709a3 15343 * @addtogroup WDOG_Register_Masks WDOG Register Masks
AnnaBridge 189:f392fc9709a3 15344 * @{
AnnaBridge 189:f392fc9709a3 15345 */
AnnaBridge 189:f392fc9709a3 15346
AnnaBridge 189:f392fc9709a3 15347 /*! @name STCTRLH - Watchdog Status and Control Register High */
AnnaBridge 189:f392fc9709a3 15348 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
AnnaBridge 189:f392fc9709a3 15349 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15350 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
AnnaBridge 189:f392fc9709a3 15351 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
AnnaBridge 189:f392fc9709a3 15352 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
AnnaBridge 189:f392fc9709a3 15353 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
AnnaBridge 189:f392fc9709a3 15354 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
AnnaBridge 189:f392fc9709a3 15355 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
AnnaBridge 189:f392fc9709a3 15356 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
AnnaBridge 189:f392fc9709a3 15357 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
AnnaBridge 189:f392fc9709a3 15358 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
AnnaBridge 189:f392fc9709a3 15359 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
AnnaBridge 189:f392fc9709a3 15360 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
AnnaBridge 189:f392fc9709a3 15361 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
AnnaBridge 189:f392fc9709a3 15362 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
AnnaBridge 189:f392fc9709a3 15363 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
AnnaBridge 189:f392fc9709a3 15364 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
AnnaBridge 189:f392fc9709a3 15365 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
AnnaBridge 189:f392fc9709a3 15366 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
AnnaBridge 189:f392fc9709a3 15367 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
AnnaBridge 189:f392fc9709a3 15368 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
AnnaBridge 189:f392fc9709a3 15369 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
AnnaBridge 189:f392fc9709a3 15370 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
AnnaBridge 189:f392fc9709a3 15371 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
AnnaBridge 189:f392fc9709a3 15372 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
AnnaBridge 189:f392fc9709a3 15373 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
AnnaBridge 189:f392fc9709a3 15374 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
AnnaBridge 189:f392fc9709a3 15375 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
AnnaBridge 189:f392fc9709a3 15376 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
AnnaBridge 189:f392fc9709a3 15377 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
AnnaBridge 189:f392fc9709a3 15378 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
AnnaBridge 189:f392fc9709a3 15379 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
AnnaBridge 189:f392fc9709a3 15380 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
AnnaBridge 189:f392fc9709a3 15381 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
AnnaBridge 189:f392fc9709a3 15382 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
AnnaBridge 189:f392fc9709a3 15383 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
AnnaBridge 189:f392fc9709a3 15384
AnnaBridge 189:f392fc9709a3 15385 /*! @name STCTRLL - Watchdog Status and Control Register Low */
AnnaBridge 189:f392fc9709a3 15386 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
AnnaBridge 189:f392fc9709a3 15387 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
AnnaBridge 189:f392fc9709a3 15388 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
AnnaBridge 189:f392fc9709a3 15389
AnnaBridge 189:f392fc9709a3 15390 /*! @name TOVALH - Watchdog Time-out Value Register High */
AnnaBridge 189:f392fc9709a3 15391 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15392 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15393 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
AnnaBridge 189:f392fc9709a3 15394
AnnaBridge 189:f392fc9709a3 15395 /*! @name TOVALL - Watchdog Time-out Value Register Low */
AnnaBridge 189:f392fc9709a3 15396 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15397 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15398 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
AnnaBridge 189:f392fc9709a3 15399
AnnaBridge 189:f392fc9709a3 15400 /*! @name WINH - Watchdog Window Register High */
AnnaBridge 189:f392fc9709a3 15401 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15402 #define WDOG_WINH_WINHIGH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15403 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
AnnaBridge 189:f392fc9709a3 15404
AnnaBridge 189:f392fc9709a3 15405 /*! @name WINL - Watchdog Window Register Low */
AnnaBridge 189:f392fc9709a3 15406 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15407 #define WDOG_WINL_WINLOW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15408 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
AnnaBridge 189:f392fc9709a3 15409
AnnaBridge 189:f392fc9709a3 15410 /*! @name REFRESH - Watchdog Refresh register */
AnnaBridge 189:f392fc9709a3 15411 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15412 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15413 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
AnnaBridge 189:f392fc9709a3 15414
AnnaBridge 189:f392fc9709a3 15415 /*! @name UNLOCK - Watchdog Unlock register */
AnnaBridge 189:f392fc9709a3 15416 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15417 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15418 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
AnnaBridge 189:f392fc9709a3 15419
AnnaBridge 189:f392fc9709a3 15420 /*! @name TMROUTH - Watchdog Timer Output Register High */
AnnaBridge 189:f392fc9709a3 15421 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15422 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15423 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
AnnaBridge 189:f392fc9709a3 15424
AnnaBridge 189:f392fc9709a3 15425 /*! @name TMROUTL - Watchdog Timer Output Register Low */
AnnaBridge 189:f392fc9709a3 15426 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15427 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15428 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
AnnaBridge 189:f392fc9709a3 15429
AnnaBridge 189:f392fc9709a3 15430 /*! @name RSTCNT - Watchdog Reset Count register */
AnnaBridge 189:f392fc9709a3 15431 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
AnnaBridge 189:f392fc9709a3 15432 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
AnnaBridge 189:f392fc9709a3 15433 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
AnnaBridge 189:f392fc9709a3 15434
AnnaBridge 189:f392fc9709a3 15435 /*! @name PRESC - Watchdog Prescaler register */
AnnaBridge 189:f392fc9709a3 15436 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
AnnaBridge 189:f392fc9709a3 15437 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
AnnaBridge 189:f392fc9709a3 15438 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
AnnaBridge 189:f392fc9709a3 15439
AnnaBridge 189:f392fc9709a3 15440
AnnaBridge 189:f392fc9709a3 15441 /*!
AnnaBridge 189:f392fc9709a3 15442 * @}
AnnaBridge 189:f392fc9709a3 15443 */ /* end of group WDOG_Register_Masks */
AnnaBridge 189:f392fc9709a3 15444
AnnaBridge 189:f392fc9709a3 15445
AnnaBridge 189:f392fc9709a3 15446 /* WDOG - Peripheral instance base addresses */
AnnaBridge 189:f392fc9709a3 15447 /** Peripheral WDOG base address */
AnnaBridge 189:f392fc9709a3 15448 #define WDOG_BASE (0x40052000u)
AnnaBridge 189:f392fc9709a3 15449 /** Peripheral WDOG base pointer */
AnnaBridge 189:f392fc9709a3 15450 #define WDOG ((WDOG_Type *)WDOG_BASE)
AnnaBridge 189:f392fc9709a3 15451 /** Array initializer of WDOG peripheral base addresses */
AnnaBridge 189:f392fc9709a3 15452 #define WDOG_BASE_ADDRS { WDOG_BASE }
AnnaBridge 189:f392fc9709a3 15453 /** Array initializer of WDOG peripheral base pointers */
AnnaBridge 189:f392fc9709a3 15454 #define WDOG_BASE_PTRS { WDOG }
AnnaBridge 189:f392fc9709a3 15455 /** Interrupt vectors for the WDOG peripheral type */
AnnaBridge 189:f392fc9709a3 15456 #define WDOG_IRQS { WDOG_EWM_IRQn }
AnnaBridge 189:f392fc9709a3 15457
AnnaBridge 189:f392fc9709a3 15458 /*!
AnnaBridge 189:f392fc9709a3 15459 * @}
AnnaBridge 189:f392fc9709a3 15460 */ /* end of group WDOG_Peripheral_Access_Layer */
AnnaBridge 189:f392fc9709a3 15461
AnnaBridge 189:f392fc9709a3 15462
AnnaBridge 189:f392fc9709a3 15463 /*
AnnaBridge 189:f392fc9709a3 15464 ** End of section using anonymous unions
AnnaBridge 189:f392fc9709a3 15465 */
AnnaBridge 189:f392fc9709a3 15466
AnnaBridge 189:f392fc9709a3 15467 #if defined(__ARMCC_VERSION)
AnnaBridge 189:f392fc9709a3 15468 #pragma pop
AnnaBridge 189:f392fc9709a3 15469 #elif defined(__CWCC__)
AnnaBridge 189:f392fc9709a3 15470 #pragma pop
AnnaBridge 189:f392fc9709a3 15471 #elif defined(__GNUC__)
AnnaBridge 189:f392fc9709a3 15472 /* leave anonymous unions enabled */
AnnaBridge 189:f392fc9709a3 15473 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 189:f392fc9709a3 15474 #pragma language=default
AnnaBridge 189:f392fc9709a3 15475 #else
AnnaBridge 189:f392fc9709a3 15476 #error Not supported compiler type
AnnaBridge 189:f392fc9709a3 15477 #endif
AnnaBridge 189:f392fc9709a3 15478
AnnaBridge 189:f392fc9709a3 15479 /*!
AnnaBridge 189:f392fc9709a3 15480 * @}
AnnaBridge 189:f392fc9709a3 15481 */ /* end of group Peripheral_access_layer */
AnnaBridge 189:f392fc9709a3 15482
AnnaBridge 189:f392fc9709a3 15483
AnnaBridge 189:f392fc9709a3 15484 /* ----------------------------------------------------------------------------
AnnaBridge 189:f392fc9709a3 15485 -- SDK Compatibility
AnnaBridge 189:f392fc9709a3 15486 ---------------------------------------------------------------------------- */
AnnaBridge 189:f392fc9709a3 15487
AnnaBridge 189:f392fc9709a3 15488 /*!
AnnaBridge 189:f392fc9709a3 15489 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
AnnaBridge 189:f392fc9709a3 15490 * @{
AnnaBridge 189:f392fc9709a3 15491 */
AnnaBridge 189:f392fc9709a3 15492
AnnaBridge 189:f392fc9709a3 15493 #define PIT0_IRQn PIT0CH0_IRQn
AnnaBridge 189:f392fc9709a3 15494 #define PIT1_IRQn PIT0CH1_IRQn
AnnaBridge 189:f392fc9709a3 15495 #define PIT2_IRQn PIT0CH2_IRQn
AnnaBridge 189:f392fc9709a3 15496 #define PIT3_IRQn PIT0CH3_IRQn
AnnaBridge 189:f392fc9709a3 15497 #define PIT_BASE PIT0_BASE
AnnaBridge 189:f392fc9709a3 15498 #define PIT PIT0
AnnaBridge 189:f392fc9709a3 15499 #define PIT_MCR PIT0_MCR
AnnaBridge 189:f392fc9709a3 15500 #define PIT_LDVAL0 PIT0_LDVAL0
AnnaBridge 189:f392fc9709a3 15501 #define PIT_CVAL0 PIT0_CVAL0
AnnaBridge 189:f392fc9709a3 15502 #define PIT_TCTRL0 PIT0_TCTRL0
AnnaBridge 189:f392fc9709a3 15503 #define PIT_TFLG0 PIT0_TFLG0
AnnaBridge 189:f392fc9709a3 15504 #define PIT_LDVAL1 PIT0_LDVAL1
AnnaBridge 189:f392fc9709a3 15505 #define PIT_CVAL1 PIT0_CVAL1
AnnaBridge 189:f392fc9709a3 15506 #define PIT_TCTRL1 PIT0_TCTRL1
AnnaBridge 189:f392fc9709a3 15507 #define PIT_TFLG1 PIT0_TFLG1
AnnaBridge 189:f392fc9709a3 15508 #define PIT_LDVAL2 PIT0_LDVAL2
AnnaBridge 189:f392fc9709a3 15509 #define PIT_CVAL2 PIT0_CVAL2
AnnaBridge 189:f392fc9709a3 15510 #define PIT_TCTRL2 PIT0_TCTRL2
AnnaBridge 189:f392fc9709a3 15511 #define PIT_TFLG2 PIT0_TFLG2
AnnaBridge 189:f392fc9709a3 15512 #define PIT_LDVAL3 PIT0_LDVAL3
AnnaBridge 189:f392fc9709a3 15513 #define PIT_CVAL3 PIT0_CVAL3
AnnaBridge 189:f392fc9709a3 15514 #define PIT_TCTRL3 PIT0_TCTRL3
AnnaBridge 189:f392fc9709a3 15515 #define PIT_TFLG3 PIT0_TFLG3
AnnaBridge 189:f392fc9709a3 15516 #define PIT_LDVAL(index) PIT0_LDVAL(index)
AnnaBridge 189:f392fc9709a3 15517 #define PIT_CVAL(index) PIT0_CVAL(index)
AnnaBridge 189:f392fc9709a3 15518 #define PIT_TCTRL(index) PIT0_TCTRL(index)
AnnaBridge 189:f392fc9709a3 15519 #define PIT_TFLG(index) PIT0_TFLG(index)
AnnaBridge 189:f392fc9709a3 15520 #define PIT0_IRQHandler PIT0CH0_IRQHandler
AnnaBridge 189:f392fc9709a3 15521 #define PIT1_IRQHandler PIT0CH1_IRQHandler
AnnaBridge 189:f392fc9709a3 15522 #define PIT2_IRQHandler PIT0CH2_IRQHandler
AnnaBridge 189:f392fc9709a3 15523 #define PIT3_IRQHandler PIT0CH3_IRQHandler
AnnaBridge 189:f392fc9709a3 15524 #define DSPI0 SPI0
AnnaBridge 189:f392fc9709a3 15525 #define DSPI1 SPI1
AnnaBridge 189:f392fc9709a3 15526 #define DSPI2 SPI2
AnnaBridge 189:f392fc9709a3 15527 #define DMAMUX0 DMAMUX
AnnaBridge 189:f392fc9709a3 15528
AnnaBridge 189:f392fc9709a3 15529 /*!
AnnaBridge 189:f392fc9709a3 15530 * @}
AnnaBridge 189:f392fc9709a3 15531 */ /* end of group SDK_Compatibility_Symbols */
AnnaBridge 189:f392fc9709a3 15532
AnnaBridge 189:f392fc9709a3 15533
AnnaBridge 189:f392fc9709a3 15534 #endif /* _MK82F25615_H_ */
AnnaBridge 189:f392fc9709a3 15535