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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_spi.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 189:f392fc9709a3 1 /**
AnnaBridge 189:f392fc9709a3 2 ******************************************************************************
AnnaBridge 189:f392fc9709a3 3 * @file stm32l4xx_ll_spi.h
AnnaBridge 189:f392fc9709a3 4 * @author MCD Application Team
AnnaBridge 189:f392fc9709a3 5 * @brief Header file of SPI LL module.
AnnaBridge 189:f392fc9709a3 6 ******************************************************************************
AnnaBridge 189:f392fc9709a3 7 * @attention
AnnaBridge 189:f392fc9709a3 8 *
AnnaBridge 189:f392fc9709a3 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 189:f392fc9709a3 10 *
AnnaBridge 189:f392fc9709a3 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 189:f392fc9709a3 12 * are permitted provided that the following conditions are met:
AnnaBridge 189:f392fc9709a3 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 189:f392fc9709a3 14 * this list of conditions and the following disclaimer.
AnnaBridge 189:f392fc9709a3 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 189:f392fc9709a3 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 189:f392fc9709a3 17 * and/or other materials provided with the distribution.
AnnaBridge 189:f392fc9709a3 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 189:f392fc9709a3 19 * may be used to endorse or promote products derived from this software
AnnaBridge 189:f392fc9709a3 20 * without specific prior written permission.
AnnaBridge 189:f392fc9709a3 21 *
AnnaBridge 189:f392fc9709a3 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 189:f392fc9709a3 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 189:f392fc9709a3 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 189:f392fc9709a3 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 189:f392fc9709a3 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 189:f392fc9709a3 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 189:f392fc9709a3 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 189:f392fc9709a3 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 189:f392fc9709a3 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 189:f392fc9709a3 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 189:f392fc9709a3 32 *
AnnaBridge 189:f392fc9709a3 33 ******************************************************************************
AnnaBridge 189:f392fc9709a3 34 */
AnnaBridge 189:f392fc9709a3 35
AnnaBridge 189:f392fc9709a3 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 189:f392fc9709a3 37 #ifndef __STM32L4xx_LL_SPI_H
AnnaBridge 189:f392fc9709a3 38 #define __STM32L4xx_LL_SPI_H
AnnaBridge 189:f392fc9709a3 39
AnnaBridge 189:f392fc9709a3 40 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 41 extern "C" {
AnnaBridge 189:f392fc9709a3 42 #endif
AnnaBridge 189:f392fc9709a3 43
AnnaBridge 189:f392fc9709a3 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 45 #include "stm32l4xx.h"
AnnaBridge 189:f392fc9709a3 46
AnnaBridge 189:f392fc9709a3 47 /** @addtogroup STM32L4xx_LL_Driver
AnnaBridge 189:f392fc9709a3 48 * @{
AnnaBridge 189:f392fc9709a3 49 */
AnnaBridge 189:f392fc9709a3 50
AnnaBridge 189:f392fc9709a3 51 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
AnnaBridge 189:f392fc9709a3 52
AnnaBridge 189:f392fc9709a3 53 /** @defgroup SPI_LL SPI
AnnaBridge 189:f392fc9709a3 54 * @{
AnnaBridge 189:f392fc9709a3 55 */
AnnaBridge 189:f392fc9709a3 56
AnnaBridge 189:f392fc9709a3 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 59 /* Private macros ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 60
AnnaBridge 189:f392fc9709a3 61 /* Exported types ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 62 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 189:f392fc9709a3 63 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge 189:f392fc9709a3 64 * @{
AnnaBridge 189:f392fc9709a3 65 */
AnnaBridge 189:f392fc9709a3 66
AnnaBridge 189:f392fc9709a3 67 /**
AnnaBridge 189:f392fc9709a3 68 * @brief SPI Init structures definition
AnnaBridge 189:f392fc9709a3 69 */
AnnaBridge 189:f392fc9709a3 70 typedef struct
AnnaBridge 189:f392fc9709a3 71 {
AnnaBridge 189:f392fc9709a3 72 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge 189:f392fc9709a3 73 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge 189:f392fc9709a3 74
AnnaBridge 189:f392fc9709a3 75 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge 189:f392fc9709a3 76
AnnaBridge 189:f392fc9709a3 77 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge 189:f392fc9709a3 78 This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge 189:f392fc9709a3 79
AnnaBridge 189:f392fc9709a3 80 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge 189:f392fc9709a3 81
AnnaBridge 189:f392fc9709a3 82 uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge 189:f392fc9709a3 83 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge 189:f392fc9709a3 84
AnnaBridge 189:f392fc9709a3 85 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge 189:f392fc9709a3 86
AnnaBridge 189:f392fc9709a3 87 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge 189:f392fc9709a3 88 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge 189:f392fc9709a3 89
AnnaBridge 189:f392fc9709a3 90 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge 189:f392fc9709a3 91
AnnaBridge 189:f392fc9709a3 92 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge 189:f392fc9709a3 93 This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge 189:f392fc9709a3 94
AnnaBridge 189:f392fc9709a3 95 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge 189:f392fc9709a3 96
AnnaBridge 189:f392fc9709a3 97 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge 189:f392fc9709a3 98 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge 189:f392fc9709a3 99
AnnaBridge 189:f392fc9709a3 100 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge 189:f392fc9709a3 101
AnnaBridge 189:f392fc9709a3 102 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge 189:f392fc9709a3 103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge 189:f392fc9709a3 104 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge 189:f392fc9709a3 105
AnnaBridge 189:f392fc9709a3 106 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge 189:f392fc9709a3 107
AnnaBridge 189:f392fc9709a3 108 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge 189:f392fc9709a3 109 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge 189:f392fc9709a3 110
AnnaBridge 189:f392fc9709a3 111 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge 189:f392fc9709a3 112
AnnaBridge 189:f392fc9709a3 113 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge 189:f392fc9709a3 114 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge 189:f392fc9709a3 115
AnnaBridge 189:f392fc9709a3 116 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge 189:f392fc9709a3 117
AnnaBridge 189:f392fc9709a3 118 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge 189:f392fc9709a3 119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge 189:f392fc9709a3 120
AnnaBridge 189:f392fc9709a3 121 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge 189:f392fc9709a3 122
AnnaBridge 189:f392fc9709a3 123 } LL_SPI_InitTypeDef;
AnnaBridge 189:f392fc9709a3 124
AnnaBridge 189:f392fc9709a3 125 /**
AnnaBridge 189:f392fc9709a3 126 * @}
AnnaBridge 189:f392fc9709a3 127 */
AnnaBridge 189:f392fc9709a3 128 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 189:f392fc9709a3 129
AnnaBridge 189:f392fc9709a3 130 /* Exported constants --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 131 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge 189:f392fc9709a3 132 * @{
AnnaBridge 189:f392fc9709a3 133 */
AnnaBridge 189:f392fc9709a3 134
AnnaBridge 189:f392fc9709a3 135 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 189:f392fc9709a3 136 * @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge 189:f392fc9709a3 137 * @{
AnnaBridge 189:f392fc9709a3 138 */
AnnaBridge 189:f392fc9709a3 139 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
AnnaBridge 189:f392fc9709a3 140 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
AnnaBridge 189:f392fc9709a3 141 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
AnnaBridge 189:f392fc9709a3 142 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
AnnaBridge 189:f392fc9709a3 143 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
AnnaBridge 189:f392fc9709a3 144 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
AnnaBridge 189:f392fc9709a3 145 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
AnnaBridge 189:f392fc9709a3 146 /**
AnnaBridge 189:f392fc9709a3 147 * @}
AnnaBridge 189:f392fc9709a3 148 */
AnnaBridge 189:f392fc9709a3 149
AnnaBridge 189:f392fc9709a3 150 /** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge 189:f392fc9709a3 151 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge 189:f392fc9709a3 152 * @{
AnnaBridge 189:f392fc9709a3 153 */
AnnaBridge 189:f392fc9709a3 154 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
AnnaBridge 189:f392fc9709a3 155 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
AnnaBridge 189:f392fc9709a3 156 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
AnnaBridge 189:f392fc9709a3 157 /**
AnnaBridge 189:f392fc9709a3 158 * @}
AnnaBridge 189:f392fc9709a3 159 */
AnnaBridge 189:f392fc9709a3 160
AnnaBridge 189:f392fc9709a3 161 /** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge 189:f392fc9709a3 162 * @{
AnnaBridge 189:f392fc9709a3 163 */
AnnaBridge 189:f392fc9709a3 164 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
AnnaBridge 189:f392fc9709a3 165 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
AnnaBridge 189:f392fc9709a3 166 /**
AnnaBridge 189:f392fc9709a3 167 * @}
AnnaBridge 189:f392fc9709a3 168 */
AnnaBridge 189:f392fc9709a3 169
AnnaBridge 189:f392fc9709a3 170 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge 189:f392fc9709a3 171 * @{
AnnaBridge 189:f392fc9709a3 172 */
AnnaBridge 189:f392fc9709a3 173 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
AnnaBridge 189:f392fc9709a3 174 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
AnnaBridge 189:f392fc9709a3 175 /**
AnnaBridge 189:f392fc9709a3 176 * @}
AnnaBridge 189:f392fc9709a3 177 */
AnnaBridge 189:f392fc9709a3 178
AnnaBridge 189:f392fc9709a3 179 /** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge 189:f392fc9709a3 180 * @{
AnnaBridge 189:f392fc9709a3 181 */
AnnaBridge 189:f392fc9709a3 182 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
AnnaBridge 189:f392fc9709a3 183 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
AnnaBridge 189:f392fc9709a3 184 /**
AnnaBridge 189:f392fc9709a3 185 * @}
AnnaBridge 189:f392fc9709a3 186 */
AnnaBridge 189:f392fc9709a3 187
AnnaBridge 189:f392fc9709a3 188 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge 189:f392fc9709a3 189 * @{
AnnaBridge 189:f392fc9709a3 190 */
AnnaBridge 189:f392fc9709a3 191 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
AnnaBridge 189:f392fc9709a3 192 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
AnnaBridge 189:f392fc9709a3 193 /**
AnnaBridge 189:f392fc9709a3 194 * @}
AnnaBridge 189:f392fc9709a3 195 */
AnnaBridge 189:f392fc9709a3 196
AnnaBridge 189:f392fc9709a3 197 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge 189:f392fc9709a3 198 * @{
AnnaBridge 189:f392fc9709a3 199 */
AnnaBridge 189:f392fc9709a3 200 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
AnnaBridge 189:f392fc9709a3 201 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
AnnaBridge 189:f392fc9709a3 202 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
AnnaBridge 189:f392fc9709a3 203 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
AnnaBridge 189:f392fc9709a3 204 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
AnnaBridge 189:f392fc9709a3 205 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
AnnaBridge 189:f392fc9709a3 206 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
AnnaBridge 189:f392fc9709a3 207 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
AnnaBridge 189:f392fc9709a3 208 /**
AnnaBridge 189:f392fc9709a3 209 * @}
AnnaBridge 189:f392fc9709a3 210 */
AnnaBridge 189:f392fc9709a3 211
AnnaBridge 189:f392fc9709a3 212 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge 189:f392fc9709a3 213 * @{
AnnaBridge 189:f392fc9709a3 214 */
AnnaBridge 189:f392fc9709a3 215 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
AnnaBridge 189:f392fc9709a3 216 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
AnnaBridge 189:f392fc9709a3 217 /**
AnnaBridge 189:f392fc9709a3 218 * @}
AnnaBridge 189:f392fc9709a3 219 */
AnnaBridge 189:f392fc9709a3 220
AnnaBridge 189:f392fc9709a3 221 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge 189:f392fc9709a3 222 * @{
AnnaBridge 189:f392fc9709a3 223 */
AnnaBridge 189:f392fc9709a3 224 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
AnnaBridge 189:f392fc9709a3 225 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
AnnaBridge 189:f392fc9709a3 226 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
AnnaBridge 189:f392fc9709a3 227 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
AnnaBridge 189:f392fc9709a3 228 /**
AnnaBridge 189:f392fc9709a3 229 * @}
AnnaBridge 189:f392fc9709a3 230 */
AnnaBridge 189:f392fc9709a3 231
AnnaBridge 189:f392fc9709a3 232 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge 189:f392fc9709a3 233 * @{
AnnaBridge 189:f392fc9709a3 234 */
AnnaBridge 189:f392fc9709a3 235 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
AnnaBridge 189:f392fc9709a3 236 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
AnnaBridge 189:f392fc9709a3 237 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
AnnaBridge 189:f392fc9709a3 238 /**
AnnaBridge 189:f392fc9709a3 239 * @}
AnnaBridge 189:f392fc9709a3 240 */
AnnaBridge 189:f392fc9709a3 241
AnnaBridge 189:f392fc9709a3 242 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge 189:f392fc9709a3 243 * @{
AnnaBridge 189:f392fc9709a3 244 */
AnnaBridge 189:f392fc9709a3 245 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
AnnaBridge 189:f392fc9709a3 246 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
AnnaBridge 189:f392fc9709a3 247 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
AnnaBridge 189:f392fc9709a3 248 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
AnnaBridge 189:f392fc9709a3 249 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
AnnaBridge 189:f392fc9709a3 250 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
AnnaBridge 189:f392fc9709a3 251 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
AnnaBridge 189:f392fc9709a3 252 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
AnnaBridge 189:f392fc9709a3 253 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
AnnaBridge 189:f392fc9709a3 254 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
AnnaBridge 189:f392fc9709a3 255 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
AnnaBridge 189:f392fc9709a3 256 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
AnnaBridge 189:f392fc9709a3 257 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
AnnaBridge 189:f392fc9709a3 258 /**
AnnaBridge 189:f392fc9709a3 259 * @}
AnnaBridge 189:f392fc9709a3 260 */
AnnaBridge 189:f392fc9709a3 261 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 189:f392fc9709a3 262
AnnaBridge 189:f392fc9709a3 263 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge 189:f392fc9709a3 264 * @{
AnnaBridge 189:f392fc9709a3 265 */
AnnaBridge 189:f392fc9709a3 266 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
AnnaBridge 189:f392fc9709a3 267 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
AnnaBridge 189:f392fc9709a3 268 /**
AnnaBridge 189:f392fc9709a3 269 * @}
AnnaBridge 189:f392fc9709a3 270 */
AnnaBridge 189:f392fc9709a3 271 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 189:f392fc9709a3 272
AnnaBridge 189:f392fc9709a3 273 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
AnnaBridge 189:f392fc9709a3 274 * @{
AnnaBridge 189:f392fc9709a3 275 */
AnnaBridge 189:f392fc9709a3 276 #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
AnnaBridge 189:f392fc9709a3 277 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
AnnaBridge 189:f392fc9709a3 278 /**
AnnaBridge 189:f392fc9709a3 279 * @}
AnnaBridge 189:f392fc9709a3 280 */
AnnaBridge 189:f392fc9709a3 281
AnnaBridge 189:f392fc9709a3 282 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
AnnaBridge 189:f392fc9709a3 283 * @{
AnnaBridge 189:f392fc9709a3 284 */
AnnaBridge 189:f392fc9709a3 285 #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
AnnaBridge 189:f392fc9709a3 286 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
AnnaBridge 189:f392fc9709a3 287 /**
AnnaBridge 189:f392fc9709a3 288 * @}
AnnaBridge 189:f392fc9709a3 289 */
AnnaBridge 189:f392fc9709a3 290
AnnaBridge 189:f392fc9709a3 291 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
AnnaBridge 189:f392fc9709a3 292 * @{
AnnaBridge 189:f392fc9709a3 293 */
AnnaBridge 189:f392fc9709a3 294 #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
AnnaBridge 189:f392fc9709a3 295 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
AnnaBridge 189:f392fc9709a3 296 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
AnnaBridge 189:f392fc9709a3 297 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
AnnaBridge 189:f392fc9709a3 298 /**
AnnaBridge 189:f392fc9709a3 299 * @}
AnnaBridge 189:f392fc9709a3 300 */
AnnaBridge 189:f392fc9709a3 301
AnnaBridge 189:f392fc9709a3 302 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
AnnaBridge 189:f392fc9709a3 303 * @{
AnnaBridge 189:f392fc9709a3 304 */
AnnaBridge 189:f392fc9709a3 305 #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
AnnaBridge 189:f392fc9709a3 306 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
AnnaBridge 189:f392fc9709a3 307 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
AnnaBridge 189:f392fc9709a3 308 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
AnnaBridge 189:f392fc9709a3 309 /**
AnnaBridge 189:f392fc9709a3 310 * @}
AnnaBridge 189:f392fc9709a3 311 */
AnnaBridge 189:f392fc9709a3 312
AnnaBridge 189:f392fc9709a3 313 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
AnnaBridge 189:f392fc9709a3 314 * @{
AnnaBridge 189:f392fc9709a3 315 */
AnnaBridge 189:f392fc9709a3 316 #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
AnnaBridge 189:f392fc9709a3 317 #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
AnnaBridge 189:f392fc9709a3 318
AnnaBridge 189:f392fc9709a3 319 /**
AnnaBridge 189:f392fc9709a3 320 * @}
AnnaBridge 189:f392fc9709a3 321 */
AnnaBridge 189:f392fc9709a3 322
AnnaBridge 189:f392fc9709a3 323 /**
AnnaBridge 189:f392fc9709a3 324 * @}
AnnaBridge 189:f392fc9709a3 325 */
AnnaBridge 189:f392fc9709a3 326
AnnaBridge 189:f392fc9709a3 327 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 328 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge 189:f392fc9709a3 329 * @{
AnnaBridge 189:f392fc9709a3 330 */
AnnaBridge 189:f392fc9709a3 331
AnnaBridge 189:f392fc9709a3 332 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 189:f392fc9709a3 333 * @{
AnnaBridge 189:f392fc9709a3 334 */
AnnaBridge 189:f392fc9709a3 335
AnnaBridge 189:f392fc9709a3 336 /**
AnnaBridge 189:f392fc9709a3 337 * @brief Write a value in SPI register
AnnaBridge 189:f392fc9709a3 338 * @param __INSTANCE__ SPI Instance
AnnaBridge 189:f392fc9709a3 339 * @param __REG__ Register to be written
AnnaBridge 189:f392fc9709a3 340 * @param __VALUE__ Value to be written in the register
AnnaBridge 189:f392fc9709a3 341 * @retval None
AnnaBridge 189:f392fc9709a3 342 */
AnnaBridge 189:f392fc9709a3 343 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 189:f392fc9709a3 344
AnnaBridge 189:f392fc9709a3 345 /**
AnnaBridge 189:f392fc9709a3 346 * @brief Read a value in SPI register
AnnaBridge 189:f392fc9709a3 347 * @param __INSTANCE__ SPI Instance
AnnaBridge 189:f392fc9709a3 348 * @param __REG__ Register to be read
AnnaBridge 189:f392fc9709a3 349 * @retval Register value
AnnaBridge 189:f392fc9709a3 350 */
AnnaBridge 189:f392fc9709a3 351 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 189:f392fc9709a3 352 /**
AnnaBridge 189:f392fc9709a3 353 * @}
AnnaBridge 189:f392fc9709a3 354 */
AnnaBridge 189:f392fc9709a3 355
AnnaBridge 189:f392fc9709a3 356 /**
AnnaBridge 189:f392fc9709a3 357 * @}
AnnaBridge 189:f392fc9709a3 358 */
AnnaBridge 189:f392fc9709a3 359
AnnaBridge 189:f392fc9709a3 360 /* Exported functions --------------------------------------------------------*/
AnnaBridge 189:f392fc9709a3 361 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge 189:f392fc9709a3 362 * @{
AnnaBridge 189:f392fc9709a3 363 */
AnnaBridge 189:f392fc9709a3 364
AnnaBridge 189:f392fc9709a3 365 /** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge 189:f392fc9709a3 366 * @{
AnnaBridge 189:f392fc9709a3 367 */
AnnaBridge 189:f392fc9709a3 368
AnnaBridge 189:f392fc9709a3 369 /**
AnnaBridge 189:f392fc9709a3 370 * @brief Enable SPI peripheral
AnnaBridge 189:f392fc9709a3 371 * @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge 189:f392fc9709a3 372 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 373 * @retval None
AnnaBridge 189:f392fc9709a3 374 */
AnnaBridge 189:f392fc9709a3 375 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 376 {
AnnaBridge 189:f392fc9709a3 377 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge 189:f392fc9709a3 378 }
AnnaBridge 189:f392fc9709a3 379
AnnaBridge 189:f392fc9709a3 380 /**
AnnaBridge 189:f392fc9709a3 381 * @brief Disable SPI peripheral
AnnaBridge 189:f392fc9709a3 382 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge 189:f392fc9709a3 383 * @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge 189:f392fc9709a3 384 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 385 * @retval None
AnnaBridge 189:f392fc9709a3 386 */
AnnaBridge 189:f392fc9709a3 387 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 388 {
AnnaBridge 189:f392fc9709a3 389 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge 189:f392fc9709a3 390 }
AnnaBridge 189:f392fc9709a3 391
AnnaBridge 189:f392fc9709a3 392 /**
AnnaBridge 189:f392fc9709a3 393 * @brief Check if SPI peripheral is enabled
AnnaBridge 189:f392fc9709a3 394 * @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge 189:f392fc9709a3 395 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 396 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 397 */
AnnaBridge 189:f392fc9709a3 398 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 399 {
AnnaBridge 189:f392fc9709a3 400 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge 189:f392fc9709a3 401 }
AnnaBridge 189:f392fc9709a3 402
AnnaBridge 189:f392fc9709a3 403 /**
AnnaBridge 189:f392fc9709a3 404 * @brief Set SPI operation mode to Master or Slave
AnnaBridge 189:f392fc9709a3 405 * @note This bit should not be changed when communication is ongoing.
AnnaBridge 189:f392fc9709a3 406 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge 189:f392fc9709a3 407 * CR1 SSI LL_SPI_SetMode
AnnaBridge 189:f392fc9709a3 408 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 409 * @param Mode This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 410 * @arg @ref LL_SPI_MODE_MASTER
AnnaBridge 189:f392fc9709a3 411 * @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge 189:f392fc9709a3 412 * @retval None
AnnaBridge 189:f392fc9709a3 413 */
AnnaBridge 189:f392fc9709a3 414 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge 189:f392fc9709a3 415 {
AnnaBridge 189:f392fc9709a3 416 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
AnnaBridge 189:f392fc9709a3 417 }
AnnaBridge 189:f392fc9709a3 418
AnnaBridge 189:f392fc9709a3 419 /**
AnnaBridge 189:f392fc9709a3 420 * @brief Get SPI operation mode (Master or Slave)
AnnaBridge 189:f392fc9709a3 421 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge 189:f392fc9709a3 422 * CR1 SSI LL_SPI_GetMode
AnnaBridge 189:f392fc9709a3 423 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 424 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 425 * @arg @ref LL_SPI_MODE_MASTER
AnnaBridge 189:f392fc9709a3 426 * @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge 189:f392fc9709a3 427 */
AnnaBridge 189:f392fc9709a3 428 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 429 {
AnnaBridge 189:f392fc9709a3 430 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
AnnaBridge 189:f392fc9709a3 431 }
AnnaBridge 189:f392fc9709a3 432
AnnaBridge 189:f392fc9709a3 433 /**
AnnaBridge 189:f392fc9709a3 434 * @brief Set serial protocol used
AnnaBridge 189:f392fc9709a3 435 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 189:f392fc9709a3 436 * @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge 189:f392fc9709a3 437 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 438 * @param Standard This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 439 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge 189:f392fc9709a3 440 * @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge 189:f392fc9709a3 441 * @retval None
AnnaBridge 189:f392fc9709a3 442 */
AnnaBridge 189:f392fc9709a3 443 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge 189:f392fc9709a3 444 {
AnnaBridge 189:f392fc9709a3 445 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge 189:f392fc9709a3 446 }
AnnaBridge 189:f392fc9709a3 447
AnnaBridge 189:f392fc9709a3 448 /**
AnnaBridge 189:f392fc9709a3 449 * @brief Get serial protocol used
AnnaBridge 189:f392fc9709a3 450 * @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge 189:f392fc9709a3 451 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 452 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 453 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge 189:f392fc9709a3 454 * @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge 189:f392fc9709a3 455 */
AnnaBridge 189:f392fc9709a3 456 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 457 {
AnnaBridge 189:f392fc9709a3 458 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge 189:f392fc9709a3 459 }
AnnaBridge 189:f392fc9709a3 460
AnnaBridge 189:f392fc9709a3 461 /**
AnnaBridge 189:f392fc9709a3 462 * @brief Set clock phase
AnnaBridge 189:f392fc9709a3 463 * @note This bit should not be changed when communication is ongoing.
AnnaBridge 189:f392fc9709a3 464 * This bit is not used in SPI TI mode.
AnnaBridge 189:f392fc9709a3 465 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge 189:f392fc9709a3 466 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 467 * @param ClockPhase This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 468 * @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge 189:f392fc9709a3 469 * @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge 189:f392fc9709a3 470 * @retval None
AnnaBridge 189:f392fc9709a3 471 */
AnnaBridge 189:f392fc9709a3 472 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge 189:f392fc9709a3 473 {
AnnaBridge 189:f392fc9709a3 474 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge 189:f392fc9709a3 475 }
AnnaBridge 189:f392fc9709a3 476
AnnaBridge 189:f392fc9709a3 477 /**
AnnaBridge 189:f392fc9709a3 478 * @brief Get clock phase
AnnaBridge 189:f392fc9709a3 479 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge 189:f392fc9709a3 480 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 481 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 482 * @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge 189:f392fc9709a3 483 * @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge 189:f392fc9709a3 484 */
AnnaBridge 189:f392fc9709a3 485 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 486 {
AnnaBridge 189:f392fc9709a3 487 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge 189:f392fc9709a3 488 }
AnnaBridge 189:f392fc9709a3 489
AnnaBridge 189:f392fc9709a3 490 /**
AnnaBridge 189:f392fc9709a3 491 * @brief Set clock polarity
AnnaBridge 189:f392fc9709a3 492 * @note This bit should not be changed when communication is ongoing.
AnnaBridge 189:f392fc9709a3 493 * This bit is not used in SPI TI mode.
AnnaBridge 189:f392fc9709a3 494 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge 189:f392fc9709a3 495 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 496 * @param ClockPolarity This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 497 * @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge 189:f392fc9709a3 498 * @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge 189:f392fc9709a3 499 * @retval None
AnnaBridge 189:f392fc9709a3 500 */
AnnaBridge 189:f392fc9709a3 501 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge 189:f392fc9709a3 502 {
AnnaBridge 189:f392fc9709a3 503 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge 189:f392fc9709a3 504 }
AnnaBridge 189:f392fc9709a3 505
AnnaBridge 189:f392fc9709a3 506 /**
AnnaBridge 189:f392fc9709a3 507 * @brief Get clock polarity
AnnaBridge 189:f392fc9709a3 508 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge 189:f392fc9709a3 509 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 510 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 511 * @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge 189:f392fc9709a3 512 * @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge 189:f392fc9709a3 513 */
AnnaBridge 189:f392fc9709a3 514 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 515 {
AnnaBridge 189:f392fc9709a3 516 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge 189:f392fc9709a3 517 }
AnnaBridge 189:f392fc9709a3 518
AnnaBridge 189:f392fc9709a3 519 /**
AnnaBridge 189:f392fc9709a3 520 * @brief Set baud rate prescaler
AnnaBridge 189:f392fc9709a3 521 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge 189:f392fc9709a3 522 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge 189:f392fc9709a3 523 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 524 * @param BaudRate This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 525 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge 189:f392fc9709a3 526 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge 189:f392fc9709a3 527 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge 189:f392fc9709a3 528 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge 189:f392fc9709a3 529 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge 189:f392fc9709a3 530 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge 189:f392fc9709a3 531 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge 189:f392fc9709a3 532 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge 189:f392fc9709a3 533 * @retval None
AnnaBridge 189:f392fc9709a3 534 */
AnnaBridge 189:f392fc9709a3 535 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge 189:f392fc9709a3 536 {
AnnaBridge 189:f392fc9709a3 537 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge 189:f392fc9709a3 538 }
AnnaBridge 189:f392fc9709a3 539
AnnaBridge 189:f392fc9709a3 540 /**
AnnaBridge 189:f392fc9709a3 541 * @brief Get baud rate prescaler
AnnaBridge 189:f392fc9709a3 542 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge 189:f392fc9709a3 543 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 544 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 545 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge 189:f392fc9709a3 546 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge 189:f392fc9709a3 547 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge 189:f392fc9709a3 548 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge 189:f392fc9709a3 549 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge 189:f392fc9709a3 550 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge 189:f392fc9709a3 551 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge 189:f392fc9709a3 552 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge 189:f392fc9709a3 553 */
AnnaBridge 189:f392fc9709a3 554 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 555 {
AnnaBridge 189:f392fc9709a3 556 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge 189:f392fc9709a3 557 }
AnnaBridge 189:f392fc9709a3 558
AnnaBridge 189:f392fc9709a3 559 /**
AnnaBridge 189:f392fc9709a3 560 * @brief Set transfer bit order
AnnaBridge 189:f392fc9709a3 561 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge 189:f392fc9709a3 562 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge 189:f392fc9709a3 563 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 564 * @param BitOrder This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 565 * @arg @ref LL_SPI_LSB_FIRST
AnnaBridge 189:f392fc9709a3 566 * @arg @ref LL_SPI_MSB_FIRST
AnnaBridge 189:f392fc9709a3 567 * @retval None
AnnaBridge 189:f392fc9709a3 568 */
AnnaBridge 189:f392fc9709a3 569 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge 189:f392fc9709a3 570 {
AnnaBridge 189:f392fc9709a3 571 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge 189:f392fc9709a3 572 }
AnnaBridge 189:f392fc9709a3 573
AnnaBridge 189:f392fc9709a3 574 /**
AnnaBridge 189:f392fc9709a3 575 * @brief Get transfer bit order
AnnaBridge 189:f392fc9709a3 576 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge 189:f392fc9709a3 577 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 578 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 579 * @arg @ref LL_SPI_LSB_FIRST
AnnaBridge 189:f392fc9709a3 580 * @arg @ref LL_SPI_MSB_FIRST
AnnaBridge 189:f392fc9709a3 581 */
AnnaBridge 189:f392fc9709a3 582 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 583 {
AnnaBridge 189:f392fc9709a3 584 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge 189:f392fc9709a3 585 }
AnnaBridge 189:f392fc9709a3 586
AnnaBridge 189:f392fc9709a3 587 /**
AnnaBridge 189:f392fc9709a3 588 * @brief Set transfer direction mode
AnnaBridge 189:f392fc9709a3 589 * @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge 189:f392fc9709a3 590 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge 189:f392fc9709a3 591 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge 189:f392fc9709a3 592 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge 189:f392fc9709a3 593 * CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge 189:f392fc9709a3 594 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 595 * @param TransferDirection This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 596 * @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge 189:f392fc9709a3 597 * @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge 189:f392fc9709a3 598 * @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge 189:f392fc9709a3 599 * @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge 189:f392fc9709a3 600 * @retval None
AnnaBridge 189:f392fc9709a3 601 */
AnnaBridge 189:f392fc9709a3 602 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge 189:f392fc9709a3 603 {
AnnaBridge 189:f392fc9709a3 604 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge 189:f392fc9709a3 605 }
AnnaBridge 189:f392fc9709a3 606
AnnaBridge 189:f392fc9709a3 607 /**
AnnaBridge 189:f392fc9709a3 608 * @brief Get transfer direction mode
AnnaBridge 189:f392fc9709a3 609 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge 189:f392fc9709a3 610 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge 189:f392fc9709a3 611 * CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge 189:f392fc9709a3 612 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 613 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 614 * @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge 189:f392fc9709a3 615 * @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge 189:f392fc9709a3 616 * @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge 189:f392fc9709a3 617 * @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge 189:f392fc9709a3 618 */
AnnaBridge 189:f392fc9709a3 619 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 620 {
AnnaBridge 189:f392fc9709a3 621 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
AnnaBridge 189:f392fc9709a3 622 }
AnnaBridge 189:f392fc9709a3 623
AnnaBridge 189:f392fc9709a3 624 /**
AnnaBridge 189:f392fc9709a3 625 * @brief Set frame data width
AnnaBridge 189:f392fc9709a3 626 * @rmtoll CR2 DS LL_SPI_SetDataWidth
AnnaBridge 189:f392fc9709a3 627 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 628 * @param DataWidth This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 629 * @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge 189:f392fc9709a3 630 * @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge 189:f392fc9709a3 631 * @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge 189:f392fc9709a3 632 * @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge 189:f392fc9709a3 633 * @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge 189:f392fc9709a3 634 * @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge 189:f392fc9709a3 635 * @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge 189:f392fc9709a3 636 * @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge 189:f392fc9709a3 637 * @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge 189:f392fc9709a3 638 * @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge 189:f392fc9709a3 639 * @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge 189:f392fc9709a3 640 * @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge 189:f392fc9709a3 641 * @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge 189:f392fc9709a3 642 * @retval None
AnnaBridge 189:f392fc9709a3 643 */
AnnaBridge 189:f392fc9709a3 644 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge 189:f392fc9709a3 645 {
AnnaBridge 189:f392fc9709a3 646 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
AnnaBridge 189:f392fc9709a3 647 }
AnnaBridge 189:f392fc9709a3 648
AnnaBridge 189:f392fc9709a3 649 /**
AnnaBridge 189:f392fc9709a3 650 * @brief Get frame data width
AnnaBridge 189:f392fc9709a3 651 * @rmtoll CR2 DS LL_SPI_GetDataWidth
AnnaBridge 189:f392fc9709a3 652 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 653 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 654 * @arg @ref LL_SPI_DATAWIDTH_4BIT
AnnaBridge 189:f392fc9709a3 655 * @arg @ref LL_SPI_DATAWIDTH_5BIT
AnnaBridge 189:f392fc9709a3 656 * @arg @ref LL_SPI_DATAWIDTH_6BIT
AnnaBridge 189:f392fc9709a3 657 * @arg @ref LL_SPI_DATAWIDTH_7BIT
AnnaBridge 189:f392fc9709a3 658 * @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge 189:f392fc9709a3 659 * @arg @ref LL_SPI_DATAWIDTH_9BIT
AnnaBridge 189:f392fc9709a3 660 * @arg @ref LL_SPI_DATAWIDTH_10BIT
AnnaBridge 189:f392fc9709a3 661 * @arg @ref LL_SPI_DATAWIDTH_11BIT
AnnaBridge 189:f392fc9709a3 662 * @arg @ref LL_SPI_DATAWIDTH_12BIT
AnnaBridge 189:f392fc9709a3 663 * @arg @ref LL_SPI_DATAWIDTH_13BIT
AnnaBridge 189:f392fc9709a3 664 * @arg @ref LL_SPI_DATAWIDTH_14BIT
AnnaBridge 189:f392fc9709a3 665 * @arg @ref LL_SPI_DATAWIDTH_15BIT
AnnaBridge 189:f392fc9709a3 666 * @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge 189:f392fc9709a3 667 */
AnnaBridge 189:f392fc9709a3 668 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 669 {
AnnaBridge 189:f392fc9709a3 670 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
AnnaBridge 189:f392fc9709a3 671 }
AnnaBridge 189:f392fc9709a3 672
AnnaBridge 189:f392fc9709a3 673 /**
AnnaBridge 189:f392fc9709a3 674 * @brief Set threshold of RXFIFO that triggers an RXNE event
AnnaBridge 189:f392fc9709a3 675 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
AnnaBridge 189:f392fc9709a3 676 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 677 * @param Threshold This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 678 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge 189:f392fc9709a3 679 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge 189:f392fc9709a3 680 * @retval None
AnnaBridge 189:f392fc9709a3 681 */
AnnaBridge 189:f392fc9709a3 682 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
AnnaBridge 189:f392fc9709a3 683 {
AnnaBridge 189:f392fc9709a3 684 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
AnnaBridge 189:f392fc9709a3 685 }
AnnaBridge 189:f392fc9709a3 686
AnnaBridge 189:f392fc9709a3 687 /**
AnnaBridge 189:f392fc9709a3 688 * @brief Get threshold of RXFIFO that triggers an RXNE event
AnnaBridge 189:f392fc9709a3 689 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
AnnaBridge 189:f392fc9709a3 690 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 691 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 692 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
AnnaBridge 189:f392fc9709a3 693 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
AnnaBridge 189:f392fc9709a3 694 */
AnnaBridge 189:f392fc9709a3 695 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 696 {
AnnaBridge 189:f392fc9709a3 697 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
AnnaBridge 189:f392fc9709a3 698 }
AnnaBridge 189:f392fc9709a3 699
AnnaBridge 189:f392fc9709a3 700 /**
AnnaBridge 189:f392fc9709a3 701 * @}
AnnaBridge 189:f392fc9709a3 702 */
AnnaBridge 189:f392fc9709a3 703
AnnaBridge 189:f392fc9709a3 704 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge 189:f392fc9709a3 705 * @{
AnnaBridge 189:f392fc9709a3 706 */
AnnaBridge 189:f392fc9709a3 707
AnnaBridge 189:f392fc9709a3 708 /**
AnnaBridge 189:f392fc9709a3 709 * @brief Enable CRC
AnnaBridge 189:f392fc9709a3 710 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 189:f392fc9709a3 711 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge 189:f392fc9709a3 712 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 713 * @retval None
AnnaBridge 189:f392fc9709a3 714 */
AnnaBridge 189:f392fc9709a3 715 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 716 {
AnnaBridge 189:f392fc9709a3 717 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge 189:f392fc9709a3 718 }
AnnaBridge 189:f392fc9709a3 719
AnnaBridge 189:f392fc9709a3 720 /**
AnnaBridge 189:f392fc9709a3 721 * @brief Disable CRC
AnnaBridge 189:f392fc9709a3 722 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 189:f392fc9709a3 723 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge 189:f392fc9709a3 724 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 725 * @retval None
AnnaBridge 189:f392fc9709a3 726 */
AnnaBridge 189:f392fc9709a3 727 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 728 {
AnnaBridge 189:f392fc9709a3 729 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge 189:f392fc9709a3 730 }
AnnaBridge 189:f392fc9709a3 731
AnnaBridge 189:f392fc9709a3 732 /**
AnnaBridge 189:f392fc9709a3 733 * @brief Check if CRC is enabled
AnnaBridge 189:f392fc9709a3 734 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 189:f392fc9709a3 735 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge 189:f392fc9709a3 736 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 737 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 738 */
AnnaBridge 189:f392fc9709a3 739 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 740 {
AnnaBridge 189:f392fc9709a3 741 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge 189:f392fc9709a3 742 }
AnnaBridge 189:f392fc9709a3 743
AnnaBridge 189:f392fc9709a3 744 /**
AnnaBridge 189:f392fc9709a3 745 * @brief Set CRC Length
AnnaBridge 189:f392fc9709a3 746 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge 189:f392fc9709a3 747 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
AnnaBridge 189:f392fc9709a3 748 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 749 * @param CRCLength This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 750 * @arg @ref LL_SPI_CRC_8BIT
AnnaBridge 189:f392fc9709a3 751 * @arg @ref LL_SPI_CRC_16BIT
AnnaBridge 189:f392fc9709a3 752 * @retval None
AnnaBridge 189:f392fc9709a3 753 */
AnnaBridge 189:f392fc9709a3 754 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
AnnaBridge 189:f392fc9709a3 755 {
AnnaBridge 189:f392fc9709a3 756 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
AnnaBridge 189:f392fc9709a3 757 }
AnnaBridge 189:f392fc9709a3 758
AnnaBridge 189:f392fc9709a3 759 /**
AnnaBridge 189:f392fc9709a3 760 * @brief Get CRC Length
AnnaBridge 189:f392fc9709a3 761 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
AnnaBridge 189:f392fc9709a3 762 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 763 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 764 * @arg @ref LL_SPI_CRC_8BIT
AnnaBridge 189:f392fc9709a3 765 * @arg @ref LL_SPI_CRC_16BIT
AnnaBridge 189:f392fc9709a3 766 */
AnnaBridge 189:f392fc9709a3 767 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 768 {
AnnaBridge 189:f392fc9709a3 769 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
AnnaBridge 189:f392fc9709a3 770 }
AnnaBridge 189:f392fc9709a3 771
AnnaBridge 189:f392fc9709a3 772 /**
AnnaBridge 189:f392fc9709a3 773 * @brief Set CRCNext to transfer CRC on the line
AnnaBridge 189:f392fc9709a3 774 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge 189:f392fc9709a3 775 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge 189:f392fc9709a3 776 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 777 * @retval None
AnnaBridge 189:f392fc9709a3 778 */
AnnaBridge 189:f392fc9709a3 779 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 780 {
AnnaBridge 189:f392fc9709a3 781 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge 189:f392fc9709a3 782 }
AnnaBridge 189:f392fc9709a3 783
AnnaBridge 189:f392fc9709a3 784 /**
AnnaBridge 189:f392fc9709a3 785 * @brief Set polynomial for CRC calculation
AnnaBridge 189:f392fc9709a3 786 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge 189:f392fc9709a3 787 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 788 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 189:f392fc9709a3 789 * @retval None
AnnaBridge 189:f392fc9709a3 790 */
AnnaBridge 189:f392fc9709a3 791 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge 189:f392fc9709a3 792 {
AnnaBridge 189:f392fc9709a3 793 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge 189:f392fc9709a3 794 }
AnnaBridge 189:f392fc9709a3 795
AnnaBridge 189:f392fc9709a3 796 /**
AnnaBridge 189:f392fc9709a3 797 * @brief Get polynomial for CRC calculation
AnnaBridge 189:f392fc9709a3 798 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge 189:f392fc9709a3 799 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 800 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 189:f392fc9709a3 801 */
AnnaBridge 189:f392fc9709a3 802 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 803 {
AnnaBridge 189:f392fc9709a3 804 return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge 189:f392fc9709a3 805 }
AnnaBridge 189:f392fc9709a3 806
AnnaBridge 189:f392fc9709a3 807 /**
AnnaBridge 189:f392fc9709a3 808 * @brief Get Rx CRC
AnnaBridge 189:f392fc9709a3 809 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge 189:f392fc9709a3 810 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 811 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 189:f392fc9709a3 812 */
AnnaBridge 189:f392fc9709a3 813 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 814 {
AnnaBridge 189:f392fc9709a3 815 return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge 189:f392fc9709a3 816 }
AnnaBridge 189:f392fc9709a3 817
AnnaBridge 189:f392fc9709a3 818 /**
AnnaBridge 189:f392fc9709a3 819 * @brief Get Tx CRC
AnnaBridge 189:f392fc9709a3 820 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge 189:f392fc9709a3 821 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 822 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge 189:f392fc9709a3 823 */
AnnaBridge 189:f392fc9709a3 824 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 825 {
AnnaBridge 189:f392fc9709a3 826 return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge 189:f392fc9709a3 827 }
AnnaBridge 189:f392fc9709a3 828
AnnaBridge 189:f392fc9709a3 829 /**
AnnaBridge 189:f392fc9709a3 830 * @}
AnnaBridge 189:f392fc9709a3 831 */
AnnaBridge 189:f392fc9709a3 832
AnnaBridge 189:f392fc9709a3 833 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge 189:f392fc9709a3 834 * @{
AnnaBridge 189:f392fc9709a3 835 */
AnnaBridge 189:f392fc9709a3 836
AnnaBridge 189:f392fc9709a3 837 /**
AnnaBridge 189:f392fc9709a3 838 * @brief Set NSS mode
AnnaBridge 189:f392fc9709a3 839 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge 189:f392fc9709a3 840 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge 189:f392fc9709a3 841 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge 189:f392fc9709a3 842 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 843 * @param NSS This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 844 * @arg @ref LL_SPI_NSS_SOFT
AnnaBridge 189:f392fc9709a3 845 * @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge 189:f392fc9709a3 846 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge 189:f392fc9709a3 847 * @retval None
AnnaBridge 189:f392fc9709a3 848 */
AnnaBridge 189:f392fc9709a3 849 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge 189:f392fc9709a3 850 {
AnnaBridge 189:f392fc9709a3 851 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge 189:f392fc9709a3 852 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge 189:f392fc9709a3 853 }
AnnaBridge 189:f392fc9709a3 854
AnnaBridge 189:f392fc9709a3 855 /**
AnnaBridge 189:f392fc9709a3 856 * @brief Get NSS mode
AnnaBridge 189:f392fc9709a3 857 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge 189:f392fc9709a3 858 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge 189:f392fc9709a3 859 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 860 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 861 * @arg @ref LL_SPI_NSS_SOFT
AnnaBridge 189:f392fc9709a3 862 * @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge 189:f392fc9709a3 863 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge 189:f392fc9709a3 864 */
AnnaBridge 189:f392fc9709a3 865 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 866 {
AnnaBridge 189:f392fc9709a3 867 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge 189:f392fc9709a3 868 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge 189:f392fc9709a3 869 return (Ssm | Ssoe);
AnnaBridge 189:f392fc9709a3 870 }
AnnaBridge 189:f392fc9709a3 871
AnnaBridge 189:f392fc9709a3 872 /**
AnnaBridge 189:f392fc9709a3 873 * @brief Enable NSS pulse management
AnnaBridge 189:f392fc9709a3 874 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge 189:f392fc9709a3 875 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
AnnaBridge 189:f392fc9709a3 876 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 877 * @retval None
AnnaBridge 189:f392fc9709a3 878 */
AnnaBridge 189:f392fc9709a3 879 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 880 {
AnnaBridge 189:f392fc9709a3 881 SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge 189:f392fc9709a3 882 }
AnnaBridge 189:f392fc9709a3 883
AnnaBridge 189:f392fc9709a3 884 /**
AnnaBridge 189:f392fc9709a3 885 * @brief Disable NSS pulse management
AnnaBridge 189:f392fc9709a3 886 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge 189:f392fc9709a3 887 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
AnnaBridge 189:f392fc9709a3 888 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 889 * @retval None
AnnaBridge 189:f392fc9709a3 890 */
AnnaBridge 189:f392fc9709a3 891 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 892 {
AnnaBridge 189:f392fc9709a3 893 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
AnnaBridge 189:f392fc9709a3 894 }
AnnaBridge 189:f392fc9709a3 895
AnnaBridge 189:f392fc9709a3 896 /**
AnnaBridge 189:f392fc9709a3 897 * @brief Check if NSS pulse is enabled
AnnaBridge 189:f392fc9709a3 898 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge 189:f392fc9709a3 899 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
AnnaBridge 189:f392fc9709a3 900 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 901 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 902 */
AnnaBridge 189:f392fc9709a3 903 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 904 {
AnnaBridge 189:f392fc9709a3 905 return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
AnnaBridge 189:f392fc9709a3 906 }
AnnaBridge 189:f392fc9709a3 907
AnnaBridge 189:f392fc9709a3 908 /**
AnnaBridge 189:f392fc9709a3 909 * @}
AnnaBridge 189:f392fc9709a3 910 */
AnnaBridge 189:f392fc9709a3 911
AnnaBridge 189:f392fc9709a3 912 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge 189:f392fc9709a3 913 * @{
AnnaBridge 189:f392fc9709a3 914 */
AnnaBridge 189:f392fc9709a3 915
AnnaBridge 189:f392fc9709a3 916 /**
AnnaBridge 189:f392fc9709a3 917 * @brief Check if Rx buffer is not empty
AnnaBridge 189:f392fc9709a3 918 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge 189:f392fc9709a3 919 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 920 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 921 */
AnnaBridge 189:f392fc9709a3 922 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 923 {
AnnaBridge 189:f392fc9709a3 924 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge 189:f392fc9709a3 925 }
AnnaBridge 189:f392fc9709a3 926
AnnaBridge 189:f392fc9709a3 927 /**
AnnaBridge 189:f392fc9709a3 928 * @brief Check if Tx buffer is empty
AnnaBridge 189:f392fc9709a3 929 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge 189:f392fc9709a3 930 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 931 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 932 */
AnnaBridge 189:f392fc9709a3 933 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 934 {
AnnaBridge 189:f392fc9709a3 935 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge 189:f392fc9709a3 936 }
AnnaBridge 189:f392fc9709a3 937
AnnaBridge 189:f392fc9709a3 938 /**
AnnaBridge 189:f392fc9709a3 939 * @brief Get CRC error flag
AnnaBridge 189:f392fc9709a3 940 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge 189:f392fc9709a3 941 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 942 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 943 */
AnnaBridge 189:f392fc9709a3 944 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 945 {
AnnaBridge 189:f392fc9709a3 946 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge 189:f392fc9709a3 947 }
AnnaBridge 189:f392fc9709a3 948
AnnaBridge 189:f392fc9709a3 949 /**
AnnaBridge 189:f392fc9709a3 950 * @brief Get mode fault error flag
AnnaBridge 189:f392fc9709a3 951 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge 189:f392fc9709a3 952 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 953 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 954 */
AnnaBridge 189:f392fc9709a3 955 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 956 {
AnnaBridge 189:f392fc9709a3 957 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge 189:f392fc9709a3 958 }
AnnaBridge 189:f392fc9709a3 959
AnnaBridge 189:f392fc9709a3 960 /**
AnnaBridge 189:f392fc9709a3 961 * @brief Get overrun error flag
AnnaBridge 189:f392fc9709a3 962 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge 189:f392fc9709a3 963 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 964 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 965 */
AnnaBridge 189:f392fc9709a3 966 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 967 {
AnnaBridge 189:f392fc9709a3 968 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge 189:f392fc9709a3 969 }
AnnaBridge 189:f392fc9709a3 970
AnnaBridge 189:f392fc9709a3 971 /**
AnnaBridge 189:f392fc9709a3 972 * @brief Get busy flag
AnnaBridge 189:f392fc9709a3 973 * @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge 189:f392fc9709a3 974 * -When the SPI is correctly disabled
AnnaBridge 189:f392fc9709a3 975 * -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge 189:f392fc9709a3 976 * -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge 189:f392fc9709a3 977 * sent
AnnaBridge 189:f392fc9709a3 978 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge 189:f392fc9709a3 979 * each data transfer.
AnnaBridge 189:f392fc9709a3 980 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge 189:f392fc9709a3 981 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 982 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 983 */
AnnaBridge 189:f392fc9709a3 984 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 985 {
AnnaBridge 189:f392fc9709a3 986 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge 189:f392fc9709a3 987 }
AnnaBridge 189:f392fc9709a3 988
AnnaBridge 189:f392fc9709a3 989 /**
AnnaBridge 189:f392fc9709a3 990 * @brief Get frame format error flag
AnnaBridge 189:f392fc9709a3 991 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge 189:f392fc9709a3 992 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 993 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 994 */
AnnaBridge 189:f392fc9709a3 995 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 996 {
AnnaBridge 189:f392fc9709a3 997 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge 189:f392fc9709a3 998 }
AnnaBridge 189:f392fc9709a3 999
AnnaBridge 189:f392fc9709a3 1000 /**
AnnaBridge 189:f392fc9709a3 1001 * @brief Get FIFO reception Level
AnnaBridge 189:f392fc9709a3 1002 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
AnnaBridge 189:f392fc9709a3 1003 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1004 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 1005 * @arg @ref LL_SPI_RX_FIFO_EMPTY
AnnaBridge 189:f392fc9709a3 1006 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
AnnaBridge 189:f392fc9709a3 1007 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
AnnaBridge 189:f392fc9709a3 1008 * @arg @ref LL_SPI_RX_FIFO_FULL
AnnaBridge 189:f392fc9709a3 1009 */
AnnaBridge 189:f392fc9709a3 1010 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1011 {
AnnaBridge 189:f392fc9709a3 1012 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
AnnaBridge 189:f392fc9709a3 1013 }
AnnaBridge 189:f392fc9709a3 1014
AnnaBridge 189:f392fc9709a3 1015 /**
AnnaBridge 189:f392fc9709a3 1016 * @brief Get FIFO Transmission Level
AnnaBridge 189:f392fc9709a3 1017 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
AnnaBridge 189:f392fc9709a3 1018 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1019 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 1020 * @arg @ref LL_SPI_TX_FIFO_EMPTY
AnnaBridge 189:f392fc9709a3 1021 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
AnnaBridge 189:f392fc9709a3 1022 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
AnnaBridge 189:f392fc9709a3 1023 * @arg @ref LL_SPI_TX_FIFO_FULL
AnnaBridge 189:f392fc9709a3 1024 */
AnnaBridge 189:f392fc9709a3 1025 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1026 {
AnnaBridge 189:f392fc9709a3 1027 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
AnnaBridge 189:f392fc9709a3 1028 }
AnnaBridge 189:f392fc9709a3 1029
AnnaBridge 189:f392fc9709a3 1030 /**
AnnaBridge 189:f392fc9709a3 1031 * @brief Clear CRC error flag
AnnaBridge 189:f392fc9709a3 1032 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge 189:f392fc9709a3 1033 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1034 * @retval None
AnnaBridge 189:f392fc9709a3 1035 */
AnnaBridge 189:f392fc9709a3 1036 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1037 {
AnnaBridge 189:f392fc9709a3 1038 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge 189:f392fc9709a3 1039 }
AnnaBridge 189:f392fc9709a3 1040
AnnaBridge 189:f392fc9709a3 1041 /**
AnnaBridge 189:f392fc9709a3 1042 * @brief Clear mode fault error flag
AnnaBridge 189:f392fc9709a3 1043 * @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge 189:f392fc9709a3 1044 * register followed by a write access to the SPIx_CR1 register
AnnaBridge 189:f392fc9709a3 1045 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge 189:f392fc9709a3 1046 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1047 * @retval None
AnnaBridge 189:f392fc9709a3 1048 */
AnnaBridge 189:f392fc9709a3 1049 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1050 {
AnnaBridge 189:f392fc9709a3 1051 __IO uint32_t tmpreg;
AnnaBridge 189:f392fc9709a3 1052 tmpreg = SPIx->SR;
AnnaBridge 189:f392fc9709a3 1053 (void) tmpreg;
AnnaBridge 189:f392fc9709a3 1054 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge 189:f392fc9709a3 1055 (void) tmpreg;
AnnaBridge 189:f392fc9709a3 1056 }
AnnaBridge 189:f392fc9709a3 1057
AnnaBridge 189:f392fc9709a3 1058 /**
AnnaBridge 189:f392fc9709a3 1059 * @brief Clear overrun error flag
AnnaBridge 189:f392fc9709a3 1060 * @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge 189:f392fc9709a3 1061 * register followed by a read access to the SPIx_SR register
AnnaBridge 189:f392fc9709a3 1062 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge 189:f392fc9709a3 1063 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1064 * @retval None
AnnaBridge 189:f392fc9709a3 1065 */
AnnaBridge 189:f392fc9709a3 1066 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1067 {
AnnaBridge 189:f392fc9709a3 1068 __IO uint32_t tmpreg;
AnnaBridge 189:f392fc9709a3 1069 tmpreg = SPIx->DR;
AnnaBridge 189:f392fc9709a3 1070 (void) tmpreg;
AnnaBridge 189:f392fc9709a3 1071 tmpreg = SPIx->SR;
AnnaBridge 189:f392fc9709a3 1072 (void) tmpreg;
AnnaBridge 189:f392fc9709a3 1073 }
AnnaBridge 189:f392fc9709a3 1074
AnnaBridge 189:f392fc9709a3 1075 /**
AnnaBridge 189:f392fc9709a3 1076 * @brief Clear frame format error flag
AnnaBridge 189:f392fc9709a3 1077 * @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge 189:f392fc9709a3 1078 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge 189:f392fc9709a3 1079 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1080 * @retval None
AnnaBridge 189:f392fc9709a3 1081 */
AnnaBridge 189:f392fc9709a3 1082 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1083 {
AnnaBridge 189:f392fc9709a3 1084 __IO uint32_t tmpreg;
AnnaBridge 189:f392fc9709a3 1085 tmpreg = SPIx->SR;
AnnaBridge 189:f392fc9709a3 1086 (void) tmpreg;
AnnaBridge 189:f392fc9709a3 1087 }
AnnaBridge 189:f392fc9709a3 1088
AnnaBridge 189:f392fc9709a3 1089 /**
AnnaBridge 189:f392fc9709a3 1090 * @}
AnnaBridge 189:f392fc9709a3 1091 */
AnnaBridge 189:f392fc9709a3 1092
AnnaBridge 189:f392fc9709a3 1093 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge 189:f392fc9709a3 1094 * @{
AnnaBridge 189:f392fc9709a3 1095 */
AnnaBridge 189:f392fc9709a3 1096
AnnaBridge 189:f392fc9709a3 1097 /**
AnnaBridge 189:f392fc9709a3 1098 * @brief Enable error interrupt
AnnaBridge 189:f392fc9709a3 1099 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge 189:f392fc9709a3 1100 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge 189:f392fc9709a3 1101 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1102 * @retval None
AnnaBridge 189:f392fc9709a3 1103 */
AnnaBridge 189:f392fc9709a3 1104 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1105 {
AnnaBridge 189:f392fc9709a3 1106 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge 189:f392fc9709a3 1107 }
AnnaBridge 189:f392fc9709a3 1108
AnnaBridge 189:f392fc9709a3 1109 /**
AnnaBridge 189:f392fc9709a3 1110 * @brief Enable Rx buffer not empty interrupt
AnnaBridge 189:f392fc9709a3 1111 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge 189:f392fc9709a3 1112 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1113 * @retval None
AnnaBridge 189:f392fc9709a3 1114 */
AnnaBridge 189:f392fc9709a3 1115 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1116 {
AnnaBridge 189:f392fc9709a3 1117 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge 189:f392fc9709a3 1118 }
AnnaBridge 189:f392fc9709a3 1119
AnnaBridge 189:f392fc9709a3 1120 /**
AnnaBridge 189:f392fc9709a3 1121 * @brief Enable Tx buffer empty interrupt
AnnaBridge 189:f392fc9709a3 1122 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge 189:f392fc9709a3 1123 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1124 * @retval None
AnnaBridge 189:f392fc9709a3 1125 */
AnnaBridge 189:f392fc9709a3 1126 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1127 {
AnnaBridge 189:f392fc9709a3 1128 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge 189:f392fc9709a3 1129 }
AnnaBridge 189:f392fc9709a3 1130
AnnaBridge 189:f392fc9709a3 1131 /**
AnnaBridge 189:f392fc9709a3 1132 * @brief Disable error interrupt
AnnaBridge 189:f392fc9709a3 1133 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge 189:f392fc9709a3 1134 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge 189:f392fc9709a3 1135 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1136 * @retval None
AnnaBridge 189:f392fc9709a3 1137 */
AnnaBridge 189:f392fc9709a3 1138 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1139 {
AnnaBridge 189:f392fc9709a3 1140 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge 189:f392fc9709a3 1141 }
AnnaBridge 189:f392fc9709a3 1142
AnnaBridge 189:f392fc9709a3 1143 /**
AnnaBridge 189:f392fc9709a3 1144 * @brief Disable Rx buffer not empty interrupt
AnnaBridge 189:f392fc9709a3 1145 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge 189:f392fc9709a3 1146 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1147 * @retval None
AnnaBridge 189:f392fc9709a3 1148 */
AnnaBridge 189:f392fc9709a3 1149 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1150 {
AnnaBridge 189:f392fc9709a3 1151 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge 189:f392fc9709a3 1152 }
AnnaBridge 189:f392fc9709a3 1153
AnnaBridge 189:f392fc9709a3 1154 /**
AnnaBridge 189:f392fc9709a3 1155 * @brief Disable Tx buffer empty interrupt
AnnaBridge 189:f392fc9709a3 1156 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge 189:f392fc9709a3 1157 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1158 * @retval None
AnnaBridge 189:f392fc9709a3 1159 */
AnnaBridge 189:f392fc9709a3 1160 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1161 {
AnnaBridge 189:f392fc9709a3 1162 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge 189:f392fc9709a3 1163 }
AnnaBridge 189:f392fc9709a3 1164
AnnaBridge 189:f392fc9709a3 1165 /**
AnnaBridge 189:f392fc9709a3 1166 * @brief Check if error interrupt is enabled
AnnaBridge 189:f392fc9709a3 1167 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge 189:f392fc9709a3 1168 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1169 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1170 */
AnnaBridge 189:f392fc9709a3 1171 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1172 {
AnnaBridge 189:f392fc9709a3 1173 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge 189:f392fc9709a3 1174 }
AnnaBridge 189:f392fc9709a3 1175
AnnaBridge 189:f392fc9709a3 1176 /**
AnnaBridge 189:f392fc9709a3 1177 * @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge 189:f392fc9709a3 1178 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge 189:f392fc9709a3 1179 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1180 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1181 */
AnnaBridge 189:f392fc9709a3 1182 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1183 {
AnnaBridge 189:f392fc9709a3 1184 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge 189:f392fc9709a3 1185 }
AnnaBridge 189:f392fc9709a3 1186
AnnaBridge 189:f392fc9709a3 1187 /**
AnnaBridge 189:f392fc9709a3 1188 * @brief Check if Tx buffer empty interrupt
AnnaBridge 189:f392fc9709a3 1189 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge 189:f392fc9709a3 1190 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1191 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1192 */
AnnaBridge 189:f392fc9709a3 1193 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1194 {
AnnaBridge 189:f392fc9709a3 1195 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge 189:f392fc9709a3 1196 }
AnnaBridge 189:f392fc9709a3 1197
AnnaBridge 189:f392fc9709a3 1198 /**
AnnaBridge 189:f392fc9709a3 1199 * @}
AnnaBridge 189:f392fc9709a3 1200 */
AnnaBridge 189:f392fc9709a3 1201
AnnaBridge 189:f392fc9709a3 1202 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge 189:f392fc9709a3 1203 * @{
AnnaBridge 189:f392fc9709a3 1204 */
AnnaBridge 189:f392fc9709a3 1205
AnnaBridge 189:f392fc9709a3 1206 /**
AnnaBridge 189:f392fc9709a3 1207 * @brief Enable DMA Rx
AnnaBridge 189:f392fc9709a3 1208 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge 189:f392fc9709a3 1209 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1210 * @retval None
AnnaBridge 189:f392fc9709a3 1211 */
AnnaBridge 189:f392fc9709a3 1212 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1213 {
AnnaBridge 189:f392fc9709a3 1214 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge 189:f392fc9709a3 1215 }
AnnaBridge 189:f392fc9709a3 1216
AnnaBridge 189:f392fc9709a3 1217 /**
AnnaBridge 189:f392fc9709a3 1218 * @brief Disable DMA Rx
AnnaBridge 189:f392fc9709a3 1219 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge 189:f392fc9709a3 1220 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1221 * @retval None
AnnaBridge 189:f392fc9709a3 1222 */
AnnaBridge 189:f392fc9709a3 1223 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1224 {
AnnaBridge 189:f392fc9709a3 1225 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge 189:f392fc9709a3 1226 }
AnnaBridge 189:f392fc9709a3 1227
AnnaBridge 189:f392fc9709a3 1228 /**
AnnaBridge 189:f392fc9709a3 1229 * @brief Check if DMA Rx is enabled
AnnaBridge 189:f392fc9709a3 1230 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge 189:f392fc9709a3 1231 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1232 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1233 */
AnnaBridge 189:f392fc9709a3 1234 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1235 {
AnnaBridge 189:f392fc9709a3 1236 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge 189:f392fc9709a3 1237 }
AnnaBridge 189:f392fc9709a3 1238
AnnaBridge 189:f392fc9709a3 1239 /**
AnnaBridge 189:f392fc9709a3 1240 * @brief Enable DMA Tx
AnnaBridge 189:f392fc9709a3 1241 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge 189:f392fc9709a3 1242 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1243 * @retval None
AnnaBridge 189:f392fc9709a3 1244 */
AnnaBridge 189:f392fc9709a3 1245 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1246 {
AnnaBridge 189:f392fc9709a3 1247 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge 189:f392fc9709a3 1248 }
AnnaBridge 189:f392fc9709a3 1249
AnnaBridge 189:f392fc9709a3 1250 /**
AnnaBridge 189:f392fc9709a3 1251 * @brief Disable DMA Tx
AnnaBridge 189:f392fc9709a3 1252 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge 189:f392fc9709a3 1253 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1254 * @retval None
AnnaBridge 189:f392fc9709a3 1255 */
AnnaBridge 189:f392fc9709a3 1256 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1257 {
AnnaBridge 189:f392fc9709a3 1258 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge 189:f392fc9709a3 1259 }
AnnaBridge 189:f392fc9709a3 1260
AnnaBridge 189:f392fc9709a3 1261 /**
AnnaBridge 189:f392fc9709a3 1262 * @brief Check if DMA Tx is enabled
AnnaBridge 189:f392fc9709a3 1263 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge 189:f392fc9709a3 1264 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1265 * @retval State of bit (1 or 0).
AnnaBridge 189:f392fc9709a3 1266 */
AnnaBridge 189:f392fc9709a3 1267 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1268 {
AnnaBridge 189:f392fc9709a3 1269 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge 189:f392fc9709a3 1270 }
AnnaBridge 189:f392fc9709a3 1271
AnnaBridge 189:f392fc9709a3 1272 /**
AnnaBridge 189:f392fc9709a3 1273 * @brief Set parity of Last DMA reception
AnnaBridge 189:f392fc9709a3 1274 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
AnnaBridge 189:f392fc9709a3 1275 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1276 * @param Parity This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1277 * @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge 189:f392fc9709a3 1278 * @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge 189:f392fc9709a3 1279 * @retval None
AnnaBridge 189:f392fc9709a3 1280 */
AnnaBridge 189:f392fc9709a3 1281 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge 189:f392fc9709a3 1282 {
AnnaBridge 189:f392fc9709a3 1283 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
AnnaBridge 189:f392fc9709a3 1284 }
AnnaBridge 189:f392fc9709a3 1285
AnnaBridge 189:f392fc9709a3 1286 /**
AnnaBridge 189:f392fc9709a3 1287 * @brief Get parity configuration for Last DMA reception
AnnaBridge 189:f392fc9709a3 1288 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
AnnaBridge 189:f392fc9709a3 1289 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1290 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 1291 * @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge 189:f392fc9709a3 1292 * @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge 189:f392fc9709a3 1293 */
AnnaBridge 189:f392fc9709a3 1294 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1295 {
AnnaBridge 189:f392fc9709a3 1296 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
AnnaBridge 189:f392fc9709a3 1297 }
AnnaBridge 189:f392fc9709a3 1298
AnnaBridge 189:f392fc9709a3 1299 /**
AnnaBridge 189:f392fc9709a3 1300 * @brief Set parity of Last DMA transmission
AnnaBridge 189:f392fc9709a3 1301 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
AnnaBridge 189:f392fc9709a3 1302 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1303 * @param Parity This parameter can be one of the following values:
AnnaBridge 189:f392fc9709a3 1304 * @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge 189:f392fc9709a3 1305 * @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge 189:f392fc9709a3 1306 * @retval None
AnnaBridge 189:f392fc9709a3 1307 */
AnnaBridge 189:f392fc9709a3 1308 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
AnnaBridge 189:f392fc9709a3 1309 {
AnnaBridge 189:f392fc9709a3 1310 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
AnnaBridge 189:f392fc9709a3 1311 }
AnnaBridge 189:f392fc9709a3 1312
AnnaBridge 189:f392fc9709a3 1313 /**
AnnaBridge 189:f392fc9709a3 1314 * @brief Get parity configuration for Last DMA transmission
AnnaBridge 189:f392fc9709a3 1315 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
AnnaBridge 189:f392fc9709a3 1316 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1317 * @retval Returned value can be one of the following values:
AnnaBridge 189:f392fc9709a3 1318 * @arg @ref LL_SPI_DMA_PARITY_ODD
AnnaBridge 189:f392fc9709a3 1319 * @arg @ref LL_SPI_DMA_PARITY_EVEN
AnnaBridge 189:f392fc9709a3 1320 */
AnnaBridge 189:f392fc9709a3 1321 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1322 {
AnnaBridge 189:f392fc9709a3 1323 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
AnnaBridge 189:f392fc9709a3 1324 }
AnnaBridge 189:f392fc9709a3 1325
AnnaBridge 189:f392fc9709a3 1326 /**
AnnaBridge 189:f392fc9709a3 1327 * @brief Get the data register address used for DMA transfer
AnnaBridge 189:f392fc9709a3 1328 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge 189:f392fc9709a3 1329 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1330 * @retval Address of data register
AnnaBridge 189:f392fc9709a3 1331 */
AnnaBridge 189:f392fc9709a3 1332 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1333 {
AnnaBridge 189:f392fc9709a3 1334 return (uint32_t) & (SPIx->DR);
AnnaBridge 189:f392fc9709a3 1335 }
AnnaBridge 189:f392fc9709a3 1336
AnnaBridge 189:f392fc9709a3 1337 /**
AnnaBridge 189:f392fc9709a3 1338 * @}
AnnaBridge 189:f392fc9709a3 1339 */
AnnaBridge 189:f392fc9709a3 1340
AnnaBridge 189:f392fc9709a3 1341 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge 189:f392fc9709a3 1342 * @{
AnnaBridge 189:f392fc9709a3 1343 */
AnnaBridge 189:f392fc9709a3 1344
AnnaBridge 189:f392fc9709a3 1345 /**
AnnaBridge 189:f392fc9709a3 1346 * @brief Read 8-Bits in the data register
AnnaBridge 189:f392fc9709a3 1347 * @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge 189:f392fc9709a3 1348 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1349 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 189:f392fc9709a3 1350 */
AnnaBridge 189:f392fc9709a3 1351 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1352 {
AnnaBridge 189:f392fc9709a3 1353 return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge 189:f392fc9709a3 1354 }
AnnaBridge 189:f392fc9709a3 1355
AnnaBridge 189:f392fc9709a3 1356 /**
AnnaBridge 189:f392fc9709a3 1357 * @brief Read 16-Bits in the data register
AnnaBridge 189:f392fc9709a3 1358 * @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge 189:f392fc9709a3 1359 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1360 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 189:f392fc9709a3 1361 */
AnnaBridge 189:f392fc9709a3 1362 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge 189:f392fc9709a3 1363 {
AnnaBridge 189:f392fc9709a3 1364 return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge 189:f392fc9709a3 1365 }
AnnaBridge 189:f392fc9709a3 1366
AnnaBridge 189:f392fc9709a3 1367 /**
AnnaBridge 189:f392fc9709a3 1368 * @brief Write 8-Bits in the data register
AnnaBridge 189:f392fc9709a3 1369 * @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge 189:f392fc9709a3 1370 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1371 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 189:f392fc9709a3 1372 * @retval None
AnnaBridge 189:f392fc9709a3 1373 */
AnnaBridge 189:f392fc9709a3 1374 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge 189:f392fc9709a3 1375 {
AnnaBridge 189:f392fc9709a3 1376 *((__IO uint8_t *)&SPIx->DR) = TxData;
AnnaBridge 189:f392fc9709a3 1377 }
AnnaBridge 189:f392fc9709a3 1378
AnnaBridge 189:f392fc9709a3 1379 #if __GNUC__
AnnaBridge 189:f392fc9709a3 1380 # define MAY_ALIAS __attribute__ ((__may_alias__))
AnnaBridge 189:f392fc9709a3 1381 #else
AnnaBridge 189:f392fc9709a3 1382 # define MAY_ALIAS
AnnaBridge 189:f392fc9709a3 1383 #endif
AnnaBridge 189:f392fc9709a3 1384
AnnaBridge 189:f392fc9709a3 1385 typedef __IO uint16_t MAY_ALIAS uint16_io_t;
AnnaBridge 189:f392fc9709a3 1386
AnnaBridge 189:f392fc9709a3 1387 /**
AnnaBridge 189:f392fc9709a3 1388 * @brief Write 16-Bits in the data register
AnnaBridge 189:f392fc9709a3 1389 * @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge 189:f392fc9709a3 1390 * @param SPIx SPI Instance
AnnaBridge 189:f392fc9709a3 1391 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 189:f392fc9709a3 1392 * @retval None
AnnaBridge 189:f392fc9709a3 1393 */
AnnaBridge 189:f392fc9709a3 1394 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge 189:f392fc9709a3 1395 {
AnnaBridge 189:f392fc9709a3 1396 *((uint16_io_t*)&SPIx->DR) = TxData;
AnnaBridge 189:f392fc9709a3 1397 }
AnnaBridge 189:f392fc9709a3 1398
AnnaBridge 189:f392fc9709a3 1399 /**
AnnaBridge 189:f392fc9709a3 1400 * @}
AnnaBridge 189:f392fc9709a3 1401 */
AnnaBridge 189:f392fc9709a3 1402 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 189:f392fc9709a3 1403 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 189:f392fc9709a3 1404 * @{
AnnaBridge 189:f392fc9709a3 1405 */
AnnaBridge 189:f392fc9709a3 1406
AnnaBridge 189:f392fc9709a3 1407 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge 189:f392fc9709a3 1408 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge 189:f392fc9709a3 1409 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge 189:f392fc9709a3 1410
AnnaBridge 189:f392fc9709a3 1411 /**
AnnaBridge 189:f392fc9709a3 1412 * @}
AnnaBridge 189:f392fc9709a3 1413 */
AnnaBridge 189:f392fc9709a3 1414 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 189:f392fc9709a3 1415 /**
AnnaBridge 189:f392fc9709a3 1416 * @}
AnnaBridge 189:f392fc9709a3 1417 */
AnnaBridge 189:f392fc9709a3 1418
AnnaBridge 189:f392fc9709a3 1419 /**
AnnaBridge 189:f392fc9709a3 1420 * @}
AnnaBridge 189:f392fc9709a3 1421 */
AnnaBridge 189:f392fc9709a3 1422
AnnaBridge 189:f392fc9709a3 1423 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
AnnaBridge 189:f392fc9709a3 1424
AnnaBridge 189:f392fc9709a3 1425 /**
AnnaBridge 189:f392fc9709a3 1426 * @}
AnnaBridge 189:f392fc9709a3 1427 */
AnnaBridge 189:f392fc9709a3 1428
AnnaBridge 189:f392fc9709a3 1429 #ifdef __cplusplus
AnnaBridge 189:f392fc9709a3 1430 }
AnnaBridge 189:f392fc9709a3 1431 #endif
AnnaBridge 189:f392fc9709a3 1432
AnnaBridge 189:f392fc9709a3 1433 #endif /* __STM32L4xx_LL_SPI_H */
AnnaBridge 189:f392fc9709a3 1434
AnnaBridge 189:f392fc9709a3 1435 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/