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cmsis/BUILD/mbed/TARGET_DISCO_L496AG/TOOLCHAIN_IAR/stm32l4xx_ll_sdmmc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	189:f392fc9709a3	1	/**
AnnaBridge	189:f392fc9709a3	2	******************************************************************************
AnnaBridge	189:f392fc9709a3	3	* @file stm32l4xx_ll_sdmmc.h
AnnaBridge	189:f392fc9709a3	4	* @author MCD Application Team
AnnaBridge	189:f392fc9709a3	5	* @brief Header file of low layer SDMMC HAL module.
AnnaBridge	189:f392fc9709a3	6	******************************************************************************
AnnaBridge	189:f392fc9709a3	7	* @attention
AnnaBridge	189:f392fc9709a3	8	*
AnnaBridge	189:f392fc9709a3	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	189:f392fc9709a3	10	*
AnnaBridge	189:f392fc9709a3	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	189:f392fc9709a3	12	* are permitted provided that the following conditions are met:
AnnaBridge	189:f392fc9709a3	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	189:f392fc9709a3	14	* this list of conditions and the following disclaimer.
AnnaBridge	189:f392fc9709a3	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	189:f392fc9709a3	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	189:f392fc9709a3	17	* and/or other materials provided with the distribution.
AnnaBridge	189:f392fc9709a3	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	189:f392fc9709a3	19	* may be used to endorse or promote products derived from this software
AnnaBridge	189:f392fc9709a3	20	* without specific prior written permission.
AnnaBridge	189:f392fc9709a3	21	*
AnnaBridge	189:f392fc9709a3	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	189:f392fc9709a3	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	189:f392fc9709a3	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	189:f392fc9709a3	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	189:f392fc9709a3	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	189:f392fc9709a3	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	189:f392fc9709a3	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	189:f392fc9709a3	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	189:f392fc9709a3	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	189:f392fc9709a3	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	189:f392fc9709a3	32	*
AnnaBridge	189:f392fc9709a3	33	******************************************************************************
AnnaBridge	189:f392fc9709a3	34	*/
AnnaBridge	189:f392fc9709a3	35
AnnaBridge	189:f392fc9709a3	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	189:f392fc9709a3	37	#ifndef __STM32L4xx_LL_SDMMC_H
AnnaBridge	189:f392fc9709a3	38	#define __STM32L4xx_LL_SDMMC_H
AnnaBridge	189:f392fc9709a3	39
AnnaBridge	189:f392fc9709a3	40	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	41	extern "C" {
AnnaBridge	189:f392fc9709a3	42	#endif
AnnaBridge	189:f392fc9709a3	43
AnnaBridge	189:f392fc9709a3	44	#if defined(SDMMC1)
AnnaBridge	189:f392fc9709a3	45
AnnaBridge	189:f392fc9709a3	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	47	#include "stm32l4xx_hal_def.h"
AnnaBridge	189:f392fc9709a3	48
AnnaBridge	189:f392fc9709a3	49	/** @addtogroup STM32L4xx_Driver
AnnaBridge	189:f392fc9709a3	50	* @{
AnnaBridge	189:f392fc9709a3	51	*/
AnnaBridge	189:f392fc9709a3	52
AnnaBridge	189:f392fc9709a3	53	/** @addtogroup SDMMC_LL
AnnaBridge	189:f392fc9709a3	54	* @{
AnnaBridge	189:f392fc9709a3	55	*/
AnnaBridge	189:f392fc9709a3	56
AnnaBridge	189:f392fc9709a3	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	58	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge	189:f392fc9709a3	59	* @{
AnnaBridge	189:f392fc9709a3	60	*/
AnnaBridge	189:f392fc9709a3	61
AnnaBridge	189:f392fc9709a3	62	/**
AnnaBridge	189:f392fc9709a3	63	* @brief SDMMC Configuration Structure definition
AnnaBridge	189:f392fc9709a3	64	*/
AnnaBridge	189:f392fc9709a3	65	typedef struct
AnnaBridge	189:f392fc9709a3	66	{
AnnaBridge	189:f392fc9709a3	67	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge	189:f392fc9709a3	68	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge	189:f392fc9709a3	69
AnnaBridge	189:f392fc9709a3	70	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	71	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
AnnaBridge	189:f392fc9709a3	72	enabled or disabled.
AnnaBridge	189:f392fc9709a3	73	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
AnnaBridge	189:f392fc9709a3	74	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	75
AnnaBridge	189:f392fc9709a3	76	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge	189:f392fc9709a3	77	disabled when the bus is idle.
AnnaBridge	189:f392fc9709a3	78	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge	189:f392fc9709a3	79
AnnaBridge	189:f392fc9709a3	80	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge	189:f392fc9709a3	81	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge	189:f392fc9709a3	82
AnnaBridge	189:f392fc9709a3	83	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge	189:f392fc9709a3	84	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge	189:f392fc9709a3	85
AnnaBridge	189:f392fc9709a3	86	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge	189:f392fc9709a3	87	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	189:f392fc9709a3	88
AnnaBridge	189:f392fc9709a3	89	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	90	uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled.
AnnaBridge	189:f392fc9709a3	91	This parameter can be a value of @ref SDMMC_LL_Transceiver */
AnnaBridge	189:f392fc9709a3	92	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	93
AnnaBridge	189:f392fc9709a3	94	}SDMMC_InitTypeDef;
AnnaBridge	189:f392fc9709a3	95
AnnaBridge	189:f392fc9709a3	96
AnnaBridge	189:f392fc9709a3	97	/**
AnnaBridge	189:f392fc9709a3	98	* @brief SDMMC Command Control structure
AnnaBridge	189:f392fc9709a3	99	*/
AnnaBridge	189:f392fc9709a3	100	typedef struct
AnnaBridge	189:f392fc9709a3	101	{
AnnaBridge	189:f392fc9709a3	102	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge	189:f392fc9709a3	103	to a card as part of a command message. If a command
AnnaBridge	189:f392fc9709a3	104	contains an argument, it must be loaded into this register
AnnaBridge	189:f392fc9709a3	105	before writing the command to the command register. */
AnnaBridge	189:f392fc9709a3	106
AnnaBridge	189:f392fc9709a3	107	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge	189:f392fc9709a3	108	Max_Data = 64 */
AnnaBridge	189:f392fc9709a3	109
AnnaBridge	189:f392fc9709a3	110	uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge	189:f392fc9709a3	111	This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge	189:f392fc9709a3	112
AnnaBridge	189:f392fc9709a3	113	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge	189:f392fc9709a3	114	enabled or disabled.
AnnaBridge	189:f392fc9709a3	115	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge	189:f392fc9709a3	116
AnnaBridge	189:f392fc9709a3	117	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge	189:f392fc9709a3	118	is enabled or disabled.
AnnaBridge	189:f392fc9709a3	119	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge	189:f392fc9709a3	120	}SDMMC_CmdInitTypeDef;
AnnaBridge	189:f392fc9709a3	121
AnnaBridge	189:f392fc9709a3	122
AnnaBridge	189:f392fc9709a3	123	/**
AnnaBridge	189:f392fc9709a3	124	* @brief SDMMC Data Control structure
AnnaBridge	189:f392fc9709a3	125	*/
AnnaBridge	189:f392fc9709a3	126	typedef struct
AnnaBridge	189:f392fc9709a3	127	{
AnnaBridge	189:f392fc9709a3	128	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
AnnaBridge	189:f392fc9709a3	129
AnnaBridge	189:f392fc9709a3	130	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
AnnaBridge	189:f392fc9709a3	131
AnnaBridge	189:f392fc9709a3	132	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge	189:f392fc9709a3	133	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge	189:f392fc9709a3	134
AnnaBridge	189:f392fc9709a3	135	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge	189:f392fc9709a3	136	is a read or write.
AnnaBridge	189:f392fc9709a3	137	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge	189:f392fc9709a3	138
AnnaBridge	189:f392fc9709a3	139	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge	189:f392fc9709a3	140	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge	189:f392fc9709a3	141
AnnaBridge	189:f392fc9709a3	142	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge	189:f392fc9709a3	143	is enabled or disabled.
AnnaBridge	189:f392fc9709a3	144	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge	189:f392fc9709a3	145	}SDMMC_DataInitTypeDef;
AnnaBridge	189:f392fc9709a3	146
AnnaBridge	189:f392fc9709a3	147	/**
AnnaBridge	189:f392fc9709a3	148	* @}
AnnaBridge	189:f392fc9709a3	149	*/
AnnaBridge	189:f392fc9709a3	150
AnnaBridge	189:f392fc9709a3	151	/* Exported constants --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	152	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge	189:f392fc9709a3	153	* @{
AnnaBridge	189:f392fc9709a3	154	*/
AnnaBridge	189:f392fc9709a3	155	#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
AnnaBridge	189:f392fc9709a3	156	#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /!< Command response received (but CRC check failed) /
AnnaBridge	189:f392fc9709a3	157	#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /!< Data block sent/received (CRC check failed) /
AnnaBridge	189:f392fc9709a3	158	#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /!< Command response timeout /
AnnaBridge	189:f392fc9709a3	159	#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /!< Data timeout /
AnnaBridge	189:f392fc9709a3	160	#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /!< Transmit FIFO underrun /
AnnaBridge	189:f392fc9709a3	161	#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /!< Receive FIFO overrun /
AnnaBridge	189:f392fc9709a3	162	#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /!< Misaligned address /
AnnaBridge	189:f392fc9709a3	163	#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
AnnaBridge	189:f392fc9709a3	164	number of transferred bytes does not match the block length */
AnnaBridge	189:f392fc9709a3	165	#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /!< An error in the sequence of erase command occurs /
AnnaBridge	189:f392fc9709a3	166	#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /!< An invalid selection for erase groups /
AnnaBridge	189:f392fc9709a3	167	#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /!< Attempt to program a write protect block /
AnnaBridge	189:f392fc9709a3	168	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
AnnaBridge	189:f392fc9709a3	169	command or if there was an attempt to access a locked card */
AnnaBridge	189:f392fc9709a3	170	#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /!< CRC check of the previous command failed /
AnnaBridge	189:f392fc9709a3	171	#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /!< Command is not legal for the card state /
AnnaBridge	189:f392fc9709a3	172	#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /!< Card internal ECC was applied but failed to correct the data /
AnnaBridge	189:f392fc9709a3	173	#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /!< Internal card controller error /
AnnaBridge	189:f392fc9709a3	174	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /!< General or unknown error /
AnnaBridge	189:f392fc9709a3	175	#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /!< The card could not sustain data reading in stream rmode /
AnnaBridge	189:f392fc9709a3	176	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /!< The card could not sustain data programming in stream mode /
AnnaBridge	189:f392fc9709a3	177	#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /!< CID/CSD overwrite error /
AnnaBridge	189:f392fc9709a3	178	#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /!< Only partial address space was erased /
AnnaBridge	189:f392fc9709a3	179	#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /!< Command has been executed without using internal ECC /
AnnaBridge	189:f392fc9709a3	180	#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
AnnaBridge	189:f392fc9709a3	181	of erase sequence command was received */
AnnaBridge	189:f392fc9709a3	182	#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /!< Error in sequence of authentication /
AnnaBridge	189:f392fc9709a3	183	#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /!< Error in case of invalid voltage range /
AnnaBridge	189:f392fc9709a3	184	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /!< Error when addressed block is out of range /
AnnaBridge	189:f392fc9709a3	185	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /!< Error when command request is not applicable /
AnnaBridge	189:f392fc9709a3	186	#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /!< the used parameter is not valid /
AnnaBridge	189:f392fc9709a3	187	#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /!< Error when feature is not insupported /
AnnaBridge	189:f392fc9709a3	188	#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /!< Error when transfer process is busy /
AnnaBridge	189:f392fc9709a3	189	#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /!< Error while DMA transfer /
AnnaBridge	189:f392fc9709a3	190	#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /!< Timeout error /
AnnaBridge	189:f392fc9709a3	191
AnnaBridge	189:f392fc9709a3	192	/**
AnnaBridge	189:f392fc9709a3	193	* @brief SDMMC Commands Index
AnnaBridge	189:f392fc9709a3	194	*/
AnnaBridge	189:f392fc9709a3	195	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /!< Resets the SD memory card. /
AnnaBridge	189:f392fc9709a3	196	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /!< Sends host capacity support information and activates the card's initialization process. /
AnnaBridge	189:f392fc9709a3	197	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
AnnaBridge	189:f392fc9709a3	198	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /!< Asks the card to publish a new relative address (RCA). /
AnnaBridge	189:f392fc9709a3	199	#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /!< Programs the DSR of all cards. /
AnnaBridge	189:f392fc9709a3	200	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge	189:f392fc9709a3	201	operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	189:f392fc9709a3	202	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
AnnaBridge	189:f392fc9709a3	203	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /!< Selects the card by its own relative address and gets deselected by any other address /
AnnaBridge	189:f392fc9709a3	204	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge	189:f392fc9709a3	205	and asks the card whether card supports voltage. */
AnnaBridge	189:f392fc9709a3	206	#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
AnnaBridge	189:f392fc9709a3	207	#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /!< Addressed card sends its card identification (CID) on the CMD line. /
AnnaBridge	189:f392fc9709a3	208	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	209	#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /!< SD card Voltage switch to 1.8V mode. /
AnnaBridge	189:f392fc9709a3	210	#else
AnnaBridge	189:f392fc9709a3	211	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /!< SD card doesn't support it. /
AnnaBridge	189:f392fc9709a3	212	#endif
AnnaBridge	189:f392fc9709a3	213	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /!< Forces the card to stop transmission. /
AnnaBridge	189:f392fc9709a3	214	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /!< Addressed card sends its status register. /
AnnaBridge	189:f392fc9709a3	215	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /!< Reserved /
AnnaBridge	189:f392fc9709a3	216	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /!< Sends an addressed card into the inactive state. /
AnnaBridge	189:f392fc9709a3	217	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge	189:f392fc9709a3	218	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge	189:f392fc9709a3	219	for SDHS and SDXC. */
AnnaBridge	189:f392fc9709a3	220	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	189:f392fc9709a3	221	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	189:f392fc9709a3	222	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge	189:f392fc9709a3	223	STOP_TRANSMISSION command. */
AnnaBridge	189:f392fc9709a3	224	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
AnnaBridge	189:f392fc9709a3	225	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /!< Speed class control command. /
AnnaBridge	189:f392fc9709a3	226	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /!< Specify block count for CMD18 and CMD25. /
AnnaBridge	189:f392fc9709a3	227	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge	189:f392fc9709a3	228	fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge	189:f392fc9709a3	229	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
AnnaBridge	189:f392fc9709a3	230	#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /!< Reserved for manufacturers. /
AnnaBridge	189:f392fc9709a3	231	#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /!< Programming of the programmable bits of the CSD. /
AnnaBridge	189:f392fc9709a3	232	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /!< Sets the write protection bit of the addressed group. /
AnnaBridge	189:f392fc9709a3	233	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /!< Clears the write protection bit of the addressed group. /
AnnaBridge	189:f392fc9709a3	234	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /!< Asks the card to send the status of the write protection bits. /
AnnaBridge	189:f392fc9709a3	235	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /!< Sets the address of the first write block to be erased. (For SD card only). /
AnnaBridge	189:f392fc9709a3	236	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /!< Sets the address of the last write block of the continuous range to be erased. /
AnnaBridge	189:f392fc9709a3	237	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge	189:f392fc9709a3	238	system set by switch function command (CMD6). */
AnnaBridge	189:f392fc9709a3	239	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge	189:f392fc9709a3	240	Reserved for each command system set by switch function command (CMD6). */
AnnaBridge	189:f392fc9709a3	241	#define SDMMC_CMD_ERASE ((uint8_t)38U) /!< Reserved for SD security applications. /
AnnaBridge	189:f392fc9709a3	242	#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	189:f392fc9709a3	243	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /!< SD card doesn't support it (Reserved). /
AnnaBridge	189:f392fc9709a3	244	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge	189:f392fc9709a3	245	the SET_BLOCK_LEN command. */
AnnaBridge	189:f392fc9709a3	246	#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge	189:f392fc9709a3	247	than a standard command. */
AnnaBridge	189:f392fc9709a3	248	#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge	189:f392fc9709a3	249	for general purpose/application specific commands. */
AnnaBridge	189:f392fc9709a3	250	#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /!< No command /
AnnaBridge	189:f392fc9709a3	251
AnnaBridge	189:f392fc9709a3	252	/**
AnnaBridge	189:f392fc9709a3	253	* @brief Following commands are SD Card Specific commands.
AnnaBridge	189:f392fc9709a3	254	* SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge	189:f392fc9709a3	255	*/
AnnaBridge	189:f392fc9709a3	256	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge	189:f392fc9709a3	257	widths are given in SCR register. */
AnnaBridge	189:f392fc9709a3	258	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /!< (ACMD13) Sends the SD status. /
AnnaBridge	189:f392fc9709a3	259	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge	189:f392fc9709a3	260	32bit+CRC data block. */
AnnaBridge	189:f392fc9709a3	261	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge	189:f392fc9709a3	262	send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge	189:f392fc9709a3	263	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
AnnaBridge	189:f392fc9709a3	264	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /!< Reads the SD Configuration Register (SCR). /
AnnaBridge	189:f392fc9709a3	265	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	189:f392fc9709a3	266	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /!< For SD I/O card only, reserved for security specification. /
AnnaBridge	189:f392fc9709a3	267
AnnaBridge	189:f392fc9709a3	268	/**
AnnaBridge	189:f392fc9709a3	269	* @brief Following commands are SD Card Specific security commands.
AnnaBridge	189:f392fc9709a3	270	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge	189:f392fc9709a3	271	*/
AnnaBridge	189:f392fc9709a3	272	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
AnnaBridge	189:f392fc9709a3	273	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
AnnaBridge	189:f392fc9709a3	274	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
AnnaBridge	189:f392fc9709a3	275	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
AnnaBridge	189:f392fc9709a3	276	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
AnnaBridge	189:f392fc9709a3	277	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
AnnaBridge	189:f392fc9709a3	278	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
AnnaBridge	189:f392fc9709a3	279	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
AnnaBridge	189:f392fc9709a3	280	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
AnnaBridge	189:f392fc9709a3	281	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
AnnaBridge	189:f392fc9709a3	282	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
AnnaBridge	189:f392fc9709a3	283
AnnaBridge	189:f392fc9709a3	284	/**
AnnaBridge	189:f392fc9709a3	285	* @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge	189:f392fc9709a3	286	*/
AnnaBridge	189:f392fc9709a3	287	#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
AnnaBridge	189:f392fc9709a3	288	#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
AnnaBridge	189:f392fc9709a3	289	#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
AnnaBridge	189:f392fc9709a3	290	#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
AnnaBridge	189:f392fc9709a3	291	#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
AnnaBridge	189:f392fc9709a3	292	#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
AnnaBridge	189:f392fc9709a3	293	#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
AnnaBridge	189:f392fc9709a3	294	#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
AnnaBridge	189:f392fc9709a3	295	#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
AnnaBridge	189:f392fc9709a3	296	#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
AnnaBridge	189:f392fc9709a3	297	#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
AnnaBridge	189:f392fc9709a3	298	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
AnnaBridge	189:f392fc9709a3	299	#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
AnnaBridge	189:f392fc9709a3	300	#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
AnnaBridge	189:f392fc9709a3	301	#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
AnnaBridge	189:f392fc9709a3	302	#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
AnnaBridge	189:f392fc9709a3	303	#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
AnnaBridge	189:f392fc9709a3	304	#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
AnnaBridge	189:f392fc9709a3	305	#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
AnnaBridge	189:f392fc9709a3	306	#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
AnnaBridge	189:f392fc9709a3	307
AnnaBridge	189:f392fc9709a3	308	/**
AnnaBridge	189:f392fc9709a3	309	* @brief Masks for R6 Response
AnnaBridge	189:f392fc9709a3	310	*/
AnnaBridge	189:f392fc9709a3	311	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
AnnaBridge	189:f392fc9709a3	312	#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
AnnaBridge	189:f392fc9709a3	313	#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
AnnaBridge	189:f392fc9709a3	314
AnnaBridge	189:f392fc9709a3	315	#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
AnnaBridge	189:f392fc9709a3	316	#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
AnnaBridge	189:f392fc9709a3	317	#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	318	#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
AnnaBridge	189:f392fc9709a3	319	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	320	#define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
AnnaBridge	189:f392fc9709a3	321	#define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
AnnaBridge	189:f392fc9709a3	322	#define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
AnnaBridge	189:f392fc9709a3	323	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	324
AnnaBridge	189:f392fc9709a3	325	#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	189:f392fc9709a3	326
AnnaBridge	189:f392fc9709a3	327	#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge	189:f392fc9709a3	328
AnnaBridge	189:f392fc9709a3	329	#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	330
AnnaBridge	189:f392fc9709a3	331	#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
AnnaBridge	189:f392fc9709a3	332	#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
AnnaBridge	189:f392fc9709a3	333	#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
AnnaBridge	189:f392fc9709a3	334
AnnaBridge	189:f392fc9709a3	335	#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
AnnaBridge	189:f392fc9709a3	336
AnnaBridge	189:f392fc9709a3	337	#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
AnnaBridge	189:f392fc9709a3	338	#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
AnnaBridge	189:f392fc9709a3	339	#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
AnnaBridge	189:f392fc9709a3	340	#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
AnnaBridge	189:f392fc9709a3	341	#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
AnnaBridge	189:f392fc9709a3	342
AnnaBridge	189:f392fc9709a3	343	#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
AnnaBridge	189:f392fc9709a3	344	#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
AnnaBridge	189:f392fc9709a3	345
AnnaBridge	189:f392fc9709a3	346	/**
AnnaBridge	189:f392fc9709a3	347	* @brief Command Class supported
AnnaBridge	189:f392fc9709a3	348	*/
AnnaBridge	189:f392fc9709a3	349	#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
AnnaBridge	189:f392fc9709a3	350
AnnaBridge	189:f392fc9709a3	351	#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
AnnaBridge	189:f392fc9709a3	352	#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
AnnaBridge	189:f392fc9709a3	353	#define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
AnnaBridge	189:f392fc9709a3	354
AnnaBridge	189:f392fc9709a3	355	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
AnnaBridge	189:f392fc9709a3	356	* @{
AnnaBridge	189:f392fc9709a3	357	*/
AnnaBridge	189:f392fc9709a3	358	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	359	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
AnnaBridge	189:f392fc9709a3	360
AnnaBridge	189:f392fc9709a3	361	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
AnnaBridge	189:f392fc9709a3	362	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
AnnaBridge	189:f392fc9709a3	363	/**
AnnaBridge	189:f392fc9709a3	364	* @}
AnnaBridge	189:f392fc9709a3	365	*/
AnnaBridge	189:f392fc9709a3	366
AnnaBridge	189:f392fc9709a3	367	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	368	/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
AnnaBridge	189:f392fc9709a3	369	* @{
AnnaBridge	189:f392fc9709a3	370	*/
AnnaBridge	189:f392fc9709a3	371	#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	372	#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
AnnaBridge	189:f392fc9709a3	373
AnnaBridge	189:f392fc9709a3	374	#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	375	((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
AnnaBridge	189:f392fc9709a3	376	/**
AnnaBridge	189:f392fc9709a3	377	* @}
AnnaBridge	189:f392fc9709a3	378	*/
AnnaBridge	189:f392fc9709a3	379	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	380
AnnaBridge	189:f392fc9709a3	381	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
AnnaBridge	189:f392fc9709a3	382	* @{
AnnaBridge	189:f392fc9709a3	383	*/
AnnaBridge	189:f392fc9709a3	384	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	385	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
AnnaBridge	189:f392fc9709a3	386
AnnaBridge	189:f392fc9709a3	387	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	388	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge	189:f392fc9709a3	389	/**
AnnaBridge	189:f392fc9709a3	390	* @}
AnnaBridge	189:f392fc9709a3	391	*/
AnnaBridge	189:f392fc9709a3	392
AnnaBridge	189:f392fc9709a3	393	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
AnnaBridge	189:f392fc9709a3	394	* @{
AnnaBridge	189:f392fc9709a3	395	*/
AnnaBridge	189:f392fc9709a3	396	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	397	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
AnnaBridge	189:f392fc9709a3	398	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
AnnaBridge	189:f392fc9709a3	399
AnnaBridge	189:f392fc9709a3	400	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
AnnaBridge	189:f392fc9709a3	401	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
AnnaBridge	189:f392fc9709a3	402	((WIDE) == SDMMC_BUS_WIDE_8B))
AnnaBridge	189:f392fc9709a3	403	/**
AnnaBridge	189:f392fc9709a3	404	* @}
AnnaBridge	189:f392fc9709a3	405	*/
AnnaBridge	189:f392fc9709a3	406
AnnaBridge	189:f392fc9709a3	407	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge	189:f392fc9709a3	408	* @{
AnnaBridge	189:f392fc9709a3	409	*/
AnnaBridge	189:f392fc9709a3	410	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	411	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
AnnaBridge	189:f392fc9709a3	412
AnnaBridge	189:f392fc9709a3	413	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	414	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge	189:f392fc9709a3	415	/**
AnnaBridge	189:f392fc9709a3	416	* @}
AnnaBridge	189:f392fc9709a3	417	*/
AnnaBridge	189:f392fc9709a3	418
AnnaBridge	189:f392fc9709a3	419	/** @defgroup SDMMC_LL_Clock_Division Clock Division
AnnaBridge	189:f392fc9709a3	420	* @{
AnnaBridge	189:f392fc9709a3	421	*/
AnnaBridge	189:f392fc9709a3	422	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	423	/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
AnnaBridge	189:f392fc9709a3	424	#define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400)
AnnaBridge	189:f392fc9709a3	425	#else
AnnaBridge	189:f392fc9709a3	426	#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
AnnaBridge	189:f392fc9709a3	427	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	428	/**
AnnaBridge	189:f392fc9709a3	429	* @}
AnnaBridge	189:f392fc9709a3	430	*/
AnnaBridge	189:f392fc9709a3	431
AnnaBridge	189:f392fc9709a3	432
AnnaBridge	189:f392fc9709a3	433	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	434	/** @defgroup SDMMC_LL_Transceiver Transceiver
AnnaBridge	189:f392fc9709a3	435	* @{
AnnaBridge	189:f392fc9709a3	436	*/
AnnaBridge	189:f392fc9709a3	437	#define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	438	#define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U)
AnnaBridge	189:f392fc9709a3	439
AnnaBridge	189:f392fc9709a3	440	#define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	441	((MODE) == SDMMC_TRANSCEIVER_ENABLE))
AnnaBridge	189:f392fc9709a3	442	/**
AnnaBridge	189:f392fc9709a3	443	* @}
AnnaBridge	189:f392fc9709a3	444	*/
AnnaBridge	189:f392fc9709a3	445	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	446
AnnaBridge	189:f392fc9709a3	447	/** @defgroup SDMMC_LL_Command_Index Command Index
AnnaBridge	189:f392fc9709a3	448	* @{
AnnaBridge	189:f392fc9709a3	449	*/
AnnaBridge	189:f392fc9709a3	450	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
AnnaBridge	189:f392fc9709a3	451	/**
AnnaBridge	189:f392fc9709a3	452	* @}
AnnaBridge	189:f392fc9709a3	453	*/
AnnaBridge	189:f392fc9709a3	454
AnnaBridge	189:f392fc9709a3	455	/** @defgroup SDMMC_LL_Response_Type Response Type
AnnaBridge	189:f392fc9709a3	456	* @{
AnnaBridge	189:f392fc9709a3	457	*/
AnnaBridge	189:f392fc9709a3	458	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	459	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
AnnaBridge	189:f392fc9709a3	460	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
AnnaBridge	189:f392fc9709a3	461
AnnaBridge	189:f392fc9709a3	462	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
AnnaBridge	189:f392fc9709a3	463	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
AnnaBridge	189:f392fc9709a3	464	((RESPONSE) == SDMMC_RESPONSE_LONG))
AnnaBridge	189:f392fc9709a3	465	/**
AnnaBridge	189:f392fc9709a3	466	* @}
AnnaBridge	189:f392fc9709a3	467	*/
AnnaBridge	189:f392fc9709a3	468
AnnaBridge	189:f392fc9709a3	469	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge	189:f392fc9709a3	470	* @{
AnnaBridge	189:f392fc9709a3	471	*/
AnnaBridge	189:f392fc9709a3	472	#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	473	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
AnnaBridge	189:f392fc9709a3	474	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
AnnaBridge	189:f392fc9709a3	475
AnnaBridge	189:f392fc9709a3	476	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
AnnaBridge	189:f392fc9709a3	477	((WAIT) == SDMMC_WAIT_IT) \|\| \
AnnaBridge	189:f392fc9709a3	478	((WAIT) == SDMMC_WAIT_PEND))
AnnaBridge	189:f392fc9709a3	479	/**
AnnaBridge	189:f392fc9709a3	480	* @}
AnnaBridge	189:f392fc9709a3	481	*/
AnnaBridge	189:f392fc9709a3	482
AnnaBridge	189:f392fc9709a3	483	/** @defgroup SDMMC_LL_CPSM_State CPSM State
AnnaBridge	189:f392fc9709a3	484	* @{
AnnaBridge	189:f392fc9709a3	485	*/
AnnaBridge	189:f392fc9709a3	486	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	487	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
AnnaBridge	189:f392fc9709a3	488
AnnaBridge	189:f392fc9709a3	489	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
AnnaBridge	189:f392fc9709a3	490	((CPSM) == SDMMC_CPSM_ENABLE))
AnnaBridge	189:f392fc9709a3	491	/**
AnnaBridge	189:f392fc9709a3	492	* @}
AnnaBridge	189:f392fc9709a3	493	*/
AnnaBridge	189:f392fc9709a3	494
AnnaBridge	189:f392fc9709a3	495	/** @defgroup SDMMC_LL_Response_Registers Response Register
AnnaBridge	189:f392fc9709a3	496	* @{
AnnaBridge	189:f392fc9709a3	497	*/
AnnaBridge	189:f392fc9709a3	498	#define SDMMC_RESP1 ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	499	#define SDMMC_RESP2 ((uint32_t)0x00000004U)
AnnaBridge	189:f392fc9709a3	500	#define SDMMC_RESP3 ((uint32_t)0x00000008U)
AnnaBridge	189:f392fc9709a3	501	#define SDMMC_RESP4 ((uint32_t)0x0000000CU)
AnnaBridge	189:f392fc9709a3	502
AnnaBridge	189:f392fc9709a3	503	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
AnnaBridge	189:f392fc9709a3	504	((RESP) == SDMMC_RESP2) \|\| \
AnnaBridge	189:f392fc9709a3	505	((RESP) == SDMMC_RESP3) \|\| \
AnnaBridge	189:f392fc9709a3	506	((RESP) == SDMMC_RESP4))
AnnaBridge	189:f392fc9709a3	507
AnnaBridge	189:f392fc9709a3	508	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	509	/** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
AnnaBridge	189:f392fc9709a3	510	* @{
AnnaBridge	189:f392fc9709a3	511	*/
AnnaBridge	189:f392fc9709a3	512	#define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
AnnaBridge	189:f392fc9709a3	513	#define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
AnnaBridge	189:f392fc9709a3	514	#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN \| SDMMC_IDMA_IDMABMODE)
AnnaBridge	189:f392fc9709a3	515	#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN \| SDMMC_IDMA_IDMABMODE \| SDMMC_IDMA_IDMABACT)
AnnaBridge	189:f392fc9709a3	516
AnnaBridge	189:f392fc9709a3	517	/**
AnnaBridge	189:f392fc9709a3	518	* @}
AnnaBridge	189:f392fc9709a3	519	*/
AnnaBridge	189:f392fc9709a3	520	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	521	/**
AnnaBridge	189:f392fc9709a3	522	* @}
AnnaBridge	189:f392fc9709a3	523	*/
AnnaBridge	189:f392fc9709a3	524
AnnaBridge	189:f392fc9709a3	525	/** @defgroup SDMMC_LL_Data_Length Data Lenght
AnnaBridge	189:f392fc9709a3	526	* @{
AnnaBridge	189:f392fc9709a3	527	*/
AnnaBridge	189:f392fc9709a3	528	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
AnnaBridge	189:f392fc9709a3	529	/**
AnnaBridge	189:f392fc9709a3	530	* @}
AnnaBridge	189:f392fc9709a3	531	*/
AnnaBridge	189:f392fc9709a3	532
AnnaBridge	189:f392fc9709a3	533	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
AnnaBridge	189:f392fc9709a3	534	* @{
AnnaBridge	189:f392fc9709a3	535	*/
AnnaBridge	189:f392fc9709a3	536	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	537	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
AnnaBridge	189:f392fc9709a3	538	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
AnnaBridge	189:f392fc9709a3	539	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
AnnaBridge	189:f392fc9709a3	540	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
AnnaBridge	189:f392fc9709a3	541	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	189:f392fc9709a3	542	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	189:f392fc9709a3	543	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge	189:f392fc9709a3	544	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
AnnaBridge	189:f392fc9709a3	545	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	189:f392fc9709a3	546	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	189:f392fc9709a3	547	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	189:f392fc9709a3	548	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	189:f392fc9709a3	549	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	189:f392fc9709a3	550	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge	189:f392fc9709a3	551
AnnaBridge	189:f392fc9709a3	552	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
AnnaBridge	189:f392fc9709a3	553	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
AnnaBridge	189:f392fc9709a3	554	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
AnnaBridge	189:f392fc9709a3	555	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
AnnaBridge	189:f392fc9709a3	556	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
AnnaBridge	189:f392fc9709a3	557	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
AnnaBridge	189:f392fc9709a3	558	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
AnnaBridge	189:f392fc9709a3	559	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
AnnaBridge	189:f392fc9709a3	560	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
AnnaBridge	189:f392fc9709a3	561	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
AnnaBridge	189:f392fc9709a3	562	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
AnnaBridge	189:f392fc9709a3	563	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
AnnaBridge	189:f392fc9709a3	564	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
AnnaBridge	189:f392fc9709a3	565	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
AnnaBridge	189:f392fc9709a3	566	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
AnnaBridge	189:f392fc9709a3	567	/**
AnnaBridge	189:f392fc9709a3	568	* @}
AnnaBridge	189:f392fc9709a3	569	*/
AnnaBridge	189:f392fc9709a3	570
AnnaBridge	189:f392fc9709a3	571	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
AnnaBridge	189:f392fc9709a3	572	* @{
AnnaBridge	189:f392fc9709a3	573	*/
AnnaBridge	189:f392fc9709a3	574	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	575	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
AnnaBridge	189:f392fc9709a3	576
AnnaBridge	189:f392fc9709a3	577	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
AnnaBridge	189:f392fc9709a3	578	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
AnnaBridge	189:f392fc9709a3	579	/**
AnnaBridge	189:f392fc9709a3	580	* @}
AnnaBridge	189:f392fc9709a3	581	*/
AnnaBridge	189:f392fc9709a3	582
AnnaBridge	189:f392fc9709a3	583	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
AnnaBridge	189:f392fc9709a3	584	* @{
AnnaBridge	189:f392fc9709a3	585	*/
AnnaBridge	189:f392fc9709a3	586	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	587	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	588	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
AnnaBridge	189:f392fc9709a3	589	#else
AnnaBridge	189:f392fc9709a3	590	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
AnnaBridge	189:f392fc9709a3	591	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	592
AnnaBridge	189:f392fc9709a3	593	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
AnnaBridge	189:f392fc9709a3	594	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
AnnaBridge	189:f392fc9709a3	595	/**
AnnaBridge	189:f392fc9709a3	596	* @}
AnnaBridge	189:f392fc9709a3	597	*/
AnnaBridge	189:f392fc9709a3	598
AnnaBridge	189:f392fc9709a3	599	/** @defgroup SDMMC_LL_DPSM_State DPSM State
AnnaBridge	189:f392fc9709a3	600	* @{
AnnaBridge	189:f392fc9709a3	601	*/
AnnaBridge	189:f392fc9709a3	602	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	603	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
AnnaBridge	189:f392fc9709a3	604
AnnaBridge	189:f392fc9709a3	605	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
AnnaBridge	189:f392fc9709a3	606	((DPSM) == SDMMC_DPSM_ENABLE))
AnnaBridge	189:f392fc9709a3	607	/**
AnnaBridge	189:f392fc9709a3	608	* @}
AnnaBridge	189:f392fc9709a3	609	*/
AnnaBridge	189:f392fc9709a3	610
AnnaBridge	189:f392fc9709a3	611	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge	189:f392fc9709a3	612	* @{
AnnaBridge	189:f392fc9709a3	613	*/
AnnaBridge	189:f392fc9709a3	614	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
AnnaBridge	189:f392fc9709a3	615	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
AnnaBridge	189:f392fc9709a3	616
AnnaBridge	189:f392fc9709a3	617	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
AnnaBridge	189:f392fc9709a3	618	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
AnnaBridge	189:f392fc9709a3	619	/**
AnnaBridge	189:f392fc9709a3	620	* @}
AnnaBridge	189:f392fc9709a3	621	*/
AnnaBridge	189:f392fc9709a3	622
AnnaBridge	189:f392fc9709a3	623	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
AnnaBridge	189:f392fc9709a3	624	* @{
AnnaBridge	189:f392fc9709a3	625	*/
AnnaBridge	189:f392fc9709a3	626	#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
AnnaBridge	189:f392fc9709a3	627	#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
AnnaBridge	189:f392fc9709a3	628	#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
AnnaBridge	189:f392fc9709a3	629	#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
AnnaBridge	189:f392fc9709a3	630	#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
AnnaBridge	189:f392fc9709a3	631	#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
AnnaBridge	189:f392fc9709a3	632	#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
AnnaBridge	189:f392fc9709a3	633	#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
AnnaBridge	189:f392fc9709a3	634	#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
AnnaBridge	189:f392fc9709a3	635	#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
AnnaBridge	189:f392fc9709a3	636	#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
AnnaBridge	189:f392fc9709a3	637	#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
AnnaBridge	189:f392fc9709a3	638	#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
AnnaBridge	189:f392fc9709a3	639	#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
AnnaBridge	189:f392fc9709a3	640	#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
AnnaBridge	189:f392fc9709a3	641	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	642	#define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
AnnaBridge	189:f392fc9709a3	643	#define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
AnnaBridge	189:f392fc9709a3	644	#define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
AnnaBridge	189:f392fc9709a3	645	#define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
AnnaBridge	189:f392fc9709a3	646	#define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
AnnaBridge	189:f392fc9709a3	647	#define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
AnnaBridge	189:f392fc9709a3	648	#define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
AnnaBridge	189:f392fc9709a3	649	#define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
AnnaBridge	189:f392fc9709a3	650	#else
AnnaBridge	189:f392fc9709a3	651	#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE
AnnaBridge	189:f392fc9709a3	652	#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE
AnnaBridge	189:f392fc9709a3	653	#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE
AnnaBridge	189:f392fc9709a3	654	#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE
AnnaBridge	189:f392fc9709a3	655	#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE
AnnaBridge	189:f392fc9709a3	656	#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE
AnnaBridge	189:f392fc9709a3	657	#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE
AnnaBridge	189:f392fc9709a3	658	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	659	/**
AnnaBridge	189:f392fc9709a3	660	* @}
AnnaBridge	189:f392fc9709a3	661	*/
AnnaBridge	189:f392fc9709a3	662
AnnaBridge	189:f392fc9709a3	663	/** @defgroup SDMMC_LL_Flags Flags
AnnaBridge	189:f392fc9709a3	664	* @{
AnnaBridge	189:f392fc9709a3	665	*/
AnnaBridge	189:f392fc9709a3	666	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
AnnaBridge	189:f392fc9709a3	667	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
AnnaBridge	189:f392fc9709a3	668	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
AnnaBridge	189:f392fc9709a3	669	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
AnnaBridge	189:f392fc9709a3	670	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
AnnaBridge	189:f392fc9709a3	671	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
AnnaBridge	189:f392fc9709a3	672	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
AnnaBridge	189:f392fc9709a3	673	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
AnnaBridge	189:f392fc9709a3	674	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
AnnaBridge	189:f392fc9709a3	675	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
AnnaBridge	189:f392fc9709a3	676	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
AnnaBridge	189:f392fc9709a3	677	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
AnnaBridge	189:f392fc9709a3	678	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
AnnaBridge	189:f392fc9709a3	679	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
AnnaBridge	189:f392fc9709a3	680	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
AnnaBridge	189:f392fc9709a3	681	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge	189:f392fc9709a3	682	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge	189:f392fc9709a3	683	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	684	#define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
AnnaBridge	189:f392fc9709a3	685	#define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
AnnaBridge	189:f392fc9709a3	686	#define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
AnnaBridge	189:f392fc9709a3	687	#define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
AnnaBridge	189:f392fc9709a3	688	#define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
AnnaBridge	189:f392fc9709a3	689	#define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
AnnaBridge	189:f392fc9709a3	690	#define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
AnnaBridge	189:f392fc9709a3	691	#define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
AnnaBridge	189:f392fc9709a3	692	#define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
AnnaBridge	189:f392fc9709a3	693	#define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
AnnaBridge	189:f392fc9709a3	694	#define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
AnnaBridge	189:f392fc9709a3	695	#define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
AnnaBridge	189:f392fc9709a3	696	#else
AnnaBridge	189:f392fc9709a3	697	#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
AnnaBridge	189:f392fc9709a3	698	#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
AnnaBridge	189:f392fc9709a3	699	#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
AnnaBridge	189:f392fc9709a3	700	#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
AnnaBridge	189:f392fc9709a3	701	#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
AnnaBridge	189:f392fc9709a3	702	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	703
AnnaBridge	189:f392fc9709a3	704	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	705	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
AnnaBridge	189:f392fc9709a3	706	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
AnnaBridge	189:f392fc9709a3	707	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
AnnaBridge	189:f392fc9709a3	708	SDMMC_FLAG_DHOLD \| SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_DABORT \|\
AnnaBridge	189:f392fc9709a3	709	SDMMC_FLAG_BUSYD0END \| SDMMC_FLAG_SDIOIT \| SDMMC_FLAG_ACKFAIL \|\
AnnaBridge	189:f392fc9709a3	710	SDMMC_FLAG_ACKTIMEOUT \| SDMMC_FLAG_VSWEND \| SDMMC_FLAG_CKSTOP \|\
AnnaBridge	189:f392fc9709a3	711	SDMMC_FLAG_IDMATE \| SDMMC_FLAG_IDMABTC))
AnnaBridge	189:f392fc9709a3	712
AnnaBridge	189:f392fc9709a3	713	#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_CTIMEOUT \| SDMMC_FLAG_CMDREND \|\
AnnaBridge	189:f392fc9709a3	714	SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_BUSYD0END))
AnnaBridge	189:f392fc9709a3	715
AnnaBridge	189:f392fc9709a3	716	#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \|\
AnnaBridge	189:f392fc9709a3	717	SDMMC_FLAG_RXOVERR \| SDMMC_FLAG_DATAEND \| SDMMC_FLAG_DHOLD \|\
AnnaBridge	189:f392fc9709a3	718	SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_DABORT \| SDMMC_FLAG_IDMATE \|\
AnnaBridge	189:f392fc9709a3	719	SDMMC_FLAG_IDMABTC))
AnnaBridge	189:f392fc9709a3	720
AnnaBridge	189:f392fc9709a3	721	#else
AnnaBridge	189:f392fc9709a3	722	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
AnnaBridge	189:f392fc9709a3	723	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
AnnaBridge	189:f392fc9709a3	724	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
AnnaBridge	189:f392fc9709a3	725	SDMMC_FLAG_DBCKEND \| SDMMC_FLAG_SDIOIT))
AnnaBridge	189:f392fc9709a3	726
AnnaBridge	189:f392fc9709a3	727	#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_CTIMEOUT \| SDMMC_FLAG_CMDREND \|\
AnnaBridge	189:f392fc9709a3	728	SDMMC_FLAG_CMDSENT))
AnnaBridge	189:f392fc9709a3	729
AnnaBridge	189:f392fc9709a3	730	#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \|\
AnnaBridge	189:f392fc9709a3	731	SDMMC_FLAG_RXOVERR \| SDMMC_FLAG_DATAEND \| SDMMC_FLAG_DBCKEND))
AnnaBridge	189:f392fc9709a3	732	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	733
AnnaBridge	189:f392fc9709a3	734	/**
AnnaBridge	189:f392fc9709a3	735	* @}
AnnaBridge	189:f392fc9709a3	736	*/
AnnaBridge	189:f392fc9709a3	737
AnnaBridge	189:f392fc9709a3	738	/**
AnnaBridge	189:f392fc9709a3	739	* @}
AnnaBridge	189:f392fc9709a3	740	*/
AnnaBridge	189:f392fc9709a3	741
AnnaBridge	189:f392fc9709a3	742	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	743	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
AnnaBridge	189:f392fc9709a3	744	* @{
AnnaBridge	189:f392fc9709a3	745	*/
AnnaBridge	189:f392fc9709a3	746
AnnaBridge	189:f392fc9709a3	747	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
AnnaBridge	189:f392fc9709a3	748	* @brief SDMMC_LL registers bit address in the alias region
AnnaBridge	189:f392fc9709a3	749	* @{
AnnaBridge	189:f392fc9709a3	750	*/
AnnaBridge	189:f392fc9709a3	751	/* ---------------------- SDMMC registers bit mask --------------------------- */
AnnaBridge	189:f392fc9709a3	752	/* --- CLKCR Register ---*/
AnnaBridge	189:f392fc9709a3	753	/* CLKCR register clear mask */
AnnaBridge	189:f392fc9709a3	754	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	755	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
AnnaBridge	189:f392fc9709a3	756	SDMMC_CLKCR_WIDBUS \|\
AnnaBridge	189:f392fc9709a3	757	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
AnnaBridge	189:f392fc9709a3	758	#else
AnnaBridge	189:f392fc9709a3	759	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
AnnaBridge	189:f392fc9709a3	760	SDMMC_CLKCR_BYPASS \| SDMMC_CLKCR_WIDBUS \|\
AnnaBridge	189:f392fc9709a3	761	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
AnnaBridge	189:f392fc9709a3	762	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	763
AnnaBridge	189:f392fc9709a3	764	/* --- DCTRL Register ---*/
AnnaBridge	189:f392fc9709a3	765	/* SDMMC DCTRL Clear Mask */
AnnaBridge	189:f392fc9709a3	766	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
AnnaBridge	189:f392fc9709a3	767	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
AnnaBridge	189:f392fc9709a3	768
AnnaBridge	189:f392fc9709a3	769	/* --- CMD Register ---*/
AnnaBridge	189:f392fc9709a3	770	/* CMD Register clear mask */
AnnaBridge	189:f392fc9709a3	771	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	772	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
AnnaBridge	189:f392fc9709a3	773	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
AnnaBridge	189:f392fc9709a3	774	SDMMC_CMD_CPSMEN \| SDMMC_CMD_CMDSUSPEND))
AnnaBridge	189:f392fc9709a3	775	#else
AnnaBridge	189:f392fc9709a3	776	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
AnnaBridge	189:f392fc9709a3	777	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
AnnaBridge	189:f392fc9709a3	778	SDMMC_CMD_CPSMEN \| SDMMC_CMD_SDIOSUSPEND))
AnnaBridge	189:f392fc9709a3	779	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	780
AnnaBridge	189:f392fc9709a3	781	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	782	/* SDMMC Initialization Frequency (400KHz max) */
AnnaBridge	189:f392fc9709a3	783	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x3C) /* 48MHz / (SDMMC_INIT_CLK_DIV * 2) < 400KHz */
AnnaBridge	189:f392fc9709a3	784
AnnaBridge	189:f392fc9709a3	785	/* SDMMC Data Transfer Frequency (25MHz max) */
AnnaBridge	189:f392fc9709a3	786	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x1) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV * 2) < 25MHz */
AnnaBridge	189:f392fc9709a3	787	#else
AnnaBridge	189:f392fc9709a3	788	/* SDMMC Initialization Frequency (400KHz max) */
AnnaBridge	189:f392fc9709a3	789	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
AnnaBridge	189:f392fc9709a3	790
AnnaBridge	189:f392fc9709a3	791	/* SDMMC Data Transfer Frequency (25MHz max) */
AnnaBridge	189:f392fc9709a3	792	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
AnnaBridge	189:f392fc9709a3	793	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	794
AnnaBridge	189:f392fc9709a3	795	/**
AnnaBridge	189:f392fc9709a3	796	* @}
AnnaBridge	189:f392fc9709a3	797	*/
AnnaBridge	189:f392fc9709a3	798
AnnaBridge	189:f392fc9709a3	799	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge	189:f392fc9709a3	800	* @brief macros to handle interrupts and specific clock configurations
AnnaBridge	189:f392fc9709a3	801	* @{
AnnaBridge	189:f392fc9709a3	802	*/
AnnaBridge	189:f392fc9709a3	803
AnnaBridge	189:f392fc9709a3	804	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	805	/**
AnnaBridge	189:f392fc9709a3	806	* @brief Enable the SDMMC device.
AnnaBridge	189:f392fc9709a3	807	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	189:f392fc9709a3	808	* @retval None
AnnaBridge	189:f392fc9709a3	809	*/
AnnaBridge	189:f392fc9709a3	810	#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN)
AnnaBridge	189:f392fc9709a3	811
AnnaBridge	189:f392fc9709a3	812	/**
AnnaBridge	189:f392fc9709a3	813	* @brief Disable the SDMMC device.
AnnaBridge	189:f392fc9709a3	814	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	189:f392fc9709a3	815	* @retval None
AnnaBridge	189:f392fc9709a3	816	*/
AnnaBridge	189:f392fc9709a3	817	#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
AnnaBridge	189:f392fc9709a3	818
AnnaBridge	189:f392fc9709a3	819	/**
AnnaBridge	189:f392fc9709a3	820	* @brief Enable the SDMMC DMA transfer.
AnnaBridge	189:f392fc9709a3	821	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	189:f392fc9709a3	822	* @retval None
AnnaBridge	189:f392fc9709a3	823	*/
AnnaBridge	189:f392fc9709a3	824	#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN)
AnnaBridge	189:f392fc9709a3	825	/**
AnnaBridge	189:f392fc9709a3	826	* @brief Disable the SDMMC DMA transfer.
AnnaBridge	189:f392fc9709a3	827	* @param __INSTANCE__: SDMMC Instance
AnnaBridge	189:f392fc9709a3	828	* @retval None
AnnaBridge	189:f392fc9709a3	829	*/
AnnaBridge	189:f392fc9709a3	830	#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
AnnaBridge	189:f392fc9709a3	831	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	832
AnnaBridge	189:f392fc9709a3	833	/**
AnnaBridge	189:f392fc9709a3	834	* @brief Enable the SDMMC device interrupt.
AnnaBridge	189:f392fc9709a3	835	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	836	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
AnnaBridge	189:f392fc9709a3	837	* This parameter can be one or a combination of the following values:
AnnaBridge	189:f392fc9709a3	838	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	839	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	840	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	189:f392fc9709a3	841	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	189:f392fc9709a3	842	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	189:f392fc9709a3	843	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	189:f392fc9709a3	844	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	189:f392fc9709a3	845	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	189:f392fc9709a3	846	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	189:f392fc9709a3	847	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	189:f392fc9709a3	848	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	189:f392fc9709a3	849	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	189:f392fc9709a3	850	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	189:f392fc9709a3	851	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	189:f392fc9709a3	852	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	189:f392fc9709a3	853	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	189:f392fc9709a3	854	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	189:f392fc9709a3	855	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	189:f392fc9709a3	856	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	189:f392fc9709a3	857	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	189:f392fc9709a3	858	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	189:f392fc9709a3	859	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	189:f392fc9709a3	860	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	189:f392fc9709a3	861	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	189:f392fc9709a3	862	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	189:f392fc9709a3	863	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	189:f392fc9709a3	864	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	189:f392fc9709a3	865	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	189:f392fc9709a3	866	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	189:f392fc9709a3	867	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	189:f392fc9709a3	868	* @retval None
AnnaBridge	189:f392fc9709a3	869	*/
AnnaBridge	189:f392fc9709a3	870	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	871
AnnaBridge	189:f392fc9709a3	872	/**
AnnaBridge	189:f392fc9709a3	873	* @brief Disable the SDMMC device interrupt.
AnnaBridge	189:f392fc9709a3	874	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	875	* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
AnnaBridge	189:f392fc9709a3	876	* This parameter can be one or a combination of the following values:
AnnaBridge	189:f392fc9709a3	877	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	878	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	879	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	189:f392fc9709a3	880	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	189:f392fc9709a3	881	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	189:f392fc9709a3	882	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	189:f392fc9709a3	883	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	189:f392fc9709a3	884	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	189:f392fc9709a3	885	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	189:f392fc9709a3	886	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	189:f392fc9709a3	887	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	189:f392fc9709a3	888	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	189:f392fc9709a3	889	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	189:f392fc9709a3	890	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	189:f392fc9709a3	891	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	189:f392fc9709a3	892	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	189:f392fc9709a3	893	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	189:f392fc9709a3	894	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	189:f392fc9709a3	895	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	189:f392fc9709a3	896	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	189:f392fc9709a3	897	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	189:f392fc9709a3	898	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	189:f392fc9709a3	899	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	189:f392fc9709a3	900	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	189:f392fc9709a3	901	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	189:f392fc9709a3	902	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	189:f392fc9709a3	903	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	189:f392fc9709a3	904	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	189:f392fc9709a3	905	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	189:f392fc9709a3	906	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	189:f392fc9709a3	907	* @retval None
AnnaBridge	189:f392fc9709a3	908	*/
AnnaBridge	189:f392fc9709a3	909	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	910
AnnaBridge	189:f392fc9709a3	911	/**
AnnaBridge	189:f392fc9709a3	912	* @brief Checks whether the specified SDMMC flag is set or not.
AnnaBridge	189:f392fc9709a3	913	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	914	* @param __FLAG__: specifies the flag to check.
AnnaBridge	189:f392fc9709a3	915	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	916	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	189:f392fc9709a3	917	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	189:f392fc9709a3	918	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	189:f392fc9709a3	919	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	189:f392fc9709a3	920	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	189:f392fc9709a3	921	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	189:f392fc9709a3	922	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	189:f392fc9709a3	923	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	189:f392fc9709a3	924	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	189:f392fc9709a3	925	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	189:f392fc9709a3	926	* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
AnnaBridge	189:f392fc9709a3	927	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge	189:f392fc9709a3	928	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge	189:f392fc9709a3	929	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge	189:f392fc9709a3	930	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge	189:f392fc9709a3	931	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge	189:f392fc9709a3	932	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge	189:f392fc9709a3	933	* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	189:f392fc9709a3	934	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	189:f392fc9709a3	935	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	189:f392fc9709a3	936	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	189:f392fc9709a3	937	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	189:f392fc9709a3	938	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	189:f392fc9709a3	939	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	189:f392fc9709a3	940	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	189:f392fc9709a3	941	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	189:f392fc9709a3	942	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge	189:f392fc9709a3	943	* @arg SDMMC_FLAG_TXACT: Data transmit in progress
AnnaBridge	189:f392fc9709a3	944	* @arg SDMMC_FLAG_RXACT: Data receive in progress
AnnaBridge	189:f392fc9709a3	945	* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge	189:f392fc9709a3	946	* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
AnnaBridge	189:f392fc9709a3	947	* @retval The new state of SDMMC_FLAG (SET or RESET).
AnnaBridge	189:f392fc9709a3	948	*/
AnnaBridge	189:f392fc9709a3	949	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
AnnaBridge	189:f392fc9709a3	950
AnnaBridge	189:f392fc9709a3	951
AnnaBridge	189:f392fc9709a3	952	/**
AnnaBridge	189:f392fc9709a3	953	* @brief Clears the SDMMC pending flags.
AnnaBridge	189:f392fc9709a3	954	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	955	* @param __FLAG__: specifies the flag to clear.
AnnaBridge	189:f392fc9709a3	956	* This parameter can be one or a combination of the following values:
AnnaBridge	189:f392fc9709a3	957	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge	189:f392fc9709a3	958	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge	189:f392fc9709a3	959	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge	189:f392fc9709a3	960	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge	189:f392fc9709a3	961	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge	189:f392fc9709a3	962	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge	189:f392fc9709a3	963	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge	189:f392fc9709a3	964	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge	189:f392fc9709a3	965	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge	189:f392fc9709a3	966	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge	189:f392fc9709a3	967	* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge	189:f392fc9709a3	968	* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge	189:f392fc9709a3	969	* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge	189:f392fc9709a3	970	* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge	189:f392fc9709a3	971	* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge	189:f392fc9709a3	972	* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge	189:f392fc9709a3	973	* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge	189:f392fc9709a3	974	* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge	189:f392fc9709a3	975	* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge	189:f392fc9709a3	976	* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge	189:f392fc9709a3	977	* @retval None
AnnaBridge	189:f392fc9709a3	978	*/
AnnaBridge	189:f392fc9709a3	979	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge	189:f392fc9709a3	980
AnnaBridge	189:f392fc9709a3	981	/**
AnnaBridge	189:f392fc9709a3	982	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
AnnaBridge	189:f392fc9709a3	983	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	984	* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
AnnaBridge	189:f392fc9709a3	985	* This parameter can be one of the following values:
AnnaBridge	189:f392fc9709a3	986	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	987	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	988	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	189:f392fc9709a3	989	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	189:f392fc9709a3	990	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	189:f392fc9709a3	991	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	189:f392fc9709a3	992	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	189:f392fc9709a3	993	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	189:f392fc9709a3	994	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge	189:f392fc9709a3	995	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge	189:f392fc9709a3	996	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge	189:f392fc9709a3	997	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge	189:f392fc9709a3	998	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge	189:f392fc9709a3	999	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge	189:f392fc9709a3	1000	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge	189:f392fc9709a3	1001	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge	189:f392fc9709a3	1002	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge	189:f392fc9709a3	1003	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	189:f392fc9709a3	1004	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	189:f392fc9709a3	1005	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	189:f392fc9709a3	1006	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	189:f392fc9709a3	1007	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	189:f392fc9709a3	1008	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	189:f392fc9709a3	1009	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	189:f392fc9709a3	1010	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	189:f392fc9709a3	1011	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	189:f392fc9709a3	1012	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge	189:f392fc9709a3	1013	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge	189:f392fc9709a3	1014	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge	189:f392fc9709a3	1015	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge	189:f392fc9709a3	1016	* @retval The new state of SDMMC_IT (SET or RESET).
AnnaBridge	189:f392fc9709a3	1017	*/
AnnaBridge	189:f392fc9709a3	1018	#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1019
AnnaBridge	189:f392fc9709a3	1020	/**
AnnaBridge	189:f392fc9709a3	1021	* @brief Clears the SDMMC's interrupt pending bits.
AnnaBridge	189:f392fc9709a3	1022	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1023	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	189:f392fc9709a3	1024	* This parameter can be one or a combination of the following values:
AnnaBridge	189:f392fc9709a3	1025	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	1026	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge	189:f392fc9709a3	1027	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge	189:f392fc9709a3	1028	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge	189:f392fc9709a3	1029	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge	189:f392fc9709a3	1030	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge	189:f392fc9709a3	1031	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge	189:f392fc9709a3	1032	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge	189:f392fc9709a3	1033	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
AnnaBridge	189:f392fc9709a3	1034	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge	189:f392fc9709a3	1035	* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge	189:f392fc9709a3	1036	* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge	189:f392fc9709a3	1037	* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge	189:f392fc9709a3	1038	* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge	189:f392fc9709a3	1039	* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge	189:f392fc9709a3	1040	* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge	189:f392fc9709a3	1041	* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge	189:f392fc9709a3	1042	* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge	189:f392fc9709a3	1043	* @retval None
AnnaBridge	189:f392fc9709a3	1044	*/
AnnaBridge	189:f392fc9709a3	1045	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge	189:f392fc9709a3	1046
AnnaBridge	189:f392fc9709a3	1047	/**
AnnaBridge	189:f392fc9709a3	1048	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	189:f392fc9709a3	1049	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1050	* @retval None
AnnaBridge	189:f392fc9709a3	1051	*/
AnnaBridge	189:f392fc9709a3	1052	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
AnnaBridge	189:f392fc9709a3	1053
AnnaBridge	189:f392fc9709a3	1054	/**
AnnaBridge	189:f392fc9709a3	1055	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	189:f392fc9709a3	1056	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1057	* @retval None
AnnaBridge	189:f392fc9709a3	1058	*/
AnnaBridge	189:f392fc9709a3	1059	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
AnnaBridge	189:f392fc9709a3	1060
AnnaBridge	189:f392fc9709a3	1061	/**
AnnaBridge	189:f392fc9709a3	1062	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	189:f392fc9709a3	1063	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1064	* @retval None
AnnaBridge	189:f392fc9709a3	1065	*/
AnnaBridge	189:f392fc9709a3	1066	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
AnnaBridge	189:f392fc9709a3	1067
AnnaBridge	189:f392fc9709a3	1068	/**
AnnaBridge	189:f392fc9709a3	1069	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	189:f392fc9709a3	1070	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1071	* @retval None
AnnaBridge	189:f392fc9709a3	1072	*/
AnnaBridge	189:f392fc9709a3	1073	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
AnnaBridge	189:f392fc9709a3	1074
AnnaBridge	189:f392fc9709a3	1075	/**
AnnaBridge	189:f392fc9709a3	1076	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	189:f392fc9709a3	1077	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1078	* @retval None
AnnaBridge	189:f392fc9709a3	1079	*/
AnnaBridge	189:f392fc9709a3	1080	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
AnnaBridge	189:f392fc9709a3	1081
AnnaBridge	189:f392fc9709a3	1082	/**
AnnaBridge	189:f392fc9709a3	1083	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	189:f392fc9709a3	1084	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1085	* @retval None
AnnaBridge	189:f392fc9709a3	1086	*/
AnnaBridge	189:f392fc9709a3	1087	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
AnnaBridge	189:f392fc9709a3	1088
AnnaBridge	189:f392fc9709a3	1089	/**
AnnaBridge	189:f392fc9709a3	1090	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	189:f392fc9709a3	1091	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1092	* @retval None
AnnaBridge	189:f392fc9709a3	1093	*/
AnnaBridge	189:f392fc9709a3	1094	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	1095	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_SDIOSUSPEND)
AnnaBridge	189:f392fc9709a3	1096	#else
AnnaBridge	189:f392fc9709a3	1097	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDSUSPEND)
AnnaBridge	189:f392fc9709a3	1098	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	1099
AnnaBridge	189:f392fc9709a3	1100	/**
AnnaBridge	189:f392fc9709a3	1101	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	189:f392fc9709a3	1102	* @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1103	* @retval None
AnnaBridge	189:f392fc9709a3	1104	*/
AnnaBridge	189:f392fc9709a3	1105	#if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	1106	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
AnnaBridge	189:f392fc9709a3	1107	#else
AnnaBridge	189:f392fc9709a3	1108	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
AnnaBridge	189:f392fc9709a3	1109	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	1110
AnnaBridge	189:f392fc9709a3	1111	/**
AnnaBridge	189:f392fc9709a3	1112	* @brief Enable the CMDTRANS mode.
AnnaBridge	189:f392fc9709a3	1113	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1114	* @retval None
AnnaBridge	189:f392fc9709a3	1115	*/
AnnaBridge	189:f392fc9709a3	1116	#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_CMDTRANS)
AnnaBridge	189:f392fc9709a3	1117
AnnaBridge	189:f392fc9709a3	1118	/**
AnnaBridge	189:f392fc9709a3	1119	* @brief Disable the CMDTRANS mode.
AnnaBridge	189:f392fc9709a3	1120	* @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge	189:f392fc9709a3	1121	* @retval None
AnnaBridge	189:f392fc9709a3	1122	*/
AnnaBridge	189:f392fc9709a3	1123	#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
AnnaBridge	189:f392fc9709a3	1124	/**
AnnaBridge	189:f392fc9709a3	1125	* @}
AnnaBridge	189:f392fc9709a3	1126	*/
AnnaBridge	189:f392fc9709a3	1127
AnnaBridge	189:f392fc9709a3	1128	/**
AnnaBridge	189:f392fc9709a3	1129	* @}
AnnaBridge	189:f392fc9709a3	1130	*/
AnnaBridge	189:f392fc9709a3	1131
AnnaBridge	189:f392fc9709a3	1132	/* Exported functions --------------------------------------------------------*/
AnnaBridge	189:f392fc9709a3	1133	/** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge	189:f392fc9709a3	1134	* @{
AnnaBridge	189:f392fc9709a3	1135	*/
AnnaBridge	189:f392fc9709a3	1136
AnnaBridge	189:f392fc9709a3	1137	/* Initialization/de-initialization functions **********************************/
AnnaBridge	189:f392fc9709a3	1138	/** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge	189:f392fc9709a3	1139	* @{
AnnaBridge	189:f392fc9709a3	1140	*/
AnnaBridge	189:f392fc9709a3	1141	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
AnnaBridge	189:f392fc9709a3	1142	/**
AnnaBridge	189:f392fc9709a3	1143	* @}
AnnaBridge	189:f392fc9709a3	1144	*/
AnnaBridge	189:f392fc9709a3	1145
AnnaBridge	189:f392fc9709a3	1146	/* I/O operation functions *****************************************************/
AnnaBridge	189:f392fc9709a3	1147	/** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge	189:f392fc9709a3	1148	* @{
AnnaBridge	189:f392fc9709a3	1149	*/
AnnaBridge	189:f392fc9709a3	1150	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1151	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
AnnaBridge	189:f392fc9709a3	1152	/**
AnnaBridge	189:f392fc9709a3	1153	* @}
AnnaBridge	189:f392fc9709a3	1154	*/
AnnaBridge	189:f392fc9709a3	1155
AnnaBridge	189:f392fc9709a3	1156	/* Peripheral Control functions ************************************************/
AnnaBridge	189:f392fc9709a3	1157	/** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge	189:f392fc9709a3	1158	* @{
AnnaBridge	189:f392fc9709a3	1159	*/
AnnaBridge	189:f392fc9709a3	1160	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1161	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	1162	HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1163	#endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	1164	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1165	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1166
AnnaBridge	189:f392fc9709a3	1167	/* Command path state machine (CPSM) management functions */
AnnaBridge	189:f392fc9709a3	1168	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
AnnaBridge	189:f392fc9709a3	1169	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1170	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
AnnaBridge	189:f392fc9709a3	1171
AnnaBridge	189:f392fc9709a3	1172	/* Data path state machine (DPSM) management functions */
AnnaBridge	189:f392fc9709a3	1173	HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
AnnaBridge	189:f392fc9709a3	1174	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1175	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1176
AnnaBridge	189:f392fc9709a3	1177	/* SDMMC Cards mode management functions */
AnnaBridge	189:f392fc9709a3	1178	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
AnnaBridge	189:f392fc9709a3	1179
AnnaBridge	189:f392fc9709a3	1180	/* SDMMC Commands management functions */
AnnaBridge	189:f392fc9709a3	1181	uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
AnnaBridge	189:f392fc9709a3	1182	uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	189:f392fc9709a3	1183	uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge	189:f392fc9709a3	1184	uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	189:f392fc9709a3	1185	uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge	189:f392fc9709a3	1186	uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	189:f392fc9709a3	1187	uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge	189:f392fc9709a3	1188	uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	189:f392fc9709a3	1189	uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge	189:f392fc9709a3	1190	uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1191	uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1192	uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
AnnaBridge	189:f392fc9709a3	1193	uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1194	uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1195	uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	189:f392fc9709a3	1196	uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	189:f392fc9709a3	1197	uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
AnnaBridge	189:f392fc9709a3	1198	uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1199	uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1200	uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	189:f392fc9709a3	1201	uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef SDMMCx, uint16_t pRCA);
AnnaBridge	189:f392fc9709a3	1202	uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	189:f392fc9709a3	1203	uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1204	uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	189:f392fc9709a3	1205	uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge	189:f392fc9709a3	1206	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	189:f392fc9709a3	1207	uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
AnnaBridge	189:f392fc9709a3	1208	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	189:f392fc9709a3	1209
AnnaBridge	189:f392fc9709a3	1210	/**
AnnaBridge	189:f392fc9709a3	1211	* @}
AnnaBridge	189:f392fc9709a3	1212	*/
AnnaBridge	189:f392fc9709a3	1213
AnnaBridge	189:f392fc9709a3	1214	/**
AnnaBridge	189:f392fc9709a3	1215	* @}
AnnaBridge	189:f392fc9709a3	1216	*/
AnnaBridge	189:f392fc9709a3	1217
AnnaBridge	189:f392fc9709a3	1218	/**
AnnaBridge	189:f392fc9709a3	1219	* @}
AnnaBridge	189:f392fc9709a3	1220	*/
AnnaBridge	189:f392fc9709a3	1221
AnnaBridge	189:f392fc9709a3	1222	/**
AnnaBridge	189:f392fc9709a3	1223	* @}
AnnaBridge	189:f392fc9709a3	1224	*/
AnnaBridge	189:f392fc9709a3	1225
AnnaBridge	189:f392fc9709a3	1226	#endif /* SDMMC1 */
AnnaBridge	189:f392fc9709a3	1227
AnnaBridge	189:f392fc9709a3	1228	#ifdef __cplusplus
AnnaBridge	189:f392fc9709a3	1229	}
AnnaBridge	189:f392fc9709a3	1230	#endif
AnnaBridge	189:f392fc9709a3	1231
AnnaBridge	189:f392fc9709a3	1232	#endif /* __STM32L4xx_LL_SDMMC_H */
AnnaBridge	189:f392fc9709a3	1233
AnnaBridge	189:f392fc9709a3	1234	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/